Preliminary specification
File under Integrated Circuits, IC02
2000 Jan 13
Page 2
Philips SemiconductorsPreliminary specification
Multistandard Picture-In-Picture (PIP)
controller
FEATURES
• Suitable for single PIP, double window and multi PIP
applications
• Data formats 4 : 1 : 1 (all modes) and 4:2:2(most
modes)
• Sample rate of 14 MHz, 720 Y*-pixels/line
• Horizontal reduction factors1⁄
• Vertical reduction factors1⁄1,1⁄2,1⁄3and1⁄
• PIP OSD for the sub channels displayed
• Detection of PAL/NTSC with overrule bit
• CTE/LTE like circuits in display part
• Replay with definable auto increment, picture sample
rate and picture number auto wrap
• Programmable Y*UV to RGB conversion matrix with
independent coefficients for NTSC and PAL sources
• Display clock and synchronisation are derived from the
main PLL
• Three 8-bit Digital-to-Analog Converters (DACs)
• Three 8-bit Analog-to-Digital Converters (ADCs)
(7-bit performance) with clamp circuit for each
acquisition channel
• Main and sub can write to the same VDRAM address
spaces under certain conditions; the reduction factors
should be the same
• Y* and UV pedestals on the acquisition sides
• Independent vertical filtering with 1 : 1 for UV and Y* at
the display part.
3
⁄4,2⁄3,1⁄2,1⁄3,1⁄4and1⁄
1
4
SAB9079HS
GENERAL DESCRIPTION
6
The SAB9079HS is a PIP controller for a multistandard
application environment in combination with a
multistandard decoder such as for example TDA8310,
TDA9143 or TDA9321H.
The SAB9079HSinserts one or two live video signals with
reduced sizes into the main/display video signal. All video
signals are expected to be analog baseband signals. The
analog signals are stripped signals without sync.
Therefore the luminance signal is referred to as Y*. The
conversion into the digital environment and back is done
on-chip as well as the internal clock generation.
The SAB9079HS is suitablefor single PIP, double window
and multi PIP applications.
digital supply voltage for the core3.03.33.6V
digital supply voltage for the
4.55.05.5V
periphery
analog supply voltage3.03.33.6V
digital supply current for the coretbf115tbfmA
digital supply current for the
tbf10tbfmA
periphery
analog supply current−170210mA
oscillator frequency3584 × HSYNC−56−MHz
system frequency1792 × HSYNC−28−MHz
896 × HSYNC−14−MHz
448 × HSYNC−7−MHz
loop bandwidth−4−kHz
short term stabilityjitter during 64 µs−−4ns
2000 Jan 133
Page 4
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2000 Jan 134
handbook, full pagewidth
BLOCK DIAGRAM
Philips SemiconductorsPreliminary specification
Multistandard Picture-In-Picture (PIP)
controller
V
bias(SA)
V
ref(T)(SA)
V
ref(B)(SA)
SHSYNC
SVSYNC
V
bias(MA)
V
ref(T)(MA)
V
ref(B)(MA)
MHSYNC
MVSYNC
V
DDA(MF)
SY
SU
SV
MY
MU
MV
V
SSA(MA)
1
105
103
101
104
107
106
94
95
126
128
2
127
124
125
9
8
V
DDA(MA)
V
V
DDA(MP)
3
4
CLAMP AND ADC
PLL AND CLOCK
GENERATOR
CLAMP AND ADC
PLL AND CLOCK
GENERATOR
V
DDA(MH)
SSA(MP)
10
11
V
V
DDA(SA)
12
V
DDA(SF)
SSA(SA)
99
100
HORIZONTAL
VERTICAL
LINE MEMORY
HORIZONTAL
VERTICAL
LINE MEMORY
V
DDA(SH)
102
AND
FILTER
AND
FILTER
V
SSA(SP)
91
V
DDA(SP)
92
93
RAS
78
CAS
WE
70 77 40 51
TEST
CONTROL
AD8
DT
to AD0
SC
79 to 83,
74 to 71
VDRAM CONTROL
AND
(RE-)FORMATTING
SAB9079HS
I2C-BUS
CONTROL
DAO0
to DAO15
41 to 46,
49, 50, 69,
67, 65, 61,
59, 57, 55, 53
DAI0
to DAI15
39 to 32,
68, 66, 64,
60, 58, 56,
54, 52
V
DDA(DA)
V
SSA(DA)
30
DAC
AND
BUFFER
DISPLAY
CONTROL
LINE MEMORY
PLL AND CLOCK
GENERATOR
V
DDD(P)
31
113
24
DY
27
DU
29
DV
28
V
bias(DA)
26
V
ref(B)(DA)
25
V
ref(T)(DA)
19
DFB
84
n.c.
21
DVSYNC
20
DHSYNC
V
DDD(C1)
to
V
DDD(C7)
15, 18, 22,
85, 88,
109, 122
V
V
16, 17, 23,
86, 87,
108, 123
SSD(C1)
to
SSD(C7)
V
SSD(P1)
to
V
SSD(P5)
13,
47, 63,
75, 90
V
DDD(P1)
to
V
DDD(P5)
14,
48, 62,
76, 89
98
TSEXT
111114
TCBD
TCBRA0
TCBCSCL
Fig.1 Block diagram.
97112116
110115
TSMSBPOR
SDA
117
TMMSB
6
TMEXT
5
TSCLK
121
96
120
TM0
TM2
TM1
119
118
TC
7
TMCLK
MGS386
SAB9079HS
Page 5
Philips SemiconductorsPreliminary specification
Multistandard Picture-In-Picture (PIP)
SAB9079HS
controller
PINNING
SYMBOLPINI/ODESCRIPTION
V
DDA(MF)
MV2Ianalog V input of main channel
V
SSA(MA)
V
DDA(MA)
TMEXT5Iset main PLL input for external mode (CMOS levels)
TMMSB6Otest main MSB output of PLL counter (CMOS levels)
TMCLK7Itest clock main input (CMOS levels)
MVSYNC8Ivertical sync input for main channel (CMOS levels with hysteresis)
MHSYNC9Ihorizontal sync input for main channel (CMOS levels with hysteresis)
V
DDA(MP)
V
SSA(MP)
V
DDA(MH)
V
SSD(P1)
V
DDD(P1)
V
DDD(C1)
V
SSD(C1)
V
SSD(C2)
V
DDD(C2)
DFB19Ofast blanking control output (CMOS levels)
DHSYNC20Ohorizontal sync output (CMOS levels)
DVSYNC21Overtical sync output (CMOS levels)
V
DDD(C3)
V
SSD(C3)
DY24Oanalog Y* output of DAC
V
ref(T)(DA)
V
ref(B)(DA)
DU27Oanalog U output of DAC
V
bias(DA)
DV29Oanalog Voutput of DAC
V
SSA(DA)
V
DDA(DA)
DAI732Imemory input data bit 7 (CMOS levels)
DAI633Imemory input data bit 6 (CMOS levels)
DAI534Imemory input data bit 5 (CMOS levels)
DAI435Imemory input data bit 4 (CMOS levels)
DAI336Imemory input data bit 3 (CMOS levels)
DAI237Imemory input data bit 2 (CMOS levels)
DAI138Imemory input data bit 1 (CMOS levels)
DAI039Imemory input data bit 0 (CMOS levels)
DT40Omemory data transfer (CMOS levels)
1Sanalog supply voltage for main channel front-end (3.3 V)
3Sanalog ground for main channel ADCs
4Sanalog supply voltage for main channel ADCs (3.3 V)
10Sanalog supply voltage for main channel PLL (3.3 V)
11Sanalog ground for main channel PLL
12Ssupply of main HSYNC input (5.0 V)
13Sdigital ground 1 for periphery; note 1
14Sdigital supply voltage 1 for periphery (5.0 V); note 2
15Sdigital supply voltage 1 for core (3.3 V); note 3
16Sdigital ground 1 for core; note 4
17Sdigital ground 2 for core; note 4
18Sdigital supply voltage 2 for core (3.3 V); note 3
22Sdigital supply voltage 3 for core (3.3 V); note 3
23Sdigital ground 3 for core; note 4
25I/Oanalog top reference for DACs
26I/Oanalog bottom reference for DACs
28I/Oanalog voltage reference DACs
30Sanalog ground for DACs
31Sanalog supply voltage for DACs (3.3 V)
2000 Jan 135
Page 6
Philips SemiconductorsPreliminary specification
Multistandard Picture-In-Picture (PIP)
controller
SYMBOLPINI/ODESCRIPTION
DAO041Omemory output data bit 0 (CMOS levels)
DAO142Omemory output data bit 1 (CMOS levels)
DAO243Omemory output data bit 2 (CMOS levels)
DAO344Omemory output data bit 3 (CMOS levels)
DAO445Omemory output data bit 4 (CMOS levels)
DAO546Omemory output data bit 5 (CMOS levels)
V
SSD(P2)
V
DDD(P2)
DAO649Omemory output data bit 6 (CMOS levels)
DAO750Omemory output data bit 7 (CMOS levels)
SC51Omemory shift clock output (CMOS levels)
DAI1552Imemory input data bit 15 (CMOS levels)
DAO1553Omemory output data bit 15 (CMOS levels)
DAI1454Imemory input data bit 14 (CMOS levels)
DAO1455Omemory output data bit 14 (CMOS levels)
DAI1356Imemory input data bit 13 (CMOS levels)
DAO1357Omemory output data bit 13 (CMOS levels)
DAI1258Imemory input data bit 12 (CMOS levels)
DAO1259Omemory output data bit 12 (CMOS levels)
DAI1160Imemory input data bit 11 (CMOS levels)
DAO1161Omemory output data bit 11 (CMOS levels)
V
DDD(P3)
V
SSD(P3)
DAI1064Imemory input data bit 10 (CMOS levels)
DAO1065Omemory output data bit 10 (CMOS levels)
DAI966Imemory input data bit 9 (CMOS levels)
DAO967Omemory output data bit 9 (CMOS levels)
DAI868Imemory input data bit 8 (CMOS levels)
DAO869Omemory output data bit 8 (CMOS levels)
CAS70Omemory column address strobe output (CMOS levels)
AD071Omemory address output bit 0 (CMOS levels)
AD172Omemory address output bit 1 (CMOS levels)
AD273Omemory address output bit 2 (CMOS levels)
AD374Omemory address output bit 3 (CMOS levels)
V
47Sdigital ground 2 for periphery; note 1
48Sdigital supply voltage 2 for periphery (5.0 V); note 2
62Sdigital supply voltage 3 for periphery (5.0 V); note 2
63Sdigital ground 3 for periphery; note 1
75Sdigital ground 4 for periphery; note 1
76Sdigital supply voltage 4 for periphery (5.0 V); note 2
SAB9079HS
2000 Jan 136
Page 7
Philips SemiconductorsPreliminary specification
Multistandard Picture-In-Picture (PIP)
SAB9079HS
controller
SYMBOLPINI/ODESCRIPTION
AD582Omemory address output bit 5 (CMOS levels)
AD483Omemory address output bit 4 (CMOS levels)
n.c.84−not used in application
V
DDD(C4)
V
SSD(C4)
V
SSD(C5)
V
DDD(C5)
V
DDD(P5)
V
SSD(P5)
V
DDA(SH)
V
SSA(SP)
V
DDA(SP)
SHSYNC94Ihorizontal sync input for sub channel (CMOS levels with hysteresis)
SVSYNC95Ivertical sync input for sub channel (CMOS levels with hysteresis)
TSCLK96Itest clock input for sub (CMOS levels)
TSMSB97Otest sub MSB output for PLL counter (CMOS levels)
TSEXT98Iset sub PLL input for external mode (CMOS levels)
V
DDA(SA)
V
SSA(SA)
SV101Ianalog V input of sub channel
V
DDA(SF)
SU103Ianalog U input of sub channel
V
bias(SA)
SY105Ianalog Y* input of sub channel
V
ref(B)(SA)
V
ref(T)(SA)
V
SSD(C6)
V
DDD(C6)
TCBC110Itest control block clock input (CMOS levels)
TCBD111Itest control block data input (CMOS levels)
TCBR112Itest control block reset input (CMOS levels)
V
DDD(P)
A0114Iaddress select pin input (I
SDA115I/Oserial input data/ACK output (I
SCL116Iserial clock input (I
POR117Ipower-on reset input (CMOS levels with hysteresis and pull-up resistor to V
TC118Itest control input (CMOS levels)
TM1119I/Otest mode input/output (CMOS levels with hysteresis and pull-up resistor to V
TM2120I/Otest mode input/output (CMOS levels with hysteresis and pull-up resistor to V
TM0121Itest mode input (CMOS levels)
V
DDD(C7)
85Sdigital supply voltage 4 for core (3.3 V); note 3
86Sdigital ground 4 for core; note 4
87Sdigital ground 5 for core; note 4
88Sdigital supply voltage 5 for core (3.3 V); note 3
89Sdigital supply voltage 5 for periphery (5.0 V); note 2
90Sdigital ground 5 for periphery; note 1
91Ssupply of sub HSYNC input (5.0 V)
92Sanalog ground for sub channel PLL
93Sanalog supply voltage for sub channel PLL (3.3 V)
99Sanalog supply voltage for sub channel ADCs (3.3 V)
100Sanalog ground for sub channel ADCs
102Sanalog supply voltage for sub channel frontend (3.3 V)
104I/Oanalog bias reference input for sub channel ADCs
106I/Oanalog bottom reference for sub channel ADCs
107I/Oanalog top reference for sub channel ADCs
108Sdigital ground 6 for core; note 4
109Sdigital supply voltage 6 for core (3.3 V); note 3
113Sdigital supply voltage for periphery (5.0 V); note 5
2
C-bus) (CMOS levels)
2
C-bus) (CMOS input levels)
2
C-bus) (CMOS levels)
122Sdigital supply voltage 7 for core (3.3 V); note 3
DD
DD
DD
)
)
)
2000 Jan 137
Page 8
Philips SemiconductorsPreliminary specification
Multistandard Picture-In-Picture (PIP)
controller
SYMBOLPINI/ODESCRIPTION
V
SSD(C7)
V
ref(T)(MA)
V
ref(B)(MA)
MY126Ianalog Y* input for main channel
V
bias(MA)
MU128Ianalog U input for main channel
Notes
1. All periphery V
2. All periphery V
3. All core V
4. All core V
5. This pin is NOT connected to the other periphery V
123Sdigital ground 7 for core; note 4
124I/Oanalog top reference for main channel ADCs
125I/Oanalog bottom reference for main channel ADCs
127I/Oanalog bias reference for main channel ADCs
are internally connected to each other, unless otherwise specified.
SS(P)
are internally connected to each other, unless otherwise specified.
An overview of the general PIP modes is given in Figs 3, 4 and 5. These pictures do not refer to all possible modes the
device can handle. These modes are guaranteed only when sufficient memory is available and enough time is available
to fetch all data from the memory.
handbook, halfpage
handbook, halfpage
handbook, halfpage
handbook, halfpage
SP-Small
SP-Large
MGD594
MGD596
handbook, halfpage
handbook, halfpage
SP-Medium
DP
MGD595
MGD597
Twin-PIP
MGD598
Fig.3 PIP modes.
2000 Jan 1310
Full Field Still
Full Field Live
MGD587
Page 11
Philips SemiconductorsPreliminary specification
Multistandard Picture-In-Picture (PIP)
controller
handbook, halfpage
MGS388
handbook, halfpage
SAB9079HS
handbook, halfpage
MGS389
handbook, halfpage
MGS390
handbook, halfpage
POP-Left
MGD588
Fig.4 PIP modes (continued).
2000 Jan 1311
handbook, halfpage
POP-Right
POP-Double
MGD589
MGD590
Page 12
Philips SemiconductorsPreliminary specification
Multistandard Picture-In-Picture (PIP)
controller
handbook, halfpage
MP7
handbook, halfpage
MGD591
handbook, halfpage
handbook, halfpage
MP8
SAB9079HS
MGD592
Quatro
handbook, halfpage
MP16
MGD584
MGD586
Fig.5 PIP modes (continued).
2000 Jan 1312
handbook, halfpage
MP9
MP13
MGD585
MGL925
Page 13
Philips SemiconductorsPreliminary specification
Multistandard Picture-In-Picture (PIP)
controller
Acquisition window
The acquisition window is 720 pixels. This is related to a
whole line of 896 pixels. So for PAL will be
acquired from the active video. For NTSC this will be
slightly less.
720
--------- 896
63.5 µs×
The vertical acquisition window is 228 lines for NTSC and
276 lines for PAL. Data will be acquired in a 4 :2:2
format. The acquisition clock is 896 × HSYNC.
Acquisition fine positioning
2
C-bus settings relate to the incoming HSYNC,
All I
whether this is a real HSYNC or a burstkey for horizontal
positioning. The same applys for the incoming VSYNC for
vertical positioning. The relationships between the
acquisition window and the internal clamp pulse are
illustrated in Fig.6. In an application the clamp pulse must
be positioned, by the I2C-bus, between the HSYNC and
the start of the active video of the incoming signal.
720
--------- 896
64 µs×
SAB9079HS
Display window
The display window available for PIP pictures is also
720 pixels wide, related to a 896 pixels line. The vertical
display window is 228 lines for NTSC and 276 lines for
PAL.
Background window
The origin of the display window is referenced to the origin
of the background window. The background area is
768 pixels wide. Vertically it is 238 lines for NTSC and
286 lines for PAL.
Display fine positioning
The I2C-bus defined fine positioning has relationships to
the internal HSYNC and VSYNC as illustrated in Fig.7.
handbook, full pagewidth
The grey area depicts the background.
MAHFP
CIPER
CIDEL
MAVFP
228/276 lines
720 pixels
MGS391
Fig.6 Acquisition fine positioning.
2000 Jan 1313
Page 14
Philips SemiconductorsPreliminary specification
Multistandard Picture-In-Picture (PIP)
controller
handbook, full pagewidth
BGHFP
BGVFP
MDVFP
MDHFP
MAIN CHANNEL
768 pixels
SDHFP
SAB9079HS
SDVFP
SUB CHANNEL
238/286 lines
MGS392
The grey area depicts the background.
Fig.7 Display fine positioning.
YUV to RGB conversion matrix
A YUV to RGB conversion matrix is available. The nine
matrixcoefficientvaluescanbe set by I2C-buscommands.
Two sets can be defined; one for PAL and one for NTSC.
The matrix must be switched on, otherwise a 1 : 1
conversion takes place and Y*, U and V will be
unmodified.
Theconversionmatrix is based on the following equations.
All results (R, G and B) fall in the range from 0 to 1. Any
results outside of this range will be clipped to the nearest
end value. It should be noted that gamma correction is not
applied as is common practice. The end of this section
contains an example.
Normalised Y, U and V (indicated by subscript ‘a’) are
given by the following four equations:
1. Ya=x×Ra+y×Ga+z×B
a
2. x+y+z=1
3. Ua=Ba−Y
4. Va=Ra−Y
a
a
Absolute or discrete (indicated by subscript ‘d’) values
for Y, U and V are given by the following three equations:
1. Yd= 255 × Ya(V), Yanormalised (range 0 to 1)
U
2.,
3.,
128127
U
d
normalised (range −1 to +1)
U
a
128127
V
d
V
normalised (range −1 to +1)
a
×+=
×+=
a
----------- 1z–
V
a
----------- 1x–
2000 Jan 1314
Page 15
Philips SemiconductorsPreliminary specification
Multistandard Picture-In-Picture (PIP)
SAB9079HS
controller
Absolute or discrete (indicated by subscript ‘d’) values for R, G and B are given by the following three equations:
RdY
1.
GdY
2.
B
3.
d
The implementation of a matrix with 9 coefficients is shown in Table 1.
Table 1Matrix coefficients
YUV TO RGB MATRIX
COEFFICIENTS
Rry=1ru=0
Ggy=1
Bby=1bv=0
255
--------- -
d
127
255
--------- -
d
127
255
Y
--------- -
d
127
V
d
x
-- -
y
U
d
128–()1x–()××+=
128–()1z–()××+=
1x–()×V
d
Y
COFACTOR: Y
255
128–()××–
--------- 127
d
z
1z–()×Ud128–()××–=
-- -
y
U
d
d
COFACTOR:2 × (Ud− 128) COFACTOR: 2 × (Vd− 128)
rv
255
gu
bu
255
--------- 254
--------- 254
z
1z–()××–=gv
-- y
1z–()×=
255
--------- 254
255
--------- 254
V
d
1x–()×=
x
×1x–()×–=
-- y
So, for example;
R=ry×Y
+ru×2×(Ud− 128) + rv × 2 × (Vd− 128)
d
Table 2 shows how the coefficients can be calculated for a specific case where x = 0.299, y = 0.587 and z = 0.114.
Calculation of xv:y* 128 (rounded to the nearest integer), translates to a binary value. Calculation of xu:xv: translates to
a binary value with the coefficients for the binary bits: −1,1⁄
1
⁄4,1⁄8,1⁄16,1⁄32,1⁄
2
1
⁄
(LSB).
64
128
Table 2Coefficient calculation
COEFFICIENTEXPRESSIONDECIMAL VALUEBINARY VALUE
ry1110000000
ru0000000000
rv0.70401011010
255
--------- 254
1x–()×
gy1110000000
gu−0.17311101010
gv−0.35811010010
255
--------- 254
255
--------- 254
z
×1z–()×–
-- y
x
×1x–()×–
-- y
by1110000000
bu0.88901110010
255
--------- 254
1z–()×
bv0000000000
2000 Jan 1315
Page 16
Philips SemiconductorsPreliminary specification
Multistandard Picture-In-Picture (PIP)
SAB9079HS
controller
PLL phase shift compensation for VCR
When a VCR is applied as source for the main channel, a
large phase jump can appear when the VCR head
switches to another field. Since this phenomenon occurs
around the VSYNC, its effects can be compensated.
A prediction mechanism generates a compensation
window around the VSYNC. This window can be
manipulated with two parameters; VsPre and VsPost.
• VsPre sets the number of lines before the predicted
VSYNC, where the compensation window will start
• VsPostsets the number of linesafter the actual VSYNC,
where the compensation window will end.
Table 3I
Table 4Description of Table 3
SSTART condition
Aacknowledge bit (generated by SAB9079HS)
PSTOP condition
SLAVEslave address; the data transmission starts with the slave address byte SLV (2CH or 2EH);
SUBsub address byte; the SUB byte indicates the sub address which has to be written; if more than
DATAdata byte; the data byte is the actual data written to the sub address; the functions of each sub
2
C-bus slave receiver protocol
SSLAVEASUBADATAADATAAP
SYMBOLDESCRIPTION
the LSB of the SLV byte is the R/
one data byte is send (as above) the internal sub address counter is automatically incremented
after each data byte
address are explained in the following Sections
W bit which is logic 0 in slave receiver mode
2
C-bus
I
2
C-BUS CONTROL
I
The SAB9079HS is a slave receiver/transmitter. The
protocols are given in Tables 3 and 5.
2
Table 5I
Table 6Description of Table 5
SSTART condition
Aacknowledge bit; after the SLV generated by the SAB9079HS; after the DATA generated by the
Nacknowledge not bit; given by the master after the last data byte
PSTOP condition
SLAVEslave address; the data transmission starts with the slave address byte SLV (2DH or 2FH);
DATAdata byte; this is put on the bus by SAB9079HS in an auto increment mode; if the master gives an
2000 Jan 1316
C-bus slave transmitter protocol
SSLAVEADATAADATAADATAN P
SYMBOLDESCRIPTION
master
the LSB of the SLV byte is the R/
acknowledge the next data byte is sent; if the SAB9079HS has sent all its data it starts again with
the first data byte and the sequence is repeated; this continues until an acknowledge not is given
by the master
W bit which is logic 1 in slave transmitter mode
Page 17
Philips SemiconductorsPreliminary specification
Multistandard Picture-In-Picture (PIP)
SAB9079HS
controller
The SAB9079HS has 8 read/status registers. The last 7 registers are reserved for future purposes. Reading a reserved
register will return zero values.
The SAB9079HS has 192 write registers. Writing to a reserved register is not allowed.
An overview of all write registers is given in Table 7.
Table 7Description of write registers
SUB ADDRESS RANGEPURPOSE
00H to 04Hdisplay
05H to 11Hpositioning and sizing of PIPs
12H to 17Hdecoder settings
18H to 1FHacquisition control
20H to 25Hdecoder and PLL settings
26H to 28Hreserved
29H to 2AHdecoder and PLL settings
2BH to 2FHreplay settings
30H to 37Hborder and colour settings
38H to 3CHOSD controls
3DH to 4EHYUV to RGB conversion matrix settings
4FH to 5FHextra decoder settings
60H to 7FHreserved
80H to DFHOSD characters
E0H to FFHreserved
2
I
C-BUS READ REGISTERS
The SAB9079HS has 8 read/status registers. The register currently used are listed in Table 8. The remaining 7 are
reserved for future purposes. Reading a reserved register will return zero values.
This bit indicates the internal interface status of the sub
channel. A logic 0 indicates that the channel is in
interlaced mode, a logic 1 indicates that the channel is
non-interlaced.
Mask ID
This bit gives the version number of the chip. A logic 0
indicates that a SAB9079N1 is used, a logic 1 indicates
that a SAB9079N2 is used.
RepChano
These bits indicate the present picture number, counting
from 0, where replay acquisition is writing.
2
C-BUS DISPLAY SETTING REGISTERS
I
MPIPON and SPIPON
If MPIPON is set to logic 1 (see Table 10) the main PIP is
on. If itis set to logic 0 the main PIP is off. If SPIPON is set
to logic 1 the sub PIPs are on, in accordance with the
scheme of the PIPG bits (see Section “Positioning and
sizing of PIPs”). If SPIPON is set to logic 0 all the sub PIPs
are off. This can also be achieved by setting all PIPG bits
to zero.
SAB9079HS
• BGHfp, BGVfp, MDHfp, MDVfp, SDHfp and SDVfp
• MHPic, MVPic, SHPic, SVPic, SHDis and SVDis
• PIPG
• MHRed, MVRed, SHRed, SVRed, MLSel,
• OSDHfp, OSDVfp, OSDHDis and OSDVDis.
FillSet and FillOff
The FillSet bit sets the colour of all sub PIPs immediately
to a 30% grey value if is set to logic 1. If FillSet is set to
logic 0 then the 30% grey PIPs stay until the data in the
VDRAM is updated (unfrozen). This bit should be used in
the event that a new PIP mode is made in which the
VDRAM data becomes invalid. FillOff works the opposite
to FillSet. If this bit is set all the VDRAM data is made
visible in the PIPs and no PIP has a grey content. This bit
is generally not used.
MiS
If the MiS bit is set to logic 0 the main and sub channels
have their own independent memory spaces. If set to
logic 1 the main and sub channels share the same
memory space, this is only valid if the main and sub
channels have the same reduction factors.
c,r
SLSel and SBSel
MFreeze and SFreeze
MFreeze and SFreeze control the writing of data to the
VDRAM. If set to logic 0 the writing to the VDRAM is
disabled after the next VSYNC. If set to logic 1 the writing
is enabled after the next VSYNC.
I2CHold
The I2C-bus hold bit is set to logic 0 (default). This means
that all I2C-bus data is directly clocked into the internal
registers. A part of the I2C-bus data will be clocked in on
thenext VSYNC (e.g. thereduction factors and thedisplay
positioning). If the I2CHold bit is logic 1 that part of the
I2C-buswillnot be clocked in on the next VSYNC.Tomake
the data available the I2CHold bit should be set to logic 0
again. This function is useful when much data has to be
sent and a screenupdate is notallowed when sendingthis
data. A list of I2C-bus registers which are clocked in on a
VSYNC is given below:
• MPIPON and SPIPON
• MFreeze, SFreeze and FillSet
• DNonInt, MNonInt and SNonInt
• PRIO
YUVFilter
These bits control the vertical filtering of 1 : 1 for both the
Y* and UV channels independently. Several display filter
modes can be set with these bits. An overview is given in
Table 9. The Y filter should not be used in vertical1⁄
modes.
ColourTransient Enhancement (CTE) canbe set on or off.
Luminance Transient Enhancement (LTE) is controllable
via a scale, setting the scale value to 0H means that LTE
is off.
2000 Jan 1318
Page 19
Philips SemiconductorsPreliminary specification
Multistandard Picture-In-Picture (PIP)
controller
MFld and SFld
The number of fields stored in the VDRAM can be set with
the MFld and SFld bits. There is a limit of 4 Mbits which
can be stored. It is best to set these bits so that 3 fields
are stored for the sub channel and 2 forthe main channel,
but this is not possiblein all cases (large PIPs). Therefore,
the number of fields stored can be reduced. This can
result in some performance loss, e.g. if the sub channel is
set to 1 field joint line errors can appear.
IntOff, DNonInt, MNonInt and SNonInt
In automatic interlace mode (IntOff is logic 0) the device
calculateswhetherinterlaced or non-interlaced signals are
applied and acts accordingly. This can be overruled by
setting bit IntOff to logic 1. Bits DNonInt, MNonint and
SNonInt then determine the interlace. If the xNonInt bits
are set to logic 0 the device is put in interlaced mode, if
they are set to logic 1 the main, sub and/or display
channels are put in non-interlaced mode. DNonint
overrules MNonint (main and display channels are
coupled).
PalOff, DPal, MPal and SPal
In automatic mode (PalOff is logic 0) the device calculates
what type of signal is applied, PAL or NTSC. In the event
that the number of lines in a field is less than 287 it is
assumed to be NTSC, otherwise it is assumed to be PAL.
This can be overruled by setting PalOff to logic 1.
SAB9079HS
The xPal bits then determine the mode of the device. A
logic 0 sets the device in NTSC mode, a logic 1 to PAL
mode. DPAL overrules MPAL (main and display channels
are coupled).
PRIO, NipCoff, Fmt411, DFilt and Yth
The PRIO bit sets the priority between the main and sub
channels. A logic 0 gives priority to the sub channel which
meansthat the sub channel PIPs, if present,are placed on
top of the main PIP. A logic 1 places the main PIP on top
of the sub PIPs. The NiPCoff bit determines whether a
grey bar is inserted in case a NTSC PIP is displayed in a
PIP with PAL PIP size. The missing lines are equally
dividedbetweenthe top part and the bottom partofthePIP
window and made 30% grey. If this bit is logic 0 the grey
bar is displayed, if this bit is logic 1 the grey bar is omitted
and the PIP data is shifted up. The Fmt411 bit sets the
YUV format. If this bit is logic 0 then the device is in
4:2:2YUVmode, if this bit is logic 1then the device is in
4:1:1 YUV mode. If the 4:2:2 format is used the
memory use is larger, so some modes are not available
and the length of a read/write cycle is larger. The Dfilt bit
controls an interpolating filter to expand the internal
720 pixels data rate to the output data rate of 2 × 720
pixels in 1FH mode. If DFilt is logic 1 then the filter is on.
The Yth
Y value is less then Yth × 16 then the fast blanking is
switched off, and the original live background will be
visible. This feature can be used to pick up sub-titles and
display them as OSD anywhere on the screen.
POSITIONING AND SIZING OF PIPS
Thebasic principle is the same as inthe SAB9076/77. The
only difference is that the main channel can only display
1 PIP. The algorithm for the sub channel is similar. The
difference for the sub channel is that the number of PIPs
for each row and the offset of the first PIP is replaced by
grid bits. In the matrix of 16 PIPs every PIP can be put on
or off. The I2C-bus registers are given in Table 11.
BGHfp and BGVfp
The BGHfp and BGVfp bits control the horizontal
(4 pixels/step) and vertical (2 line/field/step) background
positioning (upper left corner).
SDHfp and SDVfp
The SDHfp and SDVfp bits control the horizontal
(4 pixels/step) and vertical (1 line/field/step) sub display
positioning (upper left corner).
SHPic and SVPic
Bit SHPic controls the horizontal size of the sub PIP in
steps of 4 pixels (minimum is 8 pixels). Bit SVPic controls
the vertical size of the sub PIP in steps of 1 line/field for
NTSC or 2 lines/field for PAL.
SAB9079HS
SHDis and SVDis
Bit SHDis controls the horizontal distance between the left
sides of the sub PIPs on a row in steps of 4 pixels. Bit
SVDis controls the vertical distance between the top lines
of sub PIPs in steps of 1 line (both Pal and NTSC). The
distancesshouldalwaysbeequal or larger than the picture
sizesso that the PIPsof one channel donot overlap. In the
event of single PIP modes SHDis should be set to
maximum.
MDHfp and MDVfp
The MDHfp and MDVfp bits control the horizontal and
vertical main display positioning.
MHPic and MVPic
Bit MHPic controls the horizontal size of the main PIP in
steps of 4 pixels (minimum is 24 pixels). Bit MVPic
controls the vertical size of the main PIP in steps of
1 line/field for NTSC or 2 lines/field for PAL.
PIPG
row,col
The PIPG
PIP on or off in a multi PIP mode. PIPs are numbered
according to Table 12. Rows are numbered from top to
bottom, columns are numbered from left to right.
bits make it possible to set each individual
row,col
2
Table 11 I
C-bus registers for PIP
SUB
ADDRESS
05HBGHfp
BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0
(3 : 0)
06HSDHfp
07HSDVfp
08HSHPic
09HSVPic
0AHSHDis
0BHSVDis
0CHMDHfp
0DHMDVfp
0EHMHPic
0FHMVPic
10HPIPG
11HPIPG
1,3
3,3
PIPG
PIPG
1,2
3,2
PIPG
PIPG
1,1
3,1
PIPG
PIPG
DATA BYTES
(7 : 0)
(7 : 0)
(7 : 0)
(7 : 0)
(7 : 0)
(7 : 0)
(7 : 0)
(7 : 0)
(7 : 0)
(7 : 0)
1,0
3,0
PIPG
PIPG
0,3
2,3
PIPG
PIPG
BGVfp
0,2
2,2
(3 : 0)
PIPG
PIPG
0,1
2,1
PIPG
PIPG
0,0
2,0
2000 Jan 1320
Page 21
Philips SemiconductorsPreliminary specification
Multistandard Picture-In-Picture (PIP)
controller
Table 12 PIP numbering
ROWCOLUMN 0COLUMN 1COLUMN 2COLUMN 3
0PIPG
1PIPG
2PIPG
3PIPG
ACQUISITION CONTROL
Acquisition control sets the reduction factors, the
acquisition fine positioning and the channel selection bits
are given in Table 13.
SHRed, SVRed, MHRed and MVRed
The reduction factors can be set in accordance with
Table 14.
SAHfp and SAVfp
The SAHfp and SAVfp bits control the horizontal
(2 pixels/step) and vertical (1 line/field/step) sub
acquisition positioning (upper left corner). When SAHfp is
set to logic 0, the sub channel will enter the freeze mode.
0,0
1,0
2,0
3,0
SAB9079HS
PIPG
0,1
PIPG
1,1
PIPG
2,1
PIPG
3,1
SLSel and MLSel
Bits SLSel and MLSel select which PIP is updated.
A maximum of 16 PIPs can be displayed for the sub
channel. The number counting is done fromthe left toright
and from top to bottom.
If all PIPs are on (see Table 12) 16 PIPs are displayed.
If PIPs are put off the maximum number is limited to the
number of PIPs displayed. In the PIP mode where the
mainand sub channel have thesame reduction factors the
main channel can write in sub VDRAM address spaces
accordingtothesamenumbering. In all other cases MLSel
is inoperative and should be set to 0H. For replay and
other trick modes morePIPs can bestored and addressed
via the higher numbers (17 to 60). The numbers
61, 62 and 63 are not valid.
PIPG
PIPG
PIPG
PIPG
0,2
1,2
2,2
3,2
PIPG
PIPG
PIPG
PIPG
0,3
1,3
2,3
3,3
MAHfp and MAVfp
The MAHfp and MAVfp bits control the horizontal
(2 pixels/step) and vertical (1 line/field/step) main
acquisition positioning (upper left corner). When MAHfp is
set to logic 0, the main channel will enter the freeze mode.
SYClRef, SUClRef, SVClRef, MYClRef, MUClRef and
MVClRef
The clamp reference level can be set separately for each
of the 6 analog inputs; it acts as a wide range pedestal.
Under normal conditions SYClRef will be set to 0 and
SUVClRef will be set to 128.
DHsel, FidOn, VFilt, UVPol, VSPol, FPol and CCON
HORIZONTALVERTICAL
1
⁄
1
1
⁄
2
1
⁄
3
1
⁄
4
2
⁄
3
1
⁄
6
3
⁄
4
SAB9079HS
1
⁄
1
1
⁄
2
1
⁄
3
1
⁄
4
not validnot validnot valid
1
⁄
6
not validnot validnot valid
IntCoff, FbDel and YDel
BitIntCoffsetstheinterlacecorrection.Interlacecorrection
isput off if this bit issetto logic 1. FbDel
fast blank delay in 8 steps of a1⁄228 MHz clock cycle
(−4 to +3); 0H is mid-scale. YDel adjusts the Y delay with
respect to the UV delay; 0H is mid-scale from −4to+3
pixels. YDel is done on the display side and therefore both
channels,mainand sub channels, will have anequaldelay
in the luminance.
1
⁄
1
1
⁄
2
1
⁄
3
1
⁄
4
1
⁄
1
1
⁄
2
1
⁄
3
1
⁄
4
not validnot valid
canadjust the
(2 : 0)
• DHsel determines the timing of the HSYNC pulse
(burstkey = 0 or HSYNC = 1), for the display part
• FidOn enables the field identification position fine
tuning; FidOn = 1 takes the value of registers
4FH or 57H; FidOn = 0 takes a hard wired default value
• VFilt enhances the vertical reduction filter for vertical
reduction modes1⁄3and1⁄
4
• SUVPol and MUVPol invert the UV polarity of the YUV
data
• DUVPol inverts the UV polarity of the border colours
• VSPol determines the active edge of the VSYNC
(positive edge is logic 0 and negative edge is logic 1)
• FPol can invert the field ID of the incoming fields
• CCON enables the clamp correction circuit.
Pedestals
Onthe acquisition sides YUV can begivenan offset during
the clamp. Using this mechanism minor offsets in the
matricescanbe adjusted. The steps are from −8 to +7with
a resolution of 1 LSB of the ADC.
VSPre and VSPost
VSPre is the number of lines before a VSYNC where the
PLL is put in free-running mode. VSPost is the number of
lines after the VSYNC where the PLL is still free-running.
Outside this area the PLL is in normal mode.
DChaOff is the channel offset for the display. It can be
used in trick modes or software replay as the channel
number to be displayed.
DChaDis
DChaDis is the number of internal VSYNCs between two
stored and/or displayed fields.
RepMax
RepMaxis the maximum number of different fields that will
be stored in the memory during replay.
RepInc
Repinc is the auto increment used during replay
acquisition/display.
RepAcq, RepDisp, RepCont, DCha+ and DCha
−
Bit RepAcq enables the replay acquisition loop, in which
pictures are stored with DChaDis as time distance. Bit
RepDisp enables the display of stored pictures. When bit
RepCont = 1 it enables a continuous looping during
display, when bit RepCont = 0 it enables the step function.
Bit DCha+ enables one step forward (next picture), bit
DCha− enables one step back in time (previous picture). It
should be noted that if bits RepAcq and RepDisp are both
logic 1atthesametime,theinternaldisplay number will be
the present acquisition number minus 1.
2000 Jan 1323
Page 24
Philips SemiconductorsPreliminary specification
Multistandard Picture-In-Picture (PIP)
SAB9079HS
controller
Table 16 Replay settings
SUB
ADDRESS
2BH−−DChaOff
2CHDChaDis
2DH−−RepMax
2EHDCha+DCha−RepAcqRepDispRepCont−−RGBOn
2FH−−RepInc
Note
1. RGBOn enables the YUV to RGB matrix. It is not related to the replay registers.
BORDER AND COLOUR SETTINGS
Several border and colour settings are given in Table 17.
BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0
BHSize and BVSize
Bits BHSize and BVSize control thehorizontal and vertical
border size in steps of 2 pixels and 1 line.
OUVPol
Bit OUVPol sets the UV polarity for all the OSD related
colours.
FBLON
If bit FBLON is set to logic 1 the FBL pin is made HIGH
under the condition that standard signals are applied.
If PAL signals are applied, this functionis overruled for the
SAB9078HS.
Shade
Bit Shade gives the OSD characters a shade.
OSDBLK
DATA BYTES
(5 : 0)
(7 : 0)
(5 : 0)
(5 : 0)
Colour registers
The colour registers are all built-up in a similar way:
• Bit 6 is the on bit which determines whether the border
(or OSD) is visible
• Bits 5 and 4 determine the brightness level ofthe colour
(see Table 18)
• Bits 2, 1 and 0 determine the colour type (see Table 18)
• SB = Sub Border
• SBS = Sub Border Select (which PIP has a different
border colour)
• MB = Main Border
• BG = Back Ground
• OSD is the OSD character
• OSDS = the background ofthe selected OSD character.
SBSel
The SBSel bits select which sub PIPhas a differentborder
colour, if SBSON is set to logic 1. The colour type can be
set with SBSBrt and SBSCol.
(1)
Bit OSDBLK blanks all OSD characters but retains their
values in memory.
White (low)0H0%10%30%50%
Blue1H30%50%70%100%
Red2H30%50%70%100%
Magenta3H30%50%70%100%
Green4H30%50%70%100%
Cyan5H30%50%70%100%
Yellow6H30%50%70%100%
White (high)7H60%70%80%100%
DATA BYTES
(1 : 0)
(1 : 0)
(1 : 0)
(1 : 0)
(1 : 0)
(1 : 0)
BVSize
−SBCol
(3 : 0)
(2 : 0)
−SBSCol
−MBCol
−BGCol
−OSDCol
−OSDSCol
(3 : 0)
(2 : 0)
(2 : 0)
(2 : 0)
(2 : 0)
(2 : 0)
OSD CONTROLS
OSD can be placed on the screen in 4 rows of 4 strings.
Each string can hold up to 6 characters. They can be
placedontop of the sub PIPs. Finepositioningisdone with
the OSDHfp and OSDVfp bits. The OSDHDis bits
determine the distance between the strings and OSDVdis
determine the distance between the rows (see Table 19).
OSDHfp and OSDVfp
Bits OSDHfp and OSDVfp control the fine positioning of
the OSD text in steps of 4 pixels and 1 line.
OSDHDis and OSDVDis
Bit OSDHDis determines the distance between the strings
(in steps of 4 pixels) and bit OSDVdis determines the
distance between the rows (in steps of 1 line).
2000 Jan 1325
OSDEXP
It is possible to expand the OSD characters. 0xH is
standard, 10H doubles the size and 11H quadruples the
size.
OSDBG and OSDTR
BitOSDBGsetsthe OSD background. Bit OSDTR sets the
transparency of the OSD background; the options are
given in Table 20.
OSDHRep and OSDVRep
Bit OSDHRep (see Table 21) sets the actual number of
strings per row (a maximum of 4). Bit OSDVRep sets the
actual number of rows (a maximum of 4).
Page 26
Philips SemiconductorsPreliminary specification
Multistandard Picture-In-Picture (PIP)
SAB9079HS
controller
Table 19 OSD control registers
SUB
ADDRESS
BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0
38HOSDHfp
39HOSDVfp
3AHOSDHDis
3BHOSDVDis
3CHOSDEXPOSDBGOSDTROSDHRep
Table 20 OSD background
MODEOSDBGOSDTRNOTE
Only OSD0xPIP (BG)
OSD with BG1030% white
Transparent1150% PIP/30% white
Table 21 Row and string settings
DATA BYTES
(7 : 0)
(7 : 0)
(7 : 0)
(7 : 0)
(1 : 0)
OSDVRep
(1 : 0)
OSDXRep VALUEOSDHRep NR. OF STRINGSOSDVRep NR. OF ROWS
00B11
01B22
10B33
11B44
OSD CHARACTERS
The OSD characters can be written to I2C-bus sub address 80H and higher (see Table 22). Theindex OSDCHR
pos,row,col
indicates the character position in the string, the row number and the column number of the string.
The OSDChr byte is divided into groups. The lower 7 bits OSDChr
to the character ROM table. Bit 7 indicates whether the character is selected, e.g. to change the background of that
character. Selecting the first character of a string selects the whole string; selecting any other character has no effect.
3. B = BYCoef × Yd+ BUCoef × 2 × (Ud− 128) + BVCoef × 2 × (Vd− 128)
In this equation Yd is normalised for the range 0 to 255, Udand Vd for the range −128 to 128. The UV coefficients are
twos complement in the range −1 ≤ coef < 1. The Y coefficients are positives in the range 0 ≤ coef < 2. For PAL pictures
the coef1 values are used, for NTSC the coef2 values.
1. DCha+, DCha−, RepAcq, RepDisp and RepCont are used for replay settings. They are not related to the conversion
matrix.
2000 Jan 1329
Page 30
Philips SemiconductorsPreliminary specification
Multistandard Picture-In-Picture (PIP)
controller
EXTRA DECODER SETTINGS
ClDel and ClPer
XXClDel sets the delay from the rising edge of the
HSYNC/burstkey to the beginning of the internally
generated clamp pulse for signal XX in steps of 1 pixel.
XXClPer sets the pulse width of the internally generated
clamp pulse in steps of 1 pixel.
FidPos
Bit Fidpos defines the position of the field identification
window. The purpose is to set it so that the incoming
VSYNC is halfway up the window. This allows a spread of
1
⁄4line for the VSYNC (VCR and/or less sophisticated
decoder types) in steps of 2 pixels.
VGate
XVGate disables the detection of a next VSYNC for a
number of lines, after detecting an initial one in steps of
1 line.
SAB9079HS
SmlPal
If this bit is set to logic 1, the vertical acquisition and
display window for PAL is decreased from 276 lines to
258 lines
TGAct1, TGAct2, TColBar, TGenY, TGenU and TGenV
For test purposes, a built-in colour bar/ramp generator is
available which replaces the ADC digital output data. This
test generator is enabled if TGAct1 and TGAct2 are both
setto logic 1, and isdisabled when TGAct2 is setto logic 0
(it is recommended to set TGAct1 to logic 1). The test
pattern (common for main and sub channels) is set to
colour bar if TColBar is set to logic 1 and set to a ramp if
TColBar is set to logic 0. Both patterns start at a HSYNC
pulse. By use of bit(s) TGenX (active logic 1) the
Y, U and V of the pattern can be controlled independently.
These are 8-bit DACs. The maximum output sample
frequency is 28 MHz.
Acquisition channel ADCs and clamping
Theanalog input signals are convertedto digital signals by
means of three ADCs. The resolution of the ADCs is 8-bit
(DNL is 7-bit, INL is 6-bit) and the sampling is done at the
system frequency of 14 MHz. The inputs should be
AC-coupled and an internal clamp circuit will clamp the
input to V
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOLPARAMETERCONDITIONSMIN.MAX.UNIT
V
DDD(P)
V
DDD(C)
V
DDA
P
max
T
stg
T
amb
V
ESD
digital supply voltage for the peripheral−0.5+6.0V
digital supply voltage for the core−0.5+4.0V
analog supply voltage−0.5+4.0V
maximum power dissipation−1.5W
storage temperature−25+150°C
ambient temperature070°C
electrostatic handlingnote 1−3000V
The clamping starts at the active edge of the internally
generated clamp period signal. The clamp period signal,
generated from the HSYNC pulse, has a delay adjusted
with the XXCICel bits with respect to the HSYNC. Internal
video buffers amplify the standard input signals
Y*, U and V to the correct ADC levels. The bandwidth of
the input signals should be limited to 4.5 MHz for the
Y input and 1.125 MHz for the U and V inputs.
PLL
The PLL generates, from the HSYNC, an internal system
clock of 3584 HSYNC which is approximately 56 MHz.
The other system clocks are derived from this clock. They
are in the range 3584, 1792, 896 or 448 × HSYNC.
note 2−300V
Notes
1. Human body model; see
2. Machine model; see
“UZW-B0/FQ-B302”
“UZW-B0/FQ-A302”
.
.
QUALITY SPECIFICATION
According to
the
“Quality Reference Handbook”
“SNW-FQ-611 Part E”
, dated 14 december 1992. The numbers of the quality specification can be found in
. The handbook can be ordered using the code 9397 750 00192.
THERMAL CHARACTERISTICS
SYMBOLPARAMETERCONDITIONSVALUEUNIT
R
th(j-a)
thermal resistance from junction to ambientin free air37K/W
system frequencynote 1−3584xHSYNCkHz
rise time−625ns
fall time−625ns
DDD
DDD
DDD
Note
1. The internal system frequencies are 3584, 1792, 896 and 448 times the HSYNC input frequency.
TEST AND APPLICATION INFORMATION
TV application with insertion before 100 Hz feature box (double window)
In the 100 Hz application the deflection circuit operates at 100 Hz. The PIP data is inserted into the main decoder output
stream and fed to the feature box. The double window feature is made at 1Fh and the field rate is doubled in the feature
box. The internal synchronization is illustrated in Fig.9.
handbook, full pagewidth
DECODER
DECODER
Y*UV
HV
HV
Y*UV
HV
SUB
MAIN AND
DISPLAY
Y*UV/RGB
FBL
SWITCH
FEATURE
BOX
MGS829
Y*UV
HV
Fig.9 1Fh/1Fv application with insertion before the feature box.
2000 Jan 1335
Page 36
Philips SemiconductorsPreliminary specification
Multistandard Picture-In-Picture (PIP)
SAB9079HS
controller
SLAVE 2FH GENERAL DESCRIPTION
In the slave mode the main and display channel has to
follow an external 2Fh, xFv signal. The main acquisition
cannot handle such a source, the main/display PLL can.
Thus no main channel PIP is available, only the
upconverted sub channel can be inserted. The following
functions are available in 4:1:1 only unless otherwise
indicated:
• Suitable for single PIP, multi PIP, replay and channel
overview applications
• Data formats 4 : 1 : 1 (all modes) and 4 :2:2 (some
modes)
• PIP OSD for the sub channels displayed
• Detection of PAL/NTSC with overrule bit
2FH,1FV ALGORITHMS
Table 26 Available 2Fh and 1Fv algorithms
ALGORITHMFORMAT 4 : 1 : 1FORMAT 4 : 2 : 2REMARKS
progressive scanyesno; note 1proscan (median filtering)
line doublingyesyesnote 2
• CTE and LTE like circuits in display part
• Replay with definable auto increment, picture sample
rate and picture number auto wrap
• Programmable Y*UV to RGB conversion matrix with
independent coefficients for NTSC and PAL sources
• Display clock and synchronization are derived from the
main channel PLL.
The following features are only available for the sub
channel:
• Sample rate of 14 Mhz, 720 Y* pixels/line
• Horizontal reduction factors1⁄
• Vertical reduction factors1⁄1,1⁄2,1⁄3and1⁄4.
1
⁄2,1⁄3,1⁄4and1⁄
1
6
Notes
1. Median filtering in 4:2:2 mode is allowed for single PIP (no main channel) and reduction factors not greater than
1
⁄2 for both horizontal and vertical
2. The performance of the line doubling algorithm is dependent on the picture content. Line (based interlace) flickering
will remain in this mode.
via median filtering and
averaging with original
fields
Note
1. Median filtering in 4:2:2 mode is allowed for single PIP (no main channel) and reduction factors not greater than
1
⁄2 for both horizontal and vertical
yesno; note 1digital scan
yesno; note 1digital scan plus
2000 Jan 1336
Page 37
Philips SemiconductorsPreliminary specification
Multistandard Picture-In-Picture (PIP)
SAB9079HS
controller
SLAVE 2FH AND XFV RELATED I2C-BUS REGISTERS
Table 28 Overview of the I2C-bus registers and their subaddresses
SUB
ADDRESS
01HD2FHD2FV−−MFld
02HYUVFilter
BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0
(1:0)
ABMode
D2FH and D2FV
These bits control the display mode with respect to 2Fh or 100 Hz features. If D2FH is set to logic 1 the number of lines
is doubled and/or if D2FV is set to logic 1 the number of fields is doubled.
ABMode
These bits select the different algorithms for 2Fh modes; see Table 29.
Algorithm selection
Several display algorithms can be set with these bits; an overview is given in Table 29.
DATA BYTES
(1:0)
(1:0)
CTELTE
(2:0)
SFld
(1:0)
Note: BGVfp
The resolution of the MAVfp bits changes in 2Fh and xFv modes. In 2Fh and 1Fv modes the vertical resolution is
2 lines/field/step on 1Fh base. In 2Fh and 2Fv modes the vertical resolution is 2 lines/field/step on 2Fh base.
Table 29 Overview of algorithm selection
MODED2FHYUVFilterD2FVABMode
No filter000H−00H
UV 1 : 1 V filter001H000H
Y 1 : 1 V filter010H000H
YUV 1 : 1 V filter011H000H
2FH/1FV frame1xxH000H
2FH/1FV proscan1xxH001H
2FH/1FV line doubling1xxH010H
not valid1xxH011H
2FH/2FV AABB100H100H
2FH/2FV ABAB100H101H
2FH/2FV AB’A’B100H110H
2FH/2FV AB’A’B+100H111H
2000 Jan 1337
Page 38
Philips SemiconductorsPreliminary specification
Multistandard Picture-In-Picture (PIP)
SAB9079HS
controller
SLAVE 2FH MEMORY REQUIREMENTS
In the slave 2Fh modes only the sub picture can be present. The following conditions must be met:
• When vertical reduction is 1, the field mode can be set to 3
• When vertical reduction is not equal to 1, the field mode must be set to 4
• When no live picture is present, such as replay or channel overview, the field mode can be set to 1.
Under these conditions a maximum number of stored fields/pictures can be determined. Combined with the size of one
picture, the total amount needed can be calculated always supposing that 1 PIP is live.
A selected overview is given in Table 30. The VDRAM size is 262144 words of 16 bits
SLAVE 2FH DESIGN RESTRICTIONS
The design has margins for a 2Fhfrequency of 31.5 kHz. Applying a SVGA source with a horizontal frequency of 38 kHz
will stress the SAB9079HS. Therefore, a SVGA source can only be applied under the following restricted conditions:
• Power supply spread of 5% instead of 10%
• No VCR like phase jump in 2Fh signal.
Table 31 Design characteristics
SYMBOLPARAMETERCONDITIONSMIN.TYP.MAX.UNIT
Supplies
V
DDD(P)
V
DDD(C)
V
DDA
V
SS
Main PLL and clock generation
f
i(PLL)
Note
1. The PLL will lock within 20 lines to instable sources with a large phase jump if the frequency is within the range
28 to 36 kHz.
2. The PLL will lock to stable 2Fh sources with a maximum frequency of 60 kHz.
all digital supply voltages
for periphery
all digital supply voltages
for core
all analog supply voltages3.153.33.6V
all ground voltages−0−V
note 12831.5036kHz
note 2−−60kHz
4.755.05.25V
3.153.33.6V
2000 Jan 1338
Page 39
Philips SemiconductorsPreliminary specification
Multistandard Picture-In-Picture (PIP)
SAB9079HS
controller
TV APPLICATION WITH INSERTION AFTER 100 HZ (SLAVE)
In this application there is no relationship between the deflection and acquisition circuits. A double window feature can
be realized by letting the feature box compress one window and make the second window by the SAB9079HS. In this
application the HVSYNC of the feature box/line doubler is connected to the main acquisition HVSYNC. The restriction is
that no main PIPs can be displayed. The application diagram is illustrated in Fig.10.
handbook, full pagewidth
DECODER
Y*UV (not used)
DECODER
Y*UV
HV
HV
HV
SUB
DISPLAY
FEATURE BOX/
LINE DOUBLER
Y*UV/RGB
FBL
SWITCH
MGS830
Y*UV
HV
Instead of the feature box a SVGA signal can be applied.
Fig.10 2Fh/1Fh application with insertion after the feature box/line doubler.
2000 Jan 1339
Page 40
Philips SemiconductorsPreliminary specification
Multistandard Picture-In-Picture (PIP)
controller
Master 2Fh general description
A 1Fh, 1Fv signal at the acquisition side can be
upconverted to a 2Fh, 1Fv or a 2Fh, 2Fv signal. The
restriction is that both acquisition channels will be
upconvertedatthesametime.Therefore,themainchannel
displayed as 1Fh, 1Fv combined with a sub channel
displayed as 2Fh, 1Fv is not possible. In the master mode
the SAB9079HS generates the HSYNC and VSYNC for
display/deflection. There is no protection built in. HSYNC
and VSYNC cannot be coupled directly to a tube. A
deflection IC should be applied. Both main and sub
pictures can be acquired/displayed. The following
functions are available:
• Suitable for single PIP, some multi PIP modes, replay
and channel overview applications
• Data formats 4 : 1 : 1 (all modes) and 4 :2:2 (some
modes)
2FH,1FV ALGORITHMSTable 32 Available 2Fh and 1Fv algorithms
SAB9079HS
• Sample rate of 14 Mhz, 720 Y* pixels/line
• Horizontal reduction factors for main channel
3
1
⁄
⁄4,2⁄3,1⁄2,1⁄3,1⁄4and1⁄
1
• Horizontal reduction factors for sub channel
3
1
⁄
⁄4,2⁄3,1⁄2,1⁄3,1⁄4and1⁄
1
• Vertical reduction factors1⁄1,1⁄2,1⁄3and1⁄4.
• PIP OSD for the sub channels displayed
• Detection of PAL/NTSC with overrule bit
• CTE and LTE like circuits in display mode
• Replay with definable auto increment, picture sample
rate and picture number auto wrap
• Programmable Y*UV to RGB conversion matrix with
independent coefficients for NTSC and PAL sources
• Display clock and synchronization are derived from the
main channel PLL.
6
6
ALGORITHMFORMAT 4 : 1 : 1FORMAT 4 : 2 : 2REMARKS
progressive scanyesno; note 1proscan (median filtering)
line doublingyesyesnote 2
Notes
1. Median filtering in 4:2:2 mode is allowed for single PIP (no main channel) and reduction factors not greater than
1
⁄2 for both horizontal and vertical
2. The performance of the line doubling algorithm is dependent on the picture content. Line (based interlace) flickering
will remain in this mode.
These bits control the display mode with respect to 2Fh or
100 Hz features. If D2FH is set to logic 1 the number of
lines is doubled and/or if D2FV is set to logic 1 the number
of fields is doubled.
If DMaster is at logic 0 the device is in slave mode.
DHSYNC and DVSYNC should not be used. If DMaster is
at logic 1 the device is in master mode which means that
HV synchronization signals are generated. They are
derived from MHSYNC and MVSYNC. The DHSYNC and
DVSYNC output signals should be used as sync signals
for the deflection IC.
DVSPosis only valid if DMasterisset to logic 1. If DVSPos
is set to logic 0 the VSYNC pulses are generated with an
alternating field ID according to the ABAB algorithm. If
DVSPos is set to logic 1 the VSYNC pulses are generated
in the AABB scheme which means that two first fields are
alternated with two second fields.
ABMode
These bits select the different algorithms for 2Fh modes;
see Table 35.
DATA BYTES
(1:0)
(1:0)
CTELTE
HSWidth
The width of the DHSYNC can be set in the master mode.
The width is from 0 to 31 pixels and the resolution is one
2Fh pixel.
VSWidth
The width of the DVSYNC can be set in the master mode.
The scale is from 0 to 31 lines on a 2Fh base and the
resolution is1⁄22Fh.
VSDel
The position of the DVSYNC, with respect to the incoming
MVSYNC, can be set in the master mode. The delay is a
6-bit value and the steps are from 0 to 63 lines on a 2Fh
base and the resolution is1⁄22Fh line.
Algorithm selection
Several display algorithms can be set with these bits; an
overview is given in Table 35.
Note: BGVfp
The resolution of the BGVfp bits changes in 2Fh and xFv
modes. In 2Fh and 1Fv modes the vertical resolution is
2 lines/field/step on 1Fh base. In 2Fh and 2Fv modes the
vertical resolution is 2 lines/field/step on 2Fh base.
SAB9079HS
SFld
(1:0)
(2:0)
2000 Jan 1341
Page 42
Philips SemiconductorsPreliminary specification
Multistandard Picture-In-Picture (PIP)
SAB9079HS
controller
Table 35 Overview of algorithm selection
MODED2FHYUVFilterD2FVABMode
No filter000H−00H
UV 1 : 1 V filter001H000H
Y 1 : 1 V filter010H000H
YUV 1 : 1 V filter011H000H
2FH/1FV frame1xxH000H
2FH/1FV proscan1xxH001H
2FH/1FV line doubling1xxH010H
not valid1xxH011H
2FH/2FV AABB100H100H
2FH/2FV ABAB100H101H
2FH/2FV AB’A’B100H110H
2FH/2FV AB’A’B+100H111H
FIELD MODE SETTINGS
In the master mode signals will be synchronized to the main 1Fh, 1Fv input signal. This eases the restrictions on the
number of fields to be stored for the scan converted main picture. Conditions to be met for a live picture are given in
Table 36.
Table 36 Master 2Fh field mode settings
VERTICAL REDUCTION
1/123except for horizontal
other modes44−
FIELDS FOR MAIN
CHANNEL
FIELDS FOR SUB
CHANNEL
REMARKS
reduction 1/1
2000 Jan 1342
Page 43
Philips SemiconductorsPreliminary specification
Multistandard Picture-In-Picture (PIP)
SAB9079HS
controller
FEATURE BOX APPLICATION 100 HZ (MASTER)
In this mode the SAB9079HS generates the display clock which is derived from the main clock and synchronization
signals. The whole system runs at one PLL. Only full screen images of the main decoder are handled. The PIP insertion
of the sub channel is not required here; see Fig.11.
handbook, full pagewidth
Y*UV (not used)
HV (not used)
Y*UV
DECODERDEFLECTION
HV
SUB
DISPLAY
Y*UV/RGB
HV
MGS831
Y*UV
HV
Fig.11 100 Hz application with ECO-100 Hz function.
DOUBLE WINDOW AND/OR OTHER PIP FUNCTIONS AT 100 HZ (MASTER)
This is the same configuration as Fig.11 but the sub channel is also needed and, therefore, a second PLL. The
constraints apply with respect to the memory use and performance. Double window PAL is only possible if bit SmlPal is
set to logic 1, this is due to the memory limitations.
handbook, full pagewidth
DECODER
DECODERDEFLECTION
Y*UV
HV
Y*UV
HV
SUB
DISPLAY
Y*UV/RGB
HV
Y*UV
HV
MGS832
Fig.12 100 Hz application with 2 channel PIP function.
DOUBLE WINDOW AND/OR OTHER PIP FUNCTIONS AT 2FH,1FV(MASTER)
For the application diagram please refer to Fig.12.
2000 Jan 1343
Page 44
Philips SemiconductorsPreliminary specification
Multistandard Picture-In-Picture (PIP)
controller
PACKAGE OUTLINE
SQFP128: plastic shrink quad flat package;
128 leads (lead length 1.6 mm); body 14 x 20 x 2.72 mm
y
102
103
X
SAB9079HS
SOT387-3
c
65
64
A
pin 1 index
128
1
w M
b
e
DIMENSIONS (mm are the original dimensions)
A
A
UNIT
mm
max.
3.40
1
min.
A2A3b
2.90
2.50
p
D
H
D
cE
p
0.27
0.17
0.23
0.11
0.250.25
39
38
0510 mm
scale
(1)
D
20.1
19.9
(1)
eH
H
14.1
13.9
0.50
23.35
23.05
D
e
w M
b
p
v M
B
v M
E
17.35
17.05
H
E
E
A
B
LL
p
1.03
0.73
A
2
A
0.080.201.600.08
A
1
ywvθ
detail X
7°
0°
(A )
3
θ
L
p
L
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT387-3
IEC JEDEC EIAJ
REFERENCES
2000 Jan 1344
EUROPEAN
PROJECTION
ISSUE DATE
98-03-27
Page 45
Philips SemiconductorsPreliminary specification
Multistandard Picture-In-Picture (PIP)
controller
SOLDERING
Introduction to soldering surface mount packages
Thistextgives a very brief insight to a complextechnology.
A more in-depth account of soldering ICs can be found in
our
“Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface
mount IC packages. Wavesoldering is notalways suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
tothe printed-circuit board by screenprinting,stencilling or
pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling)vary
between 100 and 200 seconds depending on heating
method.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
SAB9079HS
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
• Forpackageswithleadson four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement and before soldering, thepackage must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Manual soldering
Wave soldering
Conventional single wave soldering is not recommended
forsurfacemountdevices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
2000 Jan 1345
Page 46
Philips SemiconductorsPreliminary specification
Multistandard Picture-In-Picture (PIP)
SAB9079HS
controller
Suitability of surface mount IC packages for wave and reflow soldering methods
PACKAGE
BGA, SQFPnot suitablesuitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
, SO, SOJsuitablesuitable
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
The package footprint must incorporate solder thieves downstream and at the side corners.
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
Objective specificationThis data sheet contains target or goal specifications for product development.
Preliminary specificationThis data sheet contains preliminary data; supplementary data may be published later.
Product specificationThis data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I
Purchase of Philips I
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
2
C COMPONENTS
2
C components conveys a license under the Philips’ I2C patent to use the
2000 Jan 1347
Page 48
Philips Semiconductors – a w orldwide compan y
Argentina: see South America
Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140,
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 3341 299, Fax.+381 11 3342 553
For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
2000
Internet: http://www.semiconductors.philips.com
69
Printed in The Netherlands545004/50/01/pp48 Date of release: 2000 Jan 13Document order number: 9397 750 05258
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