Preliminary specification
File under Integrated Circuits, IC02
Philips Semiconductors
February 1995
Page 2
Philips SemiconductorsPreliminary specification
Picture-in-Picture (PIP) controller for NTSCSAB9075H
FEATURES
Display
• One or two live pictures can be displayed
simultaneously
• Wide range of multi-Picture-In-Picture (PIP) modes
available
• Six 6-bit Analog-to-Digital Converters (ADC) with
clamping circuit
• Enhanced vertical resolution at most modes for live
pictures
• Two Phase-Locked-Loops (PLL) with Voltage
Controlled Oscillator (VCO) to generate the line-locked
clocks
• Three 7-bit Digital-to-Analog Converters (DAC)
• 4:1:1 data format
• Data reduction factors 1 to 4, 1 to 9 and 1 to 16.
2
I
C-bus programmable
• Different single, double and multi-PIP modes can be set
• Several aspect ratios can be handled
• Reduction factors can be set automatically and
manually
• Selection of vertical filtering type
• Freeze of live pictures
• Single-PIP display position, four corners on-screen
• Multi-PIP display position, left or right on-screen
• Fine tuned display position, H (6-bit), V (6-bit)
• Fine tuned acquisition area, H (4-bit), V (4-bit)
• Channel-border and live PIP selectable
• Eight main-border, sub-border, channel-border and
background colours selectable
• Border and background brightness adjustable, 30%,
50%, 70% and 100% IRE
• Several types of decoder input signals can be set
• 6-bit HUE and SAT signals (0 to 5 V) adjustable by
I2C-bus
• Main and sub-audio mute controllable by I2C-bus.
GENERAL DESCRIPTION
The SAB9075H is a picture-in-picture controller for the
NTSC environment in combination with the Integrated
NTSC decoder and sync processor TDA8315.
The device inserts one or two live video channels with
reduced sizes into a live video signal. All video signals are
expected to be analog baseband signals. The conversion
into the digital environment and back to the analog
environment is carried out on-chip. Internal clocks are
generated by two PLLs.
Due to the two PIP channels and a large external memory,
a wide range of PIP modes are offered. The emphasis is
put on double-PIP and multi-PIP modes. In combination
with the different border colours and some external
software the IC concept can be used as an excellent
channel selection tool.
2
Some of the I
C-bus registers are for controlling the
saturation and HUE of the colours. There are also outputs
for the mute function of main and sub-channel.
February 19952
Page 3
Philips SemiconductorsPreliminary specification
Picture-in-Picture (PIP) controller for NTSCSAB9075H
1. When using IR reflow soldering it is recommended that the Drypack instructions in the
“Quality Reference Handbook”
(order number 9398 510 63011) are followed.
QUICK REFERENCE DATA
SYMBOLPARAMETERCONDITIONSMIN.TYP.MAX.UNIT
V
I
tot
f
sys
f
loop
t
jitter
DD
supply voltageall positive supply pins4.55.05.5V
total supply currentnote 1tbf220tbfmA
system frequencynote 2−2730MHz
loop bandwidth frequency4−−kHz
short term stability timejitter during 1 line (64 µs)−−4ns
ς damping factor−0.7−−
Notes
1. Digital clocks are silent and analog bias current is zero.
2. The internal system frequencies are 1728 times the input frequency. For more detailed information about the clock
generation see Section “PLLs and clock generation”.
February 19953
Page 4
Philips SemiconductorsPreliminary specification
Picture-in-Picture (PIP) controller for NTSCSAB9075H
BLOCK DIAGRAM
refTU
refTV
refTY
bias
DAI
DAV
DAV
DAV
DBF
SCL66SDA63POR64A0
book, full pagewidth
SSA
SSD
DAVDAV
SC
WE
RAS
SSD
MV
SSD
SV
SSA
SAV
SSD
SAV
SSA
MAV
SSD
MAV
DDA
DDD
DAVDAV
AD0 to 8
DAI0 to 7
DAO0 to 7
DT
CAS
DDD
MV
DDD
SV
DDA
SAV
DDD
SAV
DDA
MAV
DDD
MAV
18DY14DU16DV19
11102021
48 to 56
26,25,30,28
41,46,37,34
2729,31,35,33
47 45 44 3236,39,40,38
72 73 98
82818990
99100 9291
98
MAIN
ACQUISITION
CLAMP AND
A/D CONVERTER
94MY96MV93
13
15
17
AND BUFFER
D/A CONVERTER
MEMORY
CONTROL
SAB9075H
97
95
87
83SY85SV88
24
DISPLAY
SUB
ACQUISITION
CLAMP AND
A/D CONVERTER
86
84
65
7565861
2
I C-BUS
6059
21
3457
79
AND PLL BLOCK
DISPLAY TIMING CONTROL
HUE AND SAT
70
69
67
78
77
7680
712374
224243
D/A CONVERTERS
68
MBE084
MTCLK
TM2
TM0
SSA
MPV
SSD
MPV
sync
MH
SSA
SPV
bias
SPI
DDD
SPV
sync
SV
SSS
V
DDD
V
VDD
2
I C
STCLK
TC
TM1
DDA
MPV
DDD
MPV
bias
MPI
DDA
SPV
sync
SH
SSD
SPV
sync
MV
Fig.1 Block diagram.
MU
bias
refB
refT
MAI
MAV
MAV
February 19954
SU
bias
SAI
refT
SAV
refB
SAV
HUE
SAT
SMUTE
MMUTE
Page 5
Philips SemiconductorsPreliminary specification
Picture-in-Picture (PIP) controller for NTSCSAB9075H
PINNING
SYMBOLPINI/OTYPEDESCRIPTION
MPV
DDA
MPV
SSA
MH
sync
MPI
bias
MPV
SSD
MTCLK6IHPP01test clock for main-channel
MPV
DDD
MV
DDD
MV
SSD
DAV
DDD
DAV
SSD
n.c.12−−not connected
DAV
refTU
DU14OE027analog U output
DAV
refTV
DV16OE027analog V output
DAV
refTY
DY18OE027analog Y output
DAI
bias
DAV
SSA
DAV
DDA
2
CV
I
DD
MV
sync
DBF24OSPF20fast blanking control output signal
DAI525IHPP01data bus input from memory; bit 5
DAI426IHPP01data bus input from memory; bit 4
SC27OOPF20memory shift clock
DAI728IHPP01data bus input from memory; bit 7
DAI029IHPP01data bus input from memory; bit 0
DAI630IHPP01data bus input from memory; bit 6
DAI131IHPP01data bus input from memory; bit 1
DT32OOPF20memory data transfer; active LOW
DAI333IHPP01data bus input from memory; bit 3
DAO734OOPF20data bus output to memory; bit 7
DAI235IHPP01data bus input from memory; bit 2
DAO036OOPF20data bus output to memory; bit 0
DAO637OOPF20data bus output to memory; bit 6
DAO338OOPF20data bus output to memory; bit 3
DAO139OOPF20data bus output to memory; bit 1
DAO240OOPF20data bus output to memory; bit 2
1I/OE030analog positive power supply for PLL main-channel
2I/OE009analog negative power supply for PLL main-channel
3IE027horizontal synchronization for main-channel
4IE027analog bias reference current for PLL main-channel
5I/OE009digital negative power supply for PLL main-channel
7I/OE030digital positive power supply for PLL main-channel
8I/OE030digital positive power supply for main-channel core
9I/OE009digital negative power supply for main-channel core
10I/OE030digital positive power supply for DACs
11I/OE009digital negative power supply for DACs
13I/OE027analog reference voltage for top U DAC
15I/OE027analog reference voltage for top V DAC
17I/OE027analog reference voltage for top Y DAC
19IE027analog bias reference current for DACs
20I/OE009analog negative power supply for DACs
21I/OE030analog positive power supply for DACs
22I/OE030positive supply for HUE and SAT decoders
23IHPP01vertical synchronization for main-channel
February 19955
Page 6
Philips SemiconductorsPreliminary specification
Picture-in-Picture (PIP) controller for NTSCSAB9075H
SYMBOLPINI/OTYPEDESCRIPTION
DAO441OOPF20data bus output to memory; bit 4
V
DDD
V
SSS
WE44OOPF20memory write enable; active LOW
CAS45OOPF20memory column address strobe; active LOW
DAO546OOPF20data bus output to memory; bit 5
RAS47OOPF20memory row address strobe; active LOW
AD048OOPF20memory address bus; bit 0
AD849OOPF20memory address bus; bit 8
AD150OOPF20memory address bus; bit 1
AD651OOPF20memory address bus; bit 6
AD252OOPF20memory address bus; bit 2
AD553OOPF20memory address bus; bit 5
AD354OOPF20memory address bus; bit 3
AD455OOPF20memory address bus; bit 4
AD756OOPF20memory address bus; bit 7
n.c.57−−not connected
TC58IHPP01test control
TM059IHPP01test mode 0
TM160IHPP01test mode 1
TM261IHPP01test mode 2
n.c.62−−not connected
POR63IHUP07power-on reset
A064IHPF01I
SCL65IHPF01shift clock for I
SDA66I/OIOI41shift I
MMUTE67OSPF20mute output for main-channel
SMUTE68OSPF20mute output for sub-channel
SAT69OE027analog output for SAT decoder
HUE70OE027analog output for HUE decoder
SV
sync
SV
SSD
SV
DDD
SPV
DDD
STCLK75IHPP01test clock for sub-channel
SPV
SSD
SPI
bias
SH
sync
SPV
SSA
SPV
DDA
SAV
DDD
42I/OE030digital positive power supply for peripherals
43I/OE009digital negative power supply for peripherals
2
C-bus address 0 selection pin
2
C-bus
2
C-bus input data; acknowledge I2C-bus output data
71IHPP01vertical synchronization for sub-channel
72I/OE009digital negative power supply for sub-channel core
73I/OE030digital positive power supply for sub-channel core
74I/OE030digital positive power supply for PLL sub-channel
76I/OE009digital negative power supply for PLL sub-channel
77IE027analog bias reference current for PLL sub-channel
78IE027horizontal synchronization for sub-channel
79I/OE009analog negative power supply for PLL sub-channel
80I/OE030analog positive power supply for PLL sub-channel
81I/OE030digital positive power supply for ADC sub-channel
February 19956
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Philips SemiconductorsPreliminary specification
Picture-in-Picture (PIP) controller for NTSCSAB9075H
SYMBOLPINI/OTYPEDESCRIPTION
SAV
SSD
SU83IE027analog U input for sub-channel
SAV
refB
SV85IE027analog V input for sub-channel
SAV
refT
SY87IE027analog Y input for sub-channel
SAI
bias
SAV
SSA
SAV
DDA
MAV
DDA
MAV
SSA
MAI
bias
MU94IE027analog U input for main-channel
MAV
refB
MV96IE027analog V input for main-channel
MAV
refT
MY98IE027analog Y input for main-channel
MAV
SSD
MAV
DDD
82I/OE009digital negative power supply for ADC sub-channel
84I/OE027analog reference voltage for bottom ADC sub-channel
86I/OE027analog reference voltage for top ADC sub-channel
88IE027analog bias reference current for ADC sub-channel
89I/OE009analog negative power supply for ADC sub-channel
90I/OE030analog positive power supply for ADC sub-channel
91I/OE030analog positive power supply for ADC main-channel
92I/OE009analog negative power supply for ADC main-channel
93IE027analog bias reference current for ADC main-channel
95I/OE027analog reference voltage for bottom ADC main-channel
97I/OE027analog reference voltage for top ADC main-channel
99I/OE009digital negative power supply for ADC main-channel
100I/OE030digital positive power supply for ADC main-channel
Table 1Pin type explanation
PIN TYPEDESCRIPTION
E030V
E009VSSpin; diode to V
E027analog input pin; diode to VDD and V
HPF01digital input pin; CMOS levels, diode to V
HPP01digital input pin; CMOS levels, diode to VDD and V
pin; diode to V
DD
SS
DD
SS
SS
SS
HUP07digital input pin; CMOS levels with hysteresis, pull up resistor to VDD, diode to VDD and V
IOI41I2C-bus pull-down output stage; CMOS input levels
OPF20digital output pin
SPF20digital output pin; slew rate controlled
SS
February 19957
Page 8
Philips SemiconductorsPreliminary specification
Picture-in-Picture (PIP) controller for NTSCSAB9075H
SSS
DDD
V
DAO4
DAO2
DAO1
DAO3
DAO6
DAO0
DAI2
DAO7
DAI3DTDAI1
32
33
34
35
36
37
38
39
40
41
42
43
44
SAB9075H
MBE083
31
DAI6
30
DAI0
29
DAI7
28
SC
27
DAI4
26
DAI5
25
DBF
24
sync
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DD
DY
DV
DU
n.c.
DDA
SSA
bias
refTY
refTV
refTU
SSD
DDD
SSD
DDD
DDD
SSD
bias
sync
SSA
DDA
MV
I C V
2
DAV
DAV
DAI
DAV
DAV
DAV
DAV
DAV
MV
MV
MPV
MTCLK
MPV
MPI
MH
MPV
MPV
Fig.2 Pin configuration.
sync
SSD
DDD
DDD
SSD
bias
sync
SSA
DDA
AD6
51
AD2
52
53
AD5
54
AD3
AD4
55
AD7
56
57
n.c.
58
TC
TM0
59
TM1
60
61
TM2
62
n.c.
63 POR
64 A0
65
SCL
66 SDA
67 MMUTE
SMUTE
68
69
SAT
70
HUE
71
SV
72
SV
73
SV
74
SPV
75 STCLK
76
SPV
77
SPI
78
SH
79
SPV
80
SPV
50 AD1
AD8
49
AD0
48
RAS
47
DAO5
46
CASWEV
45
90
89
88
87
86
85
84
83
82
81
SY
SV
DDD
SAV
SSD
SAV
SU
refB
SAV
refT
SAV
bias
SAI
SSA
SAV
DDA
SAV
February 19958
91
DDA
MAV
92
SSA
MAV
93
bias
MAI
94
MU
95
refB
MAV
96
MV
97
refT
MAV
98
MY
99
SSD
MAV
100
DDD
MAV
Page 9
Philips SemiconductorsPreliminary specification
Picture-in-Picture (PIP) controller for NTSCSAB9075H
FUNCTIONAL DESCRIPTION
Acquisition area
The acquisition area is in the centre of the visible screen
area. Vertically 228 lines are sampled. Horizontally
672 Y-pixels are processed. The exact active processing
area can be fine tuned in horizontal (2 pixels/steps,
16 steps) and vertical (1 line/step, 16 steps) direction for
both main and sub-channel by the I
2
C-bus (see Fig.3). The
given numbers are pixel numbers at a 13.5 MHz data rate.
The signals, which are dependent on the I2C-bus registers,
can also be related to the H
, in which event they are
sync
delayed by 68 pixels.
Chrominance format
The chrominance format is 4:1:1.
The YUV signals are sampled at a rate of 27 MHz and then
filtered and subsampled to a data rate of 13.5 MHz.
handbook, full pagewidth
clamp
H
sync
32
68
It is expected that the input signals do not contain
frequencies outside the video bandwidth (Y
= 4.5 MHz;
BW
UBWand VBW= 1.125 MHz).
Display area
The display area is shown in Fig.4. The given numbers are
pixels at a data rate of 13.5 MHz. The signals are related
to the burstkey and the V
registers the signals can also be related to the H
. Dependent on the I2C-bus
sync
sync
.
The internal 13.5 MHz data rate is upsampled to the
double frequency (27 MHz) and then fed to the DACs.
2
The display output can be fine positioned by the I
C-bus in
64 steps of 4 pixels in horizontal direction and 64 steps of
1 line/field in vertical direction.
864
burstkey
sync
80 FT
104 FTV
18 FT
228262.5
18 FT
672
624
1/1, 1/3 and 1/4 reduction
1/2 reduction
MBE085
Fig.3 Acquisition area.
February 19959
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Philips SemiconductorsPreliminary specification
Picture-in-Picture (PIP) controller for NTSCSAB9075H
handbook, full pagewidth
H
sync
burstkey
V
sync
68864
36 FT
672
11 FT
228262.5
11 FT
MBE086
Fig.4 Display area.
February 199510
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Philips SemiconductorsPreliminary specification
Picture-in-Picture (PIP) controller for NTSCSAB9075H
PIP modes
The controller contains two independent acquisition-channels which provide the scaling factors to support the range of
different modes. With the external memory of 2 Mbit it is possible to select between single, double and multi-PIP modes.
Table 2 gives an overview of the different PIP modes.
Table 2PIP modes
SUB SIZE
(1)
MODESUBMAIN
PIXELSREDUCTION
4 : 3 main +4:3 subto 4:3screen or 16 : 9 main + 16 : 9 sub to 16 : 9 screen
1. The given sub/main sizes are visible PIP sizes, a border is drawn around these PIPs and does not influence these
sizes. The size of the border is 4 pixels wide and 2 lines/fields high.
2. The SAB9075H can be set in automatic mode in which the reduction factors are automatically set by the mode select
and aspect ratio select bits of the I
2
C-bus. If the automatic mode is switched OFF the reduction factors can be set
manually. This will give more flexibility to adjust the aspect ratios of incoming signals.
PIP positions
The positions are graphically depicted in Figs 5 to 17.
February 199511
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Philips SemiconductorsPreliminary specification
Picture-in-Picture (PIP) controller for NTSCSAB9075H
handbook, full pagewidth
burstkey
V
sync
11 FT
11
57
92
57
11
36 FT
288
S
Fig.5 Single-PIP, size1⁄16(mode SPS).
672
2416824168
228
MBE087
handbook, full pagewidth
burstkey
V
sync
11 FT
11
76
54
76
11
36 FT
24
224
176
S
Fig.6 Single-PIP, size1⁄9(mode SPL).
February 199512
672
224
24
228
MBE088
Page 13
Philips SemiconductorsPreliminary specification
Picture-in-Picture (PIP) controller for NTSCSAB9075H
handbook, full pagewidth
burstkey
V
sync
11 FT
58
112
58
36 FT
672
24
312
312
SM
24
228
MBE089
Fig.7 Double-PIP, size1⁄16(mode DP).
handbook, full pagewidth
burstkey
V
sync
11 FT
24
57
5
57
5
57
23
36 FT
C0
C1
C2
Fig.8 Multi PIP, 3 × sub1⁄16(mode MP3).
February 199513
672
264
3616836168
228
MBE090
Page 14
Philips SemiconductorsPreliminary specification
Picture-in-Picture (PIP) controller for NTSCSAB9075H
Fig.14 Single-PIP, 4 : 3 sub to 16 : 9 screen (mode SPS).
February 199516
288
672
168
24
228
MBE097
Page 17
Philips SemiconductorsPreliminary specification
Picture-in-Picture (PIP) controller for NTSCSAB9075H
handbook, full pagewidth
burstkey
V
sync
11 FT
11
57
92
57
11
36 FT
672
176
S
Fig.15 Single-PIP, 16 : 9 sub to 4 : 3 screen (mode SPS).
2422424224
228
MBE096
handbook, full pagewidth
burstkey
V
sync
11 FT
11
76
54
76
11
36 FT
24
312
S
Fig.16 Single-PIP, 16 : 9 sub to 4 : 3 screen (mode SPL).
February 199517
672
312
24
228
MBE098
Page 18
Philips SemiconductorsPreliminary specification
Picture-in-Picture (PIP) controller for NTSCSAB9075H
handbook, full pagewidth
burstkey
V
sync
36 FT
696
11 FT
238
MBE099
Fig.17 Factory mode.
February 199518
Page 19
Philips SemiconductorsPreliminary specification
Picture-in-Picture (PIP) controller for NTSCSAB9075H
2
I
I2C-bus
The I2C-bus provides bi-directional 2-line communication
between different ICs. The SDA line is the Serial Data line
and the SCL serves as Serial Clock Line. Both lines must
be connected to a positive supply via a pull-up resistor
when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
The SAB9075H has the I2C-bus addresses 2C and 2E,
switchable by the pin A0. Valid subaddresses are
00H to 0FH.
C-bus control is in accordance with the I2C-bus protocol.
First a start sequence must be put on the I2C-bus, then the
I2C-bus address 2C or 2E, followed by a subaddress
00 to 0F. After this sequence, the data of the subaddress
must be sent. An auto-increment function then gives the
option ‘send data’ of the incremented subaddresses until a
stop sequence has been given.
Notes
1. Table 3 gives an overview of the I2C-bus addresses. They will be explained in more detail in the following pages.
2. Some address spaces are unused but already implemented for future functionality.
February 199519
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Philips SemiconductorsPreliminary specification
Picture-in-Picture (PIP) controller for NTSCSAB9075H
1. With PIPON in OFF mode the fast blanking signal is made inactive. All other functions will operate as if the circuit
were in operational mode.
2. With MANRED set to logic 0 the reduction factors will be set automatically, dependent on the PIP mode and the
aspect ratio bits of main and sub (bits 5 and 4). Table 4 indicates which bits should be set to obtain a certain PIP
mode.
3. With MANRED set to logic 1 the calculation of the reduction factors is not carried out and should be set by Register 4
(see Table 9). Only combinations with MANRED set to logic 0 are guaranteed.
4. MASPECT and SASPECT are used in automatic mode (MANRED) to indicate the type of input signals, together with
MODE the PIP mode can be set (see Table 4). In manual mode these bits are ignored.
5. The MODE bits set the PIP mode. For the multi-PIP modes the frozen PIPs are set to the 30% grey colour. Once a
PIP has been made live it will always display the last video data.
1. HPOS and VPOS determine the general location of the sub-PIP on the screen. HPOS only operates in modes SPS,
SPL, DP, MP3 and MP4. VPOS only operates in modes SPS and SPL. The default location of the sub-pictures will
be left top.
2. MFREEZE will freeze the main-picture, and SFREEZE will freeze the sub-picture selected by the live select bits as
in Register 8 (see Table 13).
3. BCOLPOL can invert the border polarity of U and V.
4. MVFILT and SVFILT set the type of vertical filtering for the main and sub-channel. Mode 1 means that diagonal lines
are linearized, in Mode 0 this option is switched OFF. This filtering mode only operates with vertical reduction
1
factors
⁄3 and1⁄4.
February 199521
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Philips SemiconductorsPreliminary specification
Picture-in-Picture (PIP) controller for NTSCSAB9075H
Table 7Register2; display horizontal fine position register
BITMODEDESCRIPTION
7−not used
6−not used
5DHFP(5)horizontal fine position (64 steps)
4DHFP(4)horizontal fine position
3DHFP(3)horizontal fine position
2DHFP(2)horizontal fine position
1DHFP(1)horizontal fine position
0DHFP(0)horizontal fine position
Note
1. The display position can be set in steps of 4 pixels/lines and 1 line/field. The offsets on the display position are
depicted in Fig.4.
Table 8Register3; display vertical fine position register
BITMODEDESCRIPTION
7−not used
6−not used
5DVFP(5)vertical fine position (64 steps)
4DVFP(4)vertical fine position
3DVFP(3)vertical fine position
2DVFP(2)vertical fine position
1DVFP(1)vertical fine position
0DVFP(0)vertical fine position
(1)
(1)
Note
1. The display position can be set in steps of 4 pixels/lines and 1 line/field. The offsets on the display position are
depicted in Fig.4.
Picture-in-Picture (PIP) controller for NTSCSAB9075H
Table 10 Register 5; channel select register
BITMODEDESCRIPTION
7−not used
(1)
6CBSEL(2)
5CBSEL(1)
4CBSEL(0)
3−not used
2SLSEL(2)
1SLSEL(1)
0SLSEL(0)
Notes
1. With CBSEL one border of the displayed sub-borders can be selected independently of the SLSEL. This only
operates when the channel select-border is ON as in Register 8 (see Table 13) and when the selected channel
number is displayed.
2. With SLSEL the active sub-live picture can be selected. This only operates when the SFREEZE is OFF as in
Register 1 (see Table 6) and when the selected channel is displayed.
channel-border select (maximum 8 channels)
(1)
channel-border select
(1)
channel-border select
(2)
sub-live select (maximum 8 channels)
(2)
sub-live select
(2)
sub-live select
Background and main, sub and channel-border
colour and brightness handling
Registers 6 to 9 (see Tables 11 to 14) handle background
and main, sub and channel-border colour and brightness.
The borders and background can be set ON and OFF.
Background, main and sub-borders are black when they
are OFF. The channel-border gets the current sub-border
colour when it is switched OFF. The brightness can be set
in 4 steps (30%, 50%, 70% and 100%). Eight different
colours can be set in accordance with Table 15.
Table 11 Register 6; main-border control register
BITMODEDESCRIPTION
7−not used
6MB0Nlogic 0 = MB is OFF; logic 1 =MB is ON
5MBBRT(1)main-border brightness (4 steps)
4MBBRT(0)main-border brightness
3−not used
2MBCOL(2)main-border colour (8 colours)
1MBCOL(1)main-border colour
0MBCOL(0)main-border colour
February 199523
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Philips SemiconductorsPreliminary specification
Picture-in-Picture (PIP) controller for NTSCSAB9075H
Table 12 Register 7; sub-border control register
BITMODEDESCRIPTION
7−not used
6SBONlogic 0 = SB is OFF; logic 1 = SB is ON
5SBBRT(1)sub-border brightness (4 steps)
4SBBRT(0)sub-border brightness
3−not used
2SBCOL(2)sub-border colour (8 colours)
1SBCOL(1)sub-border colour
0SBCOL(0)sub-border colour
Table 13 Register 8; channel-border control register
BITMODEDESCRIPTION
7−not used
6CBONlogic 0 = CB is OFF; logic 1 = CB is ON
5CBBRT(1)channel-border brightness (4 steps)
4CBBRT(0)channel-border brightness
3−not used
2CBCOL(2)channel-border colour (8 colours)
1CBCOL(1)channel-border colour
0CBCOL(0)channel-border colour
Table 14 Register 9; background control register
BITMODEDESCRIPTION
(1)
7FACMODE
6BGONlogic 0 = BG is OFF; logic 1 = BG is ON
5BGBRT(1)background brightness (4 steps)
4BGBRT(0)background brightness
3−not used
2BGCOL(2)background colour (8 colours)
1BGCOL(1)background colour
0BGCOL(0)background colour
Note
1. The FACMODE bit controls the factory mode which shows an enlarged background colour as depicted in Fig.17
(BGON must be set).
logic 0 = FM is OFF; logic 1 = FM is ON
February 199524
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Philips SemiconductorsPreliminary specification
Picture-in-Picture (PIP) controller for NTSCSAB9075H
signal or the burstkey is used as internal horizontal
sync
sync
will
The exact timing of the V
in relation to the H
sync
sync
reference pulse is depicted in Fig.18. A field identification
window determines whether a V
is being handled as a
sync
1st field or a 2nd field. This field identification window can
be inverted by the FPOL bit. If FPOL is logic 0 and an
handbook, full pagewidth
H (external)
sync
field ID (internal)
(number of pixels)
V (external)
sync
V (external)
sync
2nd field
Fig.18 V
timing and field identification.
sync
active edge of the V
occurs when the F-ID signal is
sync
logic 0, it will be regarded as the 1st field. If FPOL is logic 0
and an active edge of the V
occurs when the F-ID
sync
signal is logic 1, it will be regarded as the 2nd field. If FPOL
is logic 1 the 1st and 2nd field IDs are changed over.
43238943
1st field
MBE100
February 199526
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Philips SemiconductorsPreliminary specification
Picture-in-Picture (PIP) controller for NTSCSAB9075H
Table 18 Register B; main-acquisition area fine position
BITMODEDESCRIPTION
7MAAHFP(3)main-acquisition area horizontal fine position
6MAAHFP(2)main-acquisition area horizontal fine position
5MAAHFP(1)main-acquisition area horizontal fine position
4MAAHFP(0)main-acquisition area horizontal fine position
(2)
3MAAVFP(3)
2MAAVFP(2)
1MAAVFP(1)
0MAAVFP(0)
main-acquisition area vertical fine position
(2)
main-acquisition area vertical fine position
(2)
main-acquisition area vertical fine position
(2)
main-acquisition area vertical fine position
Notes
1. The acquisition area can be adjusted in 16 steps of 2 pixels horizontally and 1 line/field vertically.
2. With MAAVFP a complete field must have been processed before the next V
non-standard signals.
(1)
occurs. This is relevant for
sync
Table 19 Register C; sub-acquisition area fine position
BITMODEDESCRIPTION
(1)
7SAAHFP(3)sub-acquisition area horizontal fine position
6SAAHFP(2)sub-acquisition area horizontal fine position
5SAAHFP(1)sub-acquisition area horizontal fine position
4SAAHFP(0)sub-acquisition area horizontal fine position
(2)
3SAAVFP(3)
2SAAVFP(2)
1SAAVFP(1)
0SAAVFP(0)
sub-acquisition area vertical fine position
(2)
sub-acquisition area vertical fine position
(2)
sub-acquisition area vertical fine position
(2)
sub-acquisition area vertical fine position
Notes
1. The acquisition area can be adjusted in 16 steps of 2 pixels horizontally and 1 line/field vertically.
2. With SAAVFP a complete field must have been processed before the next V
occurs. This is relevant for
sync
non-standard signals.
February 199527
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Philips SemiconductorsPreliminary specification
Picture-in-Picture (PIP) controller for NTSCSAB9075H
Auxiliary registers
The Auxiliary Registers D to F (see Tables 20 to 22) are implemented to generate I2C-bus controlled signals for circuits
which do not have an on-board I2C-bus.
Table 20 Register D; Auxiliary Control Register 1
BITMODEDESCRIPTION
7−not used
6−not used
5HUE(5)hue control (output pin HUE)
4HUE(4)hue control
3HUE(3)hue control
2HUE(2)hue control
1HUE(1)hue control
0HUE(0)hue control
Table 21 Register E; Auxiliary Control Register 2
BITMODEDESCRIPTION
7−not used
6−not used
5SAT(5)saturation control (output pin SAT)
4SAT(4)saturation control
3SAT(3)saturation control
2SAT(2)saturation control
1SAT(1)saturation control
0SAT(0)saturation control
Table 22 Register F; Auxiliary Control Register 3
BITMODEDESCRIPTION
7MMUTEdata bit directly to output pin MMUTE
6SMUTEdata bit directly to output pin SMUTE
5−not used
4−not used
3−not used
2−not used
1−not used
0−not used
February 199528
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Philips SemiconductorsPreliminary specification
Picture-in-Picture (PIP) controller for NTSCSAB9075H
External memory
For the external memory two VDRAMS of type Mitsubishi
M5442256 are used. They have a storage capacity of
262144 words of 4-bit each and will be used in parallel.
An overview of the timing to the VDRAM is depicted in
Fig.19. Three different timing modes are shown. If the
SAB9075 is not in one of these three modes, it is in idle
mode in which all the control signals are HIGH. An idle
mode takes at least 4 clock periods. Switching from one
mode to another is always carried out via this idle mode.
The clock signal shown is an internal clock derived from
the PLLs and is approximately 27 MHz.
Main and sub-ADCs
Both main and sub-channels convert the analog input
signals to digital signals by three ADCs for each channel.
The input levels of the ADCs are equal and can set by the
MAV
refT
, SAV
refT
, MAV
, and SAV
refB
refB
pins.The
reference levels are made internally by a resistor network
which divides the analog VDD to a default set of preferred
signal levels of 1.5 V. If the application requires a different
set of levels the internal resistors can be shunted. External
capacitors are required to filter AC components on the
reference levels.
The resolution of the ADCs is 6-bit and the sampling is
carried out at the system frequency of 27 MHz. The
bias current I
is made internally but can be increased or
bias
decreased.
Output DACs
The digital processed signals are converted to analog
signals by means of three DACs. The output voltages of
these DACs are default set by the DAV
DAV
pins for the TOP-levels. Default signal levels are
refTY
refTU
, DAV
refTV
and
1.5 V. The output buffer after each DAC is a PMOS source
follower.
For more information see chapter “Test and application
information”.
HUE and SAT DACs
The HUE and SAT DACs are resistor DACs based on a
R2R network. They have a direct control from their I
2
C-bus
register and therefore their sample frequency is limited by
the I2C-bus frequency. The output voltage is linear with the
I2CVDD. Therefore the VDD of this block is a separate pin.
PLLs and clock generation
The SAB9075H has two PLLs on-board, one for the subchannel and one for the main-channel and the display part.
The PLLs lock to the input signals MH
sync
and SH
sync
. The
internal clock frequency is 1728 times higher which is
approximately 27 MHz in a standard NTSC system.
The positive edges of the H
signals are the driving
sync
timing points. For good short term stability they have to be
noise/jitter free.
The inputs should be AC-coupled and an internal clamping
circuit will clamp the input to MAV
for the chrominance channels. The clamping starts at the
active edge of the burstkey.
For more information see chapter “Test and application
information”.
February 199529
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Philips SemiconductorsPreliminary specification
Picture-in-Picture (PIP) controller for NTSCSAB9075H
handbook, full pagewidth
CLOCK
RAS
CAS
CLOCK
RAS
CAS
AD0 to AD8
WE
DAI0 to DAI7
refresh cycle
ROWCOLUMNCOLUMNCOLUMNCOLUMNCOLUMN
write cycle (SUB or MAIN)
CLOCK
RAS
CAS
AD0 to AD8
WE
DT
SC
DAO0 to DAO7
ROWCOLUMN
read cycle
Fig.19 VDRAM timing.
SC cycles
MBE101
February 199530
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Philips SemiconductorsPreliminary specification
Picture-in-Picture (PIP) controller for NTSCSAB9075H
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134)
SYMBOLPARAMETERMIN.MAX.UNIT
V
DD
∆V
DD
T
stg
T
amb
V
esd
P
tot
THERMAL CHARACTERISTICS
SYMBOL PARAMETERVALUE UNIT
R
thj-a
supply voltage−0.5+6.5V
supply voltage variation−0.2V
storage temperature−25+150°C
operating ambient temperature070°C
electrostatic discharge handling−−V
total power dissipation−1.5W
thermal resistance from junction to ambient in free air38K/W
QUALITY SPECIFICATION
In accordance with SNW-FQ-611, Part E, dated 14 December 1992.
February 199531
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Philips SemiconductorsPreliminary specification
Picture-in-Picture (PIP) controller for NTSCSAB9075H
CHARACTERISTICS
V
= 5.0 V; T
DD
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supplies
V
DD
V
SS
∆V
DD
∆V
SS
I
DDQ
MPIV
DDA
SPIV
DDA
MAIV
DDA
SAIV
DDA
DIV
DDA
2
CV
I
DD
I
tot
Converter and clamping
AV
refT
AV
refB
Rin
ref
V
I
V
i
R
i
R
iY
R
iV
R
iU
C
i
Resresolution−6−bit
f
s
DNLdifferential non-linearity−1.0−+1.0LSB
INLintegral non-linearity−1.0−+1.0LSB
V
os
α
cs
PSRRpower supply rejection ratiotbf40−dB
=25°C; unless otherwise specified.
amb
positive supply voltage4.55.05.5V
negative supply voltage−0−V
maximum voltage difference between
−0100mV
all positive supply pins
maximum voltage difference between
−0100mV
all negative supply pins
quiescent current digital positive
note 1−2tbfµA
supply pins
supply current PLL main−2.5tbfmA
supply current PLL sub−2.5tbfmA
supply current 3 main-ADCs−36tbfmA
supply current 3 sub-ADCs−36tbfmA
supply current 3 display DACs−18tbfmA
supply current HUE and SAT DACsnote 2−2.55mA
total supply currenttbf220tbfmA
top reference voltagenote 31.01.92.0V
bottom reference voltagenote 300.41.0V
input resistance V
DC input voltageV
refT
to V
refB
note 3; 1 ADCtbf860tbfΩ
refB
−V
refT
V
AC input voltage (peak-to-peak value)1.01.5−V
input resistanceclamping OFF1−−MΩ
input resistance for Y channelclamping ON−200−Ω
input resistance for V channelclamping ON−800−Ω
input resistance for U channelclamping ON−800−Ω
input capacitance−15−pF
1. Digital clocks are silent and analog bias current is zero.
2. The HUE and SAT DACs are based on a R2R ladder network as describe in the section “HUE and SAT DACs”. The
maximum output sample frequency is determined by the I2C-bus.
3. The input configuration of the ADCs is depicted in Fig.20. The minimum difference AV
refT
− AV
should be larger
refB
than 1.0 V. The reference voltages can be calculated as follows:
1.9
V
refT
×V=V
AV
DD
------- -
5.0
;
refB
AV
DD
0.4
×V=
------- -
5.0
4. The internal system frequencies are 1728 times the input frequency. For more detailed information about the clock
generation see section “PLLs and clock generation”.
February 199533
Page 34
Philips SemiconductorsPreliminary specification
Picture-in-Picture (PIP) controller for NTSCSAB9075H
system frequencynote 1−2730MHz
rise timeVDD= 4.5 V−625ns
fall timeVDD= 4.5 V−625ns
Note
1. The internal system frequencies are 1728 times the input frequency. For more detailed information about the clock
generation see section “PLLs and clock generation”.
February 199534
Page 35
Philips SemiconductorsPreliminary specification
Picture-in-Picture (PIP) controller for NTSCSAB9075H
TEST AND APPLICATION INFORMATION
Fig.20 shows how the ADCs and the DACs can be
connected in the application.
The generation of the reference voltages is carried out
internally and they have to be externally decoupled for AC
signals.
For all ADCs and DACs the internal resistor division is
such that a maximum signal voltage level of 1.5 V is
obtained. For the ADCs there is a DC offset voltage of
0.4 V.
handbook, full pagewidth
MAV
MAV
DDA
refT
MY
MU
R
top
ADC
ADC
A modification of these reference voltages can be
achieved by external shunting.
The ADC reference voltages are the same for all Y/U/V
channels which means that their input levels need to be
the same. The DAC voltage references can be set
separately for Y/U/V channels. These reference voltages
can be modified by shunting.
The output buffers of the DACS are PMOS source
followers with a minimum output load of 10 kΩ.
DAV
DAV
DAV
DAV
DDA
refTY
refTU
refTV
3R
top
MAV
MAV
SAV
SAV
SAV
SAV
MV
refB
SSA
DDA
refT
SY
SU
SV
refB
SSA
ADC
R
R
top
ADC
ADC
ADC
R
bottom
bottom
VIDEO
SIGNAL
PROCESSING
DAC
DAC
DAC
MGC001
Fig.20 Analog application diagram ADCs and DACs.
DY
DU
DV
DAV
SSA
February 199535
Page 36
Philips SemiconductorsPreliminary specification
Picture-in-Picture (PIP) controller for NTSCSAB9075H
handbook, full pagewidth
TMS44C250TMS44C250
5 V
5 V
5 V
5 V
5 V
MPI
MPV
MPV
MPV
MPV
SPI
SPV
SPV
SPV
SPV
SAV
SAV
bias
DDA
SSA
DDD
SSD
bias
DDA
SSA
DDD
SSD
DDD
SSD
94444
5 V
SSS
DDD
V
V
AD0 to AD8
SSA
DDA
bias
SAI
SAV
SAV
5 V
DAI4 to DAI7
DAO4 to DAO7
SAV
DAI0 to DAI3
DAO0 to DAO3
refT
refB
sync
SAV
SV
SH
sync
SC
SY
CAS
SU
WE
RAS
SAB9075H
SV
HUE
DT
SAT
2
STCLK
MTCLK
DD
SMUTE
I CV
5 V
mute output
main-channel
TC
TM0
MY
MMUTE
mute output
sub-channel
TM1
TM2
MU
5 V
DDD
SV
MV
SSD
SV
sync
MH
5 V
DDD
MV
sync
MV
0 V or 5 V
SSD
POR
MV
refB
refT
MAV
MAV
A0
SSA
MAV
SCL
DAV
DAV
DAV
DDA
MAV
5 V
SDA
DAI
DAV
DAV
DAV
DAV
MAV
MAV
bias
MAI
bias
DDA
SSA
refTY
refTU
refTV
DBF
DY
DU
DV
DDD
SSD
DDD
SSD
MGC053
SCL
SDA
5 V
fast blanking
control output
analog Y output
analog U output
analog V output
5 V
5 V
Y
U
V
SAT
VOUT
HOUT
HUE
TDA8315T
CVBS/Y sub-channel inputCVBS/Y main-channel input
Fig.21 Application diagram.
February 199536
SAT
HUE
Y U V
TDA8315T
CVBS/Y CVBS/Y
VOUT
HOUT
Page 37
Philips SemiconductorsPreliminary specification
Picture-in-Picture (PIP) controller for NTSCSAB9075H
PACKAGE OUTLINE
QFP100: plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
c
y
X
E
e
w M
p
A
A
H
E
E
2
A
A
1
8051
81
pin 1 index
100
1
50
Z
b
31
30
detail X
Q
L
p
L
SOT317-2
(A )
3
θ
w M
b
e
p
Z
D
D
H
D
0510 mm
scale
DIMENSIONS (mm are the original dimensions)
mm
A
max.
3.20
0.25
0.05
2.90
2.65
0.25
UNITA1A2A3b
cE
p
0.40
0.25
0.25
0.14
(1)
(1)(1)(1)
D
20.1
19.9
eH
14.1
13.9
0.65
24.2
23.6
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
IEC JEDEC EIAJ
REFERENCES
SOT317-2
February 199537
H
D
v M
A
B
v M
B
LLpQZywv θ
E
18.2
17.6
1.0
0.6
1.4
1.2
0.150.10.21.95
EUROPEAN
PROJECTION
Z
D
0.8
1.0
0.4
0.6
ISSUE DATE
E
o
7
o
0
92-11-17
95-02-04
Page 38
Philips SemiconductorsPreliminary specification
Picture-in-Picture (PIP) controller for NTSCSAB9075H
SOLDERING
Plastic quad flat-packs
YWAVE
B
During placement and before soldering, the component
must be fixed with a droplet of adhesive. After curing the
adhesive, the component can be soldered. The adhesive
can be applied by screen printing, pin transfer or syringe
dispensing.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder bath is
10 s, if allowed to cool to less than 150 °C within 6 s.
Typical dwell time is 4 s at 250 °C.
A modified wave soldering technique is recommended
using two solder waves (dual-wave), in which a turbulent
wave with high upward pressure is followed by a smooth
laminar wave. Using a mildly-activated flux eliminates the
need for removal of corrosive residues in most
applications.
Y SOLDER PASTE REFLOW
B
Reflow soldering requires the solder paste (a suspension
of fine solder particles, flux and binding agent) to be
applied to the substrate by screen printing, stencilling or
pressure-syringe dispensing before device placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt, infrared, and
vapour-phase reflow. Dwell times vary between 50 and
300 s according to method. Typical reflow temperatures
range from 215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 min at 45 °C.
EPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING
R
IRON OR PULSE
-HEATED SOLDER TOOL)
Fix the component by first soldering two, diagonally
opposite, end pins. Apply the heating tool to the flat part of
the pin only. Contact time must be limited to 10 s at up to
300 °C. When using proper tools, all other pins can be
soldered in one operation within 2 to 5 s at between 270
and 320 °C. (Pulse-heated soldering is not recommended
for SO packages.)
For pulse-heated solder tool (resistance) soldering of VSO
packages, solder is applied to the substrate by dipping or
by an extra thick tin/lead plating before package
placement.
DEFINITIONS
Data sheet status
Objective specificationThis data sheet contains target or goal specifications for product development.
Preliminary specificationThis data sheet contains preliminary data; supplementary data may be published later.
Product specificationThis data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
February 199538
Page 39
Philips SemiconductorsPreliminary specification
Picture-in-Picture (PIP) controller for NTSCSAB9075H
NOTES
February 199539
Page 40
Philips Semiconductors – a worldwide company
Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428)
BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,
Tel. (02)805 4455, Fax. (02)805 4466
Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213,
Tel. (01)60 101-1236, Fax. (01)60 101-1211
Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands,
CA 94088-3409, Tel. (800)234-7381, Fax. (708)296-8556
Uruguay: Coronel Mora 433, MONTEVIDEO,
Tel. (02)70-4044, Fax. (02)92 0601
For all other countries apply to: Philips Semiconductors,
International Marketing and Sales, Building BE-p,
P.O. Box 218, 5600 MD, EINDHOVEN, The Netherlands,
Telex 35000 phtcnl, Fax. +31-40-724825
All rights are reserved. Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation
or contract, is believed to be accurate and reliable and may be changed without
notice. No liability will be accepted by the publisher for any consequence of its
use. Publication thereof does not convey nor imply any license under patent- or
other industrial or intellectual property rights.
Printed in The Netherlands
533061/1500/01/pp40Date of release: February 1995
Document order number:9397 745 30011
Philips Semiconductors
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