Datasheet SAA7366 Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

SAA7366

Bitstream conversion ADC for
digital audio systems

Preliminary specification
File under Integrated Circuits, IC01

Philips Semiconductors

May 1994

Philips Semiconductors Preliminary specification

Bitstream conversion ADC for
digital audio systems

FEATURES

• Integrated buffers for simple interfacing to analog inputs

• 4 flexible serial interface modes

• Overload detection of digital signal ≥−1 dB amplitude

• Selectable high-pass filter

• 18-bit serial output

• 3.4 to 5.5 V operation of digital part

• Standby mode

• SO24 package

• Small non-critical PCB layout.

GENERAL DESCRIPTION

The SAA7366 is a CMOS cost effective stereo
analog-to-digital converter (ADC) using the Philips
bitstream conversion technique.

QUICK REFERENCE DATA

SAA7366

APPLICATIONS

The device is designed for digital acquisition of analog
audio signals for digital audio systems such as:

• CD-recordable

• Digital Compact Cassette (DCC)

• Digital Audio Tape (DAT).

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V

DDD

V

DDA

f

i

THD + N total harmonic distortion + noise −−−80 dB
DR dynamic range 90 −−dB

ORDERING INFORMATION

TYPE NUMBER

SAA7366T

Note

1. Plastic small outline package; 24 leads; body width 7.5 mm; (SOT137A); SOT137-1; 1996 Oct 29.

digital supply voltage 3.4 5.0 5.5 V
analog supply voltage 4.5 5.0 5.5 V
clock input frequency 4.608 12.288 13.568 MHz

PACKAGE

PINS PIN POSITION MATERIAL CODE

(1)

24 SO24L plastic SOT137A

May 1994 2

Philips Semiconductors Preliminary specification

Bitstream conversion ADC for
digital audio systems

BLOCK DIAGRAM

V

SSA

operational

amplifier

16

BIR

BIL

17

Ω3 k

18

REFERENCE

14

CURRENT

GENERATOR

19

20
21

23 11 24 1

Ω3 k

operational

amplifier operational

V

DACN

I

V

DACP

BOR

REF

BOL

operational

amplifier

Ω10 k

1 pF

SIGMA-

DELTA

MODULATOR

SIGMA-

DELTA

MODULATOR

1 pF

Ω10 k

amplifier

Ω10 k

Ω3 k

Ω3 k

Ω10 k

V

REFR

REFERENCE

VOLTAGE

GENERATOR

TIMING

GENERATOR

REFERENCE

VOLTAGE

GENERATOR

22

SAA7366

TEST2

TEST1

CLOCK

GENERATION

AND

CONTROL

DECIMATION FILTER

STAGE 1

COMB

FILTER

STAGE 2

3 HALF-BAND

FILTERS

HIGH-PASS

FILTER

SERIAL OUTPUT

INTERFACE

STD

SAA7366

210121513

4

CKIN

6

V

SSD

5

V

DDD

3

OVLD

7

SDO

8

SWS

9

SCK

V

DDA

Fig.1 Block diagram.

May 1994 3

V

REFL

HPEN

SLAVE

SFOR

MGA911

Philips Semiconductors Preliminary specification

Bitstream conversion ADC for

SAA7366

digital audio systems

PINNING

SYMBOL PIN DESCRIPTION

SFOR 1 Serial interface output format select. Output format is selected as follows: SFOR

HIGH = Format 1; SFOR LOW = Format 2.
STD 2 Standby mode input (active LOW).
OVLD 3 Overload indication output. This pin indicates whether the internal digital signal is within 1 dB

of maximum. In standby mode this output is high impedance.
CKIN 4 System clock input.
V

DDD

V

SSD

SDO 7 Serial interface data output. In standby mode this output is high impedance.
SWS 8 Serial interface word select signal. In master mode this pin outputs the serial interface word

SCK 9 Serial interface clock. In master mode this pin outputs the serial interface bit clock. In slave

TEST1 10 Test input 1. This pin should be left open-circuit.
HPEN 1 1 High-pass filter enable input. (HPEN HIGH = enabled). If unconnected this pin defaults HIGH.
TEST2 12 Test input 2. This pin should be left open-circuit.
V

SSA

I

REF

V

REFR

BIR 16 Buffer operational amplifier inverting input for right channel.
BOR 17 Buffer operational amplifier output for right channel.
V

DACN

V

DACP

BOL 20 Buffer operational amplifier output for left channel.
BIL 21 Buffer operational amplifier inverting input for left channel.
V

REFL

V

DDA

SLAVE 24 Serial interface operating output mode master/slave select as follows: HIGH = slave mode;

5 Supply for the digital section (3.4 to 5.5 V).
6 Ground supply for the digital section.

select signal. In slave mode this pin is the word select input to the serial interface. In standby

mode this pin is always an input (high impedance).

mode this pin is the input for the external bit clock. In standby mode this output is

high impedance.

13 Ground supply for the analog section.
14 Current reference output node.

1

15

⁄2V

reference generator output for the right channel analog section.

DDA

18 Negative 1-bit DAC reference voltage input, connected to 0 V.
19 Positive 1-bit DAC reference voltage input, connected to +5 V.

1

22

⁄2V

reference generator output for the left channel analog section.

DDA

23 Supply for the analog section.

LOW = master mode. If unconnected the pin will default LOW.

May 1994 4

Philips Semiconductors Preliminary specification

Bitstream conversion ADC for
digital audio systems

1

SFOR

2

STD

OVLD

3

CKIN

4
5

V

DDD

V

6

SSD

SDO

SWS

SCK

TEST1

HPEN

TEST2

SAA7366

7
8

9
10
11
12

Fig.2 Pin configuration.

FUNCTIONAL DESCRIPTION
General

The SAA7366 is a bitstream conversion CMOS ADC for
digital audio systems. The conversion is achieved using a
third order Sigma-Delta modulator (SDM), operating at
128 times the output sample frequency (f
oversampling ratio greatly simplifies the design of the
analog input anti-alias filter. In most cases the internal
buffer operational amplifier, configured as a low-pass filter
will suffice. The 1-bit code from the Sigma-Delta modulator
is filtered and down-sampled (decimated) to 1fs in two
stages of filtering. An optional high-pass filter is provided
to remove DC, if required. The device has been designed
with ease of use, low board area and low application costs
in mind.

Clock frequency

The external clock, input on pin CKIN, operates at
256 times f

, which can range from 18 kHz to 53 kHz.

s

Input buffer

Two input buffers are provided, one for each channel, for
signal amplitude matching, signal buffering and anti-alias
filter purposes. These are configured for inverting use.
Access is provided by pins BIL, BIR (inverting inputs) and
BOL, BOR (outputs) for left and right channels

MGA912

24
23
22
21
20
19
18
17
16
15
14
13

SLAVE
V

DDA

V

REFL

BIL
BOL
V

DACP

V

DACN

BOR
BIR
V

REFR

I

REF

V

SSA

). The high

s

SAA7366

respectively. By the choice of feedback component values,
the application signal amplitude can be matched to the
requirements of the ADC. Typically the operational
amplifiers are configured as low-pass filters with a gain
of 1 and a pole at approximately 5fs.

Remark: The complete ADC is non-inverting. Hence a
positive DC input (referenced to V
digital output.

Input level

The overall system gain is proportional V
accurately {V(V

DACP

) − V(V

DACN

ADC input signal amplitude is defined as that amplitude
seen on BOL or BOR, the operational amplifier outputs
(i.e. the input to the Sigma-Delta modulator). Also, the
0 dB input level is defined as that which provides a −1dB
(actually −1.08 dB) digital output, relative to full-scale
swing. This offset provides headroom to accommodate
small random DC offsets without causing the digital output
to clip.

Hence:

VV

()VV

0dB()

V

I

DACP

---------------------------------------------------------------­5

The user of the IC should ensure, that when all sources of
signal amplitude variation are taken into account, the
maximum input signal should conform to the 0 dB level. If
not, clipping may occur. In the event that the maximum
signal level cannot be pre-determined, e.g. a live
microphone input, the average signal level should be set
at −10 to−20 dB down. The exact value will depend on the
application and the balance between head room and
operating signal-to-noise ratio.

Behaviour during overload

As defined earlier the maximum input level for normal
operation is 0 dB. If the input level exceeds this value
clipping may occur. Infringements are limited to the
maximum permitted positive or negative values, 2

−217 respectively. If the high-pass filter has been enabled
the clipped output samples may have non-maximum
values due to the removal of the DC content. Input signals
in the range of 0 to 1 dB may or may not be clipped
depending on the values of DC dither and small random
offsets in the analog circuitry.

When using the recommended application circuitry,
clipping will initially be observed on negative peaks due to
the use of negative DC dither.

The maximum level of overload that can be safely
tolerated is application circuit dependent. In the case of the

) will yield a positive

ref

, or more

DDA

)}. For convenience the

()–

DACN

V (RMS)==

17

− 1 or

May 1994 5

Philips Semiconductors Preliminary specification

Bitstream conversion ADC for
digital audio systems

recommended circuit the following applies: the inverting
operational amplifier inputs BIL/BIR are protected from
excessive voltages (currents) by diodes to V
These have absolute maximum ratings of IIK= ±20 mA,
with a safe practical limit of ±2 mA. Given the input resistor
of 10 kΩ, ±2 mA diode current and the operation of the
operational amplifier a maximum signal (applied to the
input resistor) of ±30 V can be handled safely. This level
represents an overload of 26 dB.

During overload the in-band portion of the waveform will be
correctly converted. The out-of-band portion will be limited
as detailed above.

Sigma-Delta modulator

The SAA7366 has two third order Sigma-Delta modulators
with a quantization noise floor of approximately −104 dB.
The scaling of the feedback has been optimized for stable
operation even during overload. Thus with a maximum
signal swing of 0 V to V

on the input the digital output

DDA

remains well behaved, i.e. it does not burst into random
oscillation. During overload the output is simply a clipped
version of the input. The gain of this stage is −4.95 dB.

Decimation filter

DDA

and V

SSA

SAA7366

Table 2 High-pass filter characteristics.

.

Pass band ripple none
Pass band gain 0
Droop at 0.00045f
Attenuation at DC at 0.00000036f
Dynamic range 0 to 0.45f

Serial interface

The serial interface provides 2 formats in both master and
slave modes (see Figs 3 and 4). In both modes the
interface provides up to 18 significant bits of output data
per channel.

During standby mode (STD = LOW) all interface pins are
in their high-impedance state. On recovery from standby
the serial data output SDO is held LOW until valid data is
available from the decimation filter. This time depends on
whether the high-pass filter is selected or not as follows:

HPEN = 0; T = 1024/fs, T = 21.3 ms when fs= 48 kHz
HPEN = 1; T = 8192/fs, T = 170.6 ms when fs= 48 kHz

ITEM CONDITION

s

s

s

VALUE

(dB)

0.029
>40
116

Decimation from 128fs is performed in two stages. The first
stage is a comb filter, which decimates from 128 to 8f

.

s

The second stage, consists of 3 half-band filters, each
decimating by a factor of 2.

The overall characteristics are given in Table 1.

Table 1 Overall filter characteristics.

ITEM CONDITION

Pass band ripple 0 to 0.45f

0.45 to 0.47f

Stop band >0.55f

s

Dynamic range 0 to 0.42f

Hz ±0.1

s

s

s

VALUE

(dB)

−0.5

−60

110

Gain DC 3.87

High-pass filter

An optional high-pass filter is provided to remove
unwanted DC components. The operation is selected
when HPEN is HIGH. The filter has the characteristics
given in Table 2.

Overload Detection Indication (OVLD)

The OVLD output is used to indicate whenever the data, in
either the left or right channel, is within 1 dB of the
maximum possible digital swing. When this condition is
detected the OVLD output is forced HIGH for at least 512f
cycles (10.6 ms at fs= 48 kHz). This time-out is reset for
each infringement.

Standby mode (

STD)

The STD pin activates a power saving mode when the
device function is not required. This pin can also be used
as a chip enable, as follows.

On a HIGH-to-LOW transition, of the STD pin, the internal
control circuitry starts a timed power-down sequence. This
takes approximately 32 system clock cycles to complete.
Transitions on STD which are shorter than 32 clock cycles
have an indeterminate effect. However, the device will
always recover correctly.

s

May 1994 6

Philips Semiconductors Preliminary specification

Bitstream conversion ADC for

SAA7366

digital audio systems

During standby the following occurs:

• The internal logic clock is disabled

• The serial interface pins are forced to high impedance

• The OVLD output is forced LOW

• The analog circuitry is disabled

• The nominal external analog node voltages are

maintained by a low-power circuit. This feature ensures
a fast recovery from standby mode.

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DDA

V

I

I

IK

V

O

I

O

I

DDtot

I

SStot

T

amb

T

stg

V

es1

V

es2

analog supply voltage note 1 −0.5 +6.5 V
DC input voltage −0.5 +6.5 V
DC input diode current −±20 mA
DC output voltage −0.5 VDD + 0.5 V
DC output source or sink current −±20 mA
total DC supply current −±0.5 A
total DC supply current −±0.5 A
operating ambient temperature −40 +85 °C
storage temperature −65 +150 °C
electrostatic handling note 2 −2000 +2000 V
electrostatic handling note 3 −200 +200 V

On a LOW-to-HIGH transition the device reverts back to its
normal function. This process takes approximately 32
system clock cycles. Before SDO is enabled the output
data is forced LOW. SDO remains LOW until good data is
available from the decimation filter.

The STD pin has a Schmitt-trigger input. A simple
power-on reset function can be effected using an external
capacitor to V

and resistor to V

SSD

DDD

.

Notes

1. V

SSD

and V

pins must be externally connected to a common potential.

SSA

2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor with a rise time of 15 ns.

3. Equivalent to discharging a 200 pF capacitor via a 2.5 µH series inductor.

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.

CHARACTERISTICS

= 3.4 to 5.5 V; V

V

DDD

= 4.5 to 5.5 V; T

DDA

= −40 to +85 °C; fs = 18 to 53 kHz; unless otherwise specified.

amb

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

V
I

DDA

V
I

DDD

P

DDA

DDD

tot

analog supply voltage 4.5 5.0 5.5 V
analog supply current fs= 48 kHz − 13 − mA
digital supply voltage 3.4 5.0 5.5 V
digital supply current fs= 48 kHz − 56 − mA
total power consumption fs= 48 kHz − 345 − mW

May 1994 7

Philips Semiconductors Preliminary specification

Bitstream conversion ADC for

SAA7366

digital audio systems

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

I

STD

P

STD

Digital part: inputs

SFOR, SLAVE
V

IL

V

IH

I

LI

C

I

CLKIN
V

IL

V

IH

I

LI

C

I

STD (SCHMITT-TRIGGER)
V

IL

V

IH

∆V

I

I

LI

C

I

Digital part: Input/Outputs

standby supply current − 65 −µA
standby power consumption − 325 −µW

AND HPEN

LOW level input voltage note 1 −0.5 − +0.8 V
HIGH level input voltage note 1 2.0 − V

+ 0.5 V

DDD

input leakage current note 2 −10 − +10 µA
input capacitance −−10 pF

LOW level input voltage −0.5 − +0.3V
HIGH level input voltage 0.7V

DDD

− V

DDD

DDD

+ 0.5 V

V

input leakage current note 2 −10 − +10 µA
input capacitance −−10 pF

LOW level input voltage note 1 −0.5 − +0.4V
HIGH level input voltage note 1 2.4 − V

DDD

DDD

+ 0.5 V

V

input hysteresis − 600 − mV
input leakage current note 2 −10 − +10 µA
input capacitance −−10 pF

SWS

AND SCK

V

IL

V

IH

I

LI

C

I

V

OL

V

OH

C

L

LOW level input voltage note 1 −0.5 − +0.8 V
HIGH level input voltage note 1 2.0 − V
leakage current in 3-state note 2 −10 − +10 µA
input capacitance −−10 pF
LOW level output voltage IO= −400 µA;

HIGH level output voltage IO=20µA;

output load capacitance −−50 pF

Digital part: Outputs

OVLD
V

OL

V

OH

C

L

LOW level output voltage IO= −400 µA;

HIGH level output voltage IO=20µA;

output load capacitance −−50 pF

note 1

note 1

note 1

note 1

+ 0.5 V

DDD

−−0.4 V

2.4 −−V

−−0.4 V

2.4 −−V

May 1994 8

Philips Semiconductors Preliminary specification

Bitstream conversion ADC for

SAA7366

digital audio systems

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

SDO
V

OL

LOW level output voltage IO= −400 µA;

note 1

V

OH

HIGH level output voltage IO=20µA;

note 1

I

LI

C

L

leakage current in 3-state note 2 −10 − +10 µA
output load capacitance −−50 pF

Digital part: timing

CKIN
t

r

t

f

f

i

msr mark-to-space ratio f

clock input rise time −−10 ns
clock input fall time −−10 ns
clock input frequency note 3 4.608 12.288 13.568 MHz

> 32 kHz 40 − 60 %

s

f

≤ 32 kHz 30 − 70 %

s

Serial interface master and slave modes (see Figs 5, 6 and 7)

−−0.4 V

2.4 −−V

SCK
t

r

t

f

t

L

t

H

f

clk

t

idle

SWS
t

r

t

f

t

wL

t

wH

f

wc

t

d

t

d

t

su

SDO
t

h

t

su

t

r

t

f

clock rise time note 4 −−50 ns
clock fall time note 4 −−50 ns
clock LOW time T = 1/64f
clock HIGH time T = 1/64f

s
s

clock frequency master mode 64f

slave mode −−64f

burst clock idle time slave mode;

T = 1/f

s

0.40T − 0.60T

0.40T − 0.60T

s

64f

s

64f

s
s

0 − 0.05T

word select rise time note 4 −−50 ns
word select fall time note 4 −−50 ns
word select LOW time T = 1/f
word select HIGH time T = 1/f

s
s

word select frequency 1f

0.45T 0.50T 0.55T

0.45T 0.50T 0.55T

s

1f

s

1f

s

word select delay from SCK master mode −50 − +50 ns
word select delay from SCK slave mode 50 −−ns
word select set-up time to SCK slave mode 150 −−ns

data output hold time 100 −−ns
data output set-up time 100 −−ns
data output rise time note 4 −−50 ns
data output fall time note 4 −−50 ns

May 1994 9

Philips Semiconductors Preliminary specification

Bitstream conversion ADC for

SAA7366

digital audio systems

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Analog part (V

V

OLTAGE REFERENCE:V

V

O

Z

n

Z

s

DDD=VDDA

output voltage 0.475V
DC impedance normal mode − 750 −Ω

DC impedance standby mode − 100 − kΩ
CURRENT REFERENCE:I
V

O

I

O

DAC REFERENCE:V
V

I

V

DACP

V

I

output voltage − 0.5V

output current R = 33 kΩ− 76 −µA

DACN

input voltage − V

input voltage − V
BUFFER OPERATIONAL AMPLIFIERS: BIL, BOL, BIR AND BOR
V

R

offset
Lmax

input offset voltage −< ±10 − mV

maximum load resistance;

(drive capability)
Z

O

output impedance − 100 −Ω
THD + N total harmonic distortion plus

noise
ADC

PERFORMANCE; NOTE 5

t

gd

α

sb

group delay T = 1/f

stop band attenuation f > 0.546f
DR dynamic range note 6 90 −−dB
THD + N total harmonic distortion plus

noise
S/N signal-to-noise ratio A-weighted − tbf − dB

α

cs

channel separation note 8 − tbf − dB
G gain note 9 −1.2 −1 −0.8 dB

REFL

REF

=5V; T

AND V

REFR

=25°C; fs= 48 kHz)

amb

decoupled to
V

REF

f = 0 to 20 kHz −−85 − dB

note 7 −−−80 dB

DDA

0.5V

SSA

DDA

DDA

DDA

0.525V

DDA

− V

− V

− V

V

− 10 − kΩ

s

s

tbf − tbf µs
60 −−dB

Notes

1. Minimum VIL, VOL and maximum VIH, VOH are peak values to allow for transients.

2. I

LImin

and I

measured at VI= 0 V; I

LOmin

LImax

and I

measured at VI=V

LOmax

DDD

.

3. fi is a multiple (×256) of the system sampling frequency (fs) which can vary between 18 kHz and 53 kHz.

4. CL= 50 pF (valid for master mode only).

5. Device measured with external components shown in recommended application diagram Fig.8.

6. Input is 1 kHz and −60 dB.

7. Input is 1 kHz and 0 dB.

8. Measured by applying a 1 kHz, 0 dB signal to one channel and monitoring the level of 1 kHz (fundamental) on the
other channel.

9. See also Section “Input level” of Chapter “Functional description”; valid for left or right channel.

May 1994 10

Philips Semiconductors Preliminary specification

Bitstream conversion ADC for
digital audio systems

SAA7366

MGA914

MSB

LSB

RIGHT DATA

1 STEREO WORD

LEFT DATA

FORMAT 2

14 CLOCKS 18 CLOCKS 14 CLOCKS

LEFT DATA RIGHT DATA

18 CLOCKS

FORMAT 1

SCK

MSB

LSB

Fig.3 Serial interface master mode format.

MSB

SDO

SWS

May 1994 11

Philips Semiconductors Preliminary specification

Bitstream conversion ADC for
digital audio systems

SAA7366

MGA915

RIGHT DATA

1 STEREO WORD

n CLOCKS idle n CLOCKS

LEFT DATA

idle

SWS

FORMAT 2

SCK

MSB LSB MSB LSB MSB

SDO

1 STEREO WORD

n CLOCKS idle n CLOCKS

LEFT DATA RIGHT DATA

idle

SWS

FORMAT 1

SCK

Fig.4 Serial interface slave mode formats.

MSB LSB MSB LSB MSB

SDO

May 1994 12

1 < n < 33.

Up to 18 significant bits are available.

Philips Semiconductors Preliminary specification

Bitstream conversion ADC for
digital audio systems

SCK

SWS

SDO

SWS

t

r

VALID

2.0 V

0.8 V

t

f

t

r

t

L

t

d

t

su

FORMAT 1

MSB

SAA7366

t

H

t

h

t

wH

t

f

FORMAT 2

MSB

t

wL

timing reference
levels

MGA916

2.0 V

0.8 V

2.0 V

0.8 V

SCK

SWS

SDO

SWS

t

r

2.0 V

0.8 V

VALID

Fig.5 Serial interface master mode timing.

t

t

L

f

t

d

t

su

t

r

t

su

FORMAT 1

MSB

t

H

t

h

t

wH

t

f

FORMAT 2

MSB

timing reference
levels

t

wL

MGA917

2.0 V

0.8 V

2.0 V

0.8 V

Fig.6 Serial interface slave mode timing.

May 1994 13

Philips Semiconductors Preliminary specification

Bitstream conversion ADC for
digital audio systems

SWS

SCK

t

idle

t

SAA7366

idle

MGA918

Fig.7 Serial interface slave mode burst clock.

May 1994 14

Philips Semiconductors Preliminary specification

Bitstream conversion ADC for
digital audio systems

APPLICATION INFORMATION

47

µF

47

nF

(1)

right channel input

Ω100 k

Ω100 k

left channel input

47 µF

5 V

47 µF

Ω10 k

dither

R

Ω

270

Ω

270

Ω10 k

dither

R

(1)

47

nF

47

µF

Ω 4.7

Ω33 k

Ω330 k

Ω620 k

(1)

47

47

nF

µF

Ω10 k

47 µF

Ω10 k

22 nF

68 pF

(1)

47 nF

68 pF

SSA

V

REF

I

REFR

V

BOR BIR

DACN

V

DACP

V

REFL BIL BOL

V

DDA

V

SLAVE

24 23 22 21 20 19 18 17 16 15 14 13

SAA7366

123456789101112

SDO SWS SCK TEST1 HPEN TEST2

SSD

V

DDD

OVLD CKIN V

STD

SFOR

(1)

MGA913

DDD SSD

V or V

circuit

to serial

receiver

interface

Ω 4.7

µF

47

47 nF

input

clock

system

to microcontroller

overload detection

power-down control

from microcontroller

SAA7366

5 V

Fig.8 Application circuit.

DDD SSD

5 V

handbook, full pagewidth

V or V

May 1994 15

DDD SSD

V or V

(1) These capacitors should preferably be surface mounted components located as close as possible to the device pins.

Philips Semiconductors Preliminary specification

Bitstream conversion ADC for
digital audio systems

PACKAGE OUTLINE

handbook, full pagewidth

S

pin 1

index

112

0.9

0.4

(4x)

15.6

15.2

0.1 S

SAA7366

7.6

7.4

10.65

10.00

1324

1.1

2.45

2.25

0.3

0.1

detail A

1.0

0.32

0.23

1.1

0.5

0 to 8

MBC235 - 1

A

2.65

2.35

o

Dimensions in mm.

1.27

0.49

0.36

0.25 M
(24x)

Fig.9 Plastic SOL, 24-pin (SO24L; SOT137A).

May 1994 16

Philips Semiconductors Preliminary specification

Bitstream conversion ADC for
digital audio systems

SOLDERING
Plastic small-outline packages

YWAVE

B
During placement and before soldering, the component

must be fixed with a droplet of adhesive. After curing the
adhesive, the component can be soldered. The adhesive
can be applied by screen printing, pin transfer or syringe
dispensing.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder bath is
10 s, if allowed to cool to less than 150 °C within 6 s.
Typical dwell time is 4 s at 250 °C.

A modified wave soldering technique is recommended
using two solder waves (dual-wave), in which a turbulent
wave with high upward pressure is followed by a smooth
laminar wave. Using a mildly-activated flux eliminates the
need for removal of corrosive residues in most
applications.

SAA7366

applied to the substrate by screen printing, stencilling or
pressure-syringe dispensing before device placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt, infrared, and
vapour-phase reflow. Dwell times vary between 50 and
300 s according to method. Typical reflow temperatures
range from 215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 min at 45 °C.

EPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING

R

IRON OR PULSE

Fix the component by first soldering two, diagonally
opposite, end pins. Apply the heating tool to the flat part of
the pin only. Contact time must be limited to 10 s at up to
300 °C. When using proper tools, all other pins can be
soldered in one operation within 2 to 5 s at between 270
and 320 °C. (Pulse-heated soldering is not recommended
for SO packages.)

-HEATED SOLDER TOOL)

Y SOLDER PASTE REFLOW

B
Reflow soldering requires the solder paste (a suspension

of fine solder particles, flux and binding agent) to be

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

For pulse-heated solder tool (resistance) soldering of VSO
packages, solder is applied to the substrate by dipping or
by an extra thick tin/lead plating before package
placement.

May 1994 17

Philips Semiconductors Preliminary specification

Bitstream conversion ADC for
digital audio systems

SAA7366

NOTES

May 1994 18

Philips Semiconductors Preliminary specification

Bitstream conversion ADC for
digital audio systems

SAA7366

NOTES

May 1994 19

Philips Semiconductors – a worldwide company

Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428)

BUENOS AIRES, Tel. [phone], Fax. [phone]

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th

floor, Suite 51,

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Exchange Bldg. ST-2/A, Block 9, KDA Scheme 5, Clifton,
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Fax. [phone].

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Tel. [phone], Fax. [phone].

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Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Limited, P.O. Box 65,

Philips House, Torrington Place, LONDON, WC1E 7HD,
Tel. [phone], Fax. [phone]

United States:INTEGRATED CIRCUITS:

811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone], Fax. [phone]
DISCRETE SEMICONDUCTORS: 2001 West Blue Heron Blvd.,

P.O. Box 10330, RIVIERA BEACH, FLORIDA 33404,
Tel. [phone] and [phone], Fax. [phone]

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Tel. [phone], Fax. [phone]

For all other countries apply to: Philips Semiconductors,
International Marketing and Sales, Building BAF-1,
P.O. Box 218, 5600 MD, EINDHOVEN, The Netherlands,
Telex 35000 phtcnl, Fax. [phone]

SCD31 © Philips Electronics N.V. 1994

All rights are reserved. Reproduction in whole or in part is prohibited without the
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other industrial or intellectual property rights.

Printed in The Netherlands

513061/1500/01/pp20 Date of release: May 1994
Document order number: 9397 731 80011

Philips Semiconductors