Datasheet SAA7346H Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

SAA7346

Shock absorbing RAM addresser

Preliminary specification
File under Integrated Circuits, IC01

Philips Semiconductors

July 1994

Philips Semiconductors Preliminary specification

Shock absorbing RAM addresser SAA7346

FEATURES

• Absorbs shocks from x, y and z directions

• Absorbs rotational shocks

• Absorbs multiple shocks per second

• Interfaces directly to compact disc decoders SAA7345,

SAA7347 and SAA7370

• Multi-speed I2S-bus input with single-speed
I2S-bus output

• Controls 1 or 4 MBit of external Dynamic Random
Access Memory (DRAM)

• Easy serial interface for communication with common
microcontrollers

• Software selectable shock detectors

• By-pass/power-down mode

• Kill interface for DAC deactivation

• Can be used for:

– ‘sampling’ part of a disc
– to reduce access pauses between jumps
– to deliver a programmable delay
– to generate a fixed audio rate from Constant Angular

Velocity (CAV) discs.

GENERAL DESCRIPTION

The SAA7346 can be used to make a CD player
insensitive to shocks. To do this, SAA7346 operates
closely with a standard 1 Mbit or 4 Mbit DRAM. Audio data
is stored inside the DRAM and during shocks the data of
the DRAM can be played. The SAA7346 functions as a
customized DRAM controller with serial I/O and on-board
shock detectors.

QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V

DD

I

DD

f

clk

f

i(clk)

f

o(clk)

T

amb

T

stg

supply voltage 3.3 5.0 5.5 V
supply current − 12 − mA
clock frequency − 16.9344 − MHz
I2S input word clock frequency 44.1 88.2 176.4 kHz
I2S output word clock frequency 44.1 88.2 176.4 kHz
operating ambient temperature −40 − +85 °C
storage temperature −65 − +150 °C

ORDERING INFORMATION

PACKAGE

TYPE NUMBER

PINS PIN POSITION MATERIAL CODE

SAA7346H 44 QFP

(1)

plastic SOT307-2

Note

1. When using reflow soldering it is recommended that the Dry Packing instructions in the

Pocketbook”

are followed. The pocketbook can be ordered using the code 9398 510 34011.

“Quality Reference

July 1994 2

Philips Semiconductors Preliminary specification

Shock absorbing RAM addresser SAA7346

BLOCK DIAGRAM

handbook, full pagewidth

DD2

WCO

32, 30, 28,
26, 25, 27,
29, 31, 33,

DD1

V

34

V

A0

to

A9

RESET

TMS

14

8

SDI

WCI

SCLI

345

2

I S

INPUT

SAA7346

CFLG

KILL

D0 to D3

121319 21 20 22 23 44

DATA

MULTIPLEXER

WRITE

POINTER

REGISTER

KILLOUT

42

to

39

MULTIPLEXER

S_NSF

ADDRESS

SDO

SCLO

2

I S

OUTPUT

READ

POINTER

SICL

SIDA

SILD

V

16
15

17

MONITOR

CONTROLLER

RAS

SS1

MICROCONTROLLER

DETECTORS

24

V

SS2

INTERFACE

SHOCK

9

SSD

OTD

1211 3538373643

RSB

Fig.1 Simplified SAA7347 block diagram.

CAS

WE

OE

TIMING

CLKIN

107

RCD2

6

18

MGB429

CONFIG
FILL

July 1994 3

Philips Semiconductors Preliminary specification

Shock absorbing RAM addresser SAA7346

PINNING

SYMBOL PIN DESCRIPTION

CFLG 1 correction flag input from CD decoder
KILL 2 kill input
SCLI 3 multi-speed I
WCI 4 multi-speed I
SDI 5 multi-speed I
CONFIG 6 external DRAM select input; HIGH 4 Mbit, LOW 1 Mbit
CLKIN 7 16.9344 MHz system clock input
TMS 8 test mode select input; active HIGH
OTD 9 on/off track detector input
RCD2 10 DRAM read cycle divide-by-2 input; active HIGH
SSD 11 shock detected output; active HIGH when shock is detected
RSB 12 rotational shock busy output; active HIGH when rotational shock is detected
S_NSF 13 synthetic new subcode frame output
RESET 14 reset enable input; active LOW
SIDA 15 microcontroller interface input/output data line
SICL 16 microcontroller interface clock input
SILD 17 microcontroller interface
FILL 18 FIFO write enable output; active HIGH
KILLOUT 19 open drain output; active LOW; when in by-pass mode KILLOUT equals KILL
SDO 20 I
SCLO 21 I
WCO 22 I
V
V

DD1
SS1

23 supply voltage 1
24 supply ground 1

2

S data output

2

S bit clock output

2

S word clock output

A4 25 DRAM address bus output 4
A3 26 DRAM address bus output 3
A5 27 DRAM address bus output 5
A2 28 DRAM address bus output 2
A6 29 DRAM address bus output 6
A1 30 DRAM address bus output 1
A7 31 DRAM address bus output 7
A0 32 DRAM address bus output 0
A8 33 DRAM address bus output 8
A9 34 DRAM address bus output 9
OE 35 DRAM enable output; active LOW
RAS 36 DRAM row address strobe output; active LOW
CAS 37 DRAM column address strobe output; active LOW
WE 38 DRAM write enable output; active LOW

2

S bit clock input

2

S word clock input

2

S data input

read/write input

July 1994 4

Philips Semiconductors Preliminary specification

Shock absorbing RAM addresser SAA7346

SYMBOL PIN DESCRIPTION

D3 to D0 39 to 42 DRAM data bus inputs/outputs
V
V

SS2
DD2

43 supply ground 2
44 supply voltage 2

handbook, full pagewidth

CFLG

KILL

SCLI

WCI

SDI

CONFIG

CLKIN

TMS
OTD

RCD2

SSD

DD2

SS2

V

V

44

43

1
2
3
4
5
6
7
8

9
10
11

12

13

RSB

S_NSF

D0

D1
41

42

14

15

SIDA

RESET

D2

D3WECASOERAS

40

39

SAA7346

16

17

SILD

SICL

38

18

FILL

37

36

20

19

KILLOUT

SDO

35

21

SCLO

A9

34

22

WCO

33
32
31
30
29
28
27
26
25
24
23

MGB430

A8
A0
A7
A1
A6
A2

A5
A3
A4

V
V

SS1
DD1

Fig.2 Pin configuration.

FUNCTIONAL DESCRIPTION

2

S input/output interfaces

I

The SAA7346 contains an asynchronous serial input and
a serial output interface. The serial operation of the
interfaces is under hardware control of the external
circuitry and uses the I2S protocol. The output presents a
continuous clock signal SCLO (typically 2.8224 MHz)
which is divided from the system clock, and a word select
signal WCO, typically 44.1 kHz (fs), which is used to
distinguish between right and left channels. When in
by-pass mode WCO and SCLO are the same as the input
interface signals WCI and SCLI, enabling data to pass
through the SAA7346. Since the serial input port is
asynchronous the device is independent of the CD

July 1994 5

decoder clock speed and enables the word clock to vary
from 1.1 × f

to 4 × fs (typically 2 × fs). This is a requirement

s

of any electronic shock absorbing system since the disc
must be rotating faster than usual to assure the FIFO is full
to absorb a shock. The falling edge of WCO indicates the
start of a new transfer. Data is exchanged over the
SDI and SDO pins. The SAA7346 is compatible with a
variety of DAC ICs.

New subcode frame regeneration

The SAA7346 has a digital phase-locked loop (PLL)
system which decodes the F1 and F6 flags, from the first
1-bit signal generated by the CD decoder correction flag
output shown in Fig.3. The F1 flag is the absolute time
sync signal of the New Subcode Frame (NSF). It relates

Philips Semiconductors Preliminary specification

Shock absorbing RAM addresser SAA7346

the position of the subcode-sync to the audio data. This
signal determines the accuracy with which the SAA7346
sews audio data together after a shock. When the CD
decoder preforms a jump the NSF will be missed. The PLL
system will insert the missing pulse. The resulting signal is
the S_NSF which can be used as a time out for reading the

handbook, full pagewidth

CFLG

11.3
µs

F1 F2 F3 F4 F5 F6 F7 F1

Fig.3 CFLG input timing diagram.

0.37 ms

handbook, full pagewidth

S_NSF

subcode from the decoder shown in Fig.4. The S_NSF is
available externally and the NSF flag can be read via the
serial microcontroller interface. The F6 flag indicates at
least one hold has occurred in the decoder’s error
corrector and interpolator. The shock processor uses this
signal to evaluate whether a shock has occurred.

45.4 µs

MGA370

6.6 ms

NSF

Fig.4 S_NSF output timing diagram; n = 2.

Shock processor

The shock processor determines whether a shock has
occurred by processing all the shock detectors. The
SAA7346 will enter shock mode and set SSD when the:

•µCsd flag is set by the microcontroller in the command
register

• OTD input is active while the jmp_bz flag is not set

• RSB output is set while the e_rot_sd flag is set

• NSF pulse is lost and the full flag is not read by the

microcontroller from the status register.

When the target position has been found the
microcontroller should set the PFB flag in the command
register. The SAA7346 will respond by clearing the SSD
flag and start refilling. If CFLG still indicates a hold, the

MGB431

Variable

NSF is set until read

by the microcontroller

decoder is rolling out of its FIFO. RSB will be set which
sets SSD again thus the FIFO will not start refilling. The
microcontroller should jump one track back and look for
the correct target position again. When the motor speed is
stable and the decoder does not roll out of its FIFO, the
audio data will be glued together.

SSD will be reset whenever the microcontroller sets PFB
or the flush flags in the command register, or when the
FIFO empties while the echo flag is LOW. Note if the
microcontroller wants SSD to be clear for a while the shock
detectors should be inhibited.

FIFO controller and monitor

The SAA7346 uses a state machine to control and monitor
the conditions of the FIFO shown in Fig.5.

July 1994 6

Philips Semiconductors Preliminary specification

Shock absorbing RAM addresser SAA7346

handbook, full pagewidth

SSD and

(NSF + S_NSF)

flush + reset +

(empty and echo)

HOLD

HOLD

first nibble full

6

PFB

5

SSD

PFB

Fig.5 State machine flow diagram.

During normal operation the FIFO will fill up because
writing is carried out twice as fast as reading; this is the fill
mode. If the FIFO is full the monitor will detect and set the
full flag. At the same time the fill flag will be reset thus
preventing audio data from being written in to the FIFO.
When the microcontroller reads the full flag from the status
register, the servo control should jump back one track. The
microcontroller enters a wait loop until the same absolute
time subcode frame turns by again; this is the hold mode.
When the spot is found again the microcontroller should
set the PFB flag in the command register and the
SAA7346 will resume writing to the DRAM. While in fill
mode the write pointer address is saved at the end of each
subcode frame. When the player exists hold mode it
restores the saved address and continues writing after the
last sample.

RESET

0

FILL

1

SHOCK

7

HOLD

4

reset and sowflush + reset

SSD

SSD

flush + reset

SSD

first nibble

FILL

2

FILL

3

NSF +

S_NSF

MGB432

When a shock is detected the SAA7346 will enter shock
mode. The shock mode will last until the PFB is set by the
microcontroller or the FIFO is flushed, reset or runs empty.

Microcontroller interface

The SAA7346 has a 3-line microcontroller interface which
is compatible with TDA1301, TDA1303 and SAA7345.

W

RITING DATA TO THE SAA7346

The SAA7346 command register is shown in Table 1. This
can be written to via the microcontroller interface as shown
in Fig.6. The command register flags functions are shown
in Table 2.

Table 1 SAA7346 microcontroller interface registers.

REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

Command flush bypass echo jmp_bz otd_p e_rot_sd µCsd PFB
Status Lm Lm1 FRM_ER NSF full empty SSD fill

July 1994 7

Philips Semiconductors Preliminary specification

Shock absorbing RAM addresser SAA7346

Table 2 Command register flag functions.

COMMAND DESCRIPTION

Flush Flush, when set, will empty the FIFO, reset the read and write pointer addresses. Then writing will

resume to the FIFO. Flag reset automatically.

Bypass Bypass, when set, will power down the SAA7346. The I2S interface passes input to output directly.

The parallel interface port controls RAS, CAS, WE and OE which are pulled HIGH. KILL passes
directly to KILLOUT. When exiting by-pass mode the FIFO is automatically flushed.

Echo Echo, when set, will cause the FIFO contents to be continuously played until the correct position is

found again.

jmp_bz Jump busy, when set, indicates a jump is being preformed. The OTD shock detector input will be

disabled. After the jump has finished the flag should be reset by a write.

otd_p OTD polarity enable. Enables the polarity of the OTD input to be switched from active HIGH set,

active LOW not set.

e_rot_sd Enable rotational shock detection, when set, will detect shocks whenever the decoder rolls out of its

internal FIFO.
µCsd Microcontroller shock detected is set when the microcontroller has detected a shock.
PFB Position Found Back, when set, indicates that the microcontroller has found the absolute time frame

after a shock or hold cycle. The audio data will sew together and the flag reset automatically.

handbook, full pagewidth

SICL

SILD

SIDA

B7 B6 B5 B4 B3 B2 B1 B0

Fig.6 Microcontroller WRITE timing.

Writing operation sequence:

• SILD is held HIGH by the microcontroller.

• Microcontroller data is clocked into the internal

command register on the LOW-to-HIGH clock transition
of SICL.

• SILD is pulled LOW by the microcontroller to latch-in
data to the command register.

• SICL and SILD are pulled HIGH by the microcontroller
to indicate that communications have finished.

MGB433

R

EADING STATUS OF SAA7346

The SAA7346 has a status register shown in Table 1. This
can be read via the microcontroller interface shown in
Fig.7. The internal status signals are made available on
the SIDA pin and are shown in Table 3.

July 1994 8

Philips Semiconductors Preliminary specification

Shock absorbing RAM addresser SAA7346

Table 3 Internal status signals.

STATUS DESCRIPTION

Lm and Lm1 The two Most Significant Bits (MSB) of the FIFO. These can be used to display the FIFO length or

correct the subcode time information. The FIFO length is shown in Table 4.

FRM_ER Framing error flag is set when:

1. The microcontroller did not accept the previous subcode flag on time. When this occurs the NSF
flag will be set together with FRM_ER.

2. The S_NSF generated signal does not coincide with the NSF signal generated by the decoder.
When this occurs there has been a FIFO overflow in the decoder or a jump.

Framing error flag is reset when status register is read.

NSF New subcode frame is set when an absolute sync is recovered from the CFLG input. Reset when

status register is read. If the NSF is still set at the next occurrence of a subcode frame, FRM_ER will
be set indicating that the microcontroller has lost a frame.

Full Full is set when the FIFO is full. When the flag is set the microcontroller must jump back to the

previous track. Reset when status register is read.

Empty Empty is set when the FIFO is emptied during hold or shock modes. DRAM writing should resume

immediately unless echo is set in the command register. If set, writing can only resume when PFB or
flush are set in the command register. The latter will cause a discontinuity in music. Note when set

there is a complete word left in the FIFO giving the SAA7346 controller time to switch to fill mode.
SSD Set shock detect is set when SAA7346 detects a shock.
Fill Fill is set when writing data to the DRAM or by setting the command register flags PFB or flush. Reset

internally when full or SSD are set.

Table 4 FIFO length as a function of CONFIG, Lm and Lm1.

CONFIG Lm Lm1 FIFO LENGTH (s)

0 0 0 0.00 to 0.19
0 0 1 0.19 to 0.39
0 1 0 0.39 to 0.58
0 1 1 0.58 to 0.78
1 0 0 0.00 to 0.75
1 0 1 0.75 to 1.50
1 1 0 1.50 to 2.25
1 1 1 2.25 to 2.97

handbook, full pagewidth

SICL

SILD

SIDA

B7 B6 B5 B4 B3 B2 B1 B0

Fig.7 Microcontroller READ timing.

MGB434

July 1994 9

Philips Semiconductors Preliminary specification

Shock absorbing RAM addresser SAA7346

Read operation sequence:

• SILD is held LOW by the microcontroller.

• Status information is clocked from the internal status

register on the LOW-to-HIGH clock transition of SICL.

• SICL and SILD are pulled HIGH by the microcontroller
to indicate that communications have finished.

DRAM interface

The SAA7346 may be connected to all standard 80 ns,
1M × 4 bit or 256K × 4 bit fast page mode DRAMs. The
best performance can be expected with the 4 Mbit DRAM.
The CONFIG input selects the DRAM configuration either
HIGH 4 Mbit or LOW 1 Mbit format. The SAA7346
converts audio data from serial to parallel and stores it as
4 bits. The addresses for read or write actions are
calculated by separate read and write pointers which are
multiplexed onto a 4 bits address bus. The control signal
outputs associated with the parallel inputs/outputs are
shown in Table 5.

Table 5 Command register flag functions.

COMMAND DESCRIPTION

WE indicates write enable action
RAS row address strobe
CAS column address strobe
OE output buffer enable for external memory

during cycle.

When the SAA7346 leaves bypass mode where all parallel
Port control lines are pulled HIGH, the device initiates a
DRAM power-up routine in accordance with the JEDEC
standard.

System clock

The system clock input, CLKIN, recommended input signal
is 16.9344 MHz. The accuracy of this clock influences the
accuracy of the I2S output, therefore the performance of
the DAC and hence audio quality. The system clock is
divided by 384 to derive the I2S output word clock, WCO
divided by 8 to derive the I2S output bit clock, SCLO.
Therefore whatever clock jitter the user introduces on the
CLKIN signal will be reflected in the WCO and SCLO
outputs.

Reset

Reset should be applied for four system clock cycles.
Reset will:

• Clear SSD

• Clear the command register but leave the bypass flag

set.

After a reset has been applied the SAA7346 will start-up in
bypass mode.

Kill interface

The kill interface can be used to deactivate the DAC. The
kill input is passed directly to the
bypass flag in the command register is set. When the flag
is not set KILLOUT is generated by the SAA7346. It is
LOW after leaving bypass mode, a reset or a FIFO flush. It
will be LOW until the first error free word is read from the
FIFO. The kill input has no effect or function when the
bypass flag is not set.

Read cycle divide (RCD2)

The RCD2 input enables the modes of operation shown in
Table 6. When RCD2 is HIGH the DRAM-read requests
are halved allowing I
n is called the over-speed factor.

2

S output speeds to vary. The factor

KILLOUT output when the

July 1994 10

Philips Semiconductors Preliminary specification

Shock absorbing RAM addresser SAA7346

Table 6 SAA7346 I2S output speeds.

2

S INPUT

RCD2

LOW CAV

(2)

LOW

I

SPEED

(1)

n = 1 n = 1 delay line feature
LOW n = 2 n = 1 shock proof CD player
LOW n = 4 n = 1 high data rate CDROM/CDI player with standard audio speed
HIGH n = 2 n =
HIGH n = 4 n =

Notes

1. CAV with n = 4 speed at outer edge of disc; n = 1.5 at inner edge of disc.

2. To build-up a delay, RCD2 should be made HIGH temporarily for twice the delay time.

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

I2S OUTPUT

SPEED

APPLICATION

n = 1 CAV CDROM player with standard audio speed

1

⁄

2

1

⁄

2

musicians feature
musicians feature

SYMBOL PARAMETER MIN. MAX. UNIT

V

DD

P

max

T

stg

T

amb

supply voltage 0 6.5 V
maximum power dissipation − 500 mW
storage temperature −55 +125 °C
operating ambient temperature −40 +85 °C

THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE UNIT

R

th j-a

thermal resistance from junction to ambient in free air 80 K/W

CHARACTERISTICS

V

= 3.3 to 5.5 V; VSS=0V; T

DD

= −40 to +85 °C; unless otherwise specified.

amb

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supply

V
I

DD

I

DDb

DD

supply voltage 3.3 5.0 5.5 V
supply current VDD= 5.0 V − 12 − mA
bypass supply current VDD= 5.0 V;

− 4 − mA

bypass mode

I

DDq

quiescent supply current −−100 µA

Digital inputs

I

NPUTS: WCI, SDI, CLKIN, OTD AND RCD2; NORMAL CMOS

V

IL

V

IH

I

LI

C

I

LOW level input voltage −0.3 − 0.3V
HIGH level input voltage 0.7V
input leakage current VI=0VtoV
input capacitance −−10 pF

July 1994 11

DD

V

DD

DD

− VDD+ 0.3 V

−10 − +10 µA

Philips Semiconductors Preliminary specification

Shock absorbing RAM addresser SAA7346

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

INPUT CLKIN
f

clk

t

H

t

r

t

f

INPUTS: CFLG, KILL, CONFIG AND SILD; WITH PULL-UP
V

IL

V

IH

R

PU

C

I

INPUT TMS; WITH PULL-DOWN
V

IL

V

IH

R

PD

C

I

INPUTS: RESET, SCLI AND SICL; SCHMITT-TRIGGER
V

thr

V

thf

V

hys

C

I

INPUT RESET
t

RW

Digital outputs

system clock frequency − 16.9344 − MHz
system clock HIGH time 35 − 65 ns
system clock rise time 0.8 V to (VDD− 0.8 V) −−20 ns
system clock fall time (VDD− 0.8 V) to 0.8 V −−20 ns

LOW level input voltage −0.3 − 0.3V
HIGH level input voltage 0.7V

DD

− VDD+ 0.3 V

DD

V

input pull-up resistance VI=0V − 50 − kΩ
input capacitance −−10 pF

LOW level input voltage −0.3 − 0.3V
HIGH level input voltage 0.7V
input pull-down resistance VI=V

DD

− 50 − kΩ

DD

− VDD+ 0.3 V

DD

V

input capacitance −−10 pF

switching threshold voltage rising −−0.8V
switching threshold voltage falling 0.2V

DD

−− V

DD

V

hysteresis voltage − 0.33VDD− V
input capacitance −−10 pF

RESET pulse width; active LOW 236 −− ns

O

UTPUTS: FILL, S_NSF, RSB AND SSD; PUSH-PULL

V

OL

V

OH

C

L

t

r

LOW level output voltage IOL=4mA 0 − 0.4 V
HIGH level output voltage IOL= −4mA VDD− 0.4 − V
load capacitance −−50 pF
output rise time 0.8 V to (VDD− 0.8 V);

−−15 ns

CL=50pF

t

f

output fall time (VDD− 0.8 V) to 0.8 V;

−−15 ns

CL=50pF
OUTPUTS: SDO, SCLO, WCO, WE, OE, RAS, CAS, A0 TO A9; SLEW RATE PUSH-PULL
V

OL

V

OH

C

L

t

r

LOW level output voltage IOL=4mA 0 − 0.4 V
HIGH level output voltage IOL= −4mA VDD− 0.4 − V
load capacitance −−50 pF
output rise time 0.8 V to (VDD− 0.8 V);

−−20 ns

CL=50pF
t

f

output fall time (VDD− 0.8 V) to 0.8 V;

−−20 ns

CL=50pF

July 1994 12

DD

DD

V

V

Philips Semiconductors Preliminary specification

Shock absorbing RAM addresser SAA7346

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

OUTPUT KILLOUT; OPEN DRAIN
V

OL

I

O

C

L

t

f

INPUTS/OUTPUTS:D0TO D3; NORMAL CMOS WITH SLEW RATE CONTROLLED PUSH-PULL
V

IL

V

IH

I

LI

C

I

V

OL

V

OH

C

L

t

r

t

f

INPUT/OUTPUT SIDA; NORMAL CMOS WITH PUSH-PULL
V

IL

V

IH

I

LI

C

I

V

OL

V

OH

C

L

t

r

t

f

2

S timing

I

LOW level output voltage IOL=2mA 0 − 0.4 V
output current −−2mA
load capacitance −−50 pF
output fall time (VDD− 0.8 V) to 0.8 V;

−−30 ns

CL=50pF

LOW level input voltage −0.3 − 0.3V
HIGH level input voltage 0.7V
input leakage current VI=0VtoV

DD

−10 − +10 µA

DD

− VDD+ 0.3 V

DD

V

input capacitance −−10 pF
LOW level output voltage IOL=4mA 0 − 0.4 V
HIGH level output voltage IOL= −4mA VDD− 0.4 − V

DD

V
load capacitance −−50 pF
output rise time 0.8 V to (VDD− 0.8 V);

−−20 ns

CL=50pF

output fall time (VDD− 0.8 V) to 0.8 V;

−−20 ns

CL=50pF

LOW level input voltage −0.3 − 0.3V
HIGH level input voltage 0.7V
input leakage current VI=0VtoV

DD

−10 − +10 µA

DD

− VDD+ 0.3 V

DD

V

input capacitance −−10 pF
LOW level output voltage IOL=4mA 0 − 0.4 V
HIGH level output voltage IOL= −4mA VDD− 0.4 − V

DD

V
load capacitance −−50 pF
output rise time 0.8 V to (VDD− 0.8 V);

−−15 ns

CL=50pF

output fall time (VDD− 0.8 V) to 0.8 V;

−−15 ns

CL=50pF

RECEIVER (SEE FIG.9)

Clock input SCLI

T

cy

t

H

t

L

clock cycle time 118.1
clock HIGH time 41.3
clock LOW time 41.3

Inputs: SDI and WCI

t

su

t

h

set-up time 23.6 −− ns
hold time 10 −− ns

July 1994 13

(1)
(1)

(1)

236.2

(2)

−− ns

−− ns

472.4

(3)

ns

Philips Semiconductors Preliminary specification

Shock absorbing RAM addresser SAA7346

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

TRANSMITTER (SEE FIG.8)

Clock output SCLO

T

cy

t

H

t

L

clock cycle time − 472.4
clock HIGH time 165.3 −− ns
clock LOW time 165.3 −− ns

Outputs: SDO and WCO

t

d

t

h

delay time −−377 ns
hold time 40 −− ns

Microcontroller interface timing (see Figs 12 and 13)

I

NPUTS: SICL AND SILD

t

H

t

L

t

r

t

f

input HIGH time 180 −− ns
input LOW time 180 −− ns
rise time 0.8 V to (VDD− 0.8 V) −−240 ns
fall time (VDD− 0.8 V) to 0.8 V −−240 ns

Read mode (see Fig.12)

t

d

t

pd

delay time SILD to SIDA valid 120 −− ns
propagation delay time SICL to SIDA −−110 ns

Write mode (see Fig.13)

t
t
t

su1
h
su2

set-up time SIDA to SICL 40 −− ns
hold time SICL to SIDA −−180 ns
set-up time SICL to SILD 180 −− ns

(3)

944.8

(4)

ns

July 1994 14

Philips Semiconductors Preliminary specification

Shock absorbing RAM addresser SAA7346

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
DRAM interface timing (see Figs 14 and 15)

T

cy

t

CAC

t

OAC

t

h3

t

RH

t

RL

t

h1

t

h2

t

CL

t

h4

t

CRd

t

RCd

t

Rd

t

su1

t

RAh

t

su2

t

CAh

t

Rh

t

l

t

RCh

t

RRh

t

Wsu

t

Wh1

t

WL

t

Wh2

t

WCl

t

WRl

t

Dsu

t

Dh

t

DRh

Notes

1. n = 4.

2. n = 2.

3. n = 1.

4. n =1⁄2.

read or write cycle time 160 −− ns
access time from CAS −−20 ns
access time from OE −−20 ns
OE to data input hold time 0 −− ns
RAS HIGH time 70 −− ns
RAS LOW time 80 − 10000 ns
RAS hold time 20 −− ns
RAS hold time to OE LOW 20 −− ns
CAS LOW time 20 − 10000 ns
CAS hold time 80 −− ns
delay time from CAS HIGH to RAS 10 −− ns
delay time from RAS to CAS 25 −− ns
RAS to column address delay time 20 −− ns
row address set-up time 0 −− ns
row address hold time 15 −− ns
column address set-up time 0 −− ns
column address hold time 20 −− ns
column address hold time from RAS

60 −− ns

LOW
column address to RAS lead time 40 −− ns
read command hold time 0 −− ns
read command hold time to RAS 12 −− ns
write command set-up time 0 −− ns
write command hold time 15 −− ns
write command LOW time 15 −− ns
write command hold time from RAS 60 −− ns
write command to CAS lead time 20 −− ns
write command to RAS lead time 20 −− ns
data output set-up time 0 −− ns
data output hold time 15 −− ns
data output hold time from RAS 60 −− ns

July 1994 15

Philips Semiconductors Preliminary specification

Shock absorbing RAM addresser SAA7346

T

handbook, full pagewidth

SCLI

SDI
WCI

cy

t

L

t

su

Fig.8 I2S input timing.

t

H

V – 0.8 V

DD

0.8 V

t

h

V – 0.8 V

DD

0.8 V

MGB436

handbook, full pagewidth

handbook, full pagewidth

SCLI

WCI

T

SCLO

SDO
WCO

cy

t

L

t

H

Fig.9 I2S output timing.

LEFT CHANNEL RIGHT CHANNEL

µ5.67 s

t
t

h
d

V – 0.8 V

DD

0.8 V

V – 0.8 V

DD

0.8 V

MGB435

4.2336 MHz

88.2 kHz

SDI

MSB

LSB LSBMSB

Fig.10 Typical I2S data input waveform; f = 4.2 MHz; n = 2.

July 1994 16

MGB437

Philips Semiconductors Preliminary specification

Shock absorbing RAM addresser SAA7346

handbook, full pagewidth

SCLO

2.1168 MHz

WCO

SDO

MSB

handbook, full pagewidth

SILD

SICL

SIDA

LEFT CHANNEL RIGHT CHANNEL

µ11.34 s

LSB LSBMSB

Fig.11 Typical I2S data output waveform; f = 2.1 MHz; n = 1.

t

f

t

d

r

t

pd

tt

f

t

L

t

H

V – 0.8 V

DD

0.8 V

V – 0.8 V

DD

0.8 V

MGB439

t

r

V – 0.8 V

DD

0.8 V

44.1 kHz

MGB438

Fig.12 Microcontroller timing; READ mode.

July 1994 17

Philips Semiconductors Preliminary specification

Shock absorbing RAM addresser SAA7346

handbook, full pagewidth

SILD

SICL

SIDA

t

f

t

L

t

su1

t

H

t

h

t

r

V – 0.8 V

DD

0.8 V

V – 0.8 V

DD

0.8 V

t

su2

MGB440

Fig.13 Microcontroller timing; WRITE mode.

t

f

t

L

t

r

V – 0.8 V

DD

0.8 V

July 1994 18

This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in

_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in

white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...

July 1994 19

T

RAS

CAS

A0

to

A9

t

su1

t

CRd

t

t

RAh

t

Rd

RCd

RL

t

t

CAh

cy

h4

t

h1

t

CL

t

l

V – 0.8V

DD

0.8 V

t

t

Rh

t

su2

COLUMNROW

t

t

RH

RRh

t

CRd

V – 0.8V

DD

0.8 V

t

RCh

V – 0.8V

DD

0.8 V

Philips Semiconductors Preliminary specification

Shock absorbing RAM addresser SAA7346

WE

OE

t

h2

t

OAC

t

CAC

D0 to D3 INPUT

handbook, full pagewidth

Fig.14 READ cycle timing.

t

h3

V – 0.8V

DD

0.8 V

MGB441

V – 0.8V

DD

0.8 V

Philips Semiconductors Preliminary specification

Shock absorbing RAM addresser SAA7346

T

handbook, full pagewidth

RAS

CAS

t

su1

A0

to

A9

t

CRd

t

RAh

t

Rh

t

RCd

t

Rd

t

su2

COLUMNROW

cy

t

RL

t

h4

t

h1

t

CL

t

Rl

t

CAh

V – 0.8V

DD

0.8 V

t

RH

t

V – 0.8V

0.8 V

CRd

DD

V – 0.8V

DD

0.8 V

WE

OE

t

Wsu

t

Wh2

t

DRh

t

Dsu

D0 to D3 OUTPUT

t

Wh1

t

WL

t

RWI

V – 0.8V

DD

0.8 V

t

WCI

V – 0.8V

DD

t

Dh

V – 0.8V

DD

0.8 V

MGB442

Fig.15 WRITE cycle timing.

July 1994 20

Philips Semiconductors Preliminary specification

Shock absorbing RAM addresser SAA7346

APPLICATION INFORMATION

handbook, full pagewidth

CFLG

KILL

2

I S bus from

CD decoder

5 V

16.9 MHz
CLKIN

OTD
RCD2

SSD

V

DD

100 nF

44 43 38 37 36 35
1
2
3

4
5
6
7

8
9

10
11

S_NSF

D3 to D0 WE CAS RAS OE A9 to A0

39

to

42

SAA7346

micro-

controller

interface

5 V

1 M x 4 bit

DRAM

Ω10k

2

I S bus
to DAC

2221201918171615141312

25 to 34

24
23

MGB443

100 nF

V

DD

RESET

RSB

Fig.16 SAA7346 application diagram.

July 1994 21

KILLOUT

Philips Semiconductors Preliminary specification

Shock absorbing RAM addresser SAA7346

PACKAGE OUTLINE

handbook, full pagewidth

seating

plane

0.1 S

12.9

12.3

44

1

pin 1 index

11

12

34

22

S

1.2
(4x)

0.8

33

0.8

0.40

23

0.20

B

10.1

9.9

12.9

12.3

B

0.15 M

1.2

0.25

0.05

0.8

A

(4x)

detail X

0.95

0.55

0.85

0.75

X

0.25

0.14

0 to 10

2.10

1.70

o

Dimensions in mm.

0.8

0.40

0.20

0.15 M A

10.1

9.9

1.85

1.65

MBB944 - 2

Fig.17 Plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 × 10 × 1.75 mm; (SOT307-2; QFP44).

July 1994 22

Philips Semiconductors Preliminary specification

Shock absorbing RAM addresser SAA7346

SOLDERING
Plastic quad flat-packs

YWAVE

B
During placement and before soldering, the component

must be fixed with a droplet of adhesive. After curing the
adhesive, the component can be soldered. The adhesive
can be applied by screen printing, pin transfer or syringe
dispensing.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder bath is
10 s, if allowed to cool to less than 150 °C within 6 s.
Typical dwell time is 4 s at 250 °C.

A modified wave soldering technique is recommended
using two solder waves (dual-wave), in which a turbulent
wave with high upward pressure is followed by a smooth
laminar wave. Using a mildly-activated flux eliminates the
need for removal of corrosive residues in most
applications.

B

Y SOLDER PASTE REFLOW

Reflow soldering requires the solder paste (a suspension
of fine solder particles, flux and binding agent) to be

applied to the substrate by screen printing, stencilling or
pressure-syringe dispensing before device placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt, infrared, and
vapour-phase reflow. Dwell times vary between 50 and
300 s according to method. Typical reflow temperatures
range from 215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 min at 45 °C.

EPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING

R

IRON OR PULSE

-HEATED SOLDER TOOL)

Fix the component by first soldering two, diagonally
opposite, end pins. Apply the heating tool to the flat part of
the pin only. Contact time must be limited to 10 s at up to
300 °C. When using proper tools, all other pins can be
soldered in one operation within 2 to 5 s at between 270
and 320 °C. (Pulse-heated soldering is not recommended
for SO packages.)

For pulse-heated solder tool (resistance) soldering of VSO
packages, solder is applied to the substrate by dipping or
by an extra thick tin/lead plating before package
placement.

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

July 1994 23

Philips Semiconductors – a worldwide company

Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428)

BUENOS AIRES, Tel. [phone], Fax. [phone]

Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]

Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213,

Tel. [phone], Fax. [phone]

Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands,

Tel. [phone], Fax. [phone]

Brazil: Rua do Rocio 220 - 5

CEP: 04552-903-SÃO PAULO-SP, Brazil.
P.O. Box 7383 (01064-970).
Tel. [phone], Fax. [phone]

Canada: INTEGRATED CIRCUITS:

Tel. [phone], Fax. [phone]
DISCRETE SEMICONDUCTORS: 601 Milner Ave,
SCARBOROUGH, ONTARIO, M1B 1M8,
Tel. [phone] ext. 2336, Fax. [phone]

Chile: Av. Santa Maria 0760, SANTIAGO,

Tel. [phone], Fax. [phone]

Colombia: IPRELENSO LTDA, Carrera 21 No. 56-17,

77621 BOGOTA, Tel. [phone],
Fax. [phone]

Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,

Tel. [phone], Fax. [phone]

Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. [phone], Fax. [phone]

France: 4 Rue du Port-aux-Vins, BP317,

92156 SURESNES Cedex,
Tel. [phone], Fax. [phone]

Germany: PHILIPS COMPONENTS UB der Philips G.m.b.H.,

P.O. Box 10 63 23, 20043 HAMBURG,
Tel. [phone], Fax. [phone].

Greece: No. 15, 25th March Street, GR 17778 TAVROS,

Tel. [phone] 911, Fax. [phone]

Hong Kong: PHILIPS HONG KONG Ltd., Components Div.,

6/F Philips Ind. Bldg., 24-28 Kung Yip St., KWAI CHUNG, N.T.,
Tel. [phone], Fax. [phone]

India: Philips INDIA Ltd, Components Dept,

Shivsagar Estate, A Block ,
Dr. Annie Besant Rd. Worli, Bombay 400 018
Tel. [phone], Fax. [phone]

Indonesia: Philips House, Jalan H.R. Rasuna Said Kav. 3-4,

P.O. Box 4252, JAKARTA 12950,
Tel. [phone], Fax. [phone]

Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. [phone], Fax. [phone]

Italy: PHILIPS COMPONENTS S.r.l.,

Viale F. Testi, 327, 20162 MILANO,
Tel. [phone], Fax. [phone].

Japan: Philips Bldg13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,

Tel. [phone], Fax. [phone]

Korea: (Republic of) Philips House, 260-199 Itaewon-dong,

Yongsan-ku, SEOUL, Tel. [phone], Fax. [phone]

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA,

SELANGOR, Tel. [phone], Fax. [phone]

Mexico: Philips Components, 5900 Gateway East, Suite 200,

EL PASO, TX 79905, Tel. [phone], Fax. [phone]

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB

Tel. [phone], Fax. [phone]

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]

th

floor, Suite 51,

Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

Pakistan: Philips Electrical Industries of Pakistan Ltd.,

Exchange Bldg. ST-2/A, Block 9, KDA Scheme 5, Clifton,
KARACHI 75600, Tel. [phone],
Fax. [phone].

Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Portugal: PHILIPS PORTUGUESA, S.A.,

Rua dr. António Loureiro Borges 5, Arquiparque - Miraflores,
Apartado 300, 2795 LINDA-A-VELHA,
Tel. [phone], Fax. [phone].

Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,

Tel. [phone], Fax. [phone]

South Africa: S.A. PHILIPS Pty Ltd., Components Division,

195-215 Main Road Martindale, 2092 JOHANNESBURG,
P.O. Box 7430 Johannesburg 2000,
Tel. [phone], Fax. [phone].

Spain: Balmes 22, 08007 BARCELONA,

Tel. [phone], Fax. [phone]

Sweden: Kottbygatan 7, Akalla. S-164 85 STOCKHOLM,

Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,

Tel. [phone], Fax. [phone]

Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West

Road, Sec. 1. Taipeh, Taiwan ROC, P.O. Box 22978,
TAIPEI 100, Tel. [phone], Fax. [phone].

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,

209/2 Sanpavuth-Bangna Road Prakanong,
Bangkok 10260, THAILAND,
Tel. [phone], Fax. [phone].

Turkey:Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,

Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Limited, P.O. Box 65,

Philips House, Torrington Place, LONDON, WC1E 7HD,
Tel. [phone], Fax. [phone]

United States:INTEGRATED CIRCUITS:

811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone], Fax. [phone]
DISCRETE SEMICONDUCTORS: 2001 West Blue Heron Blvd.,

P.O. Box 10330, RIVIERA BEACH, FLORIDA 33404,
Tel. [phone] and [phone], Fax. [phone]

Uruguay: Coronel Mora 433, MONTEVIDEO,

Tel. [phone], Fax. [phone]

For all other countries apply to: Philips Semiconductors,
International Marketing and Sales, Building BAF-1,
P.O. Box 218, 5600 MD, EINDHOVEN, The Netherlands,
Telex 35000 phtcnl, Fax. [phone]

SCD31 © Philips Electronics N.V. 1994

All rights are reserved. Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation
or contract, is believed to be accurate and reliable and may be changed without
notice. No liability will be accepted by the publisher for any consequence of its
use. Publication thereof does not convey nor imply any license under patent- or
other industrial or intellectual property rights.

Printed in The Netherlands

513061/1500/01/pp24 Date of release: July 1994
Document order number: 9397 736 30011

Philips Semiconductors