Datasheet SAA7191B Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

SAA7191B

Digital Multistandard Colour
Decoder, Square Pixel
(DMSD-SQP)

Product specification
File under Integrated Circuits, IC22

August 1996

Philips Semiconductors Product specification

Digital Multistandard Colour Decoder,
Square Pixel (DMSD-SQP)

CONTENTS

1 FEATURES
2 GENERAL DESCRIPTION
3 QUICK REFERENCE DATA
4 ORDERING INFORMATION
5 BLOCK DIAGRAM
6 PINNING
7 FUNCTIONAL DESCRIPTION
8 LIMITING VALUES
9 CHARACTERISTICS
10 I2C-BUS FORMAT
11 PROGRAMMING EXAMPLE
12 PACKAGE OUTLINE
13 SOLDERING
14 DEFINITIONS
15 LIFE SUPPORT APPLICATIONS
16 PURCHASE OF PHILIPS I2C COMPONENTS

SAA7191B

August 1996 2

Philips Semiconductors Product specification

Digital Multistandard Colour Decoder,
Square Pixel (DMSD-SQP)

1 FEATURES

• Separate 8-bit luminance (Y or CVBS) and 8-bit
chrominance inputs (CVBS or C) from CVBS, Y/C,
S-Video (S-VHS or Hi8) sources

• Luminance and chrominance signal processing for
standards PAL-B/G, NTSC-M, SECAM

• Horizontal and vertical sync detection for all standards

• Real-time control output RTCO to be used for

frequency-locked digital video encoder (SAA7199B).
RTCO contains serialized information about actual clock
frequency, subcarrier frequency and PAL/SECAM
sequence.

2

• Controls via the I

• User programmable aperture correction (horizontal

peaking)

• Compatible with memory-based features (line-locked
clock)

• Cross-colour reduction by chrominance comb-filtering
(NTSC) or by special cross colour cancellation
(SECAM)

• 8-bit quantization of input signals

• 768/640 active samples per line equals 50/60 Hz (SQP)

• The YUV bus supports data rates of 780 × fH equal to

12.2727 MHz for 60 Hz (NTSC-M) and 944 × fH equal to

14.75 MHz for 50 Hz (PAL-B/G, SECAM) in 4 : 1 : 1 or
4:2:2 formats (via the I2C-bus)

• One crystal oscillator of 26.8 MHz

C-bus

SAA7191B

2 GENERAL DESCRIPTION

The SAA7191B is a digital multistandard colour decoder
suitable for 8-bit CVBS input signals or for 8-bit luminance
and 8-bit chrominance input signals (Y/C).

The SAA7191B is down-compatible with SAA7191. The
SAA7191B has additional outputs RTCO, GPSW0 and
ODD. These new outputs are in high-impedance state
when NFEN-bit = 0.

3 QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V

DD

I

DD

V

IL

V

OL

T

amb

positive supply voltage (pins 5, 18, 28, 37 and 52) 4.5 5 5.5 V
total supply current (pins 5, 18, 28, 37 and 52) 100 250 mA
input levels TTL-compatible
output levels TTL-compatible
operating ambient temperature 0 - 70 °C

4 ORDERING INFORMATION

EXTENDED TYPE

NUMBER

PINS PIN POSITION MATERIAL CODE

PACKAGE

SAA7191B 68 PLCC plastic SOT188-2

August 1996 3

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August 1996 4

handbook, full pagewidth

+5 V

V to V

DD1 DD4

5, 18. 28, 52 19, 38, 51, 67

V to V

SS1 SS4

PLIN

66

RTCO

68

internally

connected

44 1, 2

test pins

SAA7191B

5 BLOCK DIAGRAM

Digital Multistandard Colour Decoder,

Square Pixel (DMSD-SQP)

Philips Semiconductors Product specification

CVBS7 to
CVBS0

CHR7 to
CHR0

GPSW0
GPSW1
GPSW2

SDA

IICSA

RESN

14 to 17
20 to 23

6 to 13

65
24

25

40

41

INPUT

INTERFACE

LUMINANCE

PROCESSOR

PORT AND

STATUS

REGISTER

2

I C-BUS

CONTROL

43 29

3

clock
status

26 39

HCL HSY VS

CHROMINANCE PROCESSOR

SYNCHRONIZATION

30 31 32

HS

Fig.1 Block diagram.

Fig.1 Block diagram.

HL

36

LFCO

ODD

OUTPUT

INTERFACE

CLOCK

4

CREF27LLC

45 to 50, 53, 54

55 to 62

Y output
(Y7 to Y0)

UV output
(UV7 to UV0)

42
63

64
37

35

33

34

+5 V

HREF
FEON

FEIN
V

DDA

V

SSA

XTAL
XTALI

SAA7191B

MEH435

Philips Semiconductors Product specification

Digital Multistandard Colour Decoder,

SAA7191B

Square Pixel (DMSD-SQP)

6 PINNING

SYMBOL PIN DESCRIPTION

SP 1 connected to ground (shift pin for testing)
AP 2 connected to ground (action pin for testing)
RESN 3 reset, active LOW
CREF 4 clock reference, sync from external to ensure in-phase signals on the YUV-bus
V

DD1

CHR0 6
CHR1 7
CHR2 8
CHR3 9
CHR4 10
CHR5 11
CHR6 12
CHR7 13
CVBS0 14
CVBS1 15
CVBS2 16
CVBS3 17
V

DD2

V

SS1

CVBS4 20
CVBS5 21
CVBS6 22
CVBS7 23
GPSW1 24 Port 1 output for general purpose (programmable)
GPSW2 25 Port 2 output for general purpose (programmable)
HCL 26 black level clamp pulse (programmable), e.g. for TDA8708 (ADC)
LLC 27 line-locked clock input signal (29.5 MHz for 50 Hz system; 24.5454 MHz for 60 Hz system)
V

DD3

HSY 29 horizontal sync indicator output signal (programmable), e.g. for TDA8708 (ADC)
VS 30 vertical sync output signal
HS 31 horizontal sync output signal (programmable)
HL 32 horizontal lock flag, HIGH = PLL locked
XTAL 33 26.8 MHz clock output
XTALI 34 26.8 MHz connection for crystal or external oscillator (TTL compatible squarewave)
V

SSA

LFCO 36 line frequency control output signal, multiple of horizontal frequency (7.375 MHz/6.136363 MHz)
V

DDA

V

SS2

ODD 39 odd/even field identification output (odd = HIGH); active only at NFEN-bit = 1
SDA 40 I

5 +5 V supply input 1

chrominance input data bits CHR7 to CHR0
from a Y/C (VHS, Hi8) source in two’s complement format

luminance respectively CVBS lower input data bits CVBS3 to CVBS0
(CVBS with luminance, chrominance and all sync information in two’s complement format)

18 +5 V supply input 2
19 ground 1 (0 V)

luminance respectively CVBS upper input data bits CVBS7 to CVBS4
(CVBS with luminance, chrominance and all sync information in two’s complement format)

28 +5 V supply input 3

35 analog ground

37 +5 V supply input for analog part
38 ground 2 (0 V)

2

C-bus data line

August 1996 5

Philips Semiconductors Product specification

Digital Multistandard Colour Decoder,

SAA7191B

Square Pixel (DMSD-SQP)

SYMBOL PIN DESCRIPTION

SCL 41 I2C-bus clock line
HREF 42 horizontal reference output for valid YUV data (for active line 768Y or 640Y samples long)
IICSA 43 set module address input (LOW = 1000 101X; HIGH = 1000 111X)
i.c. 44 internally connected
Y7 45
Y6 46
Y5 47
Y4 48
Y3 49
Y2 50
V

SS3

V

DD4

Y1 53
Y0 54
UV7 55
UV6 56
UV5 57
UV4 58
UV3 59
UV2 60
UV1 61
UV0 62
FEON 63 output active flag (active LOW when Y and UV data in high-impedance state)
FEIN 64 fast enable input (active LOW to control fast switching due to YUV data)
GPSW0 65 Port 0 output for general purpose (programmable); active only at NFEN-bit = 1
PLIN 66 PAL flag (active LOW at inverted line); SECAM flag (LOW equals DR, HIGH equals DB line)
V

SS4

RTCO 68 real-time control output active at NFEN-bit = 1; Fig.8

Y signal output bits Y7 to Y2 (luminance), part of the digital YUV-bus

51 ground 3 (0 V)
52 +5 V supply input 4

Y signal output bits Y1 to Y0 (luminance), part of the digital YUV-bus

UV signal output bits UV7 to UV0 (colour-difference), part of the digital YUV-bus

67 ground 4 (0 V)

August 1996 6

Philips Semiconductors Product specification

Digital Multistandard Colour Decoder,
Square Pixel (DMSD-SQP)

6.1 Pin configuration

handbook, full pagewidth

UV6

UV1
UV0

FEON

FEIN

GPSW0

PLIN

V

SS4

RTCO

SP
AP

RESN

UV4

UV5

UV3

UV2

60

61
62
63

64
65

66
67
68

1

2
3

Y0

UV7

54 4950515253

5556575859

DD4VSS3

V

Y1

SAA7191B

Y2

Y3

Y4

Y5

Y6

Y7

SAA7191B

i.c.

4445464748

IICSA

43

HREF

42

41

SCL
SDA

40

39

ODD
V

38

SS2

V

37

DDA

36

LFCO
V

35

SSA

XTALI

34

XTAL

33

CREF

V

DD1

CHR0

CHR1
CHR2

CHR3

4
5

6

7

8
9

11

10 141312

CHR4

CHR5

CHR6

CHR7

15

16 2120191817 25242322

DD2

CVBS0

CVBS1

CVBS2

CVBS3

V

Fig.2 Pin configuration.

V

SS1

CVBS4

CVBS5

CVBS6

CVBS7

GPSW1

26

HCL

GPSW2

32

HL
HS

31

VS

30

HSY

29

V

28

DD3

LLC

27

MEH436

August 1996 7

Philips Semiconductors Product specification

Digital Multistandard Colour Decoder,
Square Pixel (DMSD-SQP)

7 FUNCTIONAL DESCRIPTION

7.1 Chrominance processor

The 8-bit chrominance input signal (CVBS or chrominance
format) passes a bandpass filter to eliminate DC
components and to decimate the sample rate before it is
fed to the two multipliers (quadrature demodulator), Fig.3.
Two subcarrier signals from a local oscillator (0 to 90
degree) are fed to the multiplicator inputs of the multipliers.
The multipliers operate as a quadrature demodulator for all
PAL and NTSC signals; it operates as a frequency
down-mixer for SECAM signals.
The two multiplier output signals are converted to a serial
data stream and applied to three low-pass filter stages,
then to a gain controlled amplifier. A final multiplexed
low-pass filter achieves, together with the preceding
stages, the required bandwidth performance. The signals,
originated from PAL and NTSC, are applied to a
comb-filter. The signals, originated from SECAM, are fed
through a Cloche filter (0 Hz centre frequency), a phase
demodulator and a differentiator to obtain
frequency-demodulated colour-difference signals.The
SECAM signals are fed after de-emphasis to a cross-over
switch, to provide the both serial-transmitted
colour-difference signals. These signals are fed finally to
the output formatter stages and to the output interface.

SAA7191B

August 1996 8

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August 1996 9

handbook, full pagewidth

CVBS (7-0)

CHR (7-0)

RTCO

68

INPUT

INTERFACE

CHROMINANCE

BANDPASS

HUEC
FISE
SECS
NFEN

QUADRATURE

DEMODULATOR

DISCRETE TIME

OSCILLATOR (DTO1)

AND DIVIDER

LOOP

FILTER

PI1

LOW­PASS

FILTER

FISECHRSBYPS

CKTS (4-0)
CHCV (7-0)
CKTO (4-0)
LFIS (1-0)
SECS

GAIN

CONTROLLED

AMPLIFIER

LOOP

FILTER

PI2

BURST GATE

ACCUMULATOR

CODE

LOW­PASS

FILTER

CLOCHE

FILTER

PHASE

DEMODULATOR

AND
AMPLITUDE
DETECTOR

QUAM COMB
FILTERS AND

SECAM

RECOMBINATION

SECS
HRMV

OUTPUT

FORMATTER

AND OUTPUT

INTERFACE

OFTS
COLO
OEDY
OEDC
OEHS

42
63
64

UV (7-0)
HREF
FEON
FEIN
Y (7-0)

Philips Semiconductors Product specification

Digital Multistandard Colour Decoder,

Square Pixel (DMSD-SQP)

PLIN

66

SAA7191B

PROCESSOR

PLSE(7-0)
SESE(7-0)
FISE
SECS

SEQUENCE

SEQA

DIFFERENTIATOR

SXCR

CHROMINANCE

DE-EMPHASIS

to luminance from luminance

Fig.3 Detailed block diagram; continued in Fig.4.

Fig.3(a) Detailed block diagram; continued in Fig.3(b).

SAA7191B

MEH437

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August 1996 10

from input interface

handbook, full pagewidth

to output interface

Philips Semiconductors Product specification

Digital Multistandard Colour Decoder,

Square Pixel (DMSD-SQP)

RESN

SCL

SDA

IICSA

SAMPLE RATE

CONVERTER

PREFILTER

SYNC

3

41

40

43

SAA7191B

2

I C-BUS

CONTROL

65,24,25

PREFILTER

PREF

SYNC SLICER

NFEN

LUMINANCE

PHASE DETECTOR

SYNC

CHROMINANCE

TRAP

BYPS

FISE

FINE

HRMV

HCLB (7-0)

SCEN

HCLS (7-0)

OEVS

HSYB (7-0)

OEHS

HSYS (7-0)

FISE

HPHI (7-0)
IDEL (7-0)

COUNTER

26 29 30 31 32

PHASE DETECTOR

VTRC

FISE

VARIABLE

BANDPASS

BPSS

(1-0)

COARSE

FILTER

PREF
BYPS

HLCK
STTC

VERTICAL

PROCESSOR

39

CORING

CORI (1-0)

MATCHING
AMPLIFIER

LOOP FILTER

HLCK
VTRC
HPLL

FISE

FISE

FIDT

VNOI (1-0)
HLCK
VTRC
FSEL
AUFD

NFEN

FISE

PROGRAMMABLE

DISCRETE TIME

OSCILLATOR

FISE

WEIGHTING

AND

ADDING STAGE

APER

(0-1)

DELAY

(DTO2)

DAC

36

internal clocks

VARIABLE DELAY

COMPENSATION

YDEL

(2-0)

LINE-LOCKED

CLOCK

GENERATOR

CRYSTAL

CLOCK

GENERATOR

4

CREF

27

LLC

33

XTAL

34

XTAL I

SAA7191B

GPSW(2-0)

HS

HCL

Fig.4 Detailed block diagram; continued from Fig.3.

Fig.3(b) Detailed block diagram; continued from Fig.3(a).

VSHSY

HL

ODD

LFCO

MEH438-1

Philips Semiconductors Product specification

Digital Multistandard Colour Decoder,
Square Pixel (DMSD-SQP)

7.2 Luminance processor

The luminance input signal, a digital CVBS format or an
8-bit luminance format (S-VHS, Hi8), is fed through a
sample rate converter to reduce the data rate to

14.75 MHz for PAL and SECAM (12.2727 MHz for NTSC),
Fig.4.

Sample rate is converted by means of a switchable
pre-filter. High frequency components are emphasized to
compensate for loss in the following chrominance trap
filter. This chrominance trap filter (fo= 4.43 MHz or

= 3.58 MHz centre frequency selectable) eliminates

f

o

most of the colour carrier signal, therefore, it must be
by-passed for S-Video (S-VHS and Hi8) signals.
The high frequency components of the luminance signal
can be “peaked” (control for sharpness improvement via
the I2C-bus) in two bandpass filters with selectable transfer
characteristic.
A coring circuit with selectable characteristic improves the
signal once more, this signal is then added to the original
(“unpeaked”) signal. A switchable amplifier achieves a
common DC amplification, because the DC gains are
different in both chrominance trap modes. The improved
luminance signal is fed to the variable delay
compensation.

7.3 Processing delay

The delay from input to output is 220 LLC cycles if YDEL
is set to 0. The processing delay will be influenced in future
enhancements.

7.4 Synchronization

SAA7191B

Table 1 Clock frequencies in MHz for 50/60 Hz systems

CLOCK 50 Hz 60 Hz

LLC 29.5 24.545454
LLC2 14.75 12.272727
LLC4 7.375 6.136136
LLC8 3.6875 3.068181

7.5 Line locked clock frequency

LFCO is required in an external PLL (SAA7197) to
generate the line locked clock frequency.

7.6 YUV-bus, digital outputs

The 16-bit YUV-bus transfers digital data from the output
interfaces to a feature box, or to the digital-to-analog
converter (DAC). Outputs are controlled via the I2C-bus in
normal selections, or they are controlled by output enable
chain (FEIN on pin 64, Fig.5). The YUV-bus data rate
equals LLC2 in Table 1. Timing is achieved by marking
each second positive rising edge of the clock LLC in
conjunction with CREF (clock reference).

YUV-bus formats 4:2:2 and 4:1:1
The output signals Y7 to Y0 are the bits of the digital

luminance signal. The output signals UV7 to UV0 are the
bits of the multiplexed colour-difference signals (B−Y) and
(R−Y). The frame in the following tables is the time,
required to transfer a full set of samples. In case of 4 :2:2
format two luminance samples are transmitted in
comparison to one U and one V sample within one frame.

The luminance output signal is fed to the synchronization
stage. Its bandwidth is reduced to 1 MHz in a low-pass
filter. The sync pulses are sliced and fed to the phase
detectors to be compared with the sub-divided clock
frequency.
The resulting output signal is applied to the loop filter to
accumulate all phase deviations. Adjustable output signals
(e. g. HCL and HSY) are generated according to peripheral
requirements (TDA8708A, TDA8709A). The output signals
HS, VS and PLIN are locked to the timing reference signal
HREF (Figures 7 and 8). There is no absolute timing
reference guaranteed between the input signal and the
HREF signal as further improvements to the circuit may
change the total processing delay. It is therefore not
recommended to use them for applications, which ask for
absolute timing accuracy to the input signals.
The loop filter signal drives an oscillator to generate the
line frequency control output signal LFCO.

August 1996 11

Philips Semiconductors Product specification

Digital Multistandard Colour Decoder,
Square Pixel (DMSD-SQP)

Table 2 4 : 2 : 2 format

(768 pixels per line for 50 Hz system; 640 pixels
per line for 60 Hz system)

OUTPUT PIXEL BYTE SEQUENCE

Y0 (LSB)
Y1
Y2
Y3
Y4
Y5
Y6
Y7 (MSB)

UV0 (LSB)
UV1
UV2
UV3
UV4
UV5
UV6
UV7(MSB)

Y frame 0 1 2 3 4 5
UV frame 0 2 4

Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7

U0
U1
U2
U3
U4
U5
U6
U7

Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7

V0
V1
V2
V3
V4
V5
V6
V7

Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7

U0
U1
U2
U3
U4
U5
U6
U7

Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7

V0
V1
V2
V3
V4
V5
V6
V7

Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7

U0
U1
U2
U3
U4
U5
U6
U7

SAA7191B

Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7

V0
V1
V2
V3
V4
V5
V6
V7

Notes

1. Data rate: LLC2

2. Sample frequency:
Y LLC2
U LLC4
V LLC4

The quoted frequencies are valid on the YUV-bus.
The time frames are controlled by the HREF signal.

August 1996 12

Philips Semiconductors Product specification

Digital Multistandard Colour Decoder,

SAA7191B

Square Pixel (DMSD-SQP)

Table 3 4 : 1 : 1 format (768 pixels per line for 50 Hz system and 640 pixels per line for 60 Hz system)

OUTPUT PIXEL BYTE SEQUENCE

Y0 (LSB)
Y1
Y2
Y3
Y4
Y5
Y6
Y7 (MSB)

UV0 (LSB)
UV1
UV2
UV3
UV4
UV5
UV6
UV7 (MSB)

Y frame 0 1 2 3 4 5 6 7
UV frame 0 4

Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7

0
0
0
0
V6
V7
U6
U7

Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7

0
0
0
0
V4
V5
U4
U5

Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7

0
0
0
0
V2
V3
U2
U3

Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7

0
0
0
0
V0
V1
U0
U1

Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7

0
0
0
0
V6
V7
U6
U7

Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7

0
0
0
0
V4
V5
U4
U5

Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7

0
0
0
0
V2
V3
U2
U3

Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7

0
0
0
0
V0
V1
U0
U1

Notes

1. Data rate: LLC2
sample frequency:
Y LLC2
U LLC8
V LLC8

Fast enable is achieved by setting input FEIN to LOW. This
signal is used to control fast switching on the digital
YUV-bus. HIGH on this pin forces the Y and U/V outputs
to a high-impedance state. The signal FEON is LOW when
the Y and U/V outputs are in this high-impedance state
(Fig.5).
The quoted frequencies are valid on the YUV-bus. The
time frames are controlled by the HREF signal.

Table 4 Digital output control

OEDY OEDC FEIN Y(7:0) UV(7:0) FEON

X
0
0
1
1

X
0
1
0
1

0
1
1
1
X

active
Z
Z
active
active

active
Z
active
Z
active

1
0
1
1
1

August 1996 13

Philips Semiconductors Product specification

Digital Multistandard Colour Decoder,
Square Pixel (DMSD-SQP)

handbook, full pagewidth

LLC

CREF

HREF

t

SU

FEIN

SAA7191B

from 3-stateto 3-state

t

HD

YUV

FEON

t

OH

Fig.5 Timing example of fast enable input FEIN.

t

OS

MEH441-1

August 1996 14

Philips Semiconductors Product specification

Digital Multistandard Colour Decoder,
Square Pixel (DMSD-SQP)

handbook, full pagewidth

LLC

CREF

internal
bus clock

HREF

Byte numbers for pixels:

Y signal

50 Hz

U and V signal

Y signal

60 Hz

U and V signal

U0

U0

start of
active line

0

0

V0

1

V0

1

U2

U2

SAA7191B

2

2

V2

V2

3

3

U4

U4

4

4

V4

V4

5

5

U6

U6

6

6

7

V6

7

V6

handbook, full pagewidth

LLC

CREF

HREF

Byte number for pixels:

Y signal

50 Hz

U and V signal

Y signal

60 Hz

U and V signal

762

U762

634

U634

763

V762

635

V634

764

U764

636

U636

765

V764

637

V636

end of
active line

766

U766

638

U638

MEH233-2

767

V766

639

V638

MEH234-3

Fig.6 Line control by HREF in 4:2:2 format for 50 Hz and 60 Hz systems.

August 1996 15

Philips Semiconductors Product specification

Digital Multistandard Colour Decoder,
Square Pixel (DMSD-SQP)

handbook, full pagewidth

(a) 1st field

input CVBS

HREF

VS

ODD

(b) 2nd field

input CVBS

HREF

VS

625123456789

313 314 315 316 317 318 319 320 321

SAA7191B

541 x 2/LLC

2 x 2/LLC

69 x 2/LLC

ODD

handbook, full pagewidth

(a) 1st field

input CVBS

HREF

VS

ODD

(b) 2nd field

input CVBS

HREF

VS

2 x 2/LLC

50 Hz

525123456789

2 x 2/LLC

263 264 265 266 267 268 269 270 271

59 x 2/LLC

MEH224-1

449x 2/LLC

ODD

60 Hz

Fig.7 Vertical timing diagram for 50 / 60 Hz.

August 1996 16

2 x 2/LLC

MEH225-1

Philips Semiconductors Product specification

Digital Multistandard Colour Decoder,
Square Pixel (DMSD-SQP)

handbook, full pagewidth

RTCO

(1)Sequence bit:

SECAM: 0 equals DB-line
1 equals DR-line
PAL: 0 equals (R-Y) line normal
1 equals (R-Y) line inverted
NTSC: 0 (no change)

(2) Reserve bits: 276 for 50 Hz systems; 188 for 60 Hz systems

H/L transition
(counter start)

128 clocks

13

0

HPLL

increment

bits 13 to 0

4

4 bits

reserve

0

14

198

bit
22

20

time slot

(LLC/4)

15

FSCPLL

increment

bits 21 to 0

10

not validvalid

SAA7191B

3 bits

sequence bit (1)

reserve

5

0

1

63

reserved (2)

67

MEH442

Fig.8 RTCO timing.

8 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134);
ground pins 19, 35, 38, 51 and 67 as well as supply pins 5, 18, 28, 37 and 52 connected together.

SYMBOL PARAMETER MIN. MAX. UNIT

V

DD

V

diff GND

V

I

V

O

P

tot

T

stg

T

amb

V

ESD

supply voltage (pins 5, 18, 28, 37, 52) −0.5 7.0 V
difference voltage V

SS A

− V

SS (1 to 4)

−±100 mV
voltage on all inputs −0.5 VDD+0.5 V
voltage on all outputs (I

= 20 mA) −0.5 VDD+0.5 V

O max

total power dissipation − 2.5 W
storage temperature range −65 150 °C
operating ambient temperature range 0 70 °C
electrostatic handling

(1)

for all pins −±2000 V

Note

1. Equivalent to discharging a 100 pF capacitor through an 1.5 kΩ series resistor.

August 1996 17

Philips Semiconductors Product specification

Digital Multistandard Colour Decoder,

SAA7191B

Square Pixel (DMSD-SQP)

9 CHARACTERISTICS

V

= 4.5 to 5.5 V; T

DD

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

DD

I

DD

2

C-bus, SDA and SCL (pins 40 and 41)

I

V

IL

V

IH

I

40,41

I

ACK

V

OL

supply voltage range (pins 5, 18, 28, 37, 52) 4.5 5 5.5 V
total supply current (pins 5, 18, 28, 37, 52) VDD= 5 V; inputs LOW;

input voltage LOW −0.5 − 1.5 V
input voltage HIGH 3 − VDD+0.5 V
input current −− ±10 µA
output current on pin 40 acknowledge 3 − -mA
output voltage at acknowledge I40=3mA −− 0.4 V

Data clock and control inputs (pins 3, 4, 6 to 17, 20 to 23, 27, 34, 43 and 64), Fig.11

V

IL

V

IH

V

IL

V

IH

I

LI

C

I

t

SU.DAT

t

HD.DAT

LLC input voltage LOW (pin 27)
LLC input voltage HIGH

other input voltage LOW
other input voltage HIGH

input leakage current −− 10 µA
input capacitance data inputs; note 1

input data set-up time Fig.9 11 −−ns
input data hold time 3 −−ns

LFCO output (pin 36)

V

o

V

36

output signal (peak-to-peak value) note 2 1.4 − 2.6 V
output voltage range 1 − V

YUV-bus, HREF and VS outputs (pins 30, 42, 45 to 50 and pins 53 to 62)

V

OL

V

OH

C

L

output voltage LOW notes 1 and 2 0 − 0.6 V
output voltage HIGH 2.4 − V
load capacitance 15 − 50 pF

Control outputs (pins 24 to 26, 29, 31, 32, 39, 63, 65, 66 and 68); Fig.12

V

OL

V

OH

C

L

output voltage LOW notes 1 and 2 0 − 0.6 V
output voltage HIGH 2.4 − V
load capacitance 7.5 − 25 pF

= 0 to 70 °C unless otherwise specified.

amb

outputs not connected

I/O high-ohmic
clock inputs

− 100 250 mA

−0.5

2.4−−

−0.5

2.0−−

−

−

−

−

−

−

0.6
VDD+0.5VV

0.8
VDD+0.5VV

8
8
10

DD

pF
pF
pF

V

Figures 10 and 15 to 25

DD

DD

V

V

August 1996 18

Philips Semiconductors Product specification

Digital Multistandard Colour Decoder,

SAA7191B

Square Pixel (DMSD-SQP)

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Timing of YUV-bus and control outputs

t

OH

t

OS

t

SZ

t

ZS

t

RTCO

output signal hold time YUV, HREF, VS at

output set-up time YUV, HREF, VS at

data output disable transition time to 3-state condition 16 −−ns
data output enable transition time from 3-state condition 14 −−ns
RTCO timing Fig.8

Chrominance PLL

f

C

catching range ±400 −−Hz

Crystal oscillator

f

n

∆f / f

nominal frequency 3rd harmonic − 26.8 − MHz
permissible deviation f

n

temperature deviation from f

n

n

X1 crystal specification:

temperature range T
load capacitance C
series resonance resistance R
motional capacitance C
parallel capacitance C

amb

L

S

1

0

Philips catalogue number 9922 520 30004

Line locked clock input LLC (pin 27)

t

LLC

t

p

t

r

t

f

cycle time note 3 31 − 45 ns
duty factor t
rise time −− 5ns
fall time −− 6ns

Notes

1. Data output signals are Y7 to Y0 and UV7 to UV0. All others are control output signals.

2. Levels are measured with load circuit. YUV-bus, HREF and VS outputs with 1.2 kΩ in parallel to 50 pF at 3 V (TTL
load); LFCO output with 10 kΩ in parallel to 15 pF and other outputs with 1.2 kΩ in parallel to 25 pF at 3 V (TTL load).

3. tSU, tHD, tOHand tODinclude trand tf.

Fig.8

CL= 15 pF
controls at C

CL= 50 pF;
controls at C

Fig.10

Fig.9

/ t

LLCH

LLC

13 −−ns

= 7.5 pF 13 −−ns

L

14 −−ns

= 25 pF 14 −−ns

L

−− ±50 10

−− ±20 10

0 − 70 °C
8 −−pF

− 50 80 Ω

− 1.1±20% − fF

− 3.5±20% − pF

40 − 60 %

−6

−6

August 1996 19

Philips Semiconductors Product specification

Digital Multistandard Colour Decoder,
Square Pixel (DMSD-SQP)

handbook, full pagewidth

t

LLC H

clock input LLC

t

SUtHD

input data

input CREF

t

output data

ZS

t

OS

t

OH

not valid

not valid

SAA7191B

t

LLC

2.4 V

1.5 V

0.6 V

t

f

t

r

2.0 V

0.8 V

2.0 V

0.8 V

t

t

SU

HD

2.4 V

0.6 V

input FEIN

handbook, full pagewidth

1 nF

t

SZ

t

SU

t

HD

Fig.9 Data input and output timing diagram.

26.8 MHz
(3rd harmonic)

X1

10 µH
± 20 %

10 pF

10 pF

XTAL

(1)

(1)

33

XTALI

34

(1) value depends on

crystal parameters

SAA7191B

XTAL

XTALI

33

SAA7191B

34

(a) (b)

Fig.10 Oscillator application (a) and optional clock from external source (b).

2.4 V

0.6 V

MEH231-1

MEH439

August 1996 20

Philips Semiconductors Product specification

Digital Multistandard Colour Decoder,
Square Pixel (DMSD-SQP)

handbook, full pagewidth

+127
+106

+95

-52

-64

-91

-103

-128

-132

0

reserved

luminance

PAL, SECAM

sync

luminance

NTSC

chrominance

PAL and SECAM

blanking level

chrominance

NTSC

+127

+76

0

-76

-128

chrominance

input range

(red, cyan 75 %)

SAA7191B

(a) CVBS7 to CVBS0 input signal range.

+255
+235

+128

+16

0

luminance

output range

white 100 %

black

(c) Y output signal range.

1. All levels are related to EBU colour bar.

2. Values in decimal at 100% luminance and 75% chrominance amplitude.

+255

+212

+128

U-component

output range

+44

0

(d) U output signal range (B-Y).

(b) CHR7 to CHR0 input signal range.

+255

blue 75 %

yellow 75 %

+212

+128

+44

0

V-component

output range

(e) V output signal range (R-Y).

red 75 %

cyan 75 %

MEH254-1

Fig.11 Input and output signal ranges.

August 1996 21

Philips Semiconductors Product specification

Digital Multistandard Colour Decoder,
Square Pixel (DMSD-SQP)

handbook, full pagewidth

CVBS

HSY

HSY
programming
range
(step size:
2/LLC)

HCL

HCL

programming
range
(step size:
2/LLC)

+ 191

+ 127

62 x 2/LLC

processing delay CVBS - YUV

at YDEL = 000 b

220 LLC

0

0

SAA7191B

burst

– 64

– 128

10 x 2/LLC

Y-output

HREF (50 Hz)

PLIN (50 Hz )

HS (50 Hz)

HS (50 Hz)

programming range

(step size: 8/LLC)

HREF (60 Hz)

HS (60 Hz)

HS (60 Hz)
programming range

(step size: 8/LLC)

+ 97

38 x 2/LLC

0

38 x 2/LLC

0

176 x 2/LLC768 x 2/LLC

100 x 2/LLC

64 x 2/LLC

– 118+ 117

140 x 2/LLC640 x 2/LLC

64 x 2/LLC

– 97

MEH226-2

Fig.12 Horizontal sync at HRMV = 0 and HRFS = 0 for 50/60 Hz (signals HSY, HCL, HREF and PLIN).

August 1996 22

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August 1996 23

signal source selected by GPSW1-bit (LOW = source 1)

Ω

Ω

Ω

Ω

µF

0.22 µF

10

10 µF

Ω

1 µF

1 µF

680

1 µF

+

15

+

16

+

Ω

19

+

V

DDA

24

25

26

27

28

chrominance V , source 1

chrominance V , source 2

Y or CVBS V , source 1

Y or CVBS V , source 2

HSY

HCL

LLCA

i

i

2.2 k

5.6

i

i

Ω

Ω

75

75

75

75

0.1

analog

17

18

20

21

TDA8708A

22

23

ull pagewidth

14

CVBS0

13

CVBS1

12

CVBS2

11

CVBS3

10

9

8

V

DDO

7

V

DDD

6

CLK

5

CVBS4

4

CVBS3

3

CVBS2

2

CVBS7

1

120

Ω

digital

68

pF

0.1
µF

18

0.1

5.6

Ω

digital

14

CHR0

13

CHR1

12

CHR2

11

CHR3

10

9

8

V

DDO

7

V

DDD

6

CLK

5

CHR4

4

CHR5

3

CHR6

2

CHR7

1

120

0.1 µF

Ω

0.1

µF

68 pF

18

Ω

1 µF

+

V

DDA

1 k

5.6

15

16

17

18

19

20

21

TDA8709A

22

23

24

25

26

27

28

Ω

Ω

1 µF

+

1 µF

+

Ω

680

2.2 k

Ω

0.1 µF

0.1 µF

0.1

µF

µF

Ω

5.6

Ω

4.7 k

analog

2.7 k

Ω

Ω

CHR7

to

CHR0

CVBS7
CVBS0

Philips Semiconductors Product specification

Digital Multistandard Colour Decoder,

Square Pixel (DMSD-SQP)

to

+5 V (analog supply)

+5 V (digital supply)

SAA7191B

MEH443

Fig.13 Application circuit for analog-to-digital conversions.

Philips Semiconductors Product specification

Digital Multistandard Colour Decoder,
Square Pixel (DMSD-SQP)

V

SS

handbook, full pagewidth

XTAL: Philips 9922 520 30004

X1

10 pF

10 Hµ

1 nF

0.1 Fµ

0.1 Fµ

0.1 Fµ

0.1 Fµ

digital

+5 V

chrominance
CHR7 to CHR0

luminance

CVBS7 to CVBS0

26.8 MHz

10 pF

V

DD

CHR0
CHR1
CHR2
CHR3
CHR4
CHR5
CHR6
CHR7

L0
L1
L2
L3
L4
L5
L6
L7

reset

5167 38 19

5

18

28

52

6
7
8
9
10
11
12
13

14
15
16
17
20
21
22
23

33

34
3

27
4

24 25

36

i.c.

44 32

SAA7191B

66

horizontal

lock flag

HL

62
61
60
59
58
57
56
55

54
53
50
49
48
47
46
45
39
31
30
29
26

42
41
40

68
65
63

64
43

35
37

SAA7191B

ODD

HS
VS
HSY
HCL
HREF
SCL
SDA
RTCO
GPSW0

digital

UV7 to UV0

YUV-bus

Y7 to Y0

2

I C-bus

UV0
UV1
UV2
UV3
UV4
UV5
UV6
UV7

Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7

FEON
FEIN
IICSA

2
1

VSSA
VDDA

digital

LFCO

11

S1
S2

RESN

LLCA

CREF

LLCB
LLC2A
LLC2B

19

16

12
7
15
10
14
20

Fig.14 Application circuit for digital multistandard colour decoder.

August 1996 24

PLIN

5
2
3
4
8

17

1

SAA7197

6

9
13
18

+5 V

0.1 Fµ

0.1 Fµ

0.1 Fµ

2.2 Hµ

0.1 Fµ

digital

0.1 Fµ
V

DD analog

+

10 Fµ

analog

V

DD digital

+5 V

+5 V

MEH440-1

Philips Semiconductors Product specification

Digital Multistandard Colour Decoder,

SAA7191B

Square Pixel (DMSD-SQP)

10 I2C-BUS FORMAT

S SLAVE ADDRESS A SUBADDRESS A DATA0 A DATAn A P

S = start condition
SLAVE ADDRESS = 1000 101X (IICSA = LOW) or 1000 111X (IICSA = HIGH)
A = acknowledge, generated by the slave
SUBADDRESS
DATA = data byte (Table 5)
P = stop condition

X = read/write control bit

Note

1. If more than 1 byte DATA are transmitted, then auto-increment of the subaddress is performed.

(1)

= subaddress byte (Table 5)

X = 0, order to write (the circuit is slave receiver)
X = 1, order to read (the circuit is slave transmitter)

2

Table 5 I

FUNCTION

status byte STTC HLCK FIDT X X X X CODE

Function of the bits:
STTC Horizontal time constant information for future application with logical combfilter only:

HLCK Horizontal PLL information: 0 = HPLL locked; 1 = HPLL unlocked
FIDT Field information: 0 = 50 Hz system detected; 1 = 60 Hz system detected
CODE Colour information: 0 = no colour detected; 1 = colour detected

C-bus; DATA for status byte (X = 1 in address byte; 8Bh at IICSA = LOW or 8Fh at IICSA = HIGH).

DATA

D7 D6 D5 D4 D3 D2 D1 D0

0 = TV time constant (slow);
1 = VCR time constant (fast)

August 1996 25

Philips Semiconductors Product specification

Digital Multistandard Colour Decoder,

SAA7191B

Square Pixel (DMSD-SQP)

Table 6 I2C-bus; subaddress and data bytes for writing (X = 0 in address byte; 8Ah at IICSA = LOW or 8Eh at

IICSA = HIGH).

FUNCTION SUBADDRESS

Increment delay
H sync begin, 50 Hz
H sync stop, 50 Hz

H clamp begin, 50 Hz
H clamp stop, 50 Hz
H sync after PHI1, 50 Hz

Luminance control
Hue control
Colour killer threshold QAM

Colour-killer threshold SECAM
PAL switch sensitivity
SECAM switch sensitivity

Chroma gain control settings
Standard/mode control
I/O and clock control

Control #1
Control #2
Chroma gain reference

Not used, is acknowledged
Not used, is acknowledged

H sync begin, 60 Hz
H sync stop, 60 Hz

H clamp begin, 60 Hz
H clamp stop, 60 Hz
H sync after PHI1, 60 Hz

D7 D6 D5 D4 D3 D2 D1 D0

00

IDEL7

01

HSYB7

02

HSYS7

03

HCLB7

04

HCLS7

05

HPHI7

06

BYPS

07

HUEC7

08

CKTQ4

09

CKTS4

0A

PLSE7

0B

SESE7

0C

COLO

0D

VTRC

0E

HPLL

0F

AUFD

10

0

11

CHCV7

12130

0

1415HS6B7

HS6S7

16

HC6B7

17

HC6S7

18

HP6I7

IDEL6
HSYB6
HSYS6

HCLB6
HCLS6
HPHI6

PREF
HUEC6
CKTQ3

CKTS3
PLSE6
SESE6

LFIS1
0
OEDC

FSEL
0
CHCV6

0
0

HS6B6
HS6S6

HC6B6
HC6S6
HP6I6

IDEL5
HSYB5
HSYS5

HCLB5
HCLS5
HPHI5

BPSS1
HUEC5
CKTQ2

CKTS2
PLSE5
SESE5

LFIS0
0
OEHS

SXCR
0
CHCV5

0
0

HS6B5
HS6S5

HC6B5
HC6S5
HP6I5

DATA

IDEL4
HSYB4
HSYS4

HCLB4
HCLS4
HPHI4

BPSS0
HUEC4
CKTQ1

CKTS1
PLSE4
SESE4

0
0
OEVS

SCEN
0
CHCV4

0
0

HS6B4
HS6S4

HC6B4
HC6S4
HP6I4

IDEL3
HSYB3
HSYS3

HCLB3
HCLS3
HPHI3

CORI1
HUEC3
CKTQ0

CKTS0
PLSE3
SESE3

0
NFEN
OEDY

OFTS
0
CHCV3

0
0

HS6B3
HS6S3

HC6B3
HC6S3
HP6I3

IDEL2
HSYB2
HSYS2

HCLB2
HCLS2
HPHI2

CORI0
HUEC2
0

0
PLSE2
SESE2

0
HRMV
CHRS

YDEL2
HRFS
CHCV2

0
0

HS6B2
HS6S2

HC6B2
HC6S2
HP6I2

IDEL1
HSYB1
HSYS1

HCLB1
HCLS1
HPHI1

APER1
HUEC1
0

0
PLSE1
SESE1

0
GPSW0
GPSW2

YDEL1
VNOI1
CHCV1

0
0

HS6B1
HS6S1

HC6B1
HC6S1
HP6I1

IDEL0
HSYB0
HSYS0

HCLB0
HCLS0
HPHI0

APER0
HUEC0
0

0
PLSE0
SESE0

0
SECS
GPSW1

YDEL0
VNOI0
CHCV0

0
0

HS6B0
HS6S0

HC6B0
HC6S0
HP6I0

Notes

1. Default values of register contents to obtain a picture see Table 6.

2. All unused control bits must be programmed with “0” (zero) as indicated in Table 5.

August 1996 26

Philips Semiconductors Product specification

Digital Multistandard Colour Decoder,

SAA7191B

Square Pixel (DMSD-SQP)

Function of the bits of Table 5

IDEL7
“00”

HSYB7
“01”

HSYS7
“02”

HCLB7
“03”

HCLS7
“04”

HPHI7
“05”

BYPS
“06”

− − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − −

PREF use of pre-filter: 0 = pre-filter off; 1 = pre-filter on;

− − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − −

BPSS1 to BPSS0 Aperture bandpass to select different characteristics with maximums

− − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − −

CORI1 to CORI0 Coring range for high frequency components according to 8-bit luminance, Fig.15.
“06” CORI1 CORI0 coring

to IDEL0 Increment delay time (dependent on application), step size = 4 / LLC. The delay time is

selectable from −4 / LLC (−1 decimal multiplier) to −1024 / LLC (−256 decimal multiplier)
equals data FF to 00 (hex). Different processing times in the chrominance channel and the
clock generation could result in phase errors in the chrominance processing by transients in
clock frequency . An adjustable delay (IDEL) is necessary if the processing time in the clock
generation is unknown.

to HSYB0 Horizontal sync begin for 50 Hz, step size = 2 / LLC. The delay time is selectable from

−382/LLC (+191 decimal multiplier) to +128/LLC (−64 decimal multiplier) equals data BF to
C0 (hex). Two’s complement numbers with “hidden” sign-bit. The sign-bit is generated
internally by evaluating the MSB and the MSB−1 bits.

to HSYS0 Horizontal sync stop for 50 Hz, step size = 2 / LLC. The delay time is selectable from

−382/LLC (+191 decimal multiplier) to +128/LLC (−64 decimal multiplier) equals data BF to
C0 (hex). Two’s complement numbers with “hidden” sign-bit. The sign-bit is generated
internally by evaluating the MSB and the MSB−1 bits.

to HCLB0 Horizontal clamp start for 50 Hz, step size = 2 / LLC. The delay time is selectable from

−254/LLC (+127 decimal multiplier) to +256/LLC (−128 decimal multiplier) equals data 7F to
80 (hex).

to HCLS0 Horizontal clamp stop for 50 Hz, step size = 2 / LLC. The delay time is selectable from

−254/LLC (+127 decimal multiplier) to +256/LLC (−128 decimal multiplier) equals data 7F to
80 (hex).

to HPHI0 Horizontal sync after PHI1 for 50 Hz, step size = 8 / LLC. The delay time is selectable from

−936 /LLC (+1 17 decimal multiplier) to +944/LLC (−1 18 decimal multiplier) equals data 75 to
8A (hex).

input mode select bit: 0 = CVBS mode (chrominance trap active)

1 = S-Video mode (chrominance trap bypassed)

PREF may be used if chrominance trap is active.

(0.2 to 0.3 × LLC / 2):
BPSS1 BPSS0 characteristics

0
0
1
1

0
0
1
1

0
1
0
1

0
1
0
1

)
)
)
)

coring off

±1 LSB
±2 LSB
±3 LSB

Figures 16 to 25

August 1996 27

Philips Semiconductors Product specification

Digital Multistandard Colour Decoder,

SAA7191B

Square Pixel (DMSD-SQP)

APER1 to APER0 Aperture bandpass filter weights high frequency components of luminance signal:
“06” APER1 APER0 factor

0
0
1
1

HUE7
“07”

CKTQ4
“08”

CKTS4
“09”

PLSE7
“0A”

SESE7
“0B”

COLO
“0C”

− − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − −

LFIS1 to LFIS0 Chrominance gain control (AGC filter):
“0C” LFIS1 LFIS0 loop filter time constant

VTRC
“0D”

− − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − −

NFEN SAA7191B-specified functions enable (RTCO, ODD and GPSW0 outputs)

− − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − −

HRMV HREF generation: 0 = like SAA7191; 1 = HREF is 8 x LLC2 clocks earlier
GPSWO General purpose switch 0: 0 = output pin 65 LOW; 1 = output pin 65 HIGH

− − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − −

SECS SECAM mode bit : 0 = other standards; 1 = SECAM

to HUE0 Hue control from +178.6° to −180.0°, equals data bytes 7F to 80 (hex); 0°equals 00.

to CKTQ0 Colour-killer threshold QAM from approximately −30 dB to −18 dB, equals data bytes

F8 to 07 (hex)

to CKTS0 Colour-killer threshold SECAM from approximately −30 dB to −18 dB, equals data bytes.

F8 to 07 (hex)

to PLSE0 PAL switch sensitivity from LOW-to-HIGH (HIGH means immediate sequence correction),

equals FF to 00 (hex), MEDIUM equals 80.

to SESE0 SECAM switch sensitivity from LOW-to-HIGH (HIGH means immediate sequence

correction), equals FF to 00 (hex), MEDIUM equals 80.
Colour on bit: 0 = automatic colour-killer enabled; 1 = forced colour on.

0
0
1
1

VTR/TV mode bit : 0 = TV mode (slow time constant); 1 = VTR mode (fast time constant)

0 = outputs set to high-impedance (circuit equals SAA7191); 1 = outputs active

0
1
0
1

0
1
0
1

=
=
=
=

0

)

0.25

)

0.5

)

1

)

slow
medium
fast
actual gain, stored for test purposes only

Figure 16 to 25

August 1996 28

Philips Semiconductors Product specification

Digital Multistandard Colour Decoder,

SAA7191B

Square Pixel (DMSD-SQP)

HPLL
“0E”

− − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − −

OEDC Colour-difference output

− − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − −

OEHS H-sync output enable (pins 31 and 42): 0 = HS and HREF outputs high-impedance

− − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − −

OEVS V-sync output enable (pin 30): 0 = VS output high-impedance

OEDY Luminance output enable:

− − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − −

CHRS S-VHS bit (chrominance from CVBS or from chrominance input):

− − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − −

GPSW2 to GPSW1 General purpose switches:
to “0E” GPSW2 GPSW1 set port output pins 24 (GPSW2) and 25 (GPSW1)

Horizontal clock PLL: 0 = PLL closed;

1 = PLL circuit open and horizontal frequency fixed.

0 = data outputs UV7 to UV0 can be set to

enable:

0 = data outputs Y7 to Y0 can be set to high-impedance via FEIN
1 = data outputs Y7 to Y0 active.

0 = controlled by BYPS-bit (subaddress 06)
1 = chrominance from chrominance input (CHR7 to CHR0)

0
0
1
1

0
1
0
1

high-impedance via FEIN

1 = data outputs UV7 to UV0 active.

1 = HS and HREF outputs active.

1 = VS output active.

use is dependent on
application

August 1996 29

Philips Semiconductors Product specification

Digital Multistandard Colour Decoder,

SAA7191B

Square Pixel (DMSD-SQP)

AUFD
“0F”

− − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − −

FSEL Field select (AUFD-bit = 0): 0 = 50 Hz (625 lines);

− − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − −

SXCR SECAM cross-colour reduction: 0 = reduction off;

− − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − −

SCEN Sync and clamping pulse enable: 0 = HCL and HSY outputs HIGH (pins 26 and 29);

− − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − −

OFTS Select output format: 0 = 4:1:1 format;

− − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − −

YDEL2 to YDEL0 Luminance delay compensation:

HFRS
“10”

Automatic field detection: 0 = field selection by FSEL-bit;

1 = automatic field detection.

1 = 60 Hz (525 lines)

1 = reduction on.

1 = HCL and HSY outputs active

1=4:2:2 format.

YDEL2 YDEL1 YDEL0 figure
0

0
0
0
1
1
1
1

Select HREF
position:

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0 = normal, HREF is matched to YUV output port;
1 = HREF is matched to CVBS input port.

0 × 2 / LLC
+1 × 2 / LLC
+2 × 2 / LLC step size = 2 / LLC =
+3 × 2 / LLC 67.8 ns for 50 Hz

−4 × 2 / LLC 81.5 ns for 60 Hz

−3 × 2 / LLC

−2 × 2 / LLC

−1 × 2 / LLC

− − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − −

VNOI1 to VNOI0 Vertical noise reduction

VNOI1 VNOI0 mode
0

0
1
1

CHCV7UVto CHCV0

“11”

August 1996 30

Chrominance gain control (nominal values) for QAM-modulated input signals, effects

D7 D6 D5 D4 D3 D2 D1 D0 gain
1111 1 1 11

::

0101 1 001

::

0010 1 100

::

0000 0 000

0
1
0
1

output amplitude (SECAM with fixed gain):

normal
searching window
auto-deflection
vertical noise reduction bypassed

maximum gain

to

CCIR level for PAL)

to

CCIR level for NTSC)

to

minimum gain

)
) default programmed
) values dependent
) on application
)

Philips Semiconductors Product specification

Digital Multistandard Colour Decoder,
Square Pixel (DMSD-SQP)

HS6B7
“14”

HS6S7
“15”

HC6B7
“16”

HC6S7
“17”

HP6I7
“18”

to HS6B0 Horizontal sync begin for 60 Hz, step size = 2 / LLC. The delay time is selectable from

−382/LLC (+191 decimal multiplier) to +128/LLC (−64 decimal multiplier) equals data BF to
C0 (hex). Two’s complement numbers with “hidden” sign-bit. The sign-bit is generated
internally by evaluating the MSB and the MSB−1 bits.

to HS6S0 Horizontal sync begin for 60 Hz, step size = 2 / LLC. The delay time is selectable from

−382/LLC (+191 decimal multiplier) to +128/LLC (−64 decimal multiplier) equals data BF to
C0 (hex). Two’s complement numbers with “hidden” sign-bit. The sign-bit is generated
internally by evaluating the MSB and the MSB−1 bits.

to HC6B0 Horizontal clamp begin for 60 Hz, step size=2/LLC. The delay time is selectable from

−254/LLC (+127 decimal multiplier) to +256/LLC (−128 decimal multiplier) equals data 7F
to 80 (hex).

to HC6S0 Horizontal clamp stop for 60 Hz, step size = 2 / LLC. The delay time is selectable from

−254/LLC (+127 decimal multiplier) to +256/LLC (−128 decimal multiplier) equals data 7F
to 80 (hex).

to HP6I0 Horizontal sync after PHI1 for 60 Hz, step size=8/LLC. The delay time is selectable from

−776/LLC (+97 decimal multiplier) to +776 /LLC (−97 decimal multiplier) equals data 61 to
9F (hex).

SAA7191B

handbook, full pagewidth

(a) CORI1 = 0; CORI0 = 1
(b) CORI1 = 1; CORI0 = 0
(c) CORI1 = 1; CORI0 = 1

bits

+64

+32

–32

–64

(c)

(b)

(a)

0

(a)

(b)

(c)

–32–64

0

MEH228

bits

+64+32

Fig.15 Coring function adjustment by subaddress 06 to affect the bandfilter output signal. The thresholds are

related to the 13-bit word width in the luminance processing part and influence the 1LSB to 3LSB
(Y0 to Y2) with respect to the 8-bit luminance output

August 1996 31

Philips Semiconductors Product specification

Digital Multistandard Colour Decoder,

SAA7191B

Square Pixel (DMSD-SQP)

63h

f (MHz)

MEH214

53h

73h

Y

handbook, full pagewidth

18

12

V

Y

(dB)

6

0

-6

-12

-18

-24

-30
01 32456

63h

73h

53h

43h

43h

Fig.16 Luminance control in 50 Hz / CVBS mode controllable by subaddress byte 06; pre-filter on and coring off;

maximum aperture bandpass filter characteristic.

42h

40h

MEH215

61h

f (MHz)

Y

handbook, full pagewidth

V

Y

(dB)

18

12

6

0

-6

-12

-18

-24

-30

01 32456

61h

62h

41h

42h

41h
62h

40h

Fig.17 Luminance control in 50 Hz / CVBS mode controllable by subaddress byte 06; pre-filter on and coring off;

other aperture bandpass filter characteristics.

August 1996 32

Philips Semiconductors Product specification

Digital Multistandard Colour Decoder,

SAA7191B

Square Pixel (DMSD-SQP)

13h

23h

f (MHz)

Y

MEH216

33h

00h

handbook, full pagewidth

18

12

V

Y

(dB)

6

0

-6

-12

-18

-24

-30
01 32456

23h

13h

00h

33h

03h

03h

Fig.18 Luminance control in 50 Hz / CVBS mode controllable by subaddress byte 06; pre-filter off and coring off;

maximum aperture bandpass filter characteristic.

53h

MEH217

f (MHz)

Y

andbook, full pagewidth

18

12

V

Y

(dB)

6

0

-6

-12

-18

-24

-30
01 32456

63h

73h

43h

53h

43h

63h

73h

Fig.19 Luminance control in 60 Hz / CVBS mode controllable by subaddress byte 06; pre-filter on and coring off;

maximum aperture bandpass filter characteristic.

August 1996 33

Philips Semiconductors Product specification

Digital Multistandard Colour Decoder,

SAA7191B

Square Pixel (DMSD-SQP)

42h

f (MHz)

Y

MEH218

handbook, full pagewidth

18

12

V

Y

(dB)

6

0

-6

-12

-18

-24

-30
01 32456

62h

61h

41h

50h

42h

43h

62h

50h

61h

Fig.20 Luminance control in 60 Hz / CVBS mode controllable by subaddress byte 06; pre-filter on and coring off;

other aperture bandpass filter characteristics.

13h

f (MHz)

Y

MEH219

handbook, full pagewidth

V

Y

(dB)

18

03h

00h

33h

03h

33h

23h

00h

12

6

0

-6

-12

-18

-24

-30
01 32456

23h

13h

Fig.21 Luminance control in 60 Hz / CVBS mode controllable by subaddress byte 06; pre-filter off and coring off;

maximum and minimum aperture bandpass filter characteristics.

August 1996 34

Philips Semiconductors Product specification

Digital Multistandard Colour Decoder,
Square Pixel (DMSD-SQP)

MEH220

83h

82h

80h

68

f (MHz)

Y

V

Y

(dB)

18

12

-6

-12

-18

handbook, halfpage

6

0

02

81h

4

V

Y

(dB)

18

12

-12

-18

handbook, halfpage

6

0

-6

02

C3h

C1h

4

SAA7191B

MEH221

C2h

C0h

68

f (MHz)

Y

Fig.22 Luminance control in 50 Hz / S-VHS mode

controllable by subaddress byte 06;
pre-filter off and coring off; different
aperture bandpass filter characteristics.

MEH222

82h

80h

68

f (MHz)

Y

V

Y

(dB)

18

12

-6

-12

-18

handbook, halfpage

6

0

02

83h

81h

4

Fig.23 Luminance control in 50 Hz / S-VHS mode

controllable by subaddress byte 06;
pre-filter on and coring off; different
aperture bandpass filter characteristics.

MEH223

C2h

68

f (MHz)

Y

V
(dB)

18

12

Y

-6

-12

-18

handbook, halfpage

6

0

02

C3h

C1h

C0h

4

Fig.24 Luminance control in 60 Hz / S-VHS mode

controllable by subaddress byte 06;
pre-filter off and coring off; different
aperture bandpass filter characteristics.

August 1996 35

Fig.25 Luminance control in 60 Hz / S-VHS mode

controllable by subaddress byte 06;
pre-filter on and coring off; different
aperture bandpass filter characteristics.

Philips Semiconductors Product specification

Digital Multistandard Colour Decoder,

SAA7191B

Square Pixel (DMSD-SQP)

11 PROGRAMMING EXAMPLE

Coefficients to set operation for application circuits Figures 13 and 14. (All numbers of the Table 6 are hex values).
Slave address byte is 8A at pin 43 = 0 V (or 8E at pin 43 = +5 V).

Table 7 Recommended default values

SUBADDRESS BIT NAME FUNCTION VALUE (HEX)

00
01
02

03
04
05

−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅ −⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅ −⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅ −⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−

06 BYPS, PREF, BPSS(1-0)

07
08
09

0A
0B
0C
0D

0E HPLL, OEDC, OEHS, OEVS

0F AUFD, FSEL, SXCR, SCEN,

10
11

12
13

−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅ −⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅ −⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅ −⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−

14
15

16
17
18

IDEL(7-0)
HSYB(7-0)
HSYS(7-0)

HCLB(7-0)
HCLS(7-0)
HPHI(7-0)

CORI(1-0), APER(1-0)
HUEC(7-0)
CKTQ(4-0)
CKTS(4-0)

PLSE(7-0)
SESE(7-0)
COLO, LFIS(1-0)
VTRC, NFEN,HRMV,
GPSW0 and SECS

OEDY, CHRS, GPSW(2-1)

OFTS, YDEL(2-0)
HRFS, VNOI(1-0)

CHCV(7-0)

−

−

HS6B(7-0)
HS6S(7-0)

HC6B(7-0)
HC6S(7-0)
HP6I(7-0)

increment delay
H sync beginning for 50 Hz
H sync stop for 50 Hz

H clamping beginning for 50 Hz
H clamping stop for 50 Hz
H sync position for 50 Hz

luminance bandwidth control:
hue control (0 degree)
colour-killer threshold QUAM
colour-killer threshold SECAM

PAL switch sensitivity
SECAM switch sensitivity
chroma gain control settings

standard/mode control

50
30
00

E8
B6
F4

01
00
F8
F8

90
90
00

00

(1)

(2)(4)

I/O and clock control 79, 7E

00
2C

00
00

34
0A

F4
CE
F4

(6)

(8)

miscellaneous control #1 91

miscellaneous control #2
chrominance gain nominal value

set to zero
set to zero

H sync beginning for 60 Hz
H sync stop for 60 Hz

H clamping beginning for 60 Hz
H clamping stop for 60 Hz
H sync position for 60 Hz

, 99

, 59

, 01

(5)

(3)(4)

(7)

(9)

Notes

1. dependent on application (Figures 16 to 25)

2. for QUAM standards

3. for SECAM

4. HPLL is in TV mode; value for VCR mode is 80
(81 for SECAM VCR mode)

5. for Y/C mode

6. 4:1:1 format

August 1996 36

7. 4:2:2 format

8. nominal value for UV CCIR level with NTSC source

9. nominal value for UV CCIR level with PAL source

Philips Semiconductors Product specification

Digital Multistandard Colour Decoder,
Square Pixel (DMSD-SQP)

12 PACKAGE OUTLINE

PLCC68: plastic leaded chip carrier; 68 leads

e

y

61

68

1

pin 1 index

D

X

4460

SAA7191B

SOT188-2

e

E

A

Z

E

43

b

p

b

1

w M

H

E

E

e

A

A

1

A

4

(A )

3

k

9

β

1

27

k

10 26

e

Z

D

H

D

D

v M

A

B

v M

B

0 5 10 mm

scale

DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)

UNIT A

mm

0.180

inches

0.165

A

1

min. max. max. max. max.

4.57

0.51

4.19

0.020

A

0.25

0.01

A

4

3

3.30

0.13

b

0.53

0.33

0.021

0.013

b

p

1

0.81

0.66

0.032

0.026

(1)

D

24.33

24.13

0.958

0.950

(1)

E

eH

e

D

1.27

0.05

23.62

22.61

0.930

0.890

24.33

24.13

0.958

0.950

e

23.62

22.61

0.930

0.890

H

D

E

25.27

25.27

25.02

25.02

0.995

0.995

0.985

0.985

Note

1. Plastic or metal protrusions of 0.01 inches maximum per side are not included.

OUTLINE
VERSION

SOT188-2

IEC JEDEC EIAJ

112E10 MO-047AC

REFERENCES

k

1

k

E

1.22

1.07

0.048

0.042

0.51

0.020

L

1.44

1.02

0.057

0.040

detail X

p

EUROPEAN

PROJECTION

L

p

(1) (1)

Z

Z

E

D

ywv β

0.18 0.100.18

0.007 0.0040.007

2.16

0.085

2.16

0.085

o

45

ISSUE DATE

92-11-17
95-03-11

August 1996 37

Philips Semiconductors Product specification

Digital Multistandard Colour Decoder,
Square Pixel (DMSD-SQP)

13 SOLDERING

13.1 Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“IC Package Databook”

13.2 Reflow soldering

Reflow soldering techniques are suitable for all PLCC
packages.

The choice of heating method may be influenced by larger
PLCC packages (44 leads, or more). If infrared or vapour
phase heating is used and the large packages are not
absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our

Reference Handbook”

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.

(order code 9398 652 90011).

“Quality

(order code 9397 750 00192).

SAA7191B

13.3 Wave soldering

Wave soldering techniques can be used for all PLCC
packages if the following conditions are observed:

• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.

• The longitudinal axis of the package footprint must be
parallel to the solder flow.

• The package footprint must incorporate solder thieves at
the downstream corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

13.4 Repairing soldered joints

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.

August 1996 38

Philips Semiconductors Product specification

Digital Multistandard Colour Decoder,

SAA7191B

Square Pixel (DMSD-SQP)

14 DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

15 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

16 PURCHASE OF PHILIPS I

Purchase of Philips I
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.

2

C COMPONENTS

2

C components conveys a license under the Philips’ I2C patent to use the

August 1996 39

Philips Semiconductors – a worldwide company

Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

Tel. [phone], Fax. [phone]
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. [phone], Fax. [phone]

Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,
Tel. [phone], Fax. [phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. [phone]

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. [phone], Fax. [phone]

Colombia: see South America
Czech Republic: see Austria
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,

Tel. [phone], Fax. [phone]
Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. [phone], Fax. [phone]
France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex,

Tel. [phone], Fax. [phone]
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,

Tel. [phone], Fax. [phone]
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,

Tel. [phone], Fax. [phone]

Hungary: see Austria
India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd.

Worli, MUMBAI 400 018, Tel. [phone], Fax. [phone]

Indonesia: see Singapore
Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. [phone], Fax. [phone]
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,

TEL AVIV 61180, Tel. [phone], Fax. [phone]
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,

20124 MILANO, Tel. [phone], Fax. [phone]
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,

Tel. [phone], Fax. [phone]
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,

Tel. [phone], Fax. [phone]
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,

Tel. [phone], Fax. [phone]
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,

Tel. [phone]

Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. [phone], Fax. [phone]

South America: Rua do Rocio 220, 5th floor, Suite 51,
04552-903 São Paulo, SÃO PAULO - SP, Brazil,
Tel. [phone], Fax. [phone]

Spain: Balmes 22, 08007 BARCELONA,
Tel. [phone], Fax. [phone]

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone], Fax. [phone]

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. 1997 SCA54
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

Printed in The Netherlands 657027/00/01/pp40 Date of release: August 1996 Document order number: 9397 750 02437