Datasheet SAA7186 Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

SAA7186

Digital video scaler

Preliminary specification
File under Integrated Circuits, IC22

May 1993

Philips Semiconductors Preliminary specification

Digital video scaler SAA7186

CONTENTS

1 FEATURES
2 GENERAL DESCRIPTION
3 QUICK REFERENCE DATA
4 ORDERING INFORMATION
5 BLOCK DIAGRAM
6 PINNING
7 FUNCTIONAL DESCRIPTION
8 OPERATION CYCLE
9I
10 LIMITING VALUES
11 DC CHARACTERISTICS
12 AC CHARACTERISTICS
13 PROCESSING DELAYS
14 PROGRAMMING EXAMPLE
15 PACKAGE OUTLINE
16 SOLDERING
17 DEFINITIONS
18 LIFE SUPPORT APPLICATIONS
19 PURCHASE OF PHILIPS I2C COMPONENTS

2

C-BUS FORMAT

May 1993 2

Philips Semiconductors Preliminary specification

Digital video scaler SAA7186

1 FEATURES

• Scaling of video picture windows down to randomly
sized windows

• Processes maximum 1023 pixels per line and 1023 lines
per field

• Two-dimensional data processing for improved signal
quality of scaled video data and for compression of
video data

• 16-bit YUV input data buffer

• Interlace/non-interlace video data processing and field

control

• Line memories in Y path and UV path to store two lines,
each with 2 × 768 × 8 bit capacity

• Vertical sync processing by scale control

• Non-scaled mode to get full picture or to gate videotext

lines

• UV input and output data binary/two’s complement

• Switchable RGB matrix and anti-gamma ROMs

• 16-word FIFO register for 32-bit output data

• Output formats: 5-bit and 8-bit RGB, 8-bit YUV or 8-bit

monochrome

2 GENERAL DESCRIPTION

The CMOS circuit SAA7186 scales and filters digital video
data to randomly sized picture windows. YUV input data in
4:2:2 format are required (SAA7191B source).

3 QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V

DD

I

DD tot

V

I

V

O

supply voltage 4.5 5 5.5 V
total supply current (inputs LOW, without output load) - - 180 mA
data input level TTL-compatible

data output level TTL-compatible
LLC input clock frequency - - 32 MHz
T

amb

operating ambient temperature range 0 - 70 °C

4 ORDERING INFORMATION

EXTENDED TYPE

NUMBER

PINS PIN POSITION MATERIAL CODE

PACKAGE

SAA7186 100 QFP plastic SOT317-2

May 1993 3

Philips Semiconductors Preliminary specification

Digital video scaler SAA7186

5 BLOCK DIAGRAM

HFL

port output

RGB or YUV

48

REGISTER

15

CHROMA

U

INCADR

49

56 to 64

68 to 75, 77

output pins (1):

KEYER

V

INTERPOLATOR

1

80 to 88

92 to 100

LNQ

HREFD

2

n.c.

4, 6,

i.c.

54, 60, 66, 72, 79, 84, 90, 96

9, 15, 21, 27, 29, 39, 34, 41, 52,

3, 16, 28, 42,

SS8

to V

SS1

V

53, 65, 78, 89

SAA7186

8

AP

MEH422-1

DD8

V
to

DD1

5, 14, 26,40,

V

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+5 V

BTST

VOEN

VLCK

50

47

51

8

RGB

MATRIX

Y

55, 67, 76, 91

VRO (31 to 0);

OUTPUT

OUTPUT

FORMATTER

8

8

BY

FOLLOWED

ANTI-GAMMA

V

U

32-bit VRAM

FIFO

ROMs

ARITHMETIC

LINE

VERTICAL FILTER

(2x8x768)

MEMORY

FILTER

LUMINANCE

DECIMATION

Y

33

25

to 22

to 30

YIN

(7-0)

VERTICAL FILTER

DATA

INPUT

BUFFER

20

LINE

MEMORY

CHROMA

DECIMATION

UV

13

to 10

to 17

UVIN

(7-0)

ARITHMETIC

(2x8x768)

FILTER

SCALE CONTROL

37

38

HREF

VS

43

RESN

controls

2

I C

45

SCL

CLOCK

7

363546

GENERATION

status

CONTROL

44

SDA

SP

IICSA

CREF

LLC

(1) without pins 60, 72, 84 and 96,

these pins are not connected

Fig.1 Block diagram.

Fig.1 Block diagram.

May 1993 4

Philips Semiconductors Preliminary specification

Digital video scaler SAA7186

6 PINNING

SYMBOL PIN STATUS DESCRIPTION

LNQ 1 O line qualifier signal; active polarity defined by QPL-bit in “10” (VCLK strobed)
HREFD 2 O delay-compensated HREF output signal (VCLK strobed)
V

SS1

i.c. 4 − internally connected
V

DD1

i.c. 6 − internally connected
SP 7 I connected to ground (shift pin for testing)
AP 8 I connected to ground (action pin for testing)
n.c. 9 − not connected
UVIN0 10 I
UVIN1 11 I
UVIN2 12 I
UVIN3 13 I
V

DD2

n.c. 15 − not connected
V

SS2

UVIN4 17 I
UVIN5 18 I
UVIN6 19 I
UVIN7 20 I
n.c. 21 − not connected
YIN0 22 I
YIN1 23 I
YIN2 24 I
YIN3 25 I
V

DD3

n.c. 27 − not connected
V

SS3

n.c. 29 − not connected
YIN4 30 I
YIN5 31 I
YIN6 32 I
YIN7 33 I
n.c. 34 − not connected
CREF 35 I clock reference, external sync signal
LLC 36 I line-locked system clock input signal (twice of pixel rate)
HREF 37 I horizontal reference, pixel data clock signal (also present during vertical blanking)
VS 38 I vertical sync input signal (approximately 6 lines long)
n.c. 39 − not connected
V

DD4

3 − GND1 (0 V)

5 − +5 V supply voltage 1

time-multiplexed colour-difference input data (bits 0 to 3)

14 − +5 V supply voltage 2

16 − GND2 (0 V)

time-multiplexed colour-difference input data (bits 4 to 7)

luminance input data (bits 0 to 3)

26 − +5 V supply voltage 3

28 − GND3 (0 V)

luminance input data (bits 4 to 7)

40 − +5 V supply voltage 4

May 1993 5

Philips Semiconductors Preliminary specification

Digital video scaler SAA7186

SYMBOL PIN STATUS DESCRIPTION

n.c. 41 − not connected
V

SS4

RESN 43 I reset input (active-LOW for at least 30LLC periods)
SDA 44 I/O IIC-bus data line
SCL 45 I IIC-bus clock line
IICSA 46 I set module address input of IIC-bus (LOW = B8, HIGH = BC)
BTST 47 I output disable input; HIGH sets all data outputs to high-impedance state
INCADR 48 O line increment / vertical reset control output line
HFL 49 O FIFO register half-full flag output
VOEN 50 I VRAM port output enable input (active-LOW)
VCLK 51 I FIFO register clock input signal
n.c. 52 − not connected
V

SS5

n.c. 54 − not connected
V

DD5

VRO31 56 O
VRO30 57 O
VRO29 58 O
VRO28 59 O
n.c. 60 − not connected
VRO27 61 O
VRO26 62 O
VRO25 63 O
VRO24 64 O
V

SS6

n.c. 66 − not connected
V

DD6

VRO23 68 O
VRO22 69 O
VRO21 70 O
VRO20 71 O
n.c. 72 − not connected
VRO19 73 O

VRO17 75 O
V

DD7

VRO16 77 O video output; 32-bit VRAM output port (bit16)
V

SS7

n.c. 79 − not connected

42 − GND4 (0 V)

53 − GND5 (0 V)

55 − +5 V supply voltage 5

video output; 32-bit VRAM output port (bits 31 to 28)

video output; 32-bit VRAM output port (bits 27 to 24)

65 − GND6 (0 V)

67 − +5 V supply voltage 6

video output; 32-bit VRAM output port (bits 23 to 22)

video output; 32-bit VRAM output port (bits 21 to 20)

video output; 32-bit VRAM output port (bits 19 to 17)VRO18 74 O

76 − +5 V supply voltage 7

78 − GND7 (0 V)

May 1993 6

Philips Semiconductors Preliminary specification

Digital video scaler SAA7186

SYMBOL PIN STATUS DESCRIPTION

VRO15 80 O
VRO14 81 O
VRO13 82 O
VRO12 83 O
n.c. 84 − not connected
VRO11 85 O
VRO10 86 O
VRO9 87 O
VRO8 88 O
V

SS8

n.c. 90 − not connected
V

DD8

VRO7 92 O
VRO6 93 O
VRO5 94 O
VRO4 95 O
n.c. 96 − not connected
VRO3 97 O
VRO2 98 O
VRO1 99 O
VRO0 100 O

89 O GND8 (0 V)

91 − +5 V supply voltage 8

video output; 32-bit VRAM output port (bits 15 to 12)

video output; 32-bit VRAM output port (bits 11 to 8)

video output; 32-bit VRAM output port (bits 7 to 4)

video output; 32-bit VRAM output port (bits 3 to 0)

May 1993 7

Philips Semiconductors Preliminary specification

Digital video scaler SAA7186

6.1 Pin configuration

handbook, full pagewidth

SS8

DD8

VRO7

92

n.c.

V

VRO9

V

91

VRO8

88

90

87

89

VRO10

VRO11

85

86

n.c.

84

VRO12

83

VRO13

VRO14

81

82

80
79
78
77
76
75
74
73
72
71
70
69
68

67
66
65
64

63
62
61
60
59
58
57
56
55
54
53
52

51

VRO15
n.c.
V

SS7

VRO16
V

DD7

VRO17
VRO18
VRO19

n.c.
VRO20
VRO21
VRO22
VRO23

V

DD6

n.c.

V

SS6

VRO24
VRO25

VRO26
VRO27

n.c.
VRO28
VRO29
VRO30
VRO31
V

DD5

n.c.

V

SS5

n.c.
VCLK

LNQ
HREFD.

V

SS1

i.c.
V

DD1

i.c.
SP.
AP
n.c.
UVIN0
UVIN1

UVIN2

UVIN3
V

DD2

n.c.

V

SS2

UVIN4
UVIN5
UVIN6
UVIN7

n.c.
YIN0
YIN1

YIN2
YIN3
V

DD3

n.c.
V

SS3

n.c.
YIN4

VRO0

99

100

VRO1

VRO2

98

VRO3

97

n.c.

96

VRO4

95

VRO5

94

VRO6

93

1
2
3
4
5
6
7
8

9
10
11
12

13

14
15

SAA7186

16
17

18
19

20
21

22

23

24
25

26
27

28

29
30

31

YIN5

32

YIN6

33

YIN7

34

n.c.

35

CREF

36

LLC

37

HREF

40

39

38

DD4VSS4

n.c.

V

VS

Fig.2 Pin configuration.

May 1993 8

41

n.c.

47

BTST

49

48

HFL

INCADR

VOEN

MEH421

45

46

44

43

42

RESN

SDA

SCL

IICSA

50

Philips Semiconductors Preliminary specification

Digital video scaler SAA7186

7 FUNCTIONAL DESCRIPTION

The input port is output of Philips digital video
multistandard decoders (SAA7151B, SAA7191B) or other
similar sources.
The SAA7186 input supports the 16-bit YUV 4:2:2 format.
The video data from the input port are converted into a
unique internal two’s complement data stream and are
processed in horizontal direction in two separate
decimation filters. Then they are processed in vertical
direction by the vertical processing unit (VPU).
Chrominance data are interpolated to a 4:4:4 format; a
chroma keying bit is generated.
The 4:4:4 YUV data are then converted from the YUV to
the RGB domain in a digital matrix. ROM tables in the RGB
data path can be used for anti-gamma correction of
gamma-corrected input signals.
Uncorrected RGB and YUV signals can be bypassed.
A scale control unit generates reference and gate signals
for scaling of the processed video data. After data
formatting to the various VRAM port formats, the scaled
video data are buffered in the 16 word× 32-bit output FIFO
register. The FIFO output is directly connected to the
VRAM output bus VRO(31-0). Specific reference signals
support an easy memory interfacing.
All functions of the SAA7186 are controlled via I2C-bus
using 17 subaddresses. The external microcontroller can
get information by reading the status register.

7.1 Video input port

The 16-bit YUV input data in 4:2:2 format (Table 1) consist
of 8-bit luminance data Y (pins YIN(7-0)) and 8-bit
time-multiplexed colour-difference data UV (pins
UVIN(7-0)).
The input data are clocked in by the signals LLC and
CREF (Fig.3). HREF and VS inputs define the video scan
pattern (window).

Sequential input data

• are limited to maximum 768 active pixels per line if the
vertical filter is active

• UV can be processed in straight binary and two’s
complement representation (controlled by TCC)

7.2 Decimation filters

The decimation filters perform accurate horizontal filtering
of the input data stream.
Signal characteristics are matched in front of the pixel
decimation stage, thus disturbing artifacts, caused by the
pixel dropping, are reduced. The signal bandwidth can be
reduced in steps of:

2-tap filter = −6 dB at 0.325 pixel rate
3-tap filter = −6 dB at 0.25 pixel rate
4-tap filter = −6 dB at 0.21 pixel rate
5-tap filter = −6 dB at 0.125 pixel rate
9-tap filter = −6 dB at 0.075 pixel rate

The different characteristics are chosen dependent on the
defined scaling parameters in an adaptive filter mode
(AFS-bit = 1).
The filter characteristics can also be selected
independently by control bits HF2 to HF0 at AFS-bit = 0.

7.3 Vertical filters

Y and UV data are handled in separate filters (Fig.1). Each
of the two line memories has a capacity of 2 × 768 × 8-bit.
Thus two complete video lines of 4:2:2 YUV data can be
stored. The VPU is split into two memory banks and one
arithmetic unit. The available processing modes,
respectively transfer functions, are selectable by the bits
VP1 and VP0 if AFS = 0.
An adaptive mode is selected by AFS = 1. Disturbing
artifacts, generated by line dropping, are reduced.

Adaptive filter selection (AFS = 1):

SCALING RATIO

XD/XS horizontal

≤1
≤14/15
≤11/15
≤7/15
≤3/15

YD/YS vertical

≤1
≤13/15
≤4/15

bypassed
filter 1
filter 6
filter 3
filter 4

bypassed
filter 1
filter 2

FILTER FUNCTION

(REFER TO I

2

C SECTION)

May 1993 9

Philips Semiconductors Preliminary specification

Digital video scaler SAA7186

7.4 RGB matrix

Y data and UV data are converted after interpolation into
RGB data according to CCIR601 recommendation. Data
are bypassed in YUV or monochrome modes.

Table 1 4 : 2 : 2 format (pixels per line). The time frames

are controlled by the HREF signal.

INPUT PIXEL BYTE SEQUENCE

YIN7
YIN6
YIN5
YIN4
YIN3
YIN2
YIN1
YIN0

UVIN7
UVIN6
UVIN5
UVIN4
UVIN3
UVIN2
UVIN1
UVIN0

Y frame 0 1 2 3 4
UV frame 0 2 4

Note

1. e = even pixel; o = odd pixel

The matrix equations are these considering the digital
quantization:

R=Y+1.375 V
G=Y− 0.703125 V − 0.34375 U
B=Y+1.734375 U.

Anti-gamma ROM tables:
ROM tables are implemented at the matrix output to
provide anti-gamma correction of the RGB data. A curve
for a gamma of 1.4 is implemented

The tables can be used (RTB-bit = 0) to compensate
gamma correction for linear data representation of RGB
output data.

Ye7
Ye6
Ye5
Ye4
Ye3
Ye2
Ye1
Ye0

Ue7
Ue6
Ue5
Ue4
Ue3
Ue2
Ue1
Ue0

Yo7
Yo6
Yo5
Yo4
Yo3
Yo2
Yo1
Yo0

Ve7
Ve6
Ve5
Ve4
Ve3
Ve2
Ve1
Ve0

Ye7
Ye6
Ye5
Ye4
Ye3
Ye2
Ye1
Ye0

Ue7
Ue6
Ue5
Ue4
Ue3
Ue2
Ue1
Ue0

Yo7
Yo6
Yo5
Yo4
Yo3
Yo2
Yo1
Yo0

Ve7
Ve6
Ve5
Ve4
Ve3
Ve2
Ve1
Ve0

Ye7
Ye6
Ye5
Ye4
Ye3
Ye2
Ye1
Ye0

Ue7
Ue6
Ue5
Ue4
Ue3
Ue2
Ue1
Ue0

7.5 Chrominance signal keyer

The keyer generates an alpha signal to achieve a 5-5-5 +α
RGB alpha output signal. Therefore, the processed UV
data amplitudes are compared with thresholds set via
I2C-bus (subaddresses ”0C to 0F”). A logical “1” signal is
generated if the amplitude is inside the specified amplitude
range, otherwise a logical “0” is generated.
Keying can be switched off by setting the lower limit higher
than the upper limit (“0C or 0E” and “0D or 0F”).

7.6 Scale control and vertical regions

The scale control block SC includes vertical
address/sequence counters to define the current position
in the input field and to address the internal VPU
memories.
To perform scaling, XD of XS pixel selection in horizontal
direction and YD of YS line selection in vertical direction
are applied. The pixel and line dropping are controlled at
the input of the FIFO register. To control the decimation
filter function and the vertical data processing in the
adaptive mode (AFS = 1), the scaling ratio in horizontal
and vertical direction is estimated in the SC block.

The input field can be divided into two vertical regions

− the bypass region and the scaling region, which are
defined via I
YS.

Vertical bypass region:
Data are not scaled and independent of I2C-bits FS1, FS0

the output format is always 8-bit greyscale (monochrome).
The SAA7186 outputs all active pixels of a line, defined by
the HREF input signal if the vertical bypass region is
active. This can be used, for example, to store videotext
information in the field memory.

The start line of the bypass region is defined by VS; the
number of lines to be bypassed is defined by VC.

Vertical scaling region:
Data is scaled with start at line YO and the output format

is selected when FS1, FS0 are valid.
This is the “normal operation” area.

The input/output screen dimensions in horizontal and
vertical direction are defined by the parameters

XO, XS and XD for horizontal

2

C-bus by the parameters VS, VC, YO and

May 1993 10

YO, YS and YD for vertical.

The circuit processes XS samples of a line. Remaining
pixels are ignored if a line is longer than XS. If a line is

Philips Semiconductors Preliminary specification

Digital video scaler SAA7186

shorter than XS, processing is aborted when the falling
edge of HREF is detected.

Vertical regions in Fig.4:

• the two regions can be programmed via I2C-bus,
whereby regions should not overlap (active region
overrides the bypass region).

• the start of a normal active picture depends on video
standard and has to be programmed to the correct
value.

handbook, full pagewidth

Byte numbers for pixles:

Y signal

LLC

CREF

HREF

0

start of
active line

1

• the offsets XO and YO have to be set according to the
internal processing delays to ensure the complete
number of destination pixels and lines (Table 6).

• the scaling parameters can be used to perform a
panning function over the video frame/field.

2

3

4

5

6

7

U and V signal

handbook, full pagewidth

Byte number for pixels:

LLC

CREF

HREF

Y signal

U and V signal

n – 5

Un-5

U0

n – 4

Vn-5

V0

n – 3

Un-3

U2

n – 2

Vn-3

V2

n – 1

Un-1

end of
active line

Fig.3 Horizontal and data multiplex timing.

U4

n

Vn-1

V4

U6

V6

MEH411

MEH410

May 1993 11

Philips Semiconductors Preliminary specification

Digital video scaler SAA7186

7.7 Output data representation and levels

Output data representation of the YUV data can be
modified by bit MCT (subaddress 10).
The DC gain is 1 for YUV input data. The corresponding
RGB levels are defined by the matrix equations. The
luminance levels are limited according to CCIR 601

16 (239) = black

235 (20) = white

(..) = greyscale luminance levels
if the YUV or monochrome luminance output formats are
selected.

handbook, full pagewidth

vertical sync

vertical bypass start

VS

bypass region

The signal levels of the RGB formats are limited in 8-bit to
“0” or “255”. For the 5-bit RGB formats a truncation from
8-bit to 5-bit is implemented.

Fill values are inserted dependent on longword position
and destination size:

• “0” in RGB formats and for Y two’s complement U, V

• “128” for U, V (straight binary)

• “255” in 8-bit greyscale format

The unused output values of the YUV and greyscale
formats can be used for other purposes.

vertical

blanking

YO

first valid line

vertical bypass count
equals VS

scaling region start

scaling region

Fig.4 Vertical regions.

scaling region count
equals YS Y-size source

MEH357-1

May 1993 12

Philips Semiconductors Preliminary specification

Digital video scaler SAA7186

Table 2 VRAM port output data formats at EFE-bit = 0 dependent on FS1 and FS0 bits (set via I2C-bus)

PIXEL

OUTPUT

BITS

PIXEL
ORDER n n+2n+4n n+2n+4n n+1n+2

VRO31
VRO30
VRO29
VRO28

VRO27
VRO26
VRO25
VRO24

VRO23
VRO22
VRO21
VRO20

VRO19
VRO18
VRO17
VRO16

PIXEL
ORDER n+1n+3n+5n+1n+3n+5 OUTPUTS NOT USED

VRO15
VRO14
VRO13
VRO12

VRO11
VRO10
VRO9
VRO8

VRO7
VRO6
VRO5
VRO4

VRO3
VRO2
VRO1
VRO0

FS1 = 0; FS0 = 0

RGB 5-5-5 + 1

32-BIT WORDS

α

R4
R3
R2

R1
R0
G4
G3

G2
G1
G0
B4

B3
B2
B1
B0

α

R4
R3
R2

R1
R0
G4
G3

G2
G1
G0
B4

B3
B2
B1
B0

α

R4
R3
R2

R1
R0
G4
G3

G2
G1
G0
B4

B3
B2
B1
B0

α

R4
R3
R2

R1
R0
G4
G3

G2
G1
G0
B4

B3
B2
B1
B0

α

R4
R3
R2

R1
R0
G4
G3

G2
G1
G0
B4

B3
B2
B1
B0

α

R4
R3
R2

R1
R0
G4
G3

G2
G1
G0
B4

B3
B2
B1
B0

FS1 = 0; FS0 = 1

YUV 4:2:2

32-BIT WORDS

Ye7
Ye6
Ye5
Ye4

Ye3
Ye2
Ye1
Ye0

Ue7
Ue6
Ue5
Ue4

Ue3
Ue2
Ue1
Ue0

Yo7
Yo6
Yo5
Yo4

Yo3
Yo2
Yo1
Yo0

Ve7
Ve6
Ve5
Ve4

Ve3
Ve2
Ve1
Ve0

Ye7
Ye6
Ye5
Ye4

Ye3
Ye2
Ye1
Ye0

Ue7
Ue6
Ue5
Ue4

Ue3
Ue2
Ue1
Ue0

Yo7
Yo6
Yo5
Yo4

Yo3
Yo2
Yo1
Yo0

Ve7
Ve6
Ve5
Ve4

Ve3
Ve2
Ve1
Ve0

Ye7
Ye6
Ye5
Ye4

Ye3
Ye2
Ye1
Ye0

Ue7
Ue6
Ue5
Ue4

Ue3
Ue2
Ue1
Ue0

Yo7
Yo6
Yo5
Yo4

Yo3
Yo2
Yo1
Yo0

Ve7
Ve6
Ve5
Ve4

Ve3
Ve2
Ve1
Ve0

FS1 = 1; FS0 = 0
YUV 4:2:2 TEST

16-BIT WORDS

Ye7
Ye6
Ye5
Ye4

Ye3
Ye2
Ye1
Ye0

Ue7
Ue6
Ue5
Ue4

Ue3
Ue2
Ue1
Ue0

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

Yo7
Yo6
Yo5
Yo4

Yo3
Yo2
Yo1
Yo0

Ve7
Ve6
Ve5
Ve4

Ve3
Ve2
Ve1
Ve0

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

Ye7
Ye6
Ye5
Ye4

Ye3
Ye2
Ye1
Ye0

Ue7
Ue6
Ue5
Ue4

Ue3
Ue2
Ue1
Ue0

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

FS1 = 1; FS0 = 1

8-BIT MONOCHROME

32-BIT WORDS

n
n+1

Ya7
Ya6
Ya5
Ya4

Ya3
Ya2
Ya1
Ya0

Yb7
Yb6
Yb5
Yb4

Yb3
Yb2
Yb1
Yb0

n+2
n+3

Yc7
Yc6
Yc5
Yc4

Yc3
Yc2
Yc1
Yc0

Yd7
Yd6
Yd5
Yd4

Yd3
Yd2
Yd1
Yd0

n+4
n+5

Ya7
Ya6
Ya5
Ya4

Ya3
Ya2
Ya1
Ya0

Yb7
Yb6
Yb5
Yb4

Yb3
Yb2
Yb1
Yb0

n+6
n+7

Yc7
Yc6
Yc5
Yc4

Yc3
Yc2
Yc1
Yc0

Yd7
Yd6
Yd5
Yd4

Yd3
Yd2
Yd1
Yd0

n+8
n+9

Ya7
Ya6
Ya5
Ya4

Ya3
Ya2
Ya1
Ya0

Yb7
Yb6
Yb5
Yb4

Yb3
Yb2
Yb1
Yb0

n+10
n+11

Yc7
Yc6
Yc5
Yc4

Yc3
Yc2
Yc1
Yc0

Yd7
Yd6
Yd5
Yd4

Yd3
Yd2
Yd1
Yd0

Note

1. α = keying bit; R, G, B, Y, U and V = digital signals; e = even pixel number; o = odd pixel number;

a b c d = consecutive pixels

May 1993 13

Philips Semiconductors Preliminary specification

Digital video scaler SAA7186

Table 3 VRAM port output data formats at EFE-bit = 1 dependent on FS1 and FS0 bits (set via I2C-bus)

PIXEL

OUTPUT

BITS

PIXEL
ORDER n n+1n+2n n+1n+2n n+1n+2

VRO31
VRO30
VRO29
VRO28

VRO27
VRO26
VRO25
VRO24

VRO23
VRO22
VRO21
VRO20

VRO19
VRO18
VRO17
VRO16

PIXEL
ORDER n n+1n+2n n+1n+2n n+1n+2

VRO15
VRO14
VRO13
VRO12

VRO11
VRO10
VRO9
VRO8

VRO7 (2, 3)
VRO6 (3)
VRO5 (3)
VRO4 (3)

VRO3
VRO2 (3)
VRO1 (3)
VRO0 (3)

FS1 = 0; FS0 = 0

RGB 5-5-5 + 1

16-BIT WORDS

α

R4
R3
R2

R1
R0
G4
G3

G2
G1
G0
B4

B3
B2
B1
B0

X
X
X
X

X
X
X
X

α

O/E
VGT
HGT

X
HRF
LNQ
PXQ

α

R4
R3
R2

R1
R0
G4
G3

G2
G1
G0
B4

B3
B2
B1
B0

X
X
X
X

X
X
X
X

α

O/E
VGT
HGT

X
HRF
LNQ
PXQ

α

R4
R3
R2

R1
R0
G4
G3

G2
G1
G0
B4

B3
B2
B1
B0

X
X
X
X

X
X
X
X

α

O/E
VGT
HGT

X
HRF
LNQ
PXQ

FS1 = 0; FS0 = 1

YUV 4:2:2

16-BIT WORDS

Ye7
Ye6
Ye5
Ye4

Ye3
Ye2
Ye1
Ye0

Ue7
Ue6
Ue5
Ue4

Ue3
Ue2
Ue1
Ue0

X
X
X
X

X
X
X
X

α

O/E
VGT
HGT

X
HRF
LNQ
PXQ

Yo7
Yo6
Yo5
Yo4

Yo3
Yo2
Yo1
Yo0

Ve7
Ve6
Ve5
Ve4

Ve3
Ve2
Ve1
Ve0

X
X
X
X

X
X
X
X

X
O/E
VGT
HGT

X
HRF
LNQ
PXQ

Ye7
Ye6
Ye5
Ye4

Ye3
Ye2
Ye1
Ye0

Ue7
Ue6
Ue5
Ue4

Ue3
Ue2
Ue1
Ue0

X
X
X
X

X
X
X
X

α

O/E
VGT
HGT

X
HRF
LNQ
PXQ

FS1 = 1; FS0 = 0

RGB 8-8-8

24-BIT WORDS

R7
R6
R5
R4

R3
R2
R1
R0

G7
G6
G5
G4

G3
G2
G1
G0

B7
B6
B5
B4

B3
B2
B1
B0

α

O/E
VGT
HGT

X
HRF
LNQ
PXQ

R7
R6
R5
R4

R3
R2
R1
R0

G7
G6
G5
G4

G3
G2
G1
G0

B7
B6
B5
B4

B3
B2
B1
B0

α

O/E
VGT
HGT

X
HRF
LNQ
PXQ

R7
R6
R5
R4

R3
R2
R1
R0

G7
G6
G5
G4

G3
G2
G1
G0

B7
B6
B5
B4

B3
B2
B1
B0

α

O/E
VGT
HGT

X
HRF
LNQ
PXQ

FS1 = 1; FS0 = 1

8-BIT MONOCHROME

16-BIT WORDS

n
n+1

Ya7
Ya6
Ya5
Ya4

Ya3
Ya2
Ya1
Ya0

Yb7
Yb6
Yb5
Yb4

Yb3
Yb2
Yb1
Yb0

n
n+1

X
X
X
X

X
X
X
X

α

O/E
VGT
HGT

X
HRF
LNQ
PXQ

n+2
n+3

Ya7
Ya6
Ya5
Ya4

Ya3
Ya2
Ya1
Ya0

Yb7
Yb6
Yb5
Yb4

Yb3
Yb2
Yb1
Yb0

n+2
n+3

X
X
X
X

X
X
X
X

α

O/E
VGT
HGT

X
HRF
LNQ
PXQ

n+4
n+5

Ya7
Ya6
Ya5
Ya4

Ya3
Ya2
Ya1
Ya0

Yb7
Yb6
Yb5
Yb4

Yb3
Yb2
Yb1
Yb0

n+4
n+5

X
X
X
X

X
X
X
X

α

O/E
VGT
HGT

X
HRF
LNQ
PXQ

Notes

1. α = keying bit; R, G, B, Y, U and V = digital signals; e = even pixel number; o = odd pixel number;

a b c d = consecutive pixels; O/E = odd/even flag

2. YUV 16-bit format: the keying signal α is defined only for YU time steps. The corresponding YV sample has also to

be keyed. The α signal in monochrome mode can be used only in the transparent mode (TTR = 1), in this case
Ya = Yb.

3. Data valid only when transparent mode active (TTR-bit = 1) and VCLK pin connected to LLC/2 clock rate.

May 1993 14

Philips Semiconductors Preliminary specification

Digital video scaler SAA7186

7.8 Output FIFO register and VRAM output port

The output FIFO register is the buffer between the video
data stream and the VRAM data input port. Resized video
data are buffered and formatted. 32-, 24- and 16-bit video
data modes are supported. The various formats are
selected by the bits EFE, FS1 and FS0. VRAM port
formats are shown in Tables 2 and 3. The FIFO register
capacity is 16 word × 32 bit (for 32-, 24-, or 16-bit video
data). The bits LW1 and LW0 can be used to define the
position of the first pixel each line in the 32-bit longword
formats or to shift the UV sequence to VU in the 16-bit YUV
formats (LW1 = 1).

VRAM port inputs are:
VCLK to clock the FIFO register output data and VOEN to
enable output data.

VRAM port outputs are:
the HFL flag (half-full flag), the signal INCADR (refer to
section “data burst transfer”) and the reference signals for
pixel and line selection on outputs VRO(7-0) (only for 24­and 16-bit video data formats refer to “transparent data
transfer”).

7.9 VRAM port transfer procedures

Data transfer on the VRAM port can be done
asynchronously controlled by outputs HFL, INCADR and
input VCLK (data burst transfer with bit TTR = 0).

Data transfer on the VRAM port can be done
synchronously controlled by output reference signals on
outputs VRO(7-0) and a clock rate of LLC/2 on input VCLK
(transparent data transfer with bit TTR = 1 and EFE = 1).
The scaling capability of the SAA7186 can be used in
various applications.

7.10 Data burst transfer mode

Data transfer on the VRAM port is asynchronously
(TTR = 0). This mode can be used for all output formats.
Four signals for communication with the external memory
are provided.

• HFL flag, the half-full flag of the FIFO output register is

raised when the FIFO contains at least 8 data words
(HFL = HIGH). By setting HFL = 1, the SAA7186
requests a data burst transfer by the external memory
controller, that has to start a transfer cycle within the
next 32 LLC cycles for 32-bit longword modes (16 LLC
cycles for 16- and 24-bit modes). If there are pixels in the
FIFO at the end of a line, which are not transferred, the
circuit fills up the FIFO register with “fill pixels” until it is
half-full and sets the HFL flag to request a data burst
transfer. After transfer is done, HFL is used in

combination with INCADR to indicate the line
increments (Figures 6 and 7).

• INCADR output signal is used in combination with HFL
to control horizontal and vertical address generation for
a memory controller. The pulse sequence depends on
field formats (interlace/ non-interlace or odd/even fields,
Figures 6 and 7) and control bits OF (subaddress 00).

HFL = 1 at the rising edge of INCADR:

the end of line is reached, request for line address
increment

HFL = 0 at the rising edge of INCADR:

the end of field/frame is reached, request for line and
pixel addresses reset

(The distance from the last half-full request HFL to the
INCADR pulse may be longer than 64 × LLC. The HFL
state is defined for minimum 4 × LLC in front of the rising
edge of INCADR and minimum 2 × LLC afterwards.)

• VCLK input signal to clock the FIFO register output data
VRO(n). New data are placed on the VRO(n) port with
the rising edge of VCLK (Fig.5).

• VOEN input enables output data VRO(n). The outputs
are in 3-state mode at VOEN = HIGH. VOEN changes
only when VCLK is LOW. If VCLK pulses are applied
during VOEN = HIGH, the outputs remain inactive, but
the FIFO register accepts the pulses.

7.11 Transparent data transfer mode

Data transfer on the VRAM port can be achieved
synchronously (TTR = 1). With a continuous clock rate of
LLC/2 on input VCLK, the SAA7186 delivers a
continuously processed data stream. Therefore, the
extended formats of the VRAM output port have to be
selected (bit EFE = 1; Table 3). The reference and gate
signals on outputs VRO(6-1) and the LNQ signal are
delivered in each field (means scaled and ignored fields).
The PXO signal (also VRO0) is only delivered in active
fields. The output signals VRO(7-0) can be used to buffer
qualified pre-processed RGB or YUV video data (notice:
the YUV data are only valid in qualified time slots). Control
output signals in Table 3 are:

May 1993 15

Philips Semiconductors Preliminary specification

Digital video scaler SAA7186

α keying signal of the chroma keyer
O/E odd/even field bit according

to the internal field processing

VGT vertical gate signal, “1”

marks the scaling window in vertical direction
from YO to (YO + YS) lines, cut by VS.

HGT horizontal gate signal, “1”

marks horizontal direction from XO to (XO + XS)
lines, cut by HREF.

HRF delay compensated

horizontal reference signal.

LNQ line qualifier signal, active polarity is defined by

QPL bit.

PXQ pixel qualifier signal, active polarity is defined by

QPP bit.

7.12 Power-on reset

• the FIFO register contents are undefined

• outputs VRO are set to high-impedance state

• output INCADR = HIGH

• output HFL = LOW until the VPE bit is set to “1”

• subaddress “10” is set to 00h and VPE-bit in subaddress

“00” is set to zero (Table 4).

May 1993 16

Philips Semiconductors Preliminary specification

Digital video scaler SAA7186

handbook, full pagewidth

PIXCLK

(LLC/2)

FIFO memory
filling level

HFL

VCLK

VOEN

VRO(n)

6787

min. 8 samples

available in FIFO

max. 32LLC
(16 PIXCLK

7

7

1 transfer cycle

(8 VCLK cycles)

1

0

65

2

4

5

456

3

33

7

MEH407

Fig.5 Output port transfer to VRAM at 32-bit data format without scaling. If VCLK cycles occur at VOEN = HIGH,

the FIFO register is unchanged, but the outputs VRO(31-0) remain in 3-state position.

handbook, full pagewidth

internal

signal

HFL

INCADR

(1) pulse only at

interlace scan

line n

active

video

line n+1

last half-full request for line n

64LLC

min.

64LLC

10LLC

vertical reset

vertical blanking

(1)

(1)

line increment (VRAM) only in odd field

Fig.6 Vertical reset timing to the VRAM.

May 1993 17

min. set-up time

MEH406

Philips Semiconductors Preliminary specification

Digital video scaler SAA7186

handbook, full pagewidth

internal

signal

HFL

INCADR

(1) pulse only at

interlace scan

line n

active

video

line n+1

horizontal blanking

last half-full request for line n

(1)

6LLC

min.

64LLC

6LLC

64LLC

2LLC

10LLC

(1)

line increment (VRAM)

min. set-up time

Fig.7 Horizontal increment timing to the VRAM.

active

video

first half-full request for line n+1

MEH405-1

Fig.8 Reference signals for scaling window.

May 1993 18

Philips Semiconductors Preliminary specification

Digital video scaler SAA7186

7.13 Field processing

The phase of the field sequence (odd/even dependent on
inputs HREF and VS) is detected by means of the falling
edge of VS. The current field phase is reported in the
status byte by the OEF bit (Table 5). OEF bit can be stable
0 or 1 for non-interlaced input frames or non standard input
signals VS and/or HREF (nominal condition for VS and
HREF − SAA7191 B with active vertical noise limiter). A
free-running odd/even flag is generated for internal field
processing if the detection reports a stable OEF bit.

The POE bit (subaddress 0B) can be used to change the
polarity of the internal flag (in case of non-standard VS and
HREF signals) to control the phase of the free-running flag,
and to compensate mis-detections. Thus, the SAA7186
can be used under various VS/HREF timing conditions.

The SAA7186 operates on fields. To support progressive
displays and to avoid movement blurring and artifacts, the
circuit can process both or single fields of interlaced or
non-interlaced input data. Therefore the OF bits can be
used. The bits OF1 and OF0 (Table 6) determine the
INCADR/HFL generation in “data burst transfer mode”.
One of the fields (odd or even) is ignored when OF1 = 1;
then no line increment sequence (INCADR/HFL) is
generated, the vertical reset pulse is only generated.

With OF1 = OF0 = 0 the circuit supports correct interlaced
data storage. Two INCADR/HFL sequences are generated
in each qualified line; additionally an INCADR/HFL
sequence after the vertical reset sequence of an odd field
is generated. Thereby, the scaled lines are automatically
stored in the right sequence.

8 OPERATION CYCLE

The operation is synchronized by the input field. The cycle
is specified in the flow chart (Fig.9).
The circuit is inactive after power-on reset, VPO is 0 and
the FIFO control is set “empty”. The internal control
registers are updated with the falling edge of VS signal.
The circuit is switched active and waits for a transmission
of VS and a vertical reset sequence to the memory
controller. Afterwards, the circuit waits for the beginning of
a scaling or bypass region. The processing of a current line
is finished when a vertical sync pulse appears. The circuit
performs a coefficient update and generates a new vertical
reset (if it is still active).

Line processing starts when a line is decided to be active,
the circuit starts to scale it. Active pixels are loaded into the
FIFO register. An HFL flag is generated to initialize a data
transfer when eight words are completed. The line end is
reached when the programmed pixel number is processed
or when a horizontal sync pulse occurs. If there are pixels
in the FIFO register, it is filled up until it is half-full to cause
a data transfer. Horizontal increment pulses are
transmitted after this data transfer.

Remarks:
The SAA7186 will always wait for the HREF/VS pulse
before the line increment/vertical reset sequence is
performed. After each line/field, the FIFO control is set to
empty when INCADR/HFL sequence is transmitted.
No additional actions are necessary if the memory
controller has ignored the HFL signal. There is no need to
handle overflow/underflow of the FIFO register.

May 1993 19

Philips Semiconductors Preliminary specification

Digital video scaler SAA7186

handbook, full pagewidth

EXTERNAL RESET, VPE = 0

VERTICAL SYNC

DETECTED ?

COEFFICIENT UPDATE

VPE = 1 ?

DO VERTICAL RESET

YES

VERTICAL SYNC

DETECTED ?

NO

YES

NO

YES

SET SCALING ACTIVE

IN CONTROL STAGE

YES

CURRENT

LINE IN ACTIVE

REGION ?

PROCESS A LINE

Fig.9 Operation cycle

NO

NO

CURRENT

LINE IN BYPASS

REGION ?

SET BYPASS MODE
IN CONTROL STAGE

NO

YES

MGL119

May 1993 20

Philips Semiconductors Preliminary specification

Digital video scaler SAA7186

handbook, full pagewidth

CVBS

TDA8708A

Fig.10 SAA7186 system configuration in Data Burst Transfer Mode (TTR = , VCLK = continuous).

ADC

digital

CVBS

DMSD

SAA7151B/91B

LFCO

SCGC

SAA7157/97

CPU

YUV
format 4.2:2

HREF / VS

LLC / CREF

DVS

SAA7186

VCLK
VOEN

data bus

address / control bus

HFL
INCADR

RGB/YUV

BUFFER

RAM

VIDEO

GRAPHICS

control

MEMORY

CONTROLLER

address

system
clock

display data

SYSTEM

RAM

MEH554

handbook, full pagewidth

CVBS

TDA8708A

ADC

digital

CVBS

DMSD

SAA7151B/91B

LFCO

SCGC

SAA7157/97

YUV

format 4.2:2

HREF / VS

LLC / CREF

LLC2

SAA7186

INV

Fig.11 SAA7186 system configuration in Transparent Data Transfer Mode (TTR = 1, EFE = 1,

VCLK = continuous (_LLC2)).

May 1993 21

RGB/YUV

(VRO(31-8))

DVS

qualifier
and
references
(VRO(7-0))

VOEN = 1

VCLK = LLC2

write

FIFO

BUFFER

read

CONTROLLER

RAM

VIDEO

GRAPHICS

control

MEMORY

address

MEH555

display
data

Philips Semiconductors Preliminary specification

Digital video scaler SAA7186

handbook, full pagewidth

(a) 1st field

input CVBS

HREF

VS

(b) 2nd field

input CVBS

HREF

VS

handbook, full pagewidth

(a) 1st field

625123456789

541 x 2/LLC

313 314 315 316 317 318 319 320 321

69 x 2/LLC

50 Hz

525123456789

MEH412

input CVBS

HREF

VS

ODD

(b) 2nd field

input CVBS

HREF

VS

ODD

2 x 2/LLC

263 264 265 266 267 268 269 270 271

59 x 2/LLC

2 x 2/LLC

60 Hz

Fig.12 VS timing for video input source SAA7191B.

449x 2/LLC

MEH225-1

May 1993 22

Philips Semiconductors Preliminary specification

Digital video scaler SAA7186

9I2C-BUS FORMAT

S SLAVE ADDRESS A SUBADDRESS A DATA0 A DATAn A P

S = start condition
SLAVE ADDRESS = 1011 100X (IICSA = LOW) or 1011 110X (IICSA = HIGH)
A = acknowledge, generated by the slave
SUBADDRESS
DATA = data byte (Table 4)
P = stop condition

X = read/write control bit

Note

1. If more than 1 byte DATA are transmitted, then auto-increment of the subaddress is performed.

(1)

= subaddress byte (Table 4)

X = 0, order to write (the circuit is slave receiver)
X = 1, order to read (the circuit is slave transmitter)

May 1993 23

Philips Semiconductors Preliminary specification

Digital video scaler SAA7186

Table 4 I2C-bus; subaddress and data bytes for writing (X in address byte = 0).

FUNCTION SUBADDRESS

DATA

D7 D6 D5 D4 D3 D2 D1 D0 DF

Formats and sequence 00 RTB OF1 OF0 VPE LW1 LW0 FS1 FS0 tbf
Output data pixel/line 01 XD7 XD6 XD5 XD4 XD3 XD2 XD1 XD0

continued in 04 XD9 XD8

Input data pixel/line 02 XS7 XS6 XS5 XS4 XS3 XS2 XS1 XS0

continued in 04 XS9 XS8
Horizontal window start 03 XO7 XO6 XO5 XO4 XO3 XO2 XO1 XO0
Pixel decimation filter 04 HF2 HF1 HF0 XO8 XS9 XS8 XD9 XD8
Output data lines/field 05 YD7 YD6 YD5 YD4 YD3 YD2 YD1 YD0

continued in 09 YD9 YD8
Input data lines/field 06 YS7 YS6 YS5 YS4 YS3 YS2 YS1 YS0

continued in 09 YS9 YS8
Vertical window start 07 YO7 YO6 YO5 YO4 YO3 YO2 YO1 YO0
AFS/vertical processing 08 AFS VP1 VP0 YO8 YS9 YS8 YD9 YD8
Vertical bypass start 09 VS7 VS6 VS5 VS4 VS3 VS2 VS1 VS0

continued in 0B VS8
Vertical bypass count 0A VC7 VC6 VC5 VC4 VC3 VC2 VC1 VC0

continued in 0B TCC 0 0 VS8 0 VC8 0 POE
Chroma keying

lower limit for V
upper limit for V
lower limit for U
upper limit for U

Byte 10

(2)

0C
0D
0E
0F

VL7
VU7
UL7
UU7

VL6
VU6
UL6

UU6

VL5

VU5

UL5

UU5

VL4
VU4
UL4
UU4

VL3
VU3
UL3
UU3

VL2

VU2

UL2

UU2

VL1

VU1

UL1

UU1

VL0
VU0
UL0
UU0

10 0 0 0 MCT QPL QPP TTR EFE

Unused 11 to 1F

(1)

Notes

1. Default register contents fill in by hand

2. Byte 10 is set to 00h after power-on reset.

May 1993 24

Philips Semiconductors Preliminary specification

Digital video scaler SAA7186

Table 5 I2C-bus status byte (X in address byte = 1)

FUNCTION

D7 D6 D5 D4 D3 D2 D1 D0

status byte ID3 ID2 ID1 ID0 0 0 OEF SVP
Function of status bits:

ID3 to ID0 Software version of SAA7186 compatible with

ID3 ID2 ID1 ID0 version
00 0 1 1

OEF Identification of field sequence dependent on inputs HREF and VS:

0 = even field detected; 1 = odd field detected

SVP State of VRAM port: 0 = inputs HFL and INCADR inactive;

1 = inputs HFL and INCADR active.

DATA

May 1993 25

Philips Semiconductors Preliminary specification

Digital video scaler SAA7186

Table 6 Function of the register bits of Table 4

“00”
RTB ROM table bypass switch: 0 = anti-gamma ROM active

1 = table is bypassed

−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅ −⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅

OF1 to OF0 Set output field mode:

OF1 OF0 field mode DVS process

0
0
1
1

−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅ −⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−−⋅−⋅

VPE VRAM port outputs enable: 0 = HFL and INCADR inactive; VRO outputs in 3-state

−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅ −⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅

LW1 to LW0 First pixel position in VRO data for FS1 = 0; FS0 = 0 (RGB) and FS1 = 0; FS0 = 1 (YUV):

LW1 LW0 31 to 24 23 to 16 15 to 8 7 to 0

0
0
1
1

First pixel position in VRO data for FS1 = 1; FS0 = 1 (monochrome):

LW1 LW0 31 to 24 23 to 16 15 to 8 7 to 0

0
0
1
1

0
1
0
1

0
1
0
1

0
1
0
1

pixel 0
pixel 0
black
black

pixel 0
black
black
black

both fields for interlaced storage
both fields for non-interlaced storage
odd fields only (even fields ignored) for non-interlaced storage
even fields only (odd fields ignored) for non-interlaced storage

position (HFL = LOW, INCADR = HIGH)
1 = HFL and INCADR enabled; VRO outputs dependent
on VOEN

pixel 0
pixel 0
black
black

pixel 1
pixel 0
black
black

pixel 1
pixel 1
pixel 0
pixel 0

pixel 2
pixel 1
pixel 0
black

pixel 1
pixel 1
pixel 0
pixel 0

pixel 3
pixel 2
pixel 1
pixel 0

)
)

EFE = 0, TRR = 0
)
)

)
)

EFE = 0, TRR = 0
)
)

0

0

0

1

1

0

1

1

May 1993 26

pixel 0
black
pixel 0
black

pixel 1
pixel 0
pixel 1
pixel 0

X
X
X
X

X
X
X
X

)

EFE = 1, TRR = 0;
)

LW only effects
)

greyscale format
)

Philips Semiconductors Preliminary specification

Digital video scaler SAA7186

FS1 to FS0 FIFO output register format select (EFE-bit see “10”):

EFE FS1 FS0 output format (Tables 2 and 3)
0 0 0 RGB 5-5-5 + alpa; 2×16-bit/pixel; 32-bit word length;

RGB matrix on, VRAM output format

0 0 1 YUV 4:2:2; 2×16-bit/pixel; 32-bit word length;

RGB matrix off, VRAM output format

0 1 0 YUV 4:2:2; video test mode; 1×16-bit/pixel; 16-bit word length;

RGB matrix off, optional output format

0 1 1 monochrome mode; 4×8-bit/pixel; 32-bit word length;

RGB matrix off, VRAM output format

1 0 0 RGB 5-5-5 + alpa; 1×16-bit/pixel; 16-bit word length;

RGB matrix on, VRAM output + transparent format

1 0 1 YUV 4:2:2 + alpa; 1×16-bit/pixel; 16-bit word length;

RGB matrix off, VRAM output + transparent format

1 1 0 RGB 8-8-8 + alpa; 1×24-bit/pixel; 24-bit word length;

RGB matrix on, VRAM output + transparent format

1 1 1 monochrome mode; 2×8-bit/pixel; 16-bit word length;

RGB matrix off, VRAM output + transparent format
“01 and 04”
XD9 to XD0 Pixel number per line (straight binary) on output (VRO):

00 0000 0000 to 11 1111 1111 (number of XS pixels as a maximum)
“02 and 04”
XS9 to XS0 Pixel number per line (straight binary) on inputs (YIN and UVIN):

00 0000 0000 to 11 1111 1111 (number of input pixels per line as maximum)
“03 and 04”
XO8 to XO0 Horizontal start position (straight binary) of scaling window (take care of active pixel

number per line).

start with 1st pixel after HREF rise = 0 0001 0000 to 1 1111 1111 (010 to 1FF)

window start and window end may be cut by internal delay compensated HREF = 0

phase. XO has to be matched to the internal processing delay to get full scaling range

May 1993 27

Philips Semiconductors Preliminary specification

Digital video scaler SAA7186

“04”
HF2 to HF0 Horizontal decimation filter (Figures 13 and 14):

HF2 HF1 HF0 taps filter

−1

0

0

0

0

0

1

0

1

1

0

1

0

1

1

1 1 1 4 (1/8 (1 + 3z

0
1
0
1

0
1
0

2

filter 1 (1/2 (1 + z
filter 2 (1/4 (1 + 2z−1+ z−2))

3

filter 3 (1/8 (1 + 2z−1+ 2z−2+ 2z−3+ z−4))

5

filter 4 (1/16 (1 + 2z−1+ 2z−2+ 2z−3+ 2z−4+ 2z

9

1

filter bypassed

1

filter bypassed + delay in Y channel of 1T

8

filter 5 (1/16 (1 + 3z

−1

“05 and 08”
YD9 to YD0 Line number per output field (straight binary):

00 0000 0000 to 11 1111 1111 (number of YS lines as a maximum)
“06 and 08”
YS9 to YS0 Line number per input field (straight binary):

00 0000 0000
11 1111 1111

0 line

1023 lines (maximum = number of lines/field − 3)
“07 and 08”
YO8 to YO0 Vertical start of scaling window. “0” equals 3rd line after rising slope of VS input signal.

Take care of active line number per field (straight binary).

0 0000 0000 start with 3rd line after the rising slope of VS
0 0000 0011 start with 1st line after the falling slope of nominal VS (SAA7151B/91B)
1 1111 1111 511 + 3 lines after the rising slope of VS (maximum value)

“08”
AFS Adaptive filter switch: 0 = off; use VP1, VP0 and HF2 to HF0 bits

1 = on; filter characteristics are selected by the scaler

−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅ −⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅

VP1 to VP0 Vertical data processing

VP1 VP0 processing
0

0

0

1

1

0

1

1

bypassed
delay of one line H(z) = z

−H

vertical filter 1: (H(z) = 1/2 (1 + z−H))

vertical filter 2: (H(z) = 1/4 (1 + 2z−H+ z
“09 and 0B”
VS8 to VS0 Vertical bypass start, sets begin of the bypass region (straight binary). Scaling region

overrides bypass region (YO bits):

0 0000 0000 start with 3rd line after the rising slope of VS
0 0000 0011 start with 1st line after the falling slope of nominal VS (SAA7151B/91B)
1 1111 1111 511 + 3 lines after the rising slope of VS (maximum value)

))

−1

+ 3z−2+ z−3+ z−4+ 3z

+ 3z−2+ z−3))

−2H

−5

+ 2z−6+ 2z−7+ z−8))

−5

+ 3z−6+ z−7))

))

May 1993 28

Philips Semiconductors Preliminary specification

Digital video scaler SAA7186

“0A and 0B”
VC8 to VC0 Vertical bypass count, sets length of bypass region (straight binary):

00 0000 0000 0 line length
11 1111 1111 511 lines length (maximum = number of lines/field − 3)

−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅ −⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−−⋅−⋅−⋅−⋅−⋅−⋅−⋅−−⋅−⋅−⋅−⋅−⋅−⋅−⋅−−⋅−⋅−⋅−⋅−⋅−⋅−⋅−−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−

TCC Two’s complement input data select (U, V): 0 = binary input data

1 = two’s complement input data

−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅ −⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−

POE Polarity, internally detected odd/even flag O/E:

0 = flag unchanged; 1 = flag inverted
“0C”
VL7 to VL0 Set lower limit for V colour-difference signal (8 bit; two’s complement):

1000 0000
0000 0000

0111 1111
“0D”
VU7 to VU0 Set upper limit for V colour-difference signal (8 bit; two’s complement):

1000 0000

0000 0000

0111 1111
“0E”
UL7 to UL0 Set lower limit for U colour-difference signal (8 bit; two’s complement):

1000 0000

0000 0000

0111 1111
“0F”
UU7 to UU0 Set upper limit for U colour-difference signal (8 bit; two’s complement):

1000 0000

0000 0000

0111 1111

as maximum negative value = −128 signal level
limit = 0
as maximum positive value = +127 signal level

as maximum negative value = −128 signal level
limit = 0
as maximum positive value = +127 signal level

as maximum negative value = −128 signal level
limit = 0
as maximum positive value = +127 signal level

as maximum negative value = −128 signal level
limit = 0
as maximum positive value = +127 signal level

May 1993 29

Philips Semiconductors Preliminary specification

Digital video scaler SAA7186

“10”
MCT Monochrome and two’s complement output data select:

0 = inverse greyscale luminance (if greyscale is selected by FS bits) or straight

binary U, V data output

1 = non-inverse monochrome luminance (if greyscale is selected by FS bits) or

two’s complement U, V data output

−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅ −⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−−⋅−⋅−⋅−⋅−⋅−⋅−⋅−−⋅−⋅−⋅−⋅−⋅−⋅−⋅−−⋅−⋅−⋅−⋅−⋅−⋅−⋅−−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−

QPL Line qualifier polarity flag : 0 = LNQ is active-LOW (pin 1 and on VRO1, pin 99);

1 = LNQ is active-HIGH

−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅ −⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−

QPP Pixel qualifier polarity flag : 0 = PXQ is active-LOW (VRO0, pin 100);

1 = PXQ is active-HIGH

−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅ −⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−−⋅−⋅−⋅−⋅−⋅−⋅−⋅−−⋅−⋅−⋅−⋅−⋅−⋅−⋅−−⋅−⋅−⋅−⋅−⋅−⋅−⋅−−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−

TTR Transparent data transfer: 0 = normal operation (VRAM protocol valid,)

1 = FIFO register transparent

(output FIFO in shift register mode)

−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅ −⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−−⋅−⋅−⋅−⋅−⋅−⋅−⋅−−⋅−⋅−⋅−⋅−⋅−⋅−⋅−−⋅−⋅−⋅−⋅−⋅−⋅−⋅−−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−

EFE Extended formats enable, FS-bits in subaddress “00”

May 1993 30

Philips Semiconductors Preliminary specification

Digital video scaler SAA7186

10

handbook, full pagewidth

(dB)

0

−10

−20

−30

−40

−50

0 0.1 0.2

Fig.13 Horizontal frequency characteristic of luminance signal (Y) dependent on HF2 to HF0 bits

(subaddress 04).

010
110

011

100, 101

001 111

011

110

0.3 0.4

000

f / f

Clock

MEH514

0.5

10

handbook, full pagewidth

(dB)

0

−10

−20

−30

−40

−50

0

100, 101

000

111

010 001

011, 110

011, 110

0.05 0.10 0.15 0.20
f / f

MEH513

Clock

Fig.14 Horizontal frequency characteristic of chrominance signals (UV) without UV interpolation dependent on

HF2 to HF0 bits (subaddress 04).

0.25

May 1993 31

Philips Semiconductors Preliminary specification

Digital video scaler SAA7186

10 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER MIN. MAX. UNIT

V

DD

V

I

I

DD

P

tot

T

stg

T

amb

V

ESD

Note

1. Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.

11 DC CHARACTERISTICS

V

DD1

supply voltage (pins 5, 14, 26, 40, 55, 67, 76 and 91) −0.5 6.5 V
DC input voltage on all pins −0.5 V
supply current (pins 5, 14, 26, 40, 55, 67, 76 and 91) − 70 mA
total power dissipation 0 1 W
storage temperature range −65 150 °C
operating ambient temperature range 0 70 °C
electrostatic handling

to V

= 4.5 to 5.5 V; T

DD8

(1)

for all pins −±2000 V

= 0 to 70 °C unless otherwise specified.

amb

DD

V

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

DD

supply voltage range (pins 5, 14, 26, 40,

4.5 5 5.5 V

55, 67, 76 and 91)

I

P

total supply current (I

I

+ I

DD5

+ I

DD6

DD4

+ I

DD1

DD7

+ I

+ I

DD2

DD8

+ I

)

DD3

+

inputs LOW and
outputs without load

− 80 − mA

Data and control inputs

V

I L

V

I H

I

LI

C

I

input voltage LOW −0.5 − 0.8 V
input voltage HIGH 2.0 − VDD+0.5 V
input leakage current V

=0 −−10 µA

I L

input capacitance data −−8pF

clocks −−10 pF

Data and control outputs

V

O L

V

O H

output voltage LOW note 1 −−0.6 V
output voltage HIGH note 1 2.4 −− V

3-state outputs

I

O off

C

O

2

C-bus, SDA and SCL (pins 44 and 45)

I

V

I L

V

I H

I

44, 45

I

ACK

V

O L

high-impedance output current −−±5µA
high-impedance output capacitance −−8pF

input voltage LOW −0.5 − 1.5 V
input voltage HIGH 3 − VDD+0.5 V
input current −−±10 µA
output current on pin 44 acknowledge 3 −− mA
output voltage at acknowledge I44= 3 mA −−0.4 V

May 1993 32

Philips Semiconductors Preliminary specification

Digital video scaler SAA7186

12 AC CHARACTERISTICS

to V

V

DD1

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

LLC timing (pin 36)

t

LLC

t

p

t

r

t

f

Input data and CREF timing

t

SU

t

HD

VCLK timing (pin 51)

t

VCLK

t

, t

p L

p H

t

r

t

f

Output data and reference signal timing

C

L

t

OH

t

OHL

t

OHV

t

OD

t

ODL

t

ODV

t

D

t

E

t

HFL VOE

t

HFL VCLK

= 4.5 to 5.5 V; T

DD8

= 0 to 60 °C unless otherwise specified.

amb

Fig.11

cycle time 31 − 45 ns
pulse width (duty factor) t

LLC H

/ t

LLC

40 50 60 %
rise time −−5ns
fall time −−6ns

Fig.15

setup time 11 −−ns
hold time 3 −−ns

Fig.16

VRAM port clock cycle time note 2 50 − 200 ns
LOW and HIGH times note 3 17 −−ns
rise time −−5ns
fall time −−6ns

Figures 15 and 16

load capacitance VRO outputs 15 − 40 pF

other outputs 7.5 − 25 pF

VRO data hold time CL= 10 pF; note 4 0 −−ns

related to LLC (INCADR, HFL) CL= 10 pF; note 5 0 − ns
related to VCLK (HFL) CL= 10 pF; note 5 0 − ns

VRO data delay time CL= 40 pF; note 4 −−25 ns

related to LLC (INCADR, HFL) CL= 25 pF; note 5 −−60 ns

related to VCLK (HFL) CL= 25 pF; note 5 −−60 ns
output disable time to 3-state CL= 40 pF; note 6 −−40 ns
output enable time from 3-state CL= 40 pF; note 6 −−40 ns
HFL maximum response time VRAM port enabled −−810 ns
HFL maximum response time HFL set at beginning

−−840 ns

of VCLK burst

Notes

1. Levels are measured with load circuit. VRO outputs with 1.2 kΩ in parallel to 25 pF at 3 V (TTL load).

2. Maximum t

= 200 ns for test mode only. The applicable maximum cycle time depends on data format,

VCLK

horizontal scaling and input data rate.

3. Measured at 1,5 V level; t

may be unlimited.

p L

4. Timings of VRO refer to the rising edge of VLCK.

5. The timing of INCADR refers to LLC; the rising edge of HFL always refers to LLC. During a VRAM transfer is the
falling edge of HFL generated by VCLK. Both edges of HFL refer to LLC during horizontal increment and vertical
reset cycles.

6. Asynchronous signals with timing referring to the 1.5 V switching point of VOEN input signal (pin 50).

May 1993 33

Philips Semiconductors Preliminary specification

Digital video scaler SAA7186

handbook, full pagewidth

clock input LLC

inputs CREF

input data

output HFL
and INCADR

t

SUtHD

t

OHL

t

LLC H

t

ODL

not valid

t

LLC

2.4 V

1.5 V

0.6 V

t

f

not valid

t

r

t

t

SU

HD

2.0 V

0.8 V

2.0 V

0.8 V

2.4 V

0.6 V

Fig.15 Data input timing (LLC).

May 1993 34

MEH408-1

Philips Semiconductors Preliminary specification

Digital video scaler SAA7186

handbook, full pagewidth

VOEN

VCLK

output VRO(n)

output HFL

not valid

2.0 V

1.5 V

0.8 V

t

VCLK

t

f

t

t

OHV

t

OH

t

ODV

p H

t

OD

t

EN

t

r

t

p L

2.0 V

1.5 V

0.8 V

2.4 V

0.6 V

2.4 V

0.6 V

MEH409

13 PROCESSING DELAYS

PORTS DELAY IN LLC REMARKS

YIN to VRO
UVIN to VRO
HREF to VRO

Fig.16 Data output timing (VCLK).

58
58
58

in transparent mode only
in transparent mode only
in transparent mode only

May 1993 35

Philips Semiconductors Preliminary specification

Digital video scaler SAA7186

14 PROGRAMMING EXAMPLE

Slave address byte is B8h at pin IICSA = 0 (or BCh at pin IICSA = +5 V).

2

This example shows the setting via I

Values in brackets [..]:
If no scaling or panning is wanted,

the parameters XD, XS, YD and YS should be set to the maximum value 3FFh.
the parameters XO and YO should be set to the minimum value 000h.

(in this case, HREF and VS from external define the SAA7186 processing window).

C-bus for the processing of a picture segment at 1:1 horizontal and vertical scale.

SUBADDR.

(HEX)

00

01
02
03

04

05
06
07

08

09
0A
0B

0C
0D
0E
0F

BITS FUNCTION

RTB, OF(1:0), VPE,
LW(1:0), FS(1:0),

XD(7:0)
XS(7:0)
XO(7:0)

HF(2:0), XO(8),
XS(9, 8), XD(9, 8)
YD(7:0)
YS(7:0)
YO(7:0)

AFS, VP(1:0), YO(8),
YS(9, 8), YD(9, 8)
VS(7:0)
VC(7:0)
VS(8), VC(8), TCC,
POE

VL(7:0)
VU(7:0)
UL(7:0)
UU(7:0)

ROM table control and field
sequence processing; VRAM port
enable; output format select
LSB’s output pixel/line
LSB’s input pixel/line
LSB’s for horizontal window start

horizontal filter select and MSB’s
of subaddresses 01, 02, 03
LSB’s output lines/field
LSB’s input lines/field
LSB’s vertical window start

adaptive and vertical filter select;
MSB’s of subaddresses 05, 06, 07
LSB’s vertical bypass start position
LSB’s vertical bypass lines/field
MSB’s of subaddresses 09, 0A;
UV input data representation
and odd/even polarity switch

UV keyer: lower limit V (R-Y)
UV keyer: upper limit V (R-Y)
UV keyer: lower limit U (B-Y)
UV keyer: upper limit U (B-Y)

VALUE

(HEX)

11
80 [FF]
80 [FF]
10 [00]

85 [8F]
90 [FF]
90 [FF]
03 [00]

00 [FF]
00
00

00

00
FF
00
00

COMMENT

(1)
384 pixels out
384 pixels in
1st pixel after HREF = 1

horizontal filter bypassed
144 lines out
144 lines in
1st line after VS = 0; (2)

no adaptive select
vertical filter bypassed
not bypassed
region

defined; (3) (4)

) keying is switched off
) by VU < VL

-

-

10

Notes

1. RTB = 0 ROM table is active (only for RGB formats)
OF = 00 SAA7186 processes the both fields for interlaced display
VPE = 1 VRAM port is enabled
LW = 00 longword position of first pixel in each output line = 0
FS = 01 16-bit 4:2:2 YUV output format is selected

2. for nominal VS length of 6 × H-period (input SAA7191B respectively SAA7151B with active VNL)

3. TTC = 0 straight binary UV input data expected

May 1993 36

MCT, QPP, QPL,
TTR, EFE

Y or UV output data representation,
output data transfer mode,
pixel/ line qualifier polarity.

00

(5)

Philips Semiconductors Preliminary specification

Digital video scaler SAA7186

4. odd/even polarity unchanged - can be used to change the field sequence if phase relations between HREF and VS
are not according to SAA7191B respectively SAA7151B specification

5. MCT = 0 when EFE, FS = 001h: UV output data are straight binary
QPP = 0 the pixel qualifier PXQ is “0”-active (if TTR, EFE = 1)
QPL = 0 line qualifier LNQ is “0”-active (if TTR, EFE = 1)
TTR = 0 VRAM port is set to data burst transfer
EFE = 0 32-bit longword formats selected.

May 1993 37

Philips Semiconductors Preliminary specification

Digital video scaler SAA7186

15 PACKAGE OUTLINE

QFP100: plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm

c

y

X

E

e

w M

p

A

A

H

E

E

2

A

A

1

80 51

81

pin 1 index

100

1

50

Z

b

31

30

detail X

Q

L

p

L

SOT317-2

(A )

3

θ

w M

b

0.40

0.25

p

D

H

D

(1) (1)(1)

D

0.25

20.1

0.14

19.9

e

DIMENSIONS (mm are the original dimensions)

mm

OUTLINE

VERSION

SOT317-2

A

max.

3.20

0.25

0.05

2.90

0.25

2.65

IEC JEDEC EIAJ

UNIT A1A2A3bpcE

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

Z

D

0 5 10 mm

scale

(1)

eH

14.1

13.9

REFERENCES

0.65

24.2

23.6

May 1993 38

v M

A

B

v M

B

H

D

LLpQZywv θ

E

18.2

17.6

1.0

0.6

1.4

1.2

0.15 0.10.21.95

EUROPEAN

PROJECTION

Z

D

0.8

0.4

ISSUE DATE

92-11-17
95-02-04

E

1.0

0.6

o

7

o

0

Philips Semiconductors Preliminary specification

Digital video scaler SAA7186

16 SOLDERING

16.1 Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in

“IC Package Databook”

our

16.2 Reflow soldering

Reflow soldering techniques are suitable for all QFP
packages.

The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our

Reference Handbook”

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.

(order code 9398 652 90011).

“Quality

(order code 9397 750 00192).

16.3 Wave soldering

Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

If wave soldering cannot be avoided, the following
conditions must be observed:

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)
soldering technique should be used.

• The footprint must be at an angle of 45° to the board

direction and must incorporate solder thieves
downstream and at the side corners.

Even with these conditions, do not consider wave
soldering the following packages: QFP52 (SOT379-1),
QFP100 (SOT317-1), QFP100 (SOT317-2),
QFP100 (SOT382-1) or QFP160 (SOT322-1).

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

16.4 Repairing soldered joints

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

May 1993 39

Philips Semiconductors Preliminary specification

Digital video scaler SAA7186

17 DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

18 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

2

19 PURCHASE OF PHILIPS I

Purchase of Philips I
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.

C COMPONENTS

2

C components conveys a license under the Philips’ I2C patent to use the

May 1993 40

Philips Semiconductors Preliminary specification

Digital video scaler SAA7186

NOTES

May 1993 41

Philips Semiconductors Preliminary specification

Digital video scaler SAA7186

NOTES

May 1993 42

Philips Semiconductors Preliminary specification

Digital video scaler SAA7186

NOTES

May 1993 43

Philips Semiconductors – a worldwide company

Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]
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220050 MINSK, Tel. [phone], Fax. [phone]

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Brazil: seeSouth America
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Indonesia: see Singapore
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TEL AVIV 61180, Tel. [phone], Fax. [phone]
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20124 MILANO, Tel. [phone], Fax. [phone]
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,

Tel. [phone], Fax. [phone]
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,

Tel. [phone], Fax. [phone]
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,

Tel. [phone], Fax. [phone]
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,

Tel. [phone]

Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
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Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone], Fax. [phone]

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. 1997 SCA54
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

Printed in The Netherlands 657027/00/01/pp44 Date of release: May 1993 Document order number: 9397 750 02436