Datasheet SAA7165WP Datasheet (Philips)

DATA SH EET

Product specification
Supersedes data of May 1995
File under Integrated Circuits, IC22

1996 Aug 20

INTEGRATED CIRCUITS

SAA7165

Video Enhancement and
Digital-to-Analog processor
(VEDA2)

1996 Aug 20 2

Philips Semiconductors Product specification

Video Enhancement and Digital-to-Analog
processor (VEDA2)

SAA7165

FEATURES

• CMOS circuit to enhance video data and to convert
luminance and colour-difference signals from
digital-to-analog

• Digital Colour Transient Improvement block (DCTI) to
increase the sharpness of colour transitions.
The improved pin-compatible SAA7165 can supersede
the SAA9065

• 16-bit parallel input for 4 : 1 : 1 and 4:2:2 YUV data

• Data clock input LLC (Line-Locked Clock) for a data rate

up to 36 MHz

• 8-bit luminance and 8-bit multiplexed colour-difference
formats (7-bit formats optional)

• MC input to support various clock and pixel rates

• Formatting YUV input data; 4 :2:2format,

4:1:1format and filter characteristics selectable

• HREF input to determine the active line (number of
pixels)

• Controllable peaking of luminance signal

• Coring stage with controllable threshold to eliminate

noise in luminance signal

• Interpolation filter suitable for both formats to increase
the data rate in chrominance path

• Polarity of colour-difference signals selectable

• All functions controlled via I

2

C-bus

• Separate digital-to-analog converters (9-bit resolution
for Y; 8-bit for colour-difference signals)

• 1 V (p-p)/75 Ω outputs realized by two resistors

• No external adjustments.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V

DDD

digital supply voltage 4.5 5 5.5 V

V

DDA

analog supply voltage 4.75 5 5.25 V

I

DD(tot)

total supply current − tbf − mA

V

IL

LOW-level input voltage on YUV-bus −0.5 − +0.8 V

V

IH

HIGH-level input voltage on YUV-bus 2 − V

DDD

+ 0.5 V

f

LLC

input data rate −−36 MHz

V

o(p-p)

output signals Y, (R − Y) and (B − Y) (peak-to-peak value) − 2 − V

R

L

output load resistance 125 −− Ω
ILE DC integral linearity error in output signal (8-bit data) −−1 LSB
DLE DC differential error in output signal (8-bit data) −−0.5 LSB
T

amb

operating ambient temperature range 0 − 70 °C

TYPE

NUMBER

PACKAGE

NAME DESCRIPTION VERSION

SAA7165WP PLCC44 plastic leaded chip carrier; 44 leads SOT187-2

1996 Aug 20 3

Philips Semiconductors Product specification

Video Enhancement and Digital-to-Analog

processor (VEDA2)

SAA7165

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BLOCK DIAGRAM

handbook, full pagewidth

MEH464

INTERPOLATION

FILTER

Y

FORMATTER

DCTI

SAA7165

Y

U

V

DATA

SWITCH

DAC 3

41 42

CUR

V

DDA4

25 Ω

36

PEAKING

AND

CORING

DAC 2

DAC 1

UV

FORMATTER

TIMING

CONTROL

I2C-BUS

CONTROL

TEST

CONTROL

40

V

DDA3

37

V

DDA2

32

V

DDA1

31

V

DDD2

12

13
V

SSD1

V

DDD1

data clock

21 to 14

8

Y7 to Y0

11 to 4

24

27

25
26

28

29

8

UV7 to

UV0

MC

LLC

HREF

RESET

SCL
SDA

YUV-bus

I2C-bus

25 Ω

33

(R − Y)

(B − Y)

25 Ω

39

1

Y

C

UV

REFL

UV

REFL

Y

2

C

Y

43

44

30
V

SSD2

22
AP

23
SP

34
V

SSA1

35
V

SSA2

38
V

SSA3

3
SUB

Fig.1 Block diagram.

1996 Aug 20 4

Philips Semiconductors Product specification

Video Enhancement and Digital-to-Analog
processor (VEDA2)

SAA7165

PINNING

SYMBOL PIN DESCRIPTION

REFL

Y

1 low reference of luminance DAC (connected to V

SSA1

)

C

Y

2 capacitor for luminance DAC (high reference)

SUB 3 substrate (connected to V

SSA1

)
UV0 4 UV signal input bit UV7 (digital colour-difference signal)
UV1 5 UV signal input bit UV6 (digital colour-difference signal)
UV2 6 UV signal input bit UV5 (digital colour-difference signal)
UV3 7 UV signal input bit UV4 (digital colour-difference signal)
UV4 8 UV signal input bit UV3 (digital colour-difference signal)
UV5 9 UV signal input bit UV2 (digital colour-difference signal)
UV6 10 UV signal input bit UV1 (digital colour-difference signal)
UV7 11 UV signal input bit UV0 (digital colour-difference signal)
V

DDD1

12 +5 V digital supply voltage 1

V

SSD1

13 digital ground 1 (0 V)
Y0 14 Y signal input bit Y7 (digital luminance signal)
Y1 15 Y signal input bit Y6 (digital luminance signal)
Y2 16 Y signal input bit Y5 (digital luminance signal)
Y3 17 Y signal input bit Y4 (digital luminance signal)
Y4 18 Y signal input bit Y3 (digital luminance signal)
Y5 19 Y signal input bit Y2 (digital luminance signal)
Y6 20 Y signal input bit Y1 (digital luminance signal)
Y7 21 Y signal input bit Y0 (digital luminance signal)
AP 22 connected to ground (action pin for testing)
SP 23 connected to ground (shift pin for testing)
MC 24 data clock CREF (e.g. 13.5 MHz); at MC = HIGH, the LLC divider-by-two is inactive
LLC 25 line-locked clock signal (LL27 = 27 MHz)
HREF 26 data clock for YUV data inputs (for active line 768Y or 640Y long)
RESET 27 reset input (active LOW)
SCL 28 I

2

C-bus clock line

SDA 29 I

2

C-bus data line

V

SSD2

30 digital ground 2 (0 V)
V

DDD2

31 +5 V digital supply voltage 2
V

DDA1

32 +5 V analog supply voltage for buffer of DAC 1
(R − Y) 33 ±(R − Y) output signal (analog signal)
V

SSA1

34 analog ground 1 (0 V)
V

SSA2

35 analog ground 2 (0 V)
(B − Y) 36 ±(B − Y) output signal (analog colour-difference signal)
V

DDA2

37 +5 V analog supply voltage for buffer of DAC 2
V

SSA3

38 analog ground 3 (0 V)
Y 39 Y output signal (analog luminance signal)
V

DDA3

40 +5 V analog supply voltage for buffer of DAC 3

1996 Aug 20 5

Philips Semiconductors Product specification

Video Enhancement and Digital-to-Analog
processor (VEDA2)

SAA7165

CUR 41 current input for analog output buffers
V

DDA4

42 supply and reference voltage for the three DACs
C

UV

43 capacitor for chrominance DACs (high reference)
REFL

UV

44 low reference of chrominance DACs (connected to V

SSA1

)

SYMBOL PIN DESCRIPTION

Fig.2 Pin configuration.

handbook, full pagewidth

SAA7165

MEH465

7
8

9
10
11
12
13
14
15
16
17

39
38
37
36
35
34
33
32
31
30
29

18

19

20

21

22

23

24

25

26

27

28

6

5

4

3

2

1

44

43

42

41

40

Y

SDA

V

SSA3

V

SSD2

V

SSA2

V

SSA1

V

DDA2

V

DDA1

V

DDD2

(B − Y)

(R − Y)

UV1

UV0

SUB

CYREFLYREFLUVC

UV

CUR

V

DDA4

V

DDA3

UV2

UV3
UV4
UV5
UV6
UV7

Y0
Y1
Y2
Y3

Y4

Y5

Y6

Y7

AP

SP

MC

LLC

HREF

RESET

SCL

V

DDD1

V

SSD1

1996 Aug 20 6

Philips Semiconductors Product specification

Video Enhancement and Digital-to-Analog
processor (VEDA2)

SAA7165

FUNCTIONAL DESCRIPTION

The CMOS circuit SAA7165 processes digital YUV-bus
data up to a data rate of 36 MHz. The data inputs Y7 to Y0
and UV7 to UV0 (see Fig.1) are provided with 8-bit data.
The data of digital colour-difference signals U and V are in
a multiplexed state (serial in 4 : 2:2or4:1:1format;
Tables 2 and 3).

Data is read with the rising edge of LLC (Line-Locked
Clock) to achieve a data rate of LLC at MC = HIGH only. If
MC is supplied with the frequency CREF (1⁄2LLC for
example), data is read only at every second rising edge
(see Fig.3).

The 7-bit YUV input data are also supported by means of
bit R78 (R78 = 0). Additionally, the luminance data format
is converted for internal use into a two´s complement
format by inverting the MSB. The Y input byte
(bits Y7 to Y0) represents luminance information; the UV
input byte (bits UV7 to UV0) represents one of the two
digital colour-difference signals in 4:2:2format
(Table 2).

The HREF input signal (HREF = HIGH) determines the
start and the end of an active line (see Fig.3) and the
number of pixels respectively. The analog output Y is
blanked at HREF = LOW, the (B − Y) and (R − Y) outputs
are in a colourless state. The blanking level can be set with
bit BLV. The SAA7165 is controllable via the I

2

C-bus.

Formatting Y and UV

The input data formats are formatted into the internally
used processing formats (separate for 4 :2:2 and
4:1:1formats). The IFF, IFC and IFL bits control the
input data format and determine the right interpolation filter
(see Figs 10 to 13).

Peaking and coring

Peaking is applied to the Y signal to compensate several
bandwidth reductions of the external pre-processing.
Y signals can be improved to obtain a better sharpness.
There are the two switchable bandpass filters
BF1 and BF2 controlled via the I

2

C-bus by the bits BP1,
BP0 and BFB. Thus, a frequency response is achieved in
combination with the peaking factor K (Figs 5 to 9;
K is determined by the bits BFB, WG1 and WG0).

The coring stage with controllable threshold (4 states
controlled by CO1 and CO0 bits) reduces noise
disturbances (generated by the bandpass gain) by
suppressing the amplitude of small high-frequent signal
components. The remaining high-frequent peaking
component is available for a weighted addition after
coring.

Table 1 LLCand MC configuration modes in DMSD applications (note 1)

Note

1. YUV data are only latched with the rising edge of LCC at MC = HIGH.

PIN INPUT SIGNAL DESCRIPTION

LLC LLC (LL27) The data rate on YUV-bus is half the clock rate on pin LLC, e.g. in

SAA7151B, SAA7191 and SAA7191B single scan operation.

MC CREF
LLC LLC (LL27) The data rate on YUV-bus must be identical to the clock rate on pin LLC,

e.g. in double scan applications.

MC MC = HIGH
LLC LLC (LL27) The data rate on YUV-bus must be identical to the clock rate on pin LLC,

e.g. SAA9051 single scan operation.

MC MC = HIGH

1996 Aug 20 7

Philips Semiconductors Product specification

Video Enhancement and Digital-to-Analog
processor (VEDA2)

SAA7165

Table 2 Data format 4:2:2

Table 3 Data format 4:1:1

INPUT PIXEL BYTE SEQUENCE (4 :2:2FORMAT)

Y0 (LSB) Y0 Y0 Y0 Y0 Y0 Y0
Y1 Y1 Y1 Y1 Y1 Y1 Y1
Y2 Y2 Y2 Y2 Y2 Y2 Y2
Y3 Y3 Y3 Y3 Y3 Y3 Y3
Y4 Y4 Y4 Y4 Y4 Y4 Y4
Y5 Y5 Y5 Y5 Y5 Y5 Y5
Y6 Y6 Y6 Y6 Y6 Y6 Y6
Y7 (MSB) Y7 Y7 Y7 Y7 Y7 Y7
UV0 (LSB) U0 V0 U0 V0 U0 V0
UV1 U1 V1 U1 V1 U1 V1
UV2 U2 V2 U2 V2 U2 V2
UV3 U3 V3 U3 V3 U3 V3
UV4 U4 V4 U4 V4 U4 V4
UV5 U5 V5 U5 V5 U5 V5
UV6 U6 V6 U6 V6 U6 V6
UV7 (MSB) U7 V7 U7 V7 U7 V7
Y frame 012345
UV frame 0 2 4

INPUT PIXEL BYTE SEQUENCE (4 :1:1FORMAT)

Y0 Y0 Y0 Y0 Y0 Y0 Y0 Y0 Y0
Y1 Y1 Y1 Y1 Y1 Y1 Y1 Y1 Y1
Y2 Y2 Y2 Y2 Y2 Y2 Y2 Y2 Y2
Y3 Y3 Y3 Y3 Y3 Y3 Y3 Y3 Y3
Y4 Y4 Y4 Y4 Y4 Y4 Y4 Y4 Y4
Y5 Y5 Y5 Y5 Y5 Y5 Y5 Y5 Y5
Y6 Y6 Y6 Y6 Y6 Y6 Y6 Y6 Y6
Y7 Y7 Y7 Y7 Y7 Y7 Y7 Y7 Y7
UV0 00000000
UV1 00000000
UV2 00000000
UV3 00000000
UV4 V6 V4 V2 V0 V6 V4 V2 V0
UV5 V7 V5 V3 V1 V7 V5 V3 V1
UV6 U6 U4 U2 U0 U6 U4 U2 U0
UV7 U7 U5 U3 U1 U7 U5 U3 U1
Y frame 01234567
UV frame 0 4

1996 Aug 20 8

Philips Semiconductors Product specification

Video Enhancement and Digital-to-Analog
processor (VEDA2)

SAA7165

Fig.3 Line control by HREF for 4 :2:2format, CREF = 13.5 MHz; HREF = 720 pixel; 50 and 60 Hz field.

handbook, full pagewidth

LL27

(LLC)

CREF

internal
bus clock
(LLC2)

HREF

start of
active line

0

U0

1

V0

2

U2

3

V2

4

U4

5

V4

6

U6

7

V6

Y signal

U and V signal

50 Hz

60 Hz

Byte number for pixels:

Y signal

U and V signal

MEH268

0

U0

1

V0

2

U2

3

V2

4

U4

5

V4

6

U6

7

V6

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LL27

(LLC)

CREF

internal
bus clock
(LLC2)

HREF

Y signal

U and V signal

end of
active line

714

V714

715

U716

716

V716

717

U718

718

V718

719

U714

50 Hz

MEH269

714

V714

715

U716

716

V716

717

U718

718

V718

719

U714

60 Hz

Byte number for pixels:

Y signal

U and V signal

a. Start of active line.

b. End of active line.

1996 Aug 20 9

Philips Semiconductors Product specification

Video Enhancement and Digital-to-Analog
processor (VEDA2)

SAA7165

Interpolation

The chrominance interpolation filter consists of various
filter stages, multiplexers and de-multiplexers to increase
the data rate of the colour-difference signals by a factor of
2 or 4. The switching of the filters by the bits IFF, IFC and
IFL is described previously. Additional signal samples with
significant amplitudes between two consecutive signal
samples of the low data rate are generated.
The time-multiplexed U and V samples are stored in
parallel for converting.

Data switch

The digital signals are adapted to the conversation range.
U and V data have 8-bit formats again; Y can have 9 bits
dependent on peaking. Blanking and switching to
colourless level is applied here. Bits can be inverted by
INV-bit to change the polarity of colour-difference output
signals.

Digital Colour Transient Improvement (DCTI)

The DCTI circuit improves the transition behaviour of the
UV colour-difference signals. As the CVBS signal allows
for a 4:1:1bandwidth representation only, the DCTI
improves the transients to the same performance as
signals coming from a 4:2:2source, or even more.

In order to obtain the point of inflection, the second
derivative of the signal is calculated. The improved
transition is centred with respect to the point of inflection of
the original signal. Thus, there is no horizontal shift of the
resulting signal.

The transition area length to be improved is controlled via
I

2

C-bus by the bits LI1 and LI0 (Table 5); the sensitivity of
the DCTI block is controlled by the bits GA1 and GA0.
The CMO bit controls the colour detail sensitivity. It should
be set to logic 1 (ON) if the video signal contains fine
colour details (recommended operation mode).

Digital-to-Analog Converters (DACs)

Conversion is separate for Y, U and V. The converters use
resistor chains with low-impedance output buffers.
The minimum output voltage is 200 mV to reduce integral
non-linearity errors. The analog signal, without load on
output pin, is between 0.2 and 2.2 V floating.
An application for 1 V/75 Ω on outputs is shown in Fig.14.

Each digital-to-analog converter has its own supply and
ground pins suitable for decoupling. The reference
voltage, supplying the resistor chain of all three DACs, is
the supply voltage V

DDA4

. The current into pin 41 is

0.3 mA; a larger current improves the bandwidth but
increases the integral non-linearity.

I

2

C-bus format

Table 4 I

2

C-bus format; see notes 1 to 7

Notes

1. S = START condition.

2. Slave address = 1011 111X.

3. A = acknowledge; generated by the slave.

4. Subaddress = subaddress byte (Table 5);
If more than 1 byte of DATA is transmitted, then auto-increment of the subaddress is performed.

5. Data = data byte (Table 5).

6. P = STOP condition.

7. X = R/

W control bit:
a) X = 0; order to write (the circuit is slave receiver).
b) X = 1; order to read (the circuit is slave transmitter).

S slave address A subaddress A data 0 A ... data n A P

1996 Aug 20 10

Philips Semiconductors Product specification

Video Enhancement and Digital-to-Analog
processor (VEDA2)

SAA7165

Table 5 I2C-bus transmission

Table 6 Bit functions in data bytes

Table 7 Logic levels and function of CO1and CO0

Table 8 Logic levels and function of AFB, BP1, BP0and BFB

SUBADDRESS FUNCTION

DATA BITS

D7 D6 D5 D4 D3 D2 D1 D0

01 peaking and coring AFB CO1 CO0 BP1 BP0 BFB WG1 WG0
02 input formats; interpolation IFF IFC IFL CMO LI1 LI0 GA1 GA0
03 input/output setting 0 0 DC1 DC0 DRP BLV R78 INV

BIT DESCRIPTION

CO1 and CO0 control of coring threshold; see Table7
AFB, BP1, BP0, BFB bandpass filter selection; see Table 8
BFB, WG1 and WG0 peaking factor K; see Table 9
IFF, IFC and IFL input format and filter control at 13.5 MHz data rate; see Table 10
CMO choice modification; 0 = modification off; 1 = modification on.
LI1 and LI0 DCTI timing range; see Table 11
GA1 and GA0 DCTI gain factor; see Table 12
DC1 and DC0 delay compensation of luminance signal; see Table 13
DRP UV input data code; 0 = two’s complement; 1 = offset binary
BLV blanking level on Y output; 0 = 16 LSB; 1 = 0 LSB
R78 YUV input data solution; 0 = 7-bit data; 1 = 8-bit data
INV polarity of colour-difference output signals:

0 = normal polarity equal to input signal
1 = inverted polarity

DATA BITS

FUNCTION

CO1 CO0

0 0 coring off
0 1 small noise reduction
1 0 medium noise reduction
1 1 high noise reduction

DATA BITS

FUNCTION

AFB BP1 BP0 BFB

X 0 0 0 characteristic (see Fig.5)
X 0 1 0 characteristic (see Fig.6)
X 1 0 0 characteristic (see Fig.7)
X 1 1 0 characteristic (see Fig.8)
0 X X 1 BF1 filter bypassed (see Fig.9a)
1 X X 1 BF1 filter bypassed (see Fig.9b)

1996 Aug 20 11

Philips Semiconductors Product specification

Video Enhancement and Digital-to-Analog
processor (VEDA2)

SAA7165

Table 9 Logic levels and function of BFB, WG1and WG0

Table 10 Logic levels and function of IFF, IFC and IFL

DATA BITS

FUNCTION

BFB WG1 WG0

000K=

1

⁄

8

; minimum peaking

001K=

1

⁄

4

010K=

1

⁄

2

0 1 1 K = 1; maximum peaking
1 0 0 K = 0; peaking off
101K=

1

⁄

4

; minimum peaking

110K=

1

⁄

2

1 1 1 K = 1; maximum peaking

DATA BITS

FUNCTION

IFF IFC IFL

0 0 0 4:1:1format; −3 dB attenuation at 1.6 MHz video frequency; (see Fig.10)
0 0 1 4:1:1format; −3 dB attenuation at 600 kHz video frequency; (see Fig.11)
0 1 X 4:1:1format; −3 dB attenuation at 1.2 MHz video frequency; (see Fig.12)
1 0 0 4:2:2format; −3 dB attenuation at 1.6 MHz video frequency; (see Fig.10)
1 0 1 4:2:2format; −3 dB attenuation at 600 kHz video frequency; (see Fig.11)
1 1 X 4:2:2format; −3 dB attenuation at 2.5 MHz video frequency; (see Fig.13)

Table 11 Logic levels and function of LI1 and LI0

Table 12 Logic levels and function of GA1 and GA0

DATA BITS

RANGE

LI1 LI0

0 0 +4 to −4
0 1 +6 to −6
1 0 +8 to −8
1 1 +12 to −12

DATA BITS

FACTOR

GA1 GA0

0 0 off
01

1

⁄

4

10

1

⁄

2

111

Table 13 Logic levels and function of DC1 and DC0

DATA BITS

DELAYED CLOCK

CYCLES

DC1 DC0

000
01+1
10−2
11−1

1996 Aug 20 12

Philips Semiconductors Product specification

Video Enhancement and Digital-to-Analog
processor (VEDA2)

SAA7165

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC134).

Note

1. Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER MIN. MAX. UNIT

V

DDD1

digital supply voltage 1 (pin 12) −0.3 +7 V

V

DDD2

digital supply voltage 2 (pin 31) −0.3 +7 V

V

DDA1

analog supply voltage 1 (pin 32) −0.3 +7 V

V

DDA2

analog supply voltage 2 (pin 37) −0.3 +7 V

V

DDA3

analog supply voltage 3 (pin 40) −0.3 +7 V

V

DDA4

analog supply voltage 4 (pin 42) −0.3 +7 V

V

DDD

digital supply voltage −0.5 +7 V

∆V

GND

difference voltage V

SSD

− V

SSA

−±100 mV

V

I

voltage on all input pins 4 to 11, 14 to 27 and 41 −0.3 V

DDD

V

V

O

voltage on analog output pins 33, 36 and 39 −0.3 V

DDD

V

V

ESD

electrostatic handling for all pins ±2000 − V

P

tot

total power dissipation 0 tbf mW

T

stg

storage temperature −55 +150 °C

T

amb

operating ambient temperature 0 70 °C

SYMBOL PARAMETER VALUE UNIT

R

th j-a

thermal resistance from junction to ambient in free air 46 K/W

1996 Aug 20 13

Philips Semiconductors Product specification

Video Enhancement and Digital-to-Analog
processor (VEDA2)

SAA7165

CHARACTERISTICS

V

DDD

= 4.5 to 5.5 V; V

DDA

= 4.75 to 5.25 V; LLC = LL27; MC = CREF = 13.5 MHz; T

amb

= 0 to 70 °C; measurements

taken in Fig.14; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

DDD1

supply voltage range (pin 12) for digital part 4.5 5 5.5 V

V

DDD2

supply voltage range (pin 31) for digital part 4.5 5 5.5 V

V

DDA1

supply voltage range (pin 32) for buffer of DAC 1 4.75 5 5.25 V

V

DDA2

supply voltage range (pin 37) for buffer of DAC 2 4.75 5 5.25 V

V

DDA3

supply voltage range (pin 40) for buffer of DAC 3 4.75 5 5.25 V

V

DDA4

supply voltage range (pin 42) DAC reference voltage 4.75 5 5.25 V

I

DDD

supply current (I

DDD1+IDDD2

) for digital part − tbf tbf mA

I

DDA

supply current (I

DDA1+IDDA4

) for DACs and buffers − tbf tbf mA
YUV-bus inputs (pins 4 to 11 and 14 to 21) (see Figs 3 and 4)
V

IL

LOW-level input voltage −0.5 − +0.8 V

V

IH

HIGH-level input voltage 2.0 − V

DDD

+ 0.5 V

C

I

input capacitance VI= HIGH −−10 pF

I

LI

input leakage current −−4.5 µA

Inputs AP, SP, MC, LLC, HREF and

RESET (pins 22 to 27)

V

IL

LOW-level input voltage −0.5 − +0.8 V

V

IH

HIGH-level input voltage 2.0 − V

DDD

+ 0.5 V

C

I

input capacitance VI= HIGH −−10 pF

I

LI

input leakage current −−4.5 µA

V

24

MC input voltage for LL27 27 MHz data rate 2.0 − V

DDD

+ 0.5 V

CREF signal on MC input CREF data rate; note 1 −−− V

I

2

C-bus SCL and SDA (pins 28 and 29)

V

IL

LOW-level input voltage −0.5 − +1.5 V

V

IH

HIGH-level input voltage 3.0 − V

DDD

+ 0.5 V

I

I

input current VI= LOW or HIGH −−±10 µA

V

ACK

output voltage at acknowledge
(pin 29)

I29=3mA −−0.4 V

I

29

output current during acknowledge 3 −− mA

Digital-to-analog converters (pins 1, 2, 41, 42, 43 and 44)

V

DAC

input reference voltage for internal
resistor chains (pin 42)

4.75 5 5.25 V

I

CUR

input current (pin 41) R

41-42

=15kΩ−300 −µA

V

1,44

reference voltage LOW pin connected to V

SSA1

− 0 − V

C

L

external blocking capacitor to
V

SSA1

for reference voltage HIGH

(pins 2 and 43)

− 0.1 −µF

f

LLC

data conversation rate (clock) Fig.3 −−36 MHz

1996 Aug 20 14

Philips Semiconductors Product specification

Video Enhancement and Digital-to-Analog
processor (VEDA2)

SAA7165

Notes

1. YUV-bus data is read at MC = HIGH (pin 24) clocked with LLC (see Fig.5); data is read only with every second rising
edge of LLC when CREF =1⁄2LLC on pin 24.

2. 0.2 to 2.2 V output voltage range at 8-bit DAC input data; the data word can increase to 9-bit dependent on peaking
factor.

3. The luminance signal is set to the digital black level: 16 LSB for BLV-bit = 0; 0 LSB for BLV-bit = 1.

4. The chrominance amplitudes are set to the digital colourless level of 128 LSB.

5. The circuit is prepared for a new data initialization.

RES

DAC

resolution luminance DAC − 9 − bits

chrominance DACs − 8 − bits
ILE DC integral linearity error 8-bit data −−1.0 LSB
DLE DC differential error 8-bit data −−0.5 LSB

Y, (R − Y) and (B − Y) analog outputs (pins 33, 36 and 39)

V

o(p-p)

output signal voltage
(peak to peak value)

without load − 2 − V

V

33,36,39

output voltage range without load; note 2 0.2 − 2.2 V

V

39

output blanking level Y output; note 3 − 16 − LSB

V

33,36

output no-colour level ±(R − Y), ±(B − Y);

note 4

− 128 − LSB

R

33,36,39

internal serial output resistance − 25 −Ω

R

L33,36,39

output load resistance external load 125 −− Ω
B output signal bandwidth −3dB 20 −− MHz
t

d

signal delay from input to Y output − tbf − ns
LCC timing (pin 25) (see Fig.3)
T

LLC

cycle time 27.7 37 41 ns
t

pH

pulse width 40 50 60 %
t

r

rise time −−5ns
t

f

fall time −−6ns
YUV-bus timing (pins 4 to 11 and 14 to 21) (see Fig.5)
t

SU;DAT

input data set-up time 10 −− ns
t

HD;DAT

input data hold time 3 −− ns
MC timing (pin 24) (see Fig.5)
t

SU;DAT

input data set-up time 10 −− ns
t

HD;DAT

input data hold time 3 −− ns

RESET timing (pin 27)

t

SU

set-up time after power-on or

failure

active LOW; note 5 4 × t

LLC

−− ns

1996 Aug 20 15

Philips Semiconductors Product specification

Video Enhancement and Digital-to-Analog
processor (VEDA2)

SAA7165

Fig.4 YUV-bus data and CREF timing.

handbook, full pagewidth

MEH270

1.5 V

input clock

LLC (LL27)

input data

YUV-bus,

CREF (MC)

0.6 V

2.0 V

t

SU;DAT(min)

t

HD;DAT(min)

t

HD;DAT

T

LLC

data valid

t

f

t

r

T

LLCH

0.8 V

2.4 V

Table 14 YUV-bus data processing delay

PROCESSING DELAY LLC CYCLES REMARKS

YUV digital input 66 at MC = 1
YUV analog output 132 at MC =1⁄2LLC

1996 Aug 20 16

Philips Semiconductors Product specification

Video Enhancement and Digital-to-Analog
processor (VEDA2)

SAA7165

Fig.5 Peaking frequency response with I2C-bus control bits BP1 = 0; BP0 = 0 and BFB = 0.

handbook, full pagewidth

MEH271

03

2

45

12

16

10

14

8

6

4

2

0

fY (MHz)

V

Y

(dB)

1 6

7

(1)

(2)

(3)

(4)

(1) K = 1
(2) K =1⁄

2

(3) K =1⁄

4

(4) K =1⁄

8

Fig.6 Peaking frequency response with I2C-bus control bits BP1 = 0; BP0 = 1 and BFB = 0.

handbook, full pagewidth

MEH272

03

2

45

12

16

10

14

8

6

4

2

0

fY (MHz)

V

Y

(dB)

1 6

7

(1)

(2)

(3)

(4)

(1) K = 1
(2) K =1⁄

2

(3) K =1⁄

4

(4) K =1⁄

8

1996 Aug 20 17

Philips Semiconductors Product specification

Video Enhancement and Digital-to-Analog
processor (VEDA2)

SAA7165

Fig.7 Peaking frequency response with I2C-bus control bits BP1 = 1; BP0 = 0 and BFB = 0.

handbook, full pagewidth

MEH273

03

2

45

12

16

10

14

8

6

4

2

0

fY (MHz)

V

Y

(dB)

1 6

7

(1)

(2)

(3)

(4)

(1) K = 1
(2) K =1⁄

2

(3) K =1⁄

4

(4) K =1⁄

8

Fig.8 Peaking frequency response with I2C-bus control bits BP1 = 1; BP0 = 1 and BFB = 0.

handbook, full pagewidth

MEH274

03

2

45

12

16

10

14

8

6

4

2

0

fY (MHz)

V

Y

(dB)

1 6

7

(1)

(2)

(3)

(4)

(1) K = 1
(2) K =1⁄

2

(3) K =1⁄

4

(4) K =1⁄

8

1996 Aug 20 18

Philips Semiconductors Product specification

Video Enhancement and Digital-to-Analog
processor (VEDA2)

SAA7165

Fig.9 Peaking frequency response with I2C-bus control bits BP1 = 0; BP0 = 0 and BFB = 1; bandpass filter BF1

bypassed and peaking off.

handbook, full pagewidth

MEH470

03

2

45

2

6

0

4

f

Y

(MHz)

V

Y

(dB)

1 6

7

8

10

−2

−4

(1)

(2)

(3)

(4)

handbook, full pagewidth

MEH471

03

2

45

2

6

0

4

f

Y

(MHz)

V

Y

(dB)

1 6

7

8

10

−2

−4

(1)

(2)

(3)

(4)

a. AFB = 0.

b. AFB = 1.

(1) K = 1
(2) K =1⁄

2

(3) K =1⁄

4

(4) K = 0

1996 Aug 20 19

Philips Semiconductors Product specification

Video Enhancement and Digital-to-Analog
processor (VEDA2)

SAA7165

Fig.10 Interpolation filter at DCTI off with I2C-bus control bits IFF = 0; IFC = 0 and IFL = 0 in 4 : 1 : 1 format and

control bits IFF = 1; IFC = 0 and IFL = 0 in 4 : 2 : 2 format; 13.5 MHz data rate.

handbook, full pagewidth

MEH474

03

2

45

−24

−20

−16

−12

−8

−4

0

fY (MHz)

V

U

(dB)

1 6

7

−28

−32

Fig.11 Interpolation filter at DCTI off with I2C-bus control bits IFF = 0; IFC = 0 and IFL = 1 in 4 : 1 : 1 format and

control bits IFF = 1; IFC = 0 and IFL = 1 in 4 : 2 : 2 format; 13.5 MHz data rate.

handbook, full pagewidth

MEH473

03

2

45

−24

−20

−16

−12

−8

−4

0

fY (MHz)

V

U

(dB)

1 6

7

−28

−32

1996 Aug 20 20

Philips Semiconductors Product specification

Video Enhancement and Digital-to-Analog
processor (VEDA2)

SAA7165

Fig.12 Interpolation filter at DCTI off with I2C-bus control bits IFF = 0; IFC = 1 and IFL = 0 in 4:1:1format;

13.5 MHz data rate.

handbook, full pagewidth

MEH472

03

2

45

−24

−20

−16

−12

−8

−4

0

fY (MHz)

V

U

(dB)

1 6

7

−28

−32

Fig.13 Interpolation filter with I2C-bus control bits IFF = 1; IFC = 1 and IFL = X in 4 : 2 : 2 format;

13.5 MHz data rate.

handbook, full pagewidth

MEH475

03

2

45

−48

−40

−32

−3 dB

−24

−16

−8

0

fY (MHz)

V

U

(dB)

1 6

7

−56

−64

1996 Aug 20 21

Philips Semiconductors Product specification

Video Enhancement and Digital-to-Analog

processor (VEDA2)

SAA7165

This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in

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APPLICATION INFORMATION

handbook, full pagewidth

MBH537

INTERPOLATION

FILTER

Y

FORMATTER

0.1 µF

DCTI

SAA7165

Y

U

V

DATA

SWITCH

DAC 3

41 42

CUR

V

DDA4

25 Ω

36

PEAKING

AND

CORING

DAC 2

DAC 1

UV

FORMATTER

TIMING

CONTROL

I2C-BUS

CONTROL

TEST

CONTROL

40

V

DDA3

37

V

DDA2

32

V

DDA1

31

+5 V

V

DDD2

12

13
V

SSD1

V

DDD1

data clock

21 to 14

8

Y7 to Y0

11 to 4

24

27

25
26

28

29

8

UV7 to

UV0

CREF

LL27

MC

LLC

HREF

RESET

SCL

SDA

YUV-bus

I2C-bus

25 Ω

33

±(B − Y)

25 Ω

50 Ω

1 V (p−p)

75 Ω

39

1

15 kΩ

Y

C

UV

REFL

UV

REFL

Y

2

C

Y

43

44

30
V

SSD2

22
AP

23
SP

34
V

SSA1

35
V

SSA2

38
V

SSA3

3
SUB

0.1 µF 0.1 µF

+5 V

+5 V

0.1 µF 0.1 µF

0.1 µF

0.1 µF

0.1 µF

0.1 µF

(1)

(1)

50 Ω

1 V (p−p)

75 Ω

(1)

(1)

±(R − Y)

50 Ω

1 V (p−p)

75 Ω

(1)

(1)

Fig.14 Application diagram.

(1) output amplitude determined by resistors (RL> 125Ω).

1996 Aug 20 22

Philips Semiconductors Product specification

Video Enhancement and Digital-to-Analog
processor (VEDA2)

SAA7165

PACKAGE OUTLINE

UNIT A

A

min. max. max. max. max.

1

A

4

b

p

E

(1)

(1) (1)

eH

E

Z

ywv β

REFERENCES

OUTLINE
VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

mm

4.57

4.19

0.51

3.05

0.53

0.33

0.021

0.013

16.66

16.51

1.27

17.65

17.40

0.51

2.16
45

o

0.18 0.100.18

DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)

Note

1. Plastic or metal protrusions of 0.01 inches maximum per side are not included.

SOT187-2

D

(1)

16.66

16.51

H

D

17.65

17.40

E

Z

2.16

D

b

1

0.81

0.66

k

1.22

1.07

k

1

0.180

0.165

0.020

0.12

A

3

0.25

0.01

0.656

0.650

0.05

0.695

0.685

0.020

0.085

0.007 0.0040.007

L

p

1.44

1.02

0.057

0.040

0.656

0.650

0.695

0.685

e

E

e

D

16.00

14.99

0.630

0.590

16.00

14.99

0.630

0.590

0.085

0.032

0.026

0.048

0.042

2939

44

1

6

717

28

18

40

detail X

(A )

3

b

p

w M

A

1

A

A

4

L

p

b

1

β

k

1

k

X

y

e

E

B

D

H

E

e

E

H

v M

B

D

Z

D

A

Z

E

e

v M

A

pin 1 index

112E10 MO-047AC

0 5 10 mm

scale

95-02-25
97-12-16

inches

PLCC44: plastic leaded chip carrier; 44 leads

SOT187-2

D

e

1996 Aug 20 23

Philips Semiconductors Product specification

Video Enhancement and Digital-to-Analog
processor (VEDA2)

SAA7165

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“IC Package Databook”

(order code 9398 652 90011).

Reflow soldering

Reflow soldering techniques are suitable for all PLCC
packages.

The choice of heating method may be influenced by larger
PLCC packages (44 leads, or more). If infrared or vapour
phase heating is used and the large packages are not
absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our

“Quality

Reference Handbook”

(order code 9397 750 00192).

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.

Wave soldering

Wave soldering techniques can be used for all PLCC
packages if the following conditions are observed:

• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.

• The longitudinal axis of the package footprint must be
parallel to the solder flow.

• The package footprint must incorporate solder thieves at
the downstream corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

1996 Aug 20 24

Philips Semiconductors Product specification

Video Enhancement and Digital-to-Analog
processor (VEDA2)

SAA7165

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

PURCHASE OF PHILIPS I

2

C COMPONENTS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Purchase of Philips I

2

C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.

1996 Aug 20 25

Philips Semiconductors Product specification

Video Enhancement and Digital-to-Analog
processor (VEDA2)

SAA7165

NOTES

1996 Aug 20 26

Philips Semiconductors Product specification

Video Enhancement and Digital-to-Analog
processor (VEDA2)

SAA7165

NOTES

1996 Aug 20 27

Philips Semiconductors Product specification

Video Enhancement and Digital-to-Analog
processor (VEDA2)

SAA7165

NOTES

Internet: http://www.semiconductors.philips.com

Philips Semiconductors – a worldwide company

© Philips Electronics N.V. 1996 SCA51
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

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Metro MANILA, Tel. [phone], Fax. [phone]

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Indonesia: see Singapore
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Printed in The Netherlands 657021/1200/02/pp28 Date of release: 1996 Aug20 Document order number: 9397 750 01047