Datasheet SAA7157T, SAA7157 Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

SAA7157

Clock signal generator circuit for
digital TV systems (SCGC)

Product specification
File under Integrated Circuits, IC02

May 1992

Philips Semiconductors Product specification

Clock signal generator circuit for digital

SAA7157

TV systems (SCGC)

FEATURES

• Clock generation suitable for digital TV systems (line-locked)

• PLL frequency multiplier to generate 4 times of input frequency

• Dividers to generate clocks LL1.5A, LL1.5B, LL3A and LL3B (4th and 2nd multiples of input frequency)

• PLL mode or VCO mode selectable

• Reset control and power fail detection

• Suitable for applications with feature box and picture memory

GENERAL DESCRIPTION

The SAA7157 generates all clock signals required for a digital TV system suitable for the SAA715x family and the
SAA7199B (DENC). The circuit operates in either the phase-locked loop mode (PLL) or voltage controlled oscillator
mode (VCO).

QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V
V
I

DDA

I

DDD

V

f

i

V

V

T

DDA
DDD

LFCO

I

O

amb

analog supply voltage (pin 5) 4.5 5.0 5.5 V
digital supply voltage (pins 8, 17) 4.5 5.0 5.5 V
analog supply current 3 - 9 mA
digital supply current 10 - 60 mA
LFCO input voltage

(peak-to-peak value) 1 - V

DDA

V
input frequency range 6.0 - 7.25 MHz
input voltage LOW

input voltage HIGH
output voltage LOW

output voltage HIGH

0

2.0-­0

2.6--

0.8
V

0.6
V

DDD

DDD

V

V

V

V
operating ambient temperature range 0 - 70 °C

ORDERING INFORMATION

EXTENDED

TYPE NUMBER

PINS PIN POSITION MATERIAL CODE

SAA7157 20 DIL plastic SOT146

SAA7157T 20 mini-pack (SO20) plastic SOT163A

Note

1. SOT146-1; 1996 December 17.

2. SOT163-1; 1996 December 17.

May 1992 2

PACKAGE

(1)

(2)

Philips Semiconductors Product specification

Clock signal generator circuit for digital TV
systems (SCGC)

handbook, full pagewidth

MS

LFCO

LFCO2

CE

1

LOOP

FILTER

MS = LOW

PHASE

DETECTOR

11

19
2

PRE-FILTER

AND

PULSE

SHAPER

V

DDAVDDD1VDDD2

5 8 17

VCO

SAA7157

FREQUENCY

DIVIDER

1 : 2

POWER-ON

RESET

LFCOSEL

316 4 6, 9, 13, 18

PORD

FREQUENCY

DIVIDER

1 : 2

DELAY

V

SSA

V

SSD

10

14

20

15

12

MEH452

SAA7157

7

LL1.5A
(LL27A)

LL1.5B
(LL27B)

LL3A

LL3B

CREF

RESN

Fig.1 Block diagram.

FUNCTIONAL DESCRIPTION

The SAA7157 generates all clock signals required for a
digital TV system suitable for the SAA715x family
consisting of an 8-bit analog-to-digital converter (ADC8),
digital video multistandard decoder (DMSD2) and video
enhancement and D/A processor circuit (VEDA). Optional
extras (feature box, video memory etc.) can be driven via
external buffers, advantageous for a digital TV system
based on display standard conversion concepts.
The 6.75 MHz input signal LFCO (triangular waveform)
coming from the DMSD or LFCO2 is multiplied to 27 MHz
by the PLL (including phase detector, loop filter, VCO and
frequency divider) and output on LL1.5A (pin 7) and
LL1.5B (pin 10). The 13.5 MHz frequencies are generated
by dividers using ratio of 1:2 and are output on LL3A (pin

14) and LL3B (pin 20).
The rectangular output signals have 50% duty factor.
Outputs with equal frequency may be connected together
externally. The clock outputs go HIGH during power-on
reset (and chip enable) to ensure that no output clock
signals are available before the PLL has locked-on.

Mode select MS

The LFCO input signal is directly connected to the VCO at
MS = HIGH. The circuit operates as an oscillator and
frequency divider. This function is not tested.

Source select LFCOSEL

Line frequency control signal (LFCO) is selected by
LFCOSEL input.
LFCOSEL = LOW:
signal from LFCO (pin 11) is selected.
LFCOSEL = HIGH:
signal from LFCO2 (pin 19) is selected.
This function is not tested.

Chip enable CE

The buffer outputs are enabled and RESN is set to HIGH
by
CE = HIGH (Fig.4).
CE = LOW sets the clock outputs HIGH and RESN output
LOW.

May 1992 3

Philips Semiconductors Product specification

Clock signal generator circuit for digital TV

SAA7157

systems (SCGC)

CREF output

TV2 digital clock reference output signal. Clock qualifier signal to TV system with 2 times of LFCO or LFCO2 frequency.

Power-on reset

Power-on reset is activated at power-on, when the supply voltage decreases below 3.5 V (Fig.4) or when chip enable is
done. The indicator output RESN is LOW for a time determined by capacitor on pin 3. The RESN signal can be applied
to reset other circuits of this digital TV system.
The LFCO or LFCO2 input signals have to be applied before RESN becomes HIGH.

PINNING

SYMBOL PIN DESCRIPTION

MS 1 mode select input (LOW = PLL mode)
CE 2 chip enable /reset (HIGH = outputs enabled)
PORD 3 power-on reset delay, dependent on external capacitor
V

SSA

V

DDA

V

SSD1

LL1.5A 7 line-locked clock output signal 1.5A (4 times f
V

DDD1

V

SSD2

LL1.5B 10 line-locked clock output signal 1.5B (4 times f
LFCO 11 line-locked frequency control input signal 1
RESN 12 reset output (active-LOW, Fig.4)
V

SSD3

LL3A 14 line-locked clock output signal 3A (2 times f
CREF 15 clock reference output, qualifier signal (2 times f
LFCOSEL 16 LFCO source select (LOW = LFCO selected)
V

DDD2

V

SSD4

LFCO2 19 line-locked frequency control input signal 2
LL3B 20 line-locked clock output signal 3B (2 times f

4 analog ground (0 V)
5 analog supply voltage (+5 V)
6 digital ground 1 (0 V)

8 digital supply voltage 1 (+5 V)
9 digital ground 2 (0 V)

13 digital ground 3 (0 V)

17 digital supply voltage 2 (+5 V)
18 digital ground 4 (0 V)

LFCO

(1)

LFCO

LFCO

LFCO

(1)

)

)

)

LFCO

)

)

Note

1. MS and LFCO2 functions are not tested. LFCO2 is a multiple of horizontal frequency.

May 1992 4

Philips Semiconductors Product specification

Clock signal generator circuit for digital TV
systems (SCGC)

PIN CONFIGURATION

Fig.2 Pin configuration.

SAA7157

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134); ground pins as well as supply pins together
connected.

SYMBOL PARAMETER MIN. MAX. UNIT

V

DDA

V

DDD

V

diff GND

V

O

P

tot

T

stg

T

amb

V

ESD

analog supply voltage (pin 5) −0.5 7.0 V
digital supply voltage (pins 8 and 17) −0.5 7.0 V
difference voltage V
output voltage (IOM= 20 mA) −0.5 V

DDA

− V

DDD

- ±100 mV

DDD

V

total power dissipation (DIL20) 0 1.1 W
storage temperature range −65 150 °C
operating ambient temperature range 0 70 °C
electrostatic handling

(1)

for all pins - tbf V

Notes

1. Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
recommended to take normal handling precautions appropriate to

“Handling MOS devices”

.

May 1992 5

Philips Semiconductors Product specification

Clock signal generator circuit for digital TV

SAA7157

systems (SCGC)

CHARACTERISTICS

= 4.5 to 5.5 V; V

V

DDA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

DDA

V

DDD

I

DDA

I

DDD

V

reset

analog supply voltage (pin 5) 4.5 5.0 5.5 V
digital supply voltage (pins 8 and 17) 4.5 5.0 5.5 V
analog supply current (pin 5) 3 − 9mA
digital supply current (I8+ I17) note 1 10 − 60 mA

power-on reset threshold voltage Fig.4 − 3.5 − V
Input LFCO (pin 11)
V

11

V

i

f

LFCO

C

11

DC input voltage 0 − V

input signal (peak-to-peak value) 1 − V

input frequency range 6.0 − 7.25 MHz

input capacitance −−10 pF
Inputs MS, CE, LFCOSEL and LFCO2 (pins 1, 2, 16 and 19); note 3
V

IL

V

IH

f

LFCO2

I

LI

C

I

input voltage LOW 0 − 0.8 V

input voltage HIGH 2.0 − V

input frequency range for LFCO2 6.0 − 7.25 MHz

input leakage current LFCOSEL 50 − 150 µA

input capacitance −−5pF
Output RESN (pin 12)
V

OL

V

OH

t

d

output voltage LOW I

output voltage HIGH IOH= −0.5 mA 2.4 − V

RESN delay time C3= 0.1 µF; Fig.4 20 − 200 ms
Output CREF (pin 15)
V

OL

V

OH

f

CREF

C

L

t

SU

t

HD

output voltage LOW I

output voltage HIGH IOH= −0.5 mA 2.4 − V

output frequency CREF Fig.3 − 2 f

output load capacitance 15 − 40 pF

set-up time Fig.3; note 1 12 −−ns

hold time Fig.3; note 1 4 −−ns

= 4.5 to 5.5 V; f

DDD

= 6.0 to 7.25 MHz and T

LFCO

others −−10 µA

O L

O L

= 0 to 70 °C unless otherwise specified.

amb

DDA
DDA

DDD

= 2 mA 0 − 0.4 V

DDD

= 2 mA 0 − 0.6 V

DDD

LFCO(2)

V
V

V

V

V
MHz

May 1992 6

Philips Semiconductors Product specification

Clock signal generator circuit for digital TV

SAA7157

systems (SCGC)

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Output signals LL1.5A, LL1.5B, LL3A and LL3B (pins 7, 10, 14, and 20); note 3

V

OL

V

OH

t

comp

f

LL

t

, t

r

f

t

LL

Notes

1. f

LFCO

2. t

is the rise time from LOW of all clocks to HIGH of all clocks (Fig.3) including rise time, skew and jitter

comp

components. Measurements taken between 0.6 V and 2.6 V. Skew between two LLx clocks will not deviate more
than ±2 ns if output loads are matched within 20%.

3. MS and LFCO2 functions not tested.

output voltage LOW I

= 2 mA 0 - 0.6 V

O L

output voltage HIGH IOH= −0.5 mA 2.6 - V

composite rise time Fig.3; notes 1 and 2 - - 8 ns

output frequency LL1.5A Fig.3 - 4 f

output frequency LL1.5B - 4 f

output frequency LL3A - 2 f

output frequency LL3B - 2 f

LFCO(2)
LFCO(2)
LFCO(2)
LFCO(2)

rise and fall times note 1; Fig.3 - - 5 ns

duty factor LL1.5A, LL1.5B, LL3A

and LL3B (mean values)

= 7.0 MHz and output load 40 pF (Fig.3). V

note 1; Fig.3;
at 1.5 V level 43 50 57 %

SSA

and V

short connected together.

SSD

DDD

V

MHz
MHz
MHz
MHz

handbook, full pagewidth

CREF

LL1.5A
LL1.5B

LL3A
LL3B

t

comp

t

HD

t

LL1.5H

t

LL3H

t

SU

t

LL1.5

t

LL1.5L

t

f

t

LL3

t

f

Fig.3 Output timing.

2.4 V

0.6 V

t

HD

2.6 V

1.5 V

0.6 V

t

r

t

LL3L

2.6 V

1.5 V

0.6 V

t

r

MEH456

May 1992 7

Philips Semiconductors Product specification

Clock signal generator circuit for digital TV
systems (SCGC)

handbook, full pagewidth

V

DDA

V

DDD

LFCO

RESN

LL1.5A
LL1.5B
LL3A
LL3B

power-on

t

clock HIGH

during

internal reset

reset time

d

oscillation

operation

PLL lock-on

normal

oscillation disturbed

t

d

power failure
starts a new

reset procedure

normal

operation

SAA7157

+3.5 V

0 V

MEH457

handbook, full pagewidth

MS
CE
LFCOSEL
LFCO2

LFCO

Fig.4 Reset procedure.

V

V

DDD

SSD

1

2
16
19

11

V

V

V

V

DDD

SSD

DDD

SSD

10
14
15
20

12

7

LL1.5A
LL1.5B
LL3A
LL3B
CREF

RESN

MEH468

Fig.5 Internal circuit.

May 1992 8

Philips Semiconductors Product specification

Clock signal generator circuit for digital TV
systems (SCGC)

PACKAGE OUTLINE

DIP20: plastic dual in-line package; 20 leads (300 mil)

D

seating plane

L

Z

20

e

b

SAA7157

SOT146-1

M

E

A

2

A

A

1

w M

b

1

11

c

(e )

1

M

H

pin 1 index

1

0 5 10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

A

A

UNIT

inches

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

max.

mm

OUTLINE
VERSION

SOT146-1

1 2

min.

max.

1.73

1.30

0.068

0.051

IEC JEDEC EIAJ

b

b

1

0.53

0.38

0.021

0.015

0.36

0.23

0.014

0.009

REFERENCES

cD E e M

(1) (1)

26.92

26.54

1.060

1.045

SC603

6.40

6.22

0.25

0.24

E

10

(1)

M

e

L

1

3.60

3.05

0.14

0.12

8.25

7.80

0.32

0.31

EUROPEAN

PROJECTION

H

E

10.0

0.2542.54 7.62

8.3

0.39

0.010.10 0.30

0.33

ISSUE DATE

92-11-17
95-05-24

Z

w

max.

2.04.2 0.51 3.2

0.0780.17 0.020 0.13

May 1992 9

Philips Semiconductors Product specification

Clock signal generator circuit for digital TV
systems (SCGC)

SO20: plastic small outline package; 20 leads; body width 7.5 mm

D

c

y

Z

20

11

SAA7157

SOT163-1

E

H

E

A

X

v M

A

pin 1 index

1

e

0 5 10 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

UNIT

mm

inches

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

A

max.

2.65

0.10

A

1

0.30

0.10

0.012

0.004

A2A

2.45

2.25

0.096

0.089

0.25

0.01

b

0.49

0.36

p

cD

0.32

0.23

0.013

0.009

3

0.019

0.014

10

w M

b

p

scale

(1)E(1) (1)

13.0

12.6

0.51

0.30

0.49

0.29

eHELLpQ

7.6

1.27

7.4

0.050

10.65

10.00

0.419

0.394

Q

A

2

A

1

1.4

0.055

1.1

0.4

0.043

0.016

detail X

1.1

1.0

0.043

0.039

(A )

L

p

L

0.25

0.01

A

3

θ

0.25 0.1

0.01

ywv θ

Z

0.9

0.4

0.035

0.004

0.016

o

8

o

0

OUTLINE

VERSION

SOT163-1

IEC JEDEC EIAJ

075E04 MS-013AC

REFERENCES

May 1992 10

EUROPEAN

PROJECTION

ISSUE DATE

95-01-24
97-05-22

Philips Semiconductors Product specification

Clock signal generator circuit for digital TV
systems (SCGC)

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in

“IC Package Databook”

our

DIP

SOLDERING BY DIPPING OR BY WA VE
The maximum permissible temperature of the solder is

260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.

R

EPAIRING SOLDERED JOINTS

Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.

SO

REFLOW SOLDERING

(order code 9398 652 90011).

). If the

stg max

SAA7157

method. Typical reflow temperatures range from
215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.

W

AVE SOLDERING

Wave soldering techniques can be used for all SO
packages if the following conditions are observed:

• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.

• The longitudinal axis of the package footprint must be
parallel to the solder flow.

• The package footprint must incorporate solder thieves at
the downstream end.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

R

EPAIRING SOLDERED JOINTS

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

Reflow soldering techniques are suitable for all SO
packages.

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating

May 1992 11

Philips Semiconductors Product specification

Clock signal generator circuit for digital TV

SAA7157

systems (SCGC)

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

May 1992 12