Datasheet SAA7126H, SAA7127H Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

SAA7126H; SAA7127H

Digital video encoder

Product specification
File under Integrated Circuits, IC22

1999 May 31

Philips Semiconductors Product specification

Digital video encoder SAA7126H; SAA7127H

FEATURES

• Monolithic CMOS 3.3 V device, 5 V I2C-bus optionally

• Digital PAL/NTSC encoder

• System pixel frequency 13.5 MHz

• 54 MHz double-speed multiplexed D1 interface capable

of splitting data into two separate channels (encoded
and baseband)

• Four Digital-to-Analog Converters (DACs) for CVBS
(CSYNC, VBS), RED (Cr, C), GREEN (Y, VBS) and
BLUE (Cb, CVBS) two times oversampled (signals in
parenthesis are optionally). RED (Cr), GREEN (Y) and
BLUE (Cb) signal outputs with 9-bit resolution, whereas
all other signal outputs have 10-bit resolution; CSYNC is
an advanced composite sync on the CVBS output for
RGB display centring.

• Real-time control of subcarrier

• Cross-colour reduction filter

• Closed captioning encoding and World Standard

Teletext (WST) and North-American Broadcast Text
System (NABTS) teletext encoding including sequencer
and filter

• Copy Generation Management System (CGMS)
encoding (CGMS described by standard CPR-1204 of
EIAJ); 20 bits in lines 20/283 (NTSC) can be loaded via

2

C-bus

the I

• Fast I2C-bus control port (400 kHz)

• Line 23 Wide Screen Signalling (WSS) encoding

• Video Programming System (VPS) data encoding in

line 16 (CCIR line count)

• Encoder can be master or slave

• Programmable horizontal and vertical input

synchronization phase

• Programmable horizontal sync output phase

• Internal Colour Bar Generator (CBG)

• Macrovision Pay-per-View copy protection system

rev. 7.01 and rev. 6.1 as option; ‘handsfree’ Macrovision
pulse support through on-chip timer for pulse amplitude
modulation; this applies to SAA7126H only. The device
is protected by USA patent numbers 4631603, 4577216
and 4819098 and other intellectual property rights.
Use of the Macrovision anti-copy process in the device
is licensed for non-commercial home use only. Reverse
engineering or disassembly is prohibited. Please
contact your nearest Philips Semiconductors sales
office for more information.

• Controlled rise/fall times of output syncs and blanking

• On-chip crystal oscillator (3rd-harmonic or fundamental

crystal)

• Down mode (low output voltage) or power-save mode of
DACs

• QFP44 package.

GENERAL DESCRIPTION

The SAA7126H; SAA7127H encodes digital Cb-Y-Cr
video data to an NTSC or PAL CVBS or S-video signal.
Simultaneously, RGB or bypassed but interpolated
Cb-Y-Cr signals are available via three additional
Digital-to-Analog Converters (DACs). The circuit at a
54 MHz multiplexed digital D1 input port accepts two CCIR
compatible Cb-Y-Cr data streams with 720 active pixels
per line in 4 :2:2multiplexed formats, for example MPEG
decoded data with overlay and MPEG decoded data
without overlay, whereas one data stream is latched at the
rising, the other one at the falling clock edge.

It includes a sync/clock generator and on-chip DACs.

ORDERING INFORMATION

TYPE NUMBER

SAA7126H QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm);
SAA7127H

1999 May 31 2

NAME DESCRIPTION VERSION

body 10 × 10 × 1.75 mm

PACKAGE

SOT307-2

Philips Semiconductors Product specification

Digital video encoder SAA7126H; SAA7127H

QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V

DDA

V

DDD

I

DDA

I

DDD

V

i

V

o(p-p)

R

L

LE

lf(i)

LE

lf(d)

T

amb

BLOCK DIAGRAM

analog supply voltage 3.15 3.3 3.45 V
digital supply voltage 3.0 3.3 3.6 V
analog supply current − 77 100 mA
digital supply current − 37 46 mA
input signal voltage levels TTL compatible
analog output signal voltages Y, C and CVBS

1.30 1.45 1.55 V

without load (peak-to-peak value)
load resistance 75 − 300 Ω
low frequency integral linearity error −−±3 LSB
low frequency differential linearity error −−±1 LSB
ambient temperature 0 − 70 °C

handbook, full pagewidth

V

DD(I2C)

SA

RES

MP7

to

MP0

TTX

n.c.

20
21

1

9 to 16

44

24, 27

V

5

SSD1

I2C-bus

control

MP1

MP2

V

SSD2

RESET SDA SCL

40 42 41

I2C-BUS

INTERFACE

2

C-bus

I

control

DATA

MANAGER

18

V

SSD3

38

V

DDD1

6

V

SAA7126H
SAA7127H

Y

CbCr

17

V

DDD3

DDD2

39

XTALI

ENCODER

RCV1

XTAL

35 4

clock

and timing

I2C-bus

control

19

RTCI

TTXRQ

RCV2

8433734

7

SYNC/CLOCK

Y

C

Y

CbCr

23

SP AP

LLC1

XCLK

2

C-bus

I

control

I2C-bus

control

OUTPUT

INTERFACE

I2C-bus

control

RGB

PROCESSOR

V

DDA1

V

SSA1

V

25

DDA2

V

28

D

22

V

SSA2

V

DDA3

31

A

32

V

SSA3

DDA4

36

33

30

23

26

29

MHB498

CVBS

RED

GREEN

BLUE

Fig.1 Block diagram.

1999 May 31 3

Philips Semiconductors Product specification

Digital video encoder SAA7126H; SAA7127H

PINNING

SYMBOL TYPE PIN DESCRIPTION

RES − 1 reserved pin; do not connect
SP I 2 test pin; connected to digital ground for normal operation
AP I 3 test pin; connected to digital ground for normal operation
LLC1 I 4 line-locked clock input; this is the 27 MHz master clock
V

SSD1

V

DDD1

RCV1 I/O 7 raster control 1 for video port; this pin receives/provides a VS/FS/FSEQ signal
RCV2 I/O 8 raster control 2 for video port; this pin provides an HS pulse of programmable length or

MP7 I 9 double-speed 54 MHz MPEG port; it is an input for
MP6 I 10
MP5 I 11
MP4 I 12
MP3 I 13
MP2 I 14
MP1 I 15
MP0 I 16
V

DDD2

V

SSD2

RTCI I 19 real-time control input (I

V

DD(I2C)

SA I 21 select I
V

SSA1

RED O 23 analog output of RED (Cr) or (C) signal
n.c. − 24 not connected
V

DDA1

GREEN O 26 analog output of GREEN (Y) or (VBS) signal
n.c. − 27 not connected
V

DDA2

BLUE O 29 analog output of BLUE (Cb) or (CVBS) signal
CVBS O 30 analog output of CVBS (CSYNC) or (VBS) signal
V

DDA3

V

SSA2

V

SSA3

XTAL O 34 crystal oscillator output
XTALI I 35 crystal oscillator input; if the oscillator is not used, this pin should be connected to ground
V

DDA4

− 5 digital ground 1

− 6 digital supply voltage 1

receives an HS pulse

“CCIR 656”

style multiplexed Cb-Y-Cr
data; data is sampled on the rising and falling clock edge; data sampled on the rising edge is
then sent to the encoding part of the device; data sampled on the falling edge is sent to the
RGB part of the device (or vice versa, depending on programming)

− 17 digital supply voltage 2

− 18 digital ground 2

2

C-bus register SRES = 0): if the LLC1 clock is provided by an
SAA7111 or SAA7151B, RTCI should be connected to the RTCO pin of the respective
decoder to improve the signal quality. Sync reset input (I2C-bus register SRES = 1): a HIGH
impulse resets synchronization of the encoder (first field, first line).

− 20 sense input for I2C-bus voltage; connect to I2C-bus supply

2

C-bus address; LOW selects slave address 88H, HIGH selects slave address 8CH

− 22 analog ground 1 for RED (Cr) (C) and GREEN (Y) (VBS) outputs

− 25 analog supply voltage 1 for RED (Cr) (C) output

− 28 analog supply voltage 2 for GREEN (Y) (VBS) output

− 31 analog supply voltage 3 for BLUE (Cb) (CVBS) and CVBS (CSYNC) (VBS) outputs

− 32 analog ground 2 for BLUE (Cb) (CVBS) and CVBS (CSYNC) (VBS) outputs

− 33 analog ground 3 for the DAC reference ladder and the oscillator

− 36 analog supply voltage 4 for the DAC reference ladder and the oscillator

1999 May 31 4

Philips Semiconductors Product specification

Digital video encoder SAA7126H; SAA7127H

SYMBOL TYPE PIN DESCRIPTION

XCLK O 37 clock output of the crystal oscillator
V

SSD3

V

DDD3

RESET I 40 reset input, active LOW. After reset is applied, all digital I/Os are in input mode; PAL black

SCL I 41 I
SDA I/O 42 I
TTXRQ O 43 teletext request output, indicating when text bits are requested
TTX I 44 teletext bit stream input

− 38 digital ground 3

− 39 digital supply voltage 3

burst on CVBS, VBS and C; RGB outputs set to lowest voltage. The I2C-bus receiver waits
for the START condition.

2

C-bus serial clock input

2

C-bus serial data input/output

handbook, full pagewidth

V

SSD1

V

DDD1
RCV1

RCV2

RES

SP
AP

LLC1

MP7
MP6
MP5

RESET

40

SAA7126H
SAA7127H

16

MP1

MP0

DDD3

V

39

17

DDD2

V

V
38

18

SSD2

V

XCLK
37

19

RTCI

V

XTALI

36

35

21

20

SA

DD(I2C)

V

XTAL
34

22

SSA1

V

V

33

V

32

V

31
30

CVBS
BLUE

29

V

28

n.c.

27

GREEN

26

V

25
24

n.c.
RED

23

MHB499

SSA3
SSA2
DDA3

DDA2

DDA1

SDA

TTXRQ
43

42

13

14

MP2

MP3

SCL
41

15

TTX

44

1
2
3
4
5
6
7
8

9
10
11

12

MP4

DDA4

SSD3

Fig.2 Pin configuration.

1999 May 31 5

Philips Semiconductors Product specification

Digital video encoder SAA7126H; SAA7127H

FUNCTIONAL DESCRIPTION

The digital video encoder encodes digital luminance and
colour difference signals into analog CVBS, S-video and
simultaneously RGB or Cr-Y-Cb signals. NTSC-M, PAL
B/G and sub-standards are supported.

Both interlaced and non-interlaced operation is possible
for all standards.

The basic encoder function consists of subcarrier
generation, colour modulation and insertion of
synchronization signals. Luminance and chrominance
signals are filtered in accordance with the standard
requirements of

For ease of analog post filtering the signals are twice
oversampled with respect to the pixel clock before
digital-to-analog conversion.

The total filter transfer characteristics are illustrated in
Figs 3 to 8. The DACs for Y, C and CVBS are realized with
full 10-bit resolution; 9-bit resolution for RGB output.
The Cr-Y-Cb to RGB dematrix can be bypassed optionally
in order to provide the upsampled Cr-Y-Cb input signals.

The 8-bit multiplexed Cb-Y-Cr formats are
(D1 format) compatible, but the SAV and EAV codes can
be decoded optionally; when the device is operated in
slave mode. Two independent data streams can be
processed, one latched by the rising edge of LLC1, the
other latched by the falling edge of LLC1. The purpose of
that is e.g. to forward one of the data streams containing
both video and On Screen Display (OSD) information to
the RGB outputs, and the other stream containing video
only to the encoded outputs CVBS and S-video.

For optimum display of RGB signals through a
euro-connector TV set, an early composite sync pulse (up
to 31LLC1 clock periods) can be provided optionally on the
CVBS output.

It is also possible to connect a Philips digital video decoder
(SAA7111, SAA7711A, SAA7112 or SAA7151B) to the
SAA7126H; SAA7127H. Information concerning the actual
subcarrier, PAL-ID and (with SAA7111 and newer types)
definite subcarrier phase can be inserted via the RTCI pin,
connected to the RTCO pin of a decoder.

The SAA7126H; SAA7127H synthesizes all necessary
internal signals, colour subcarrier frequency and
synchronization signals from that clock.

Wide screen signalling data can be loaded via the I2C-bus
and is inserted into line 23 for standards using a 50 Hz
field rate.

“RS-170-A”

and

“ITU-R BT.470-3”

.

“CCIR 656”

VPS data for program dependent automatic start and stop
of such featured VCR’s is loadable via the I

The IC also contains closed caption and extended data
services encoding (line 21), and supports anti-taping
signal generation in accordance with Macrovision. It is also
possible to load data for copy generation management
system into line 20 of every field (525/60 line counting).

A number of possibilities are provided for setting different
video parameters such as:

• Black and blanking level control

• Colour subcarrier frequency

• Variable burst amplitude etc.

During reset (RESET = LOW) and after reset is released,
all digital I/O stages are set to the input mode and the
encoder is set to PAL mode and outputs a ‘black burst’
signal on CVBS and S-video outputs, while RGB outputs
are set to their lowest output voltages. A reset forces the
I2C-bus interface to abort any running bus transfer.

Data manager

In the data manager, alternatively to the external video
data, a pre-defined colour look-up table located in this
block can be read out in a pre-defined sequence (8 steps
per active video line), achieving a colour bar test pattern
generator without need for an external data source.

Encoder

V

IDEO PATH

The encoder generates out of Y, U and V baseband
signals luminance and colour subcarrier output signals,
suitable for use as CVBS or separate Y and C signals.

Luminance is modified in gain and in offset (latter
programmable in a certain range to enable different black
level set-ups). After insertion of a fixed synchronization
pulse tip level, in accordance with standard composite
synchronization schemes, a blanking level can be set.
Other manipulations used for the Macrovision anti-taping
process such as additional insertion of AGC super-white
pulses (programmable in height) are supported by
SAA7126H only.

In order to enable easy analog post filtering, luminance is
interpolated from 13.5 MHz data rate to 27 MHz data rate,
providing luminance in 10-bit resolution. The transfer
characteristic of the luminance interpolation filter are
illustrated in Figs 5 and 6. Appropriate transients at
start/end of active video and for synchronization pulses
are ensured.

2

C-bus.

1999 May 31 6

Philips Semiconductors Product specification

Digital video encoder SAA7126H; SAA7127H

Chrominance is modified in gain (programmable
separately for U and V), standard dependent burst is
inserted, before baseband colour signals are interpolated
from a 6.75 MHz data rate to a 27 MHz data rate. One of
the interpolation stages can be bypassed, thus providing a
higher colour bandwidth, which can be made use of for
Y and C output. The transfer characteristics of the
chrominance interpolation filter are illustrated in
Figs 3 and 4.

The amplitude, beginning and ending of the inserted burst,
is programmable in a certain range that is suitable for
standard signals and for special effects. Behind the
succeeding quadrature modulator, colour in 10-bit
resolution is provided on the subcarrier.

The numeric ratio between the Y and C outputs is in
accordance with set standards.

T

ELETEXT INSERTION AND ENCODING

Pin TTX receives a WST or NABTS teletext bitstream
sampled at the LLC clock. Two protocols are provided: at
each rising edge of output signal (TTXRQ) a single teletext
bit has to be provided after a programmable delay at input
pin TTX. Or: the signal TTXRQ performs only a single
LOW-to-HIGH transition and remains at HIGH level for
360, 296 or 288 teletext bits, depending on the chosen
standard.

The actual line number where data is to be encoded in, can
be modified in a certain range.

The data clock frequency is in accordance with the
definition for NTSC-M standard 32 times horizontal line
frequency.

Data LOW at the output of the DACs corresponds to 0 IRE,
data HIGH at the output of the DACs corresponds to
approximately 50 IRE.

It is also possible to encode closed caption data for 50 Hz
field frequencies at 32 times the horizontal line frequency.

ANTI-TAPING (SAA7126H ONLY)
For more information contact your nearest Philips

Semiconductors sales office.

RGB processor

This block contains a dematrix in order to produce red,
green and blue signals to be fed to a SCART plug.

Before Y, Cb and Cr signals are de-matrixed, individual
gain adjustment for Y and colour difference signals and
2 times oversampling for luminance and 4 times
oversampling for colour difference signals is performed.
The transfer curves of luminance and colour difference
components of RGB are illustrated in Figs 7 and 8.

Phase variant interpolation is achieved on this bitstream in
the internal teletext encoder, providing sufficient small
phase jitter on the output text lines.

TTXRQ provides a fully programmable request signal to
the teletext source, indicating the insertion period of
bitstream at lines which are selectable independently for
both fields. The internal insertion window for text is set
to 360 (PAL-WST), 296 (NTSC-WST) or 288 (NABTS)
teletext bits including clock run-in bits. The protocol and
timing are illustrated in Fig.14.

V

IDEO PROGRAMMING SYSTEM (VPS) ENCODING

Five bytes of VPS information can be loaded via the
I2C-bus and will be encoded in the appropriate format into
line 16.

C

LOSED CAPTION ENCODER

Using this circuit, data in accordance with the specification
of closed caption or extended data service, delivered by
the control interface, can be encoded (line 21).
Two dedicated pairs of bytes (two bytes per field), each
pair preceded by run-in clocks and framing code, are
possible.

Output interface/DACs

In the output interface, encoded Y and C signals are
converted from digital-to-analog in a 10-bit resolution.
Y and C signals are also combined to a 10-bit CVBS
signal.

The CVBS output occurs with the same processing delay
(equal to 51 LLC clock periods, measured from MP input
to the analog outputs) as the Y, C and RGB outputs.
Absolute amplitude at the input of the DAC for CVBS is
reduced by

15

⁄16 with respect to Y and C DACs to make

maximum use of conversion ranges.
Red, green and blue signals are also converted from

digital-to-analog, each providing a 9-bit resolution.
Outputs of the DACs can be set together via software

control to minimum output voltage (approximately 0.2 V
DC) for either purpose. Alternatively, the buffers can be
switched into 3-state output condition; this allows for ‘wired
AND’ing with other 3-state outputs and can also be used
as a power-save mode.

1999 May 31 7

Philips Semiconductors Product specification

Digital video encoder SAA7126H; SAA7127H

Synchronization

The synchronization of the SAA7126H; SAA7127H is able
to operate in two modes; slave mode and master mode.

In master mode (see Fig.10), the circuit generates all
necessary timings in the video signal itself, and it can
provide timing signals at the RCV1 and RCV2 ports.
In slave mode, it accepts timing information either from the
RCV pins or from the embedded timing data of the
CCIR 656 data stream.

For the SAA7126H; SAA7127H, the only difference
between master and slave mode is that it ignores the
timing information at its inputs in master mode. Thus, if in
slave mode, any timing information is missing, the IC will
continue running free without a visible effect. But there
must not be any additional pulses (with wrong phase)
because the circuit will not ignore them.

In slave mode (see Fig.9), an interface circuit decides,
which signal is expected at the RCV1 port and which
information is taken from its active slope. The polarity can
be chosen, if PRCV1 is logic 0 the rising slope will be
active.

The signal can be:

• A Vertical Sync (VS) pulse; the active slope sets the
vertical phase

• An odd/even signal; the active slope sets the vertical
phase, the internal field flag to odd and optionally sets
the horizontal phase

• A Field Sequence (FSEQ) signal; it marks the first field
of the 4 (NTSC) or 8 (PAL) field sequence. In addition to
the odd/even signal, it also sets the PAL phase and
optionally defines the subcarrier phase.

from line 0 to line 15 counted from the first serration pulse
in half line steps.

Whenever a synchronization information cannot be
derived directly from the inputs, the SAA7126H;
SAA7127H will calculate it from the internal horizontal,
vertical and PAL phase. This gives good flexibility with
respect to external synchronization but the circuit does not
suppress illegal settings. In such an event, e.g the
odd/even information may vanish as it does in the
non-interlaced modes.

In master mode, the line lengths are fixed to 1728 clocks
at 50 Hz and 1716 clocks at 60 Hz. To allow
non-interlaced frames, the field lengths can be varied by
±0.5 lines. In the event of non-interlace, the SAA7126H;
SAA7127H does not provide odd/even information and the
output signal does not contain the PAL ‘Bruch sequence’.

At the RCV1 pin the IC can provide:

• A Vertical Sync (VS) signal with 2.5 (50 Hz) or 3 (60 Hz)
lines duration

• An odd/even signal which is LOW in odd fields

• A Field Sequence (FSEQ) signal which is HIGH in the

first field of the 4 or 8 field sequence.

At the RCV2 pin, there is a horizontal pulse of
programmable phase and duration available. This pulse
can be suppressed in the programmable inactive part of a
field giving a composite blank signal.

The directions and polarities of the RCV ports can be
chosen independently. Timing references can be found in
Tables 29 and 37.

Clock

On the RCV2 port, the IC can provide a horizontal pulse
with programmable start and stop phase; this pulse can be
inhibited in the vertical blanking period to build up, for
example, a composite blanking signal.

The horizontal phase can be set via a separate input
RCV2. In the event of VS pulses at RCV1, this is
mandatory. It is also possible to set the signal path to blank
via this input.

From the CCIR 656 data stream, the SAA7126H;
SAA7127H decodes only the start of the first line in the odd
field. All other information is ignored and may miss. If this
kind of slave mode is active, the RCV pins may be
switched to output mode.

In slave mode, the horizontal trigger phase can be
programmed to any point in the line, the vertical phase

1999 May 31 8

The input at LLC1 can either be an external clock source
or the buffered on-chip clock XCLK. The internal crystal
oscillator can be run with either a 3rd-harmonic or a
fundamental crystal.

2

C-bus interface

I

The I2C-bus interface is a standard slave transceiver,
supporting 7-bit slave addresses and 400 kbits/s
guaranteed transfer rate. It uses 8-bit subaddressing with
an auto-increment function. All registers are write and
readable, except one read only status byte.

The I2C-bus slave address is defined as 88H with pin 21
(SA) tied LOW and as 8CH with pin 21 (SA) tied HIGH.

Philips Semiconductors Product specification

Digital video encoder SAA7126H; SAA7127H

Input levels and formats

The SAA7126H; SAA7127H expects digital Y, Cb, Cr data
with levels (digital codes) in accordance with

“CCIR 601”

For C and CVBS outputs, deviating amplitudes of the
colour difference signals can be compensated by

The RGB, respectively Cr-Y-Cb path features a gain
setting individually for luminance (GY) and colour
difference signals (GCD).

.

Reference levels are measured with a colour bar,
100% white, 100% amplitude and 100% saturation.

independent gain control setting, while gain for luminance
is set to predefined values, distinguishable for 7.5 IRE
set-up or without set-up.

Table 1

COLOUR

“CCIR 601”

signal component levels

SIGNALS

YCbCrR

(1)

(2)

(2)

G

B

White 235 128 128 235 235 235
Yellow 210 16 146 235 235 16
Cyan 170 166 16 16 235 235
Green 145 54 34 16 235 16
Magenta 106 202 222 235 16 235
Red 81 90 240 235 16 16
Blue 41 240 110 16 16 235
Black 16 128 128 16 16 16

(2)

Notes

1. Transformation:
a) R = Y + 1.3707 × (Cr − 128)
b) G = Y − 0.3365 × (Cb − 128) − 0.6982 × (Cr − 128)
c) B = Y + 1.7324 × (Cb − 128).

2. Representation of R, G and B (or Cr, Y and Cb) at the output is 9 bits at 27 MHz.

Table 2 8-bit multiplexed format (similar to

“CCIR 601”

)

BITS

TIME

01234567

Sample Cb

Y

0

Cr

0

Y

0

Cb

1

Y

2

Cr

2

Y

2

3

Luminance pixel number 0123
Colour pixel number 0 2

1999 May 31 9

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1999 May 31 10

Bit allocation map
Table 3 Slave receiver (slave address 88H)

REGISTER FUNCTION

Status byte (read only) 00H VER2 VER1 VER0 CCRDO CCRDE 0 FSEQ O_E
Null 01H to 25H 00000000
Wide screen signal 26H WSS7 WSS6 WSS5 WSS4 WSS3 WSS2 WSS1 WSS0
Wide screen signal 27H WSSON 0 WSS13 WSS12 WSS11 WSS10 WSS9 WSS8
Real-time control, burst start 28H DECCOL DECFIS BS5 BS4 BS3 BS2 BS1 BS0
Sync reset enable, burst end 29H SRES 0 BE5 BE4 BE3 BE2 BE1 BE0
Copy generation 0 2AH CG07 CG06 CG05 CG04 CG03 CG02 CG01 CG00
Copy generation 1 2BH CG15 CG14 CG13 CG12 CG11 CG10 CG09 CG08
CG enable, copy generation 2 2CH CGEN 0 0 0 CG19 CG18 CG17 CG16
Output port control 2DH VBSEN1 VBSEN0 CVBSEN CEN CVBSTRI RTRI GTRI BTRI
Null 2EH to 37H 00000000
Gain luminance for RGB 38H 0 0 0 GY4 GY3 GY2 GY1 GY0
Gain colour difference for RGB 39H 0 0 0 GCD4 GCD3 GCD2 GCD1 GCD0
Input port control 1 3AH CBENB 0 0 SYMP DEMOFF CSYNC MP2C2 MP2C1
VPS enable, input control 2 54H VPSEN CCIRS 0000EDGE2 EDGE1
VPS byte 5 55H VPS57 VPS56 VPS55 VPS54 VPS53 VPS52 VPS51 VPS50
VPS byte 11 56H VPS117 VPS116 VPS115 VPS114 VPS113 VPS112 VPS111 VPS110
VPS byte 12 57H VPS127 VPS126 VPS125 VPS124 VPS123 VPS122 VPS121 VPS120
VPS byte 13 58H VPS137 VPS136 VPS135 VPS134 VPS133 VPS132 VPS131 VPS130
VPS byte 14 59H VPS147 VPS146 VPS145 VPS144 VPS143 VPS142 VPS141 VPS140
Chrominance phase 5AH CHPS7 CHPS6 CHPS5 CHPS4 CHPS3 CHPS2 CHPS1 CHPS0
Gain U 5BH GAINU7 GAINU6 GAINU5 GAINU4 GAINU3 GAINU2 GAINU1 GAINU0
Gain V 5CH GAINV7 GAINV6 GAINV5 GAINV4 GAINV3 GAINV2 GAINV1 GAINV0
Gain U MSB, real-time control,

black level
Gain V MSB, real-time

control, blanking level
CCR, blanking level VBI 5FH CCRS1 CCRS0 BLNVB5 BLNVB4 BLNVB3 BLNVB2 BLNVB1 BLNVB0
Null 60H 00000000
Standard control 61H DOWNB DOWNA INPI YGS 0 SCBW PAL FISE

SUB ADDR

(HEX)

5DH GAINU8 DECOE BLCKL5 BLCKL4 BLCKL3 BLCKL2 BLCKL1 BLCKL0

5EH GAINV8 DECPH BLNNL5 BLNNL4 BLNNL3 BLNNL2 BLNNL1 BLNNL0

D7 D6 D5 D4 D3 D2 D1 D0

DATA BYTE

(1)

Philips Semiconductors Product specification

Digital video encoder SAA7126H; SAA7127H

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1999 May 31 11

REGISTER FUNCTION

RTC enable, burst amplitude 62H RTCE BSTA6 BSTA5 BSTA4 BSTA3 BSTA2 BSTA1 BSTA0
Subcarrier 0 63H FSC07 FSC06 FSC05 FSC04 FSC03 FSC02 FSC01 FSC00
Subcarrier 1 64H FSC15 FSC14 FSC13 FSC12 FSC11 FSC10 FSC09 FSC08
Subcarrier 2 65H FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16
Subcarrier 3 66H FSC31 FSC30 FSC29 FSC28 FSC27 FSC26 FSC25 FSC24
Line 21 odd 0 67H L21O07 L21O06 L21O05 L21O04 L21O03 L21O02 L21O01 L21O00
Line 21 odd 1 68H L21O17 L21O16 L21O15 L21O14 L21O13 L21O12 L21O11 L21O10
Line 21 even 0 69H L21E07 L21E06 L21E05 L21E04 L21E03 L21E02 L21E01 L21E00
Line 21 even 1 6AH L21E17 L21E16 L21E15 L21E14 L21E13 L21E12 L21E11 L21E10
RCV port control 6BH SRCV11 SRCV10 TRCV2 ORCV1 PRCV1 CBLF ORCV2 PRCV2
Trigger control 6CH HTRIG7 HTRIG6 HTRIG5 HTRIG4 HTRIG3 HTRIG2 HTRIG1 HTRIG0
Trigger control 6DH HTRIG10 HTRIG9 HTRIG8 VTRIG4 VTRIG3 VTRIG2 VTRIG1 VTRIG0
Multi control 6EH SBLBN BLCKON PHRES1 PHRES0 LDEL1 LDEL0 FLC1 FLCO
Closed caption, teletext enable 6FH CCEN1 CCEN0 TTXEN SCCLN4 SCCLN3 SCCLN2 SCCLN1 SCCLN0
RCV2 output start 70H RCV2S7 RCV2S6 RCV2S5 RCV2S4 RCV2S3 RCV2S2 RCV2S1 RCV2S0
RCV2 output end 71H RCV2E7 RCV2E6 RCV2E5 RCV2E4 RCV2E3 RCV2E2 RCV2E1 RCV2E0
MSBs RCV2 output 72H 0 RCV2E10 RCV2E9 RCV2E8 0 RCV2S10 RCV2S9 RCV2S8
TTX request H start 73H TTXHS7 TTXHS6 TTXHS5 TTXHS4 TTXHS3 TTXHS2 TTXHS1 TTXHS0
TTX request H delay, length 74H TTXHL3 TTXHL2 TTXHL1 TTXHL0 TTXHD3 TTXHD2 TTXHD1 TTXHD0
CSYNC advance, Vsync shift 75H CSYNCA4 CSYNCA3 CSYNCA2 CSYNCA1 CSYNCA0 VS_S2 VS_S1 VS_S0
TTX odd request vertical start 76H TTXOVS7 TTXOVS6 TTXOVS5 TTXOVS4 TTXOVS3 TTXOVS2 TTXOVS1 TTXOVS0
TTX odd request vertical end 77H TTXOVE7 TTXOVE6 TTXOVE5 TTXOVE4 TTXOVE3 TTXOVE2 TTXOVE1 TTXOVE0
TTX even request vertical start 78H TTXEVS7 TTXEVS6 TTXEVS5 TTXEVS4 TTXEVS3 TTXEVS2 TTXEVS1 TTXEVS0
TTX even request vertical end 79H TTXEVE7 TTXEVE6 TTXEVE5 TTXEVE4 TTXEVE3 TTXEVE2 TTXEVE1 TTXEVE0
First active line 7AH FAL7 FAL6 FAL5 FAL4 FAL3 FAL2 FAL1 FAL0
Last active line 7BH LAL7 LAL6 LAL5 LAL4 LAL3 LAL2 LAL1 LAL0
TTX mode, MSB vertical 7CH TTX60 LAL8 TTXO FAL8 TTXEVE8 TTXOVE8 TTXEVS8 TTXOVS8
Null 7DH 00000000
Disable TTX line 7EH LINE12 LINE11 LINE10 LINE9 LINE8 LINE7 LINE6 LINE5
Disable TTX line 7FH LINE20 LINE19 LINE18 LINE17 LINE16 LINE15 LINE14 LINE13

SUB ADDR

(HEX)

D7 D6 D5 D4 D3 D2 D1 D0

DATA BYTE

(1)

Philips Semiconductors Product specification

Digital video encoder SAA7126H; SAA7127H

Note

1. All bits labelled ‘0’ are reserved. They must be programmed with logic 0.

Philips Semiconductors Product specification

Digital video encoder SAA7126H; SAA7127H

I2C-bus format

2

Table 4 I

S SLAVE ADDRESS ACK SUBADDRESS ACK DATA 0 ACK -------- DATA n ACK P

Table 5 Explanation of Table 4

S START condition
Slave address 1000100X or 1 0 0 0 1 1 0 X; note 1
ACK acknowledge, generated by the slave
Subaddress; note 2 subaddress byte
DATA data byte

-------- continued data bytes and ACKs
P STOP condition

Notes

1. X is the read/write control bit; X = logic 0 is order to write; X = logic 1 is order to read.

2. If more than 1 byte of DATA is transmitted, then auto-increment of the subaddress is performed.

C-bus address; see Table 5

PART DESCRIPTION

Slave receiver
Table 6 Subaddresses 26H and 27H

DATA BYTE

WSS − wide screen signalling bits

WSSON 0 wide screen signalling output is disabled; default after reset

Table 7 Subaddress 28H

DATA BYTE

BS − starting point of burst in clock cycles PAL: BS=33 (21H); default after reset

DECCOL 0 disable colour detection bit of RTCI input

DECFIS 0 field sequence as FISE in subaddress 61

LOGIC
LEVEL

3 to 0 = aspect ratio
7 to 4 = enhanced services
10 to 8 = subtitles
13 to 11 = reserved

1 wide screen signalling output is enabled

LOGIC
LEVEL

1 enable colour detection bit of RTCI input bit RTCE must be set to logic 1 (see Fig.13)

1 field sequence as FISE bit in RTCI input bit RTCE must be set to logic 1 (see Fig.13)

DESCRIPTION REMARKS

DESCRIPTION

NTSC: BS = 25 (19H)

1999 May 31 12

Philips Semiconductors Product specification

Digital video encoder SAA7126H; SAA7127H

Table 8 Subaddress 29H

DATA BYTE

BE − ending point of burst in clock cycles PAL: BE=29 (1DH); default after reset

SRES 0 pin 19 is Real-Time Control Input (RTCI)

Table 9 Subaddresses 2AH to 2CH

DATA BYTE

CG − LSB of the respective bytes are encoded immediately after run-in, the MSBs of the

CGEN 0 copy generation data output is disabled; default after reset

Table 10 Subaddress 2DH

DATA BYTE

BTRI 0 DAC for BLUE output in 3-state mode (high-impedance)

GTRI 0 DAC for GREEN output in 3-state mode (high-impedance)

RTRI 0 DAC for RED output in 3-state mode (high-impedance)

CVBSTRI 0 DAC for CVBS output in 3-state mode (high-impedance)

CEN 0 RED output signal is switched to R DAC; default after reset

CVBSEN 0 BLUE output signal is switched to B DAC; default after reset

VBSEN0 0 if CSYNC = 0, CVBS output signal is switched to CVBS DAC; default after reset

VBSEN1 0 GREEN output signal is switched to G DAC; default after reset

LOGIC
LEVEL

1 pin 19 is Sync Reset input (SRES) a HIGH impulse resets synchronization of the

LOGIC
LEVEL

respective bytes have to carry the CRCC bits, in accordance with the definition of copy
generation management system encoding format.

1 copy generation data output is enabled

LOGIC
LEVEL

1 DAC for BLUE output in normal operation mode; default after reset

1 DAC for GREEN output in normal operation mode; default after reset

1 DAC for RED output in normal operation mode; default after reset

1 DAC for CVBS output in normal operation mode; default after reset

1 chrominance output signal is switched to R DAC

1 CVBS output signal is switched to B DAC

1 if CSYNC = 0, luminance (VBS) output signal is switched to CVBS DAC

1 luminance (VBS) output signal is switched to G DAC

DESCRIPTION REMARKS

NTSC: BE = 29 (1DH)

encoder (first field, first line)

DESCRIPTION

DESCRIPTION

1999 May 31 13

Philips Semiconductors Product specification

Digital video encoder SAA7126H; SAA7127H

Table 11 Subaddresses 38H and 39H

DATA BYTE DESCRIPTION

16

GY0 to GY4 gain luminance of RGB (Cr, Y and Cb) output, ranging from (1 −

Suggested nominal value = −6 (11010b), depending on external application.

GCD0 to GCD4 gain colour difference of RGB (Cr, Y and Cb) output, ranging from (1 −

Suggested nominal value = −6 (11010b), depending on external application.

Table 12 Subaddress 3AH

⁄32)to(1+15⁄32).

16

⁄32)to(1+15⁄32).

DATA BYTE

MP2C1 0 input data is twos complement from MP1 input port (encoder path)

MP2C2 0 input data is twos complement from MP2 input port (RGB path)

CSYNC 0 If VBSEN0 = 0, CVBS output signal is switched to CVBS DAC.

DEMOFF 0 Y, Cb and Cr for RGB dematrix is active; default after reset

SYMP 0 horizontal and vertical trigger is taken from RCV2 and RCV1 respectively; default after reset

CBENB 0 data from input ports is encoded; default after reset

Table 13 Subaddress 54H

DATA BYTE

EDGE1 0 MP1 data is sampled on the rising clock edge; default after reset

EDGE2 0 MP2 data is sampled on the rising clock edge; default after reset

CCIRS 0 If SYMP = 1, horizontal and vertical trigger is decoded out of

VPSEN 0 video programming system data insertion is disabled; default after reset

LOGIC
LEVEL

1 input data is straight binary from MP1 input port; default after reset

1 input data is straight binary from MP2 input port; default after reset

If VBSEN0 = 1, luminance output signal is switched to CVBS DAC; default after reset.

1 advanced composite sync is switched to CVBS DAC

1 Y, Cb and Cr for RGB dematrix is bypassed

1 horizontal and vertical trigger is decoded out of

1 colour bar with fixed colours is encoded

LOGIC
LEVEL

1 MP1 data is sampled on the falling clock edge

1 MP2 data is sampled on the falling clock edge

MP2 port; default after reset.

1 If SYMP = 1, horizontal and vertical trigger is decoded out of

MP1 port.

1 video programming system data insertion in line 16 is enabled

DESCRIPTION

“CCIR 656”

DESCRIPTION

compatible data at MP port

“CCIR 656”

“CCIR 656”

compatible data at

compatible data at

1999 May 31 14

Philips Semiconductors Product specification

Digital video encoder SAA7126H; SAA7127H

Table 14 Subaddresses 55H to 59H

DATA BYTE DESCRIPTION REMARKS

VPS5 fifth byte of video programming system data LSBs of the respective bytes are encoded
VPS11 eleventh byte of video programming system data
VPS12 twelfth byte of video programming system data
VPS13 thirteenth byte of video programming system data
VPS14 fourteenth byte of video programming system data

Table 15 Subaddress 5AH

DATA BYTE DESCRIPTION VALUE RESULT

CHPS phase of encoded colour subcarrier

(including burst) relative to horizontal
sync; can be adjusted in steps of
360/256 degrees

6BH PAL-B/G and data from input ports

95H PAL-B/G and data from look-up table

A3H NTSC-M and data from input ports

46H NTSC-M and data from look-up table

immediately after run-in and framing code in
line 16; all other bytes are not relevant for
VPS

Table 16 Subaddresses 5BH and 5DH

DATA BYTE DESCRIPTION CONDITIONS REMARKS

GAINU variable gain for

Cb signal; input
representation in
accordance with

“CCIR 601”

Table 17 Subaddresses 5CH and 5EH

DATA BYTE DESCRIPTION CONDITIONS REMARKS

GAINV variable gain for

Cr signal; input
representation in
accordance with

“CCIR 601”

white-to-black = 92.5 IRE GAINU = −2.17 × nominal to +2.16 × nominal
GAINU = 0 output subcarrier of U contribution = 0
GAINU = 118 (76H) output subcarrier of U contribution = nominal
white-to-black = 100 IRE GAINU = −2.05 × nominal to +2.04 × nominal
GAINU = 0 output subcarrier of U contribution = 0
GAINU = 125 (7DH) output subcarrier of U contribution = nominal

white-to-black = 92.5 IRE GAINV = −1.55 × nominal to +1.55 × nominal
GAINV = 0 output subcarrier of V contribution = 0
GAINV = 165 (A5H) output subcarrier of V contribution = nominal
white-to-black = 100 IRE GAINV = −1.46 × nominal to +1.46 × nominal
GAINV = 0 output subcarrier of V contribution = 0
GAINV = 175 (AFH) output subcarrier of V contribution = nominal

1999 May 31 15

Philips Semiconductors Product specification

Digital video encoder SAA7126H; SAA7127H

Table 18 Subaddress 5DH

DATA BYTE DESCRIPTION CONDITIONS REMARKS

BLCKL variable black level; input

representation in
accordance with

“CCIR 601”

DECOE real-time control logic 0 disable odd/even field control bit from RTCI

Notes

1. Output black level/IRE = BLCKL × 2/6.29 + 28.9.

2. Output black level/IRE = BLCKL × 2/6.18 + 26.5.

white-to-sync = 140 IRE;
note 1

BLCKL = 0; note 1 output black level = 29 IRE
BLCKL = 63 (3FH); note 1 output black level = 49 IRE
white-to-sync = 143 IRE;

note 2
BLCKL = 0; note 2 output black level = 27 IRE
BLCKL = 63 (3FH); note 2 output black level = 47 IRE

logic 1 enable odd/even field control bit from RTCI

recommended value: BLCKL = 58 (3AH)

recommended value: BLCKL = 51 (33H)

(see Fig.13)

Table 19 Subaddress 5EH

DATA BYTE DESCRIPTION CONDITIONS REMARKS

BLNNL variable blanking level white-to-sync = 140 IRE;

note 1
BLNNL = 0; note 1 output blanking level = 25 IRE
BLNNL = 63 (3FH); note 1 output blanking level = 45 IRE
white-to-sync = 143 IRE;

note 2
BLNNL = 0; note 2 output blanking level = 26 IRE
BLNNL = 63 (3FH); note 2 output blanking level = 46 IRE

DECPH real-time control logic 0 disable subcarrier phase reset bit from RTCI

logic 1 enable subcarrier phase reset bit from RTCI

Notes

1. Output black level/IRE = BLNNL × 2/6.29 + 25.4.

2. Output black level/IRE = BLNNL × 2/6.18 + 25.9; default after reset: 35H.

Table 20 Subaddress 5FH

DATA BYTE DESCRIPTION

BLNVB variable blanking level during vertical blanking interval is typically identical to value of BLNNL
CCRS select cross-colour reduction filter in luminance; see Table 21

recommended value: BLNNL = 46 (2EH)

recommended value: BLNNL = 53 (35H)

(see Fig.13)

1999 May 31 16

Philips Semiconductors Product specification

Digital video encoder SAA7126H; SAA7127H

Table 21 Logic levels and function of CCRS

CCRS1 CCRS0 DESCRIPTION

0 0 no cross-colour reduction; for overall transfer characteristic of luminance see Fig.5
0 1 cross-colour reduction #1 active; for overall transfer characteristic see Fig.5
1 0 cross-colour reduction #2 active; for overall transfer characteristic see Fig.5
1 1 cross-colour reduction #3 active; for overall transfer characteristic see Fig.5

Table 22 Subaddress 61H

DATA BYTE

FISE 0 864 total pixel clocks per line; default after reset

PAL 0 NTSC encoding (non-alternating V component)

SCBW 0 enlarged bandwidth for chrominance encoding (for overall transfer characteristic of

YGS 0 luminance gain for white − black 100 IRE; default after reset

INPI 0 PAL switch phase is nominal; default after reset

DOWNA 0 DAC for CVBS in normal operational mode; default after reset

DOWNB 0 DACs for R, G and B in normal operational mode

Table 23 Subaddress 62AH

DATA BYTE

RTCE 0 no real-time control of generated subcarrier frequency; default after reset

LOGIC
LEVEL

1 858 total pixel clocks per line

1 PAL encoding (alternating V component); default after reset

chrominance in baseband representation see Figs 3 and 4)

1 standard bandwidth for chrominance encoding (for overall transfer characteristic of

chrominance in baseband representation see Figs 3 and 4); default after reset

1 luminance gain for white − black 92.5 IRE including 7.5 IRE set-up of black

1 PAL switch phase is inverted compared to nominal if RTC is enabled (see Table 23)

1 DAC for CVBS forced to lowest output voltage

1 DACs for R, G and B forced to lowest output voltage; default after reset

LOGIC
LEVEL

1 real-time control of generated subcarrier frequency through SAA7151B or SAA7111; for

timing see Fig.13

DESCRIPTION

DESCRIPTION

1999 May 31 17

Philips Semiconductors Product specification



Digital video encoder SAA7126H; SAA7127H

Table 24 Subaddress 62BH

DATA BYTE DESCRIPTION CONDITIONS REMARKS

BSTA amplitude of colour burst;

input representation in
accordance with

“CCIR 601”

white-to-black = 92.5 IRE;
burst = 40 IRE; NTSC encoding

BSTA = 0 to 2.02 × nominal

white-to-black = 92.5 IRE;
burst = 40 IRE; PAL encoding

BSTA = 0 to 2.82 × nominal

white-to-black = 100 IRE;
burst = 43 IRE; NTSC encoding

BSTA = 0 to 1.90 × nominal

white-to-black = 100 IRE;
burst = 43 IRE; PAL encoding

BSTA = 0 to 3.02 × nominal

Table 25 Subaddresses 63H to 66H (four bytes to program subcarrier frequency)

recommended value:
BSTA = 63 (3FH)

recommended value:
BSTA = 45 (2DH)

recommended value:
BSTA = 67 (43H)

recommended value:
BSTA = 47 (2FH); default after
reset

DATA BYTE DESCRIPTION CONDITIONS REMARKS

FSC0 to FSC3 f

= subcarrier frequency

fsc

(in multiples of line
frequency); f

= clock

llc

frequency (in multiples of

FSC round

=

note 1

f

32

fsc



2

;

×

------- ­f



llc

FSC3 = most significant byte;
FSC0 = least significant byte

line frequency)

Note

1. Examples:
a) NTSC-M: f
b) PAL-B/G: f

= 227.5, f

fsc

= 283.7516, f

fsc

= 1716 → FSC = 569408543 (21F07C1FH).

llc

= 1728 → FSC = 705268427 (2A098ACBH).

llc

Table 26 Subaddresses 67H to 6AH

DATA BYTE DESCRIPTION REMARKS

L21O0 first byte of captioning data, odd field LSBs of the respective bytes are encoded
L21O1 second byte of captioning data, odd field
L21E0 first byte of extended data, even field
L21E1 second byte of extended data, even field

immediately after run-in and framing code, the
MSBs of the respective bytes have to carry the
parity bit, in accordance with the definition of
line 21 encoding format.

1999 May 31 18

Philips Semiconductors Product specification

Digital video encoder SAA7126H; SAA7127H

Table 27 Subaddress 6BH

DATA BYTE

PRCV2 0 polarity of RCV2 as output is active HIGH, rising edge is taken when input, respectively;

ORCV2 0 pin RCV2 is switched to input; default after reset

CBLF 0 If ORCV2 = HIGH, pin RCV2 provides an HREF signal (horizontal reference pulse that is

PRCV1 0 polarity of RCV1 as output is active HIGH, rising edge is taken when input; default after

ORCV1 0 pin RCV1 is switched to input; default after reset

TRCV2 0 horizontal synchronization is taken from RCV1 port (at bit SYMP = LOW) or from decoded

SRCV1 − defines signal type on pin RCV1; see Table 28

LOGIC
LEVEL

default after reset

1 polarity of RCV2 as output is active LOW, falling edge is taken when input, respectively

1 pin RCV2 is switched to output

defined by RCV2S and RCV2E, also during vertical blanking interval); default after reset.
If ORCV2 = LOW and bit SYMP = LOW, the signal input to RCV2 is used for horizontal
synchronization only (if TRCV2 = 1); default after reset.

1 If ORCV2 = HIGH, pin RCV2 provides a ‘composite-blanking-not’ signal, for example a

reference pulse that is defined by RCV2S and RCV2E, excluding vertical blanking interval,
which is defined by FAL and LAL. If ORCV2 = LOW and bit SYMP = LOW, the signal input
to RCV2 is used for horizontal synchronization (if TRCV2 = 1) and as an internal blanking
signal.

reset

1 polarity of RCV1 as output is active LOW, falling edge is taken when input

1 pin RCV1 is switched to output

frame sync of

1 horizontal synchronization is taken from RCV2 port (at bit SYMP = LOW)

“CCIR 656”

input (at bit SYMP = HIGH); default after reset

DESCRIPTION

Table 28 Logic levels and function of SRCV1

DATA BYTE

SRCV11 SRCV10

0 0 VS VS vertical sync each field; default after reset
0 1 FS FS frame sync (odd/even)
1 0 FSEQ FSEQ field sequence, vertical sync every fourth field (PAL = 0)

1 1 not applicable not applicable −

Table 29 Subaddresses 6CH and 6DH

DATA BYTE DESCRIPTION

HTRIG sets the horizontal trigger phase related to signal on RCV1 or RCV2 input

1999 May 31 19

AS OUTPUT AS INPUT FUNCTION

or eighth field (PAL = 1)

values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed; increasing HTRIG
decreases delays of all internally generated timing signals; reference mark:analog output
horizontal sync (leading slope) coincides with active edge of RCV used for triggering at
HTRIG = 39H

Philips Semiconductors Product specification

Digital video encoder SAA7126H; SAA7127H

Table 30 Subaddress 6DH

DATA BYTE DESCRIPTION

VTRIG sets the vertical trigger phase related to signal on RCV1 input

increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines;
variation range of VTRIG=0to31(1FH)

Table 31 Subaddress 6EH

DATA BYTE

SBLBN 0 vertical blanking is defined by programming of FAL and LAL; default after reset

BLCKON 0 encoder in normal operation mode

PHRES − selects the phase reset mode of the colour subcarrier generator; see Table 32
LDEL − selects the delay on luminance path with reference to chrominance path; see Table 33
FLC − field length control; see Table 34

Table 32 Logic levels and function of PHRES

DATA BYTE

PHRES1 PHRES0

0 0 no reset or reset via RTCI from SAA7111 if bit RTCE = 1; default after reset
0 1 reset every two lines
1 0 reset every eight fields
1 1 reset every four fields

Table 33 Logic levels and function of LDEL

DATA BYTE

LDEL1 LDEL0

0 0 no luminance delay; default after reset
0 1 1 LLC luminance delay
1 0 2 LLC luminance delay
1 1 3 LLC luminance delay

LOGIC

LEVEL

1 vertical blanking is forced in accordance with

1 output signal is forced to blanking level; default after reset

DESCRIPTION

“CCIR 624”

DESCRIPTION

DESCRIPTION

(50 Hz) or RS170A (60 Hz)

Table 34 Logic levels and function of FLC

DATA BYTE

FLC1 FLC0

0 0 interlaced 312.5 lines/field at 50 Hz, 262.5 lines/field at 60 Hz; default after reset
0 1 non-interlaced 312 lines/field at 50 Hz, 262 lines/field at 60 Hz
1 0 non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz
1 1 non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz

1999 May 31 20

DESCRIPTION

Philips Semiconductors Product specification

Digital video encoder SAA7126H; SAA7127H

Table 35 Subaddress 6FH

DATA BYTE

CCEN − enables individual line 21 encoding; see Table 36
TTXEN 0 disables teletext insertion; default after reset

SCCLN − selects the actual line, where closed caption or extended data are encoded;

Table 36 Logic levels and function of CCEN

DATA BYTE

CCEN1 CCEN0

0 0 line 21 encoding off; default after reset
0 1 enables encoding in field 1 (odd)
1 0 enables encoding in field 2 (even)
1 1 enables encoding in both fields

Table 37 Subaddresses 70H to 72H

DATA BYTE DESCRIPTION

RCV2S start of output signal on RCV2 pin

RCV2E end of output signal on RCV2 pin

LOGIC
LEVEL

1 enables teletext insertion

line = (SCCLN + 4) for M-systems; line = (SCCLN + 1) for other systems

values above 1715 (FISE = 1) or [1727 (FISE = 0)] are not allowed; first active pixel at analog
outputs (corresponding input pixel coinciding with RCV2) at RCV2S = 11AH [0FDH]

values above 1715 (FISE = 1) or [1727 (FISE = 0)] are not allowed; last active pixel at analog
outputs (corresponding input pixel coinciding with RCV2) at RCV2E = 694H (687H)

DESCRIPTION

DESCRIPTION

Table 38 Subaddress 73H

DATA BYTE DESCRIPTION REMARKS

TTXHS start of signal on pin TTXRQ; see Fig.14 PAL: TTXHS = 42H

NTSC: TTXHS = 54H

Table 39 Subaddress 74H

DATA BYTE DESCRIPTION REMARKS

TTXHL length of TTXRQ window; only active at old TTX protocol:

bit TTXO = 1

TTXHD indicates the delay in clock cycles between rising edge of TTXRQ

output and valid data at pin TTX

1999 May 31 21

TTXHL = 0: TTXRQ = 1398LLC;
TTXHL = 15: TTXRQ = 1413LLC

minimum value: TTXHD = 2

Philips Semiconductors Product specification

Digital video encoder SAA7126H; SAA7127H

Table 40 Subaddress 75H

DATA BYTE DESCRIPTION

VS_S vertical sync shift between RCV1 and RCV2 (switched to output); in master mode it is possible to shift

H-sync (RCV2; CBLF = 0) against V-sync (RCV1; SRCV1 = 00)

standard value: VS_S = 3

CSYNCA advanced composite sync against RGB output from 0LLC to 31LLC

Table 41 Subaddresses 76H, 77H and 7CH

DATA BYTE DESCRIPTION REMARKS

TTXOVS first line of occurrence of signal on pin TTXRQ in odd field PAL: TTXOVS = 05H;

line = (TTXOVS + 4) for M-systems
line = (TTXOVS + 1) for other systems

TTXOVE last line of occurrence of signal on pin TTXRQ in odd field PAL: TTXOVE = 16H;

line = (TTXOVE + 3) for M-systems
line = TTXOVE for other systems

NTSC: TTXOVS = 06H

NTSC: TTXOVE = 10H

Table 42 Subaddresses 78H, 79H and 7CH

DATA BYTE DESCRIPTION REMARKS

TTXEVS first line of occurrence of signal on pin TTXRQ in even field PAL: TTXEVS = 04H;

line = (TTXEVS + 4) for M-systems
line = (TTXEVS + 1) for other systems

TTXEVE last line of occurrence of signal on pin TTXRQ in even field PAL: TTXEVS = 16H;

line = (TTXEVE + 3) for M-systems
line = TTXEVE for other systems

Table 43 Subaddress 7CH

DATA BYTE

TTXO 0 new TTX protocol selected: at each rising edge of TTXRQ a single TTX bit is requested

TTX60 0 enables NABTS (FISE = 1) or European TTX (FISE = 0); default after reset

Table 44 Subaddresses 7AH to 7CH

LOGIC
LEVEL

see Fig.14; default after reset

1 old TTX protocol selected: the encoder provides a window of TTXRQ going HIGH; the

length of the window depends on the chosen TTX standard see Fig.14

1 enables world standard teletext 60 Hz (FISE = 1)

DESCRIPTION

NTSC: TTXEVS = 05H

NTSC: TTXEVS = 10H

DATA BYTE DESCRIPTION

FAL first active line = FAL + 4 for M-systems, = FAL + 1 for other systems, measured in lines

FAL = 0 coincides with the first field synchronization pulse

LAL last active line = LAL + 3 for M-systems, = LAL for other system, measured in lines

LAL = 0 coincides with the first field synchronization pulse

1999 May 31 22

Philips Semiconductors Product specification

Digital video encoder SAA7126H; SAA7127H

Table 45 Subaddresses 7EH and 7FH

DATA BYTE DESCRIPTION

LINE individual lines in both fields (PAL counting) can be disabled for insertion of teletext by the respective

bits, disabled line = LINExx (50 Hz field rate)

this bit mask is effective only, if the lines are enabled by TTXOVS/TTXOVE and TTXEVS/TTXEVE

In subaddresses 5BH, 5CH, 5DH, 5EH and 62H all IRE values are rounded up.

Slave transmitter
Table 46 Slave transmitter (slave address 89H)

REGISTER
FUNCTION

Status byte 00H VER2 VER1 VER0 CCRDO CCRDE 0 FSEQ O_E

Table 47 Subaddress 00H

DATA BYTE

VER − version identification of the device: it will be changed with all versions of the IC that have

CCRDO 1 closed caption bytes of the odd field have been encoded

CCRDE 1 closed caption bytes of the even field have been encoded

FSEQ 1 during first field of a sequence (repetition rate: NTSC = 4 fields, PAL = 8 fields)

O_E 1 during even field

SUBADDRESS

D7 D6 D5 D4 D3 D2 D1 D0

LOGIC
LEVEL

different programming models; current version is 000 binary

0 the bit is reset after information has been written to the subaddresses 67H and 68H; it is

set immediately after the data has been encoded

0 the bit is reset after information has been written to the subaddresses 69H and 6AH; it is

set immediately after the data has been encoded

0 not first field of a sequence

0 during odd field

DATA BYTE

DESCRIPTION

1999 May 31 23

Philips Semiconductors Product specification

Digital video encoder SAA7126H; SAA7127H

handbook, full pagewidth

6

G

v

(dB)

0

−6

−12

−18

−24

−30

−36

−42

−48

−54

024

(1) SCBW = 1.
(2) SCBW = 0.

(1) (2)

Fig.3 Chrominance transfer characteristic 1.

MBE737

6 8 10 12 14

f (MHz)

handbook, halfpage

(1) SCBW = 1.
(2) SCBW = 0.

2

G

v

(dB)

0

−2

−4

−6

0 0.4 0.8 1.6

Fig.4 Chrominance transfer characteristic 2.

1999 May 31 24

MBE735

(1)

(2)

1.2

f (MHz)

Philips Semiconductors Product specification

Digital video encoder SAA7126H; SAA7127H

6

G

handbook, full pagewidth

v

(dB)

0

−6

−12

−18

−24

−30

−36

−42

−48

−54

024

(1) CCRS1 = 0; CCRS0 = 1.
(2) CCRS1 = 1; CCRS0 = 0.
(3) CCRS1 = 1; CCRS0 = 1.
(4) CCRS1 = 0; CCRS0 = 0.

MGD672

(4)

(3)

(2)

(1)

6

8101214

f (MHz)

(1) CCRS1 = 0; CCRS0 = 0.

Fig.5 Luminance transfer characteristic 1.

handbook, halfpage

1

G

v

(dB)

0

−1

−2

−3

−4

−5

02

(1)

Fig.6 Luminance transfer characteristic 2.

MBE736

4

f (MHz)

6

1999 May 31 25

Philips Semiconductors Product specification

Digital video encoder SAA7126H; SAA7127H

handbook, full pagewidth

6

G

v

(dB)

0

−6

−12

−18

−24

−30

−36

−42

−48

−54

024

6 8 10 12 14

Fig.7 Luminance transfer characteristic in RGB.

MGB708

f (MHz)

handbook, full pagewidth

6

G

v

(dB)

0

−6

−12

−18

−24

−30

−36

−42

−48

−54

024

6 8 10 12 14

Fig.8 Colour difference transfer characteristic in RGB.

MGB706

f (MHz)

1999 May 31 26

Philips Semiconductors Product specification

Digital video encoder SAA7126H; SAA7127H

handbook, full pagewidth

CVBS output

RCV2 input

55LLC

MP input

HTRIG = 0
PRCV2 = 0.
TRCV2 = 1.
ORCV2 = 0.

handbook, full pagewidth

CVBS output

RCV2 output

51LLC

Fig.9 Sync and video input timing.

MHB500

49LLC

RCV2S = 0.
PRCV2 = 0.
ORCV2 = 1.

Fig.10 Sync and video output timing.

1999 May 31 27

MHB501

Philips Semiconductors Product specification

Digital video encoder SAA7126H; SAA7127H

CHARACTERISTICS

V

= 3.0 to 3.6 V; T

DDD

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

Supplies

V
V
I

DDA

I

DDD

DDA
DDD

analog supply voltage 3.15 3.45 V
digital supply voltage 3.0 3.6 V
analog supply current note 1 − 100 mA
digital supply current V

Inputs

V

IL

LOW-level input voltage (pins LLC1, RCV1,
RCV2, MP7 to MP0, RTCI, SA, RESET
and TTX)

V

IH

HIGH-level input voltage (pins LLC1, RCV1,
RCV2, MP7 to MP0, RTCI, SA, RESET
and TTX)

I

LI

C

i

input leakage current − 1 µA
input capacitance clocks − 10 pF

=0to70°C; unless otherwise specified.

amb

= 3.3 V; note 1 − 46 mA

DDD

−0.5 +0.8 V

2.0 V

DDD

+ 0.3 V

data − 8pF
I/Os at high-impedance − 8pF

Outputs; pins RCV1, RCV2 and TTXRQ

V

OL

V

OH

2

C-bus; SDA and SCL

I

V

IL

V

IH

I

i

V

OL

I

o

LOW-level output voltage IOL=2mA − 0.4 V
HIGH-level output voltage IOH= 2 mA 2.4 − V

LOW-level input voltage −0.5 0.3V
HIGH-level input voltage 0.7V
input current Vi= LOW or HIGH −10 +10 µA
LOW-level output voltage (pin SDA) IOL=3mA − 0.4 V
output current during acknowledge 3 − mA

Clock timing (pins LLC1 and XCLK)

T

LLC1

δ duty factor t

cycle time note 2 34 41 ns

LLC1 input 40 60 %
XCLK output typical

duty factor t

HIGH/TLLC1
HIGH/TXCLK

50%

t

r

t

f

rise time note 2 − 5ns
fall time note 2 − 6ns

Input timing; pins LLC1, RCV1, RCV2, MP7 to MP0, RTCI, SA and TTX

t

SU;DAT

t

HD;DAT

input data set-up time 6 − ns
input data hold time 3 − ns

Crystal oscillator

f

n

∆f/f

n

nominal frequency (usually 27 MHz) 3rd-harmonic − 30 MHz
permissible deviation of nominal frequency note 3 −50 +50 10

DD(I2C)

DD(I2C)VDD(I2C)

V

+ 0.3 V

40 60 %

−6

1999 May 31 28

Philips Semiconductors Product specification

Digital video encoder SAA7126H; SAA7127H

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

C

RYSTAL SPECIFICATION

T

amb

C

L

R

S

C

1

C

0

Data and reference signal output timing

C

L

t

h

t

d

CVBS and RGB outputs

V

o(p-p)

∆V

o

R

s(int)

R

L

B output signal bandwidth of DACs −3dB 10 − MHz
LE

lf(i)

LE

lf(d)

t

d(pipe)(MP)

Notes

1. At maximum supply voltage with highly active input signals.

2. The data is for both input and output direction.

3. If an internal oscillator is used, crystal deviation of nominal frequency is directly proportional to the deviation of
subcarrier frequency and line/field frequency.

4. For full digital range, without load, V
voltage (digital zero at DAC) is 0.2 V.

ambient temperature 0 70 °C
load capacitance 8 − pF
series resistance − 80 Ω
motional capacitance (typical) 1.5 − 20% 1.5 + 20% fF
parallel capacitance (typical) 3.5 − 20% 3.5 + 20% pF

output load capacitance 7.5 40 pF
output hold time 4 − ns
output delay time − 25 ns

output signal voltage (peak-to-peak value) note 4 1.30 1.55 V
inequality of output signal voltages − 2%
internal serial resistance 1 3 Ω
output load resistance 75 300 Ω

low frequency integral linearity error of DACs −±3 LSB
low frequency differential linearity error of

−±1 LSB

DACs
total pipeline delay from MP port 27 MHz − 51 LLC

= 3.3 V. The typical voltage swing is 1.45 V, the typical minimum output

DDA

1999 May 31 29

Philips Semiconductors Product specification

Digital video encoder SAA7126H; SAA7127H

handbook, full pagewidth

XCLK

LLC1

input data

output data

t

SU; DAT

t

HD; DAT

valid

t

h

valid

T

t

d

LLC1

t

f

T

LLC1

t

f

not valid

not valid

t

HIGH

t

HIGH

Fig.11 Clock data timing.

2.6 V

1.5 V

0.6 V

t

r

2.4 V

1.5 V

0.8 V

t

r

valid

valid

MHB502

2.0 V

0.8 V

2.4 V

0.6 V

handbook, full pagewidth

LLC

MP(n)

RCV2

The data demultiplexing phase is coupled to the internal horizontal phase.
The phase of the RCV2 signal is programmed to tbf (tbf for 50 Hz) in this example in output mode (RCV2S).

Cb(0) Y(0) Cr(0) Y(1) Cb(2)

Fig.12 Functional timing.

1999 May 31 30

MGB699

Philips Semiconductors Product specification

Digital video encoder SAA7126H; SAA7127H

Explanation of RTCI data bits

8/LLC

3 bits

reserved

(5)

(4)

(6)

(3)

6764 69 72 74

68

MHB503

(7)

(8)

handbook, full pagewidth

RTCI

(1) SAA7111/12 provides 14 to 0 bits, resulting in 2 reserved bits before FSCPLL increment.
(2) SAA7151 provides 21 to 0 bits only, resulting in 5 reserved bits before sequence bit.
(3) Sequence bit: PAL: 0 = (R − Y) line normal, 1 = (R − Y) line inverted; NTSC: 0 = no change.
(4) Reset bit: only from SAA7111 and SAA7112 decoder.
(5) FISE bit: 0 = 50 Hz, 1 = 60 Hz.
(6) Odd/even bit: odd_even from external.
(7) Colour detection: 0 = no colour detected, 1 = colour detected.
(8) Reserved bits: 229 with 50 Hz systems, 226 with 60 Hz systems.

H/L transition

count start

128

time slot:

LOW

not used in SAA7126H/27H

13

01

HPLL

increment

reserved

(1)

0 022

14 19

4 bits

FSCPLL increment

valid

sample

invalid

sample

(2)

Fig.13 RTCI timing.

1. The HPLL increment is not evaluated by SAA7126H; SAA7127H.

2. The SAA7126H; SAA7127H generates the subcarrier frequency from the FSCPLL increment if enabled (see item 7.).

3. The PAL bit indicates the line with inverted (R − Y) component of colour difference signal.

4. If the reset bit is enabled (RTCE = 1; DECPH = 1; PHRES = 00), the phase of the subcarrier is reset in each line
whenever the reset bit of RTCI input is set to logic 1.

5. If the FISE bit is enabled (RTCE = 1; DECFIS = 1), the SAA7126H; SAA7127H takes this bit instead of the FISE bit
in subaddress 61H.

6. If the odd/even bit is enabled (RTCE = 1; DECOE = 1), the SAA7126H; SAA7127H ignores it’s internally generated
odd/even flag and takes the odd/even bit from RTCI input.

7. If the colour detection bit is enabled (RTCE = 1; DECCOL = 1) and no colour was detected (colour detection bit = 0),
the subcarrier frequency is generated by the SAA7126H; SAA7127H. In the other case (colour detection bit = 1) the
subcarrier frequency is evaluated out of FSCPLL increment.

If the colour detection bit is disabled (RTCE = 1; DECCOL = 0), the subcarrier frequency is evaluated out of FSCPLL
increment, independent of the colour detection bit of RTCI input.

1999 May 31 31

Philips Semiconductors Product specification

Digital video encoder SAA7126H; SAA7127H

Teletext timing

Time tFD is the time needed to interpolate input data TTX
and insert it into the CVBS and VBS output signal, such
that it appears at t

= 9.78 µs (PAL) or t

TTX

TTX

= 10.5 µs
(NTSC) after the leading edge of the horizontal
synchronization pulse.

Time t

d(pipe)(MP)

is the pipeline delay time introduced by the
source that is gated by TTXRQ in order to deliver TTX
data. This delay is programmable by register TTXHD. For
every active HIGH state at output pin TTXRQ, a new
teletext bit must be provided by the source (new protocol)
or a window of TTXRQ going HIGH is provided and the
number of teletext bits, depending on the chosen TTX
standard, is requested at input pin TTX (old protocol).

Since the beginning of the pulses representing the TTXRQ
signal and the delay between the rising edge of TTXRQ
and valid teletext input data are fully programmable
(TTXHS and TTXHD), the TTX data is always inserted at
the correct position after the leading edge of outgoing
horizontal synchronization pulse.

Time t

is the internally used insertion window for

i(TTXW)

TTX data; it has a constant length that allows insertion of
360 teletext bits at a text data rate of 6.9375 Mbits/s
(PAL), 296 teletext bits at a text data rate of 5.7272 Mbits/s
(world standard TTX) or 288 teletext bits at a text data rate
of 5.7272 Mbits/s (NABTS). The insertion window is not
opened if the control bit TTXEN is zero.

Using appropriate programming, all suitable lines of the
odd field (TTXOVS and TTXOVE) plus all suitable lines of
the even field (TTXEVS and TTXEVE) can be used for
teletext insertion.

handbook, full pagewidth

CVBS/Y

TTX

TTXRQ (new)

TTXRQ (old)

t

TTX

text bit #: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

t

PD

t

FD

t

i(TTXW)

MHB504

Fig.14 Teletext timing.

1999 May 31 32

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1999 May 31 33

ok, full pagewidth

APPLICATION INFORMATION

Philips Semiconductors Product specification

Digital video encoder SAA7126H; SAA7127H

0.1 µH

digital

inputs and

outputs

1 nF

DGND

10 pF

10 pF

27.0 MHz
X1

3rd harmonic

XTALI XTAL

+

3.3 V digital

0.1 µF

V

DDD1

use one capacitor
for each V

SAA7126H
SAA7127H

DDD

DGND

to V

5, 18, 38

V

AGND

DDD3

SSD1

to V

+

3.3 V analog

0.1 µF

SSD3

V

DAC1

DAC2

DAC3

DAC4

DDA4

0.1 µF

use one capacitor
for each V

V

to V

DDA1

25, 28, 31366, 17, 3935 34

22, 32, 33

V

to V

SSA1

AGND

DDA

DDA3

SSA3

2 Ω

2 Ω

2 Ω

2 Ω

(1)

(1)

(1)

(1)

MHB505

23 RED

26

GREEN

BLUE

29

CVBS

30

23 Ω

75 Ω

23 Ω

75 Ω

23 Ω

75 Ω

4.7 Ω

75 Ω

U

R

0.70 V (p-p)

AGND

U

G

0.70 V (p-p)

AGND

U

B

0.70 V (p-p)

AGND

U

CVBS

1.23 V (p-p)

AGND

(2)

(2)

(2)

(2)

(1) Typical value.

100

(2) For

⁄

colour bar.

100

DGND

AGND

Fig.15 Application circuit.

Philips Semiconductors Product specification

Digital video encoder SAA7126H; SAA7127H

Analog output voltages

The analog output voltages are dependent on the open-loop voltage of the operational amplifiers for full-scale conversion
(typical value 1.375 V), the internal series resistor (typical value 2 Ω), the external series resistor and the external load
impedance.

The digital output signals in front of the DACs under nominal conditions occupy different conversion ranges, as indicated
in Table 48 for a

Values for the external series resistors result in a 75 Ω load.

Table 48 Digital output signals conversion range

CVBS, SYNC

TIP-TO-PEAK CARRIER

100

⁄

colour bar signal.

100

CONVERSION RANGE (peak-to-peak)

Y (VBS)

SYNC TIP-TO-WHITE

(digits)

1016 881 712

(digits)

BLACK-TO-WHITE AT GDY = GDC = −6

RGB (Y)

(digits)

1999 May 31 34

Philips Semiconductors Product specification

Digital video encoder SAA7126H; SAA7127H

PACKAGE OUTLINE

QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm

c

y

X

A

33 23

34

pin 1 index

44

1

22

Z

E

e

H

E

E

w M

b

p

12

11

A

2

A

A

1

detail X

SOT307-2

(A )

3

θ

L

p

L

w M

b

e

DIMENSIONS (mm are the original dimensions)

mm

OUTLINE
VERSION

SOT307-2

A

max.

2.10

0.25

0.05

1.85

1.65

UNIT A1A2A3bpcE

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

p

D

H

D

0.40

0.20

0.25

0.14

0.25

IEC JEDEC EIAJ

Z

D

B

0 2.5 5 mm

scale

(1)

(1) (1)(1)

D

10.1

9.9

REFERENCES

eH

10.1

9.9

12.9

0.8 1.3

12.3

1999 May 31 35

v M

H

v M

D

A

B

E

12.9

12.3

LL

p

0.95

0.55

0.15 0.10.15

EUROPEAN

PROJECTION

Z

D

1.2

0.8

Zywv θ

E

o

1.2

10

o

0.8

0

ISSUE DATE

95-02-04
97-08-01

Philips Semiconductors Product specification

Digital video encoder SAA7126H; SAA7127H

SOLDERING
Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

Wave soldering

Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

1999 May 31 36

Philips Semiconductors Product specification

Digital video encoder SAA7126H; SAA7127H

Suitability of surface mount IC packages for wave and reflow soldering methods

PACKAGE

WAVE REFLOW

(1)

BGA, SQFP not suitable suitable

SOLDERING METHOD

HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable

(3)

PLCC

, SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended
SSOP, TSSOP, VSO not recommended

(2)

(3)(4)
(5)

suitable

suitable
suitable

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

.

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

1999 May 31 37

Philips Semiconductors Product specification

Digital video encoder SAA7126H; SAA7127H

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

PURCHASE OF PHILIPS I

2

C COMPONENTS

Purchase of Philips I
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.

2

C components conveys a license under the Philips’ I2C patent to use the

1999 May 31 38

Philips Semiconductors Product specification

Digital video encoder SAA7126H; SAA7127H

NOTES

1999 May 31 39

Philips Semiconductors – a worldwide company

Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

Tel. [phone], Fax. [phone]
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. [phone], Fax. [phone]

Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,
Tel. [phone], Fax. [phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. [phone], Fax. [phone]

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. [phone], Fax. [phone]

Colombia: see South America
Czech Republic: see Austria
Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,

Tel. [phone], Fax. [phone]
Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. [phone], Fax. [phone]
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,

Tel. [phone], Fax. [phone]
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,

Tel. [phone], Fax. [phone]

Hungary: see Austria
India: Philips INDIA Ltd, Band Box Building, 2nd floor,

254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. [phone], Fax. [phone]

Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. [phone] ext. 2501, Fax. [phone]

Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. [phone], Fax. [phone]

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. [phone], Fax. [phone]

Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. [phone], Fax. [phone]

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. [phone], Fax. [phone]

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. [phone], Fax. [phone]

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. [phone], Fax. [phone]

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. [phone], Fax [phone]

Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
Tel. [phone], Fax. [phone]

South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. [phone], Fax. [phone]

Spain: Balmes 22, 08007 BARCELONA,
Tel. [phone], Fax. [phone]

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone] Fax. [phone]

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone], Fax. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

1999 65

Internet: http://www.semiconductors.philips.com

Printed in The Netherlands 545006/01/pp40 Date of release: 1999 May 31 Document order number: 9397 750 05278