Datasheet SAA7118E, SAA7118H Datasheet (Philips)

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Page 1

INTEGRATED CIRCUITS

DATA SH EET

SAA7118

Multistandard video decoder with adaptivecombfilterandcomponent video input

Preliminary speciﬁcation Supersedes data of 2000 Nov 27 File under Integrated Circuits, IC22

2001 May 30

Page 2

Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive comb ﬁlter and component video input

CONTENTS

1 FEATURES

1.1 Video acquisition/clock

1.2 Video decoder

1.3 Component video processing

1.4 Video scaler

1.5 Vertical Blanking Interval (VBI) data decoder and slicer

1.6 Audio clock generation

1.7 Digital I/O interfaces

1.8 Miscellaneous

2 APPLICATIONS 3 GENERAL DESCRIPTION 4 QUICK REFERENCE DATA 5 ORDERING INFORMATION 6 BLOCK DIAGRAM 7 PINNING 8 FUNCTIONAL DESCRIPTION

8.1 Decoder

8.2 Component video processing

8.3 Decoder output formatter

8.4 Scaler

8.5 VBI-data decoder and capture (subaddresses 40H to 7FH)

8.6 Image port output formatter (subaddresses 84H to 87H)

8.7 Audio clock generation (subaddresses 30H to 3FH)

9 INPUT/OUTPUT INTERFACES AND PORTS

9.1 Analog terminals

9.2 Audio clock signals

9.3 Clock and real-time synchronization signals

9.4 Interrupt handling

9.5 Video expansion port (X-port)

9.6 Image port (I-port)

9.7 Host port for 16-bit extension ofvideo data I/O (H-port)

9.8 Basic input and output timing diagrams I-port and X-port

10 BOUNDARY SCAN TEST

10.1 Initialization of boundary scan circuit

10.2 Device identification codes

11 LIMITING VALUES 12 THERMAL CHARACTERISTICS 13 CHARACTERISTICS 14 APPLICATION INFORMATION 15 I2C-BUS DESCRIPTION

15.1 I2C-bus format

15.2 I2C-bus details

15.3 Programming register RGB/Y-PB-P

15.4 Interrupt mask registers

15.5 Programming register audio clock generation

15.6 Programming register VBI-data slicer

15.7 Programming register interfaces and scaler

16 PROGRAMMING START SET-UP

16.1 Decoder part

16.2 Component video part and interrupt mask

16.3 Audio clock generation part

16.4 Data slicer and data type control part

16.5 Scaler and interfaces 17 PACKAGE OUTLINES 18 SOLDERING

18.1 Introduction to soldering surface mount

18.2 Reflow soldering

18.3 Wave soldering

18.4 Manual soldering

18.5 Suitability of surface mount IC packages for

19 DATA SHEET STATUS 20 DEFINITIONS 21 DISCLAIMERS 22 PURCHASE OF PHILIPS I2C COMPONENTS

SAA7118

component input processing

part

packages

wave and reflow soldering methods

2001 May 30 2

Page 3

Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive comb ﬁlter and component video input

1 FEATURES

1.1 Video acquisition/clock

• Up to sixteen analog CVBS, split as desired (all of the

CVBS inputs optionally can be used to convert e.g. Vestigial Side Band (VSB) signals)

• Up to eight analog Y + C inputs, split as desired

• Up to four analog component inputs, with embedded or

separate sync, split as desired

• Four on-chip anti-aliasing filters in front of the

Analog-to-Digital Converters (ADCs)

• Automatic Clamp Control (ACC) for CVBS, Y and C

(or VSB) and component signals

• Switchable white peak control

• Four 9-bit low noise CMOS ADCs running at twice the

oversampling rate (27 MHz)

• Fully programmable static gain or Automatic Gain

Control (AGC), matching to the particular signal properties

• On-chip line-locked clock generation in accordance with

“ITU 601”

• Requires only one crystal (32.11 or 24.576 MHz) for all

standards

• Horizontal and vertical sync detection.

1.2 Video decoder

• Digital PLL for synchronization and clock generation

from all standards and non-standard video sources e.g. consumer grade VTR

• Automatic detection of any supported colour standard

• Luminance and chrominance signal processing for

PAL B, G, D, H, I and N, combination PAL N, PAL M, NTSC M, NTSC-Japan, NTSC 4.43 and SECAM

• Adaptive 2/4-line comb filter for two dimensional

chrominance/luminance separation, also with VTR signals

– Increasedluminanceandchrominancebandwidthfor

all PAL and NTSC standards

– Reduced cross colour and cross luminance artefacts

• PAL delay line for correcting PAL phase errors

• Brightness Contrast Saturation (BCS) adjustment,

separately for composite and baseband signals

• User programmable sharpness control

• Detection of copy-protected signals according to the

macrovision standard, indicating level of protection

SAA7118

• Independent gain and offset adjustment for raw data path.

1.3 Component video processing

• RGB component inputs

• Y-PB-PR component inputs

• Fast blanking between CVBS and synchronous

component inputs

• Digital RGB to Y-CB-CR matrix.

1.4 Video scaler

• Horizontal and vertical downscaling and upscaling to randomly sized windows

• Horizontal and vertical scaling range: variable zoom to

⁄64(icon) (note: H and V zoom are restricted by the

transfer data rates)

• Anti-alias and accumulating filter for horizontal scaling

• Vertical scaling with linear phase interpolation and

accumulating filter for anti-aliasing (6-bit phase accuracy)

• Horizontal phase correct up and downscaling for improved signal quality of scaled data, especially for compression and video phone applications, with 6-bit phase accuracy (1.2 ns step width)

• Two independent programming sets for scaler part, to define two ‘ranges’ per field or sequences over frames

• Fieldwise switching between decoder part and expansion port (X-port) input

• Brightness, contrast and saturation controls for scaled outputs.

1.5 Vertical Blanking Interval (VBI) data decoder

and slicer

• Versatile VBI-data decoder, slicer, clock regeneration and byte synchronization e.g. for World Standard Teletext (WST), North-American Broadcast Text System(NABTS),closecaption,WideScreen Signalling (WSS) etc.

2001 May 30 3

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Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive comb ﬁlter and component video input

1.6 Audio clock generation

• Generation of a field-locked audio master clock to support a constant number of audio clocks per video field

• Generation of an audio serial and left/right (channel) clock signal.

1.7 Digital I/O interfaces

• Real-time signal port (R port), inclusive continuous line-locked reference clock and real-time status information supporting RTC level 3.1 (refer to document

“RTC Functional Specification”

• Bidirectional expansion port (X-port) with half duplex functionality (D1), 8-bit Y-CB-C

– Output from decoder part, real-time and unscaled – Input to scaler part, e.g. video from MPEG decoder

(extension to 16-bit possible)

• Video image port (I-port) configurable for 8-bit data (extension to 16-bit possible) in master mode (own clock), or slave mode (external clock), with auxiliary timing and handshake signals

• Discontinuous data streams supported

• 32-word × 4-byte FIFO register for video output data

• 28-word × 4-byte FIFO register for decoded VBI-data

output

• Scaled 4:2:2, 4:1:1, 4:2:0, 4:1:0 Y-CB-C output

• Scaled 8-bit luminance only and raw CVBS data output

• Sliced, decoded VBI-data output.

1.8 Miscellaneous

• Power-on control

• 5 V tolerant digital inputs and I/O ports

• Software controlled power saving standby modes

supported

• Programming via serial I2C-bus, full read back ability by an external controller, bit rate up to 400 kbits/s

• Boundary scan test circuit complies with the

1149.b1 - 1994”

for details)

“IEEE Std.

SAA7118

2 APPLICATIONS

• PC-video capture and editing

• Personal video recorders (time shifting)

• Cable, terrestrial, and satellite set-top boxes

• Internet terminals

• Flat-panel monitors

• DVD-recordable players

• AV-ready hard-disk drivers

• Digital televisions/scan conversion

• Video surveillance/security

• Video editing/post production

• Video phones

• Video projectors

• Digital VCRs.

3 GENERAL DESCRIPTION

The SAA7118 is a video capture device for applications at the image port of VGA controllers.

Philips X-VIP is a new multistandard comb filter video decoder chip with additional component processing, providing high quality, optionally scaled, video.

The SAA7118 is a combination of a four-channel analog preprocessing circuit including source selection, anti-aliasing filter and ADC with succeeding decimation filters from 27 to 13.5 MHz data rate. Each preprocessing channel comes with an automatic clamp and gain control. The SAA7118 combines a Clock Generation Circuit (CGC), a digital multistandard decoder containing two-dimensionalchrominance/luminance separationbyan adaptive comb filter and a high performance scaler, including variable horizontal and vertical up and downscaling and a brightness, contrast and saturation control circuit.

2001 May 30 4

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Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive comb ﬁlter and component video input

It is a highly integrated circuit for desktop video and similar applications. The decoder is based on the principle of line-lockedclock decoding and is abletodecode the colour of PAL, SECAM and NTSC signals into ITU 601 compatible colour component values. The SAA7118 accepts CVBS or S-video (Y/C) as analog inputs from TV or VCR sources, including weak and distorted signals as well as baseband component signals Y-PB-PRor RGB. An expansion port (X-port) for digital video (bidirectional half duplex, D1 compatible) is also supported to connect to MPEG or video phone codec. At the so called image port (I-port) the SAA7118 supports 8 or 16-bit wide output data with auxiliary reference data for interfacing to VGA controllers.

The target application for the SAA7118 is to capture and scale video images, to be provided as digital video stream through the image port of a VGA controller, for capture to system memory, or just to provide digital baseband video to any picture improvement processing.

SAA7118

The SAA7118 also provides a means for capturing the serially coded data in the vertical blanking interval (VBI-data). Two principal functions are available:

1. To capture raw video samples, after interpolation to the required output data rate, via the scaler

2. A versatile data slicer (data recovery) unit.

The SAA7118 also incorporates field-locked audio clock generation. This function ensures that there is always the same number of audio samples associated with a field, or a set of fields. This prevents the loss of synchronization between video and audio during capture or playback.

All of the ADCs may be used to digitize a VSB signal for subsequent decoding; a dedicated output port and a selectable VSB clock input is provided.

The circuit is I2C-bus controlled (full write/read capability for all programming registers, bit rate up to 400 kbits/s).

4 QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

DDD

DDDC

DDA

amb

A+D

Note

1. Power dissipation is measured in component mode (four ADCs active) and 8-bit image port output mode, expansion port is 3-stated.

5 ORDERING INFORMATION

TYPE

NUMBER

SAA7118E BGA156 plastic ball grid array package; 156 balls; body 15 × 15 × 1.15 mm SOT472-1 SAA7118H QFP160 plastic quad ﬂat package; 160 leads (lead length 1.6 mm);

digital supply voltage 3.0 3.3 3.6 V digital core supply voltage 3.0 3.3 3.6 V analog supply voltage 3.1 3.3 3.5 V ambient temperature 0 − 70 °C analog and digital power dissipation note 1 − 1.1 1.35 W

PACKAGE

NAME DESCRIPTION VERSION

SOT322-2

body 28 × 28 × 3.4 mm; high stand-off height

2001 May 30 5

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2001 May 30 6

]

ADP[8:0

CLKEXT

RES

DNC0 to DNC5

dbook, full pagewidth

INT_ASCLSDACE

6 BLOCK DIAGRAM

Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive

comb ﬁlter and component video input

FSW

AI11 AI12 AI13 AI14

AI1D

AI21 AI22 AI23 AI24

AI2D

AI31 AI32 AI33 AI34

AI3D

AI41 AI42 AI43 AI44

AI4D

AOUT

AGND

AGNDA

AD PORT

ANALOG1

ADC1

ANALOG2

ADC2

ANALOG3

ADC3

ANALOG4

ADC4

POWER-ON CONTROL

POWER SUPPLY

CONTROL

I2C-BUS REGISTER MAP

FAST SWITCH DELAY

R G

COMPONENTS

PROCESSING

RAW

CROMINANCE PROCESSING

COMB FILTER

ANALOG INPUT CONTROL

LUMININANCE

PROCESSING

SYNCHRONIZATION VIDEO/TEXT ARBITER

VIDEO

CLOCK

GPO CRYSTAL X PORT

Y-CB-C

DECODER OUTPUT CONTROL

RAW Y-CB-C

Y-CB-CRS

FIRST TASK I2C-BUS REGISTER MAP SCALER

SECOND TASK I2C-BUS REGISTER MAP SCALER

SCALER EVENT CONTROLLER

PRESCALER

BCS-SCALER

FIR-PREFILTER

LINE FIFO BUFFER

HORIZONTAL

VERTICAL SCALING

FINE (PHASE) SCALING

SAA7118

VBI-DATA SLICER

CB-C

H PORT

CB-C

AUDIO

CLOCK

VIDEO FIFO

TEXT

FIFO

BOUNDARY

SCAN

IGP1 IGP0 IGPV IGPH

]

IPD[7:0

ICLK IDQ

OUTPUT FORMATTER I PORT

ITRDY ITRI

SSA

DDA

SSD

DDD

SS(xtal)

DD(xtal)

LLC

LLC2

RTS0

RTS1

RTCO

XTALO

XTALI

XRDY

XTOUT

XCLK

XPD[7:0

Fig.1 Block diagram.

HPD[7:0

AMXCLK

]

XTRIXRH

]

XDQ

XRV

ALRCLK

AMCLK

ASCLK

TDO

TDI TCK

TRST

TMS

SAA7118

Page 7

Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive comb ﬁlter and component video input

7 PINNING

SYMBOL

QFP160 BGA156

DNC6 1 B2 O do not connect, reserved for future extensions and for testing AI41 2 B1 I analog input 41 AGND 3 C2 P analog ground V

SSA4

4 C1 P ground for analog inputs AI4x AI42 5 D2 I analog input 42 AI4D 6 D3 I differential input for ADC channel 4 (pins AI41 to AI44) AI43 7 D1 I analog input 43 V

DDA4

DDA4A

8 D4 P analog supply voltage for analog inputs AI4x (3.3 V)

9 E2 P analog supply voltage for analog inputs AI4x (3.3 V) AI44 10 E1 I analog input 44 AI31 11 E3 I analog input 31 V

SSA3

12 E4 P ground for analog inputs AI3x AI32 13 F2 I analog input 32 AI3D 14 F1 I/O differential input for ADC channel 3 (pins AI31 to AI34) AI33 15 F3 I analog input 33 V

DDA3

DDA3A

16 F4 P analog supply voltage for analog inputs AI3x (3.3 V)

17 G2 P analog supply voltage for analog inputs AI3x (3.3 V) AI34 18 G1 I analog input 34 AI21 19 G4 I analog input 21 V

SSA2

20 H3 P ground for analog inputs AI2x AI22 21 G3 I analog input 22 AI2D 22 H1 I differential input for ADC channel 2 (pins AI24 to AI21) AI23 23 H2 I analog input 23 V

DDA2

DDA2A

24 H4 P analog supply voltage for analog inputs AI2x

25 J1 P analog supply voltage for analog inputs AI2x AI24 26 J3 I analog input 24 AI11 27 J2 I analog input 11 V

SSA1

28 J4 P ground for analog inputs AI1x AI12 29 K1 I analog input 12 AI1D 30 K3 I differential input for ADC channel 1 (pins AI14 to AI11) AI13 31 K2 I analog input 13 V

DDA1

DDA1A

32 K4 P analog supply voltage for analog inputs AI1x (3.3 V)

33 L1 P analog supply voltage for analog inputs AI1x (3.3 V) AI14 34 L3 I analog input 14 AGNDA 35 L2 P analog signal ground AOUT 36 M1 O analog test output (do not connect) V V

DDA0 SSA0

37 M3 P analog supply voltage (3.3 V) for internal clock generation circuit

38 M2 P ground for internal Clock Generation Circuit (CGC)

TYPE

(1)

DESCRIPTION

SAA7118

2001 May 30 7

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Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive

SAA7118

comb ﬁlter and component video input

SYMBOL

QFP160 BGA156

DNC13 39 N1 NC do not connect, reserved for future extensions and for testing DNC14 40 N2 I/pu do not connect, reserved for future extensions and for testing DNC18 41 P2 I/O do not connect, reserved for future extensions and for testing DNC15 42 N3 I/pd do not connect, reserved for future extensions and for testing EXMCLR 43 P3 I/pd external mode clear (with internal pull-down) CE 44 N4 I/pu chip enable or reset input (with internal pull-up) V

DDD1

45 C5 P digital supply voltage 1 (peripheral cells) LLC 46 P4 O line-locked system clock output (27 MHz nominal) V

SSD1

47 D5 P digital ground 1 (peripheral cells) LLC2 48 N5 O line-locked1⁄2clock output (13.5 MHz nominal) RES 49 P5 O reset output (active LOW) V V

DDD2 SSD2

50 C8 P digital supply voltage 2 (core)

51 D7 P digital ground 2 (core; substrate connection) CLKEXT 52 N6 I external clock input intended for analog-to-digital conversion of VSB

ADP8 53 P6 O MSB of direct analog-to-digital converted output data (VSB) ADP7 54 M6 O MSB − 1 of direct analog-to-digital converted output data (VSB) ADP6 55 L6 O MSB − 2 of direct analog-to-digital converted output data (VSB) ADP5 56 N7 O MSB − 3 of direct analog-to-digital converted output data (VSB) ADP4 57 P7 O MSB − 4 of direct analog-to-digital converted output data (VSB) ADP3 58 L7 O MSB − 5 of direct analog-to-digital converted output data (VSB) V

DDD3

59 C9 P digital supply voltage 3 (peripheral cells) ADP2 60 M7 O MSB − 6 of direct analog-to-digital converted output data (VSB) ADP1 61 P8 O MSB − 7 of direct analog-to-digital converted output data (VSB) ADP0 62 N8 O LSB of direct analog-to-digital converted output data (VSB) V

SSD3

63 D9 P digital ground 3 (peripheral cells) INT_A 64 P9 O/od I2C-bus interrupt ﬂag (LOW if any enabled status bit has changed) V

DDD4

65 C10 P digital supply voltage 4 (core) SCL 66 N9 I serial clock input (I2C-bus) V

SSD4

67 D10 P digital ground 4 (core) SDA 68 P10 I/O/od serial data input/output (I2C-bus) RTS0 69 M10 O real-time status or sync information, controlled by subaddresses

RTS1 70 N10 O real-time status or sync information, controlled by subaddresses

RTCO 71 L10 O/st/pd real-time control output; contains information about actual system clock

AMCLK 72 P11 O audio master clock output, up to 50% of crystal clock

TYPE

(1)

DESCRIPTION

signals (36 MHz)

11H and 12H

frequency, ﬁeld rate, odd/even sequence, decoder status, subcarrier frequency and phase and PAL sequence (see document

Description”

, available on request); the RTCO pin is enabled via I2C-bus

“RTC Functional

bit RTCE; see notes 5, 6 and Table 35

2001 May 30 8

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Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive

SAA7118

comb ﬁlter and component video input

SYMBOL

QFP160 BGA156

DDD5

73 D12 P digital supply voltage 5 (peripheral cells) ASCLK 74 N11 O audio serial clock output ALRCLK 75 P12 O/st/pd audio left/right clock output; can be strapped to supply via a 3.3 kΩ resistor

AMXCLK 76 M12 I audio master external clock input ITRDY 77 N12 I target ready input for image port data DNC0 78 P13 I/pu do not connect, reserved for future extensions and for testing: scan input DNC16 79 N13 NC do not connect, reserved for future extensions and for testing DNC17 80 N14 NC do not connect, reserved for future extensions and for testing DNC19 81 − NC do not connect, reserved for future extensions and for testing DNC20 82 − NC do not connect, reserved for future extensions and for testing FSW 83 M13 I/pd fast switch (blanking) with internal pull-down inserts component inputs into

ICLK 84 M14 I/O clock output signal for image port, or optional asynchronous back-end

IDQ 85 L13 O output data qualiﬁer for image port (optional: gated clock output) ITRI 86 L12 I/(O) image port output control signal, affects all input port pins inclusive ICLK,

IGP0 87 L14 O general purpose output signal 0; image port (controlled by subaddresses

SSD5

88 D11 P digital ground 5 (peripheral cells) IGP1 89 K13 O general purpose output signal 1; image port (controlled by subaddresses

IGPV 90 K14 O multi purpose vertical reference output signal; image port (controlled by

IGPH 91 K12 O multi purpose horizontal reference output signal; image port (controlled by

IPD7 92 K11 O MSB of image port data output IPD6 93 J13 O MSB − 1 of image port data output IPD5 94 J14 O MSB − 2 of image port data output V V

DDD6 SSD6

95 F12 P digital supply voltage 6 (core)

96 F11 P digital ground 6 (core) IPD4 97 H13 O MSB − 3 of image port data output IPD3 98 H14 O MSB − 4 of image port data output IPD2 99 H11 O MSB − 5 of image port data output IPD1 100 G12 O MSB − 6 of image port data output V

DDD7

101 H12 P digital supply voltage 7 (peripheral cells)

IPD0 102 G14 O LSB of image port data output

TYPE

(1)

DESCRIPTION

to indicate that the default 24.576 MHz crystal (ALRCLK = 0; internal pull-down) has been replaced by a 32.110 MHz crystal (ALRCLK = 1); notes 5 and 7

CVBS signal

clock input

enable and active polarity is under software control (bits IPE in subaddress 87H); output path used for testing: scan output

84H and 85H)

subaddresses 84H and 85H)

2001 May 30 9

Page 10

Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive

SAA7118

comb ﬁlter and component video input

SYMBOL

QFP160 BGA156

HPD7 103 G13 I/O MSB of host port data I/O, extended CB-CR input for expansion port,

SSD7

104 G11 P digital ground 7 (peripheral cells)

HPD6 105 F14 I/O MSB − 1 of host port data I/O, extended CB-CR input for expansion port,

DDD8

106 J12 P digital supply voltage 8 (core)

HPD5 107 F13 I/O MSB − 2 of host port data I/O, extended CB-CR input for expansion port,

SSD8

108 J11 P digital ground 8 (core)

HPD4 109 E14 I/O MSB − 3 of host port data I/O, extended CB-CR input for expansion port,

HPD3 110 E12 I/O MSB − 4 of host port data I/O, extended CB-CR input for expansion port,

HPD2 111 E13 I/O MSB − 5 of host port data I/O, extended CB-CR input for expansion port,

HPD1 112 E11 I/O MSB − 6 of host port data I/O, extended CB-CR input for expansion port,

HPD0 113 D14 I/O LSB of host port data I/O, extended CB-CR input for expansion port,

DDD9

114 M4 P digital supply voltage 9 (peripheral cells) DNC1 115 D13 I/pu do not connect, reserved for future extensions and for testing: scan input DNC2 116 C14 I/pu do not connect, reserved for future extensions and for testing: scan input DNC7 117 B13 NC do not connect, reserved for future extensions and for testing DNC8 118 B14 NC do not connect, reserved for future extensions and for testing DNC11 119 C12 NC do not connect, reserved for future extensions and for testing DNC12 120 C13 NC do not connect, reserved for future extensions and for testing DNC21 121 − NC do not connect, reserved for future extensions and for testing DNC22 122 − NC do not connect, reserved for future extensions and for testing DNC3 123 A13 I/pu do not connect, reserved for future extensions and for testing: scan input DNC4 124 B12 O do not connect, reserved for future extensions and for testing: scan output DNC5 125 A12 I/pu do not connect, reserved for future extensions and for testing: scan input XTRI 126 B11 I X-port output control signal, affects all X-port pins (XPD7 to XPD0, XRH,

XPD7 127 C11 I/O MSB of expansion port data XPD6 128 A11 I/O MSB − 1 of expansion port data V

SSD9

129 L4 P digital ground 9 (peripheral cells) XPD5 130 B10 I/O MSB − 2 of expansion port data XPD4 131 A10 I/O MSB − 3 of expansion port data V

DDD10

SSD10

132 M5 P digital supply voltage 10 (core)

133 L5 P digital ground 10 (core)

TYPE

(1)

DESCRIPTION

extended CB-CR output for image port

XRV, XDQ and XCLK), enable and active polarity is under software control (bits XPE in subaddress 83H)

2001 May 30 10

Page 11

Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive

SAA7118

comb ﬁlter and component video input

SYMBOL

QFP160 BGA156

XPD3 134 B9 I/O MSB − 4 of expansion port data XPD2 135 A9 I/O MSB − 5 of expansion port data V

DDD11

SSD11

136 M8 P digital supply voltage 11 (peripheral cells)

137 L8 P digital ground 11 (peripheral cells) XPD1 138 B8 I/O MSB − 6 of expansion port data XPD0 139 A8 I/O LSB of expansion port data XRV 140 D8 I/O vertical reference I/O expansion port XRH 141 C7 I/O horizontal reference I/O expansion port V

DDD12

142 M9 P digital supply voltage 12 (core) XCLK 143 A7 I/O clock I/O expansion port XDQ 144 B7 I/O data qualiﬁer for expansion port V

SSD12

145 L9 P digital ground 12 (core) XRDY 146 A6 O task ﬂag or ready signal from scaler, controlled by XRQT TRST 147 C6 I/pu test reset input (active LOW), for boundary scan test (with internal pull-up);

TCK 148 B6 I/pu test clock for boundary scan test; note 2 TMS 149 D6 I/pu test mode select input for boundary scan test or scan test; note 2 TDO 150 A5 O test data output for boundary scan test; note 2 V

DDD13

151 M11 P digital supply voltage 13 (peripheral cells) TDI 152 B5 I/pu test data input for boundary scan test; note 2 V

SSD13

SS(xtal)

153 L11 P digital ground 13 (peripheral cells)

154 A4 P ground for crystal oscillator XTALI 155 B4 I input terminal for 24.576 MHz (32.11 MHz) crystal oscillator or connection

XTALO 156 A3 O 24.576 MHz (32.11 MHz) crystal oscillator output; not connected if TTL

DD(xtal)

157 B3 P supply voltage for crystal oscillator XTOUT 158 A2 O crystal oscillator output signal; auxiliary signal DNC9 159 C3 NC do not connect, reserved for future extensions and for testing DNC10 160 C4 NC do not connect, reserved for future extensions and for testing

TYPE

(1)

DESCRIPTION

notes 2, 3 and 4

of external oscillator with TTL compatible square wave clock signal

clock input of XTALI is used

Notes

1. I = input, O = output, P = power, NC = not connected, st = strapping, pu = pull-up, pd = pull-down, od = open-drain.

2. In accordance with the

“IEEE1149.1”

standard the pads TDI, TMS, TCK and TRST are input pads with an internal

pull-up transistor and TDO is a 3-state output pad.

3. For board design without boundary scan implementation connect the TRST pin to ground.

4. This pin provides easy initialization of the Boundary Scan Test (BST) circuit. TRST can be used to force the Test Access Port (TAP) controller to the TEST_LOGIC_RESET state (normal operation) at once.

5. Pin strapping is done by connecting the pin to the supply via a 3.3 kΩ resistor. During the power-up reset sequence the corresponding pins are switched to input mode to read the strapping level. For the default setting no strapping resistor is necessary (internal pull-down).

2001 May 30 11

Page 12

Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive

SAA7118

comb ﬁlter and component video input

6. Pin RTCO operates as I2C-bus slave address pin; RTCO = 0 slave address 42H/43H (default); RTCO = 1 slave address 40H/41H.

7. Pin ALRCLK: 0 = 24.576 MHz crystal (default); 1 = 32.110 MHz crystal.

handbook, full pagewidth

DD(xtal)

SS(xtal)VSSD13

DNC6

AGND

SSA4

AI4D

DDA4

DDA4A

SSA3

AI3D

DDA3

DDA3A

SSA2

AI2D

DDA2

DDA2A

SSA1

AI1D

DDA1

DDA1A

AGNDA

AOUT

DDA0

SSA0

DNC13 DNC14

AI41

AI42

AI43

AI44 AI31

AI32

AI33

AI34 AI21

AI22

AI23

AI24 AI11

AI12

AI13

AI14

153

TDI 152

DDD13

V 151

TDO 150

TMS 149

TCK 148

DNC10

DNC9

XTOUT

XTALO

XTALI

160

159

158

157

156

155

154

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

TRST 147

XRDY 146

SSD12

XDQ

145

144

DDD12

XCLK

XRH

XRV

143

142

141

140

SAA7118H

XPD0 139

SSD11VDDD11

XPD1

138

137

136

XPD2

XPD3

135

134

SSD10VDDD10

XPD4

133

132

131

XPD5 130

SSD9

V 129

XPD6 128

XPD7 127

XTRI 126

DNC5 125

DNC4

DNC3

124

123

DNC22

DNC21

122

121

120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

DNC12 DNC11 DNC8 DNC7 DNC2 DNC1 V

DDD9

HPD0 HPD1 HPD2 HPD3 HPD4 V

SSD8

HPD5 V

DDD8

HPD6 V

SSD7

HPD7 IPD0 V

DDD7

IPD1 IPD2 IPD3 IPD4 V

SSD6

DDD6

IPD5 IPD6 IPD7 IGPH IGPV IGP1 V

SSD5

IGP0 ITRI IDQ ICLK FSW DNC20 DNC19

414243444546474849505152535455565758596061626364656667686970717273747576777879

DNC18

DNC15

EXMCLR

DDD1

LLC

SSD1

LLC2

RES

DDD2

SSD2

ADP8

CLKEXT

ADP7

ADP6

ADP5

ADP4

ADP3

DDD3

Fig.2 Pin configuration (QFP160).

2001 May 30 12

ADP2

ADP1

ADP0

SSD3

INT_A

SCL

DDD4

SSD4

SDA

RTS0

RTS1

RTCO

DDD5

AMCLK

ASCLK

ALRCLK

ITRDY

AMXCLK

DNC0

DNC16

DNC17

MXXxxx

Page 13

Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive comb ﬁlter and component video input

handbook, halfpage

P N M

L K

J H G

E D C B A

234567891011121314

Fig.3 Pin configuration (BGA156).

SAA7118E

SAA7118

MHB725

2001 May 30 13

Page 14

2001 May 30 14

Table 1 Pin assignment (top view)

1234567891011121314

Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive

comb ﬁlter and component video input

A XTOUT XTALO V

B AI41 TEST3 V

C V

SSA4

AGND TEST7 TEST8 V

DD(xtal)

D AI43 AI42 AI4D V

E AI44 V

DDA4A

AI31 V

F AI3D AI32 AI33 V

G AI34 V

DDA3A

H AI2D AI23 V

J V

DDA2A

AI11 AI24 V

AI22 AI21 V

SSA2

K AI12 AI13 AI1D V

SS(xtal)

TDO XRDY XCLK XPD0 XPD2 XPD4 XPD6 TEST1 TEST2

XTALI TDI TCK XDQ XPD1 XPD3 XPD5 XTRI TEST4 TEST5 TEST6

DDA4

SSA3

DDA3

DDA2

SSA1

DDA1

DDD1

SSD1

TRST XRH V

TMS V

SSD2

DDD2

XRV V

DDD3

SSD3

DDD4

SSD4

XPD7 TEST9 TEST10 TEST11

SSD5

DDD5

TEST12 HPD0

HPD1 HPD3 HPD2 HPD4

SSD6

SSD7

IPD2 V

SSD8

DDD6

HPD5 HPD6

IPD1 HPD7 IPD0

IPD4 IPD3

IPD6 IPD5

DDD7

DDD8

IPD7 IGPH IGP1 IGPV

L V

DDA1A

M AOUT V

AGNDA AI14 V

SSA0

DDA0

SSD9

DDD9

SSD10

DDD10

ADP6 ADP3 V

ADP7 ADP2 V

SSD11VSSD12

DDD11VDDD12

RTCO V

RTS0 V

SSD13

DDD13

ITRI IDQ IGP0

AMXCLK FSW ICLK

N TEST13 TEST14 TEST15 CE LLC2 CLKEXT ADP5 ADP0 SCL RTS1 ASCLK ITRDY TEST16 TEST17

P TEST18 EXMCLR LLC RES ADP8 ADP4 ADP1 INT_A SDA AMCLK ALRCLK TEST19

SAA7118

Page 15

2001 May 30 15

Table 2 8-bit/16-bit and alternative pin functional conﬁgurations

(1)

C11, A11, B10, A10, B9, A9, B8, A8 (127, 128,130, 131,134, 135,138,

139) A7 (143) XCLK clock

B7 (144) XDQ data

A6 (146) XRDY input

C7 (141) XRH horizontal

D8 (140) XRV vertical

B11 (126)

SYMBOL

XPD7 to XPD0

XTRI output

8-BIT

INPUT

MODES

D1 data input

input

qualiﬁer input

ready output

reference input

enable input

16-BIT INPUT

MODES (ONLY

FOR I2C-BUS

PROGRAMMING)

Y data input D1

ALTERNATIVE

INPUT

FUNCTIONS

gated clock input

active task A/B ﬂag

8-BIT

OUTPUT

MODES

decoder output

decoder clock output

data qualiﬁer output (HREFand VREF gate)

decoder horizontal reference output

decoder vertical reference output

16-BIT OUTPUT

MODES (ONLY

FOR I2C-BUS

PROGRAMMING)

ALTERNATIVE

OUTPUT

FUNCTIONS

I/O

CONFIGURATION

PROGRAMMING

BITS

XCODE[92H[3]] XPE[1:0] 83H[1:0] + pin XTRI

XPE[1:0] 83H[1:0] + pin XTRI XPCK[1:0] 83H[5:4] XCKS[92H[0]]

XDQ[92H[1]] XPE[1:0] 83H[1:0] + pin XTRI

XRQT[83H[2]] XPE[1:0] 83H[1:0] + pin XTRI

XDH[92H[2]] XPE[1:0] 83H[1:0] + pin XTRI

XDV[1:0] 92H[5:4] XPE[1:0] 83H[1:0] + pin XTRI

XPE[1:0] 83H[1:0]

Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive

comb ﬁlter and component video input

SAA7118

Page 16

2001 May 30 16

(1)

G13, F14, F13, E14, E12, E13, E11,D14 (103, 105,107, 109 to

113) K11,

J13,J14, H13, H14, H11, G12, G14 (92 to 94, 97 to 99, 100,

102) M14 (84) ICLK clock

L13 (85) IDQ data

N12 (77) ITRDY target

K12 (91) IGPH H-gate

SYMBOL

HPD7 to HPD0

IPD7 to IPD0

8-BIT

INPUT

MODES

16-BIT INPUT

MODES (ONLY

FOR I2C-BUS

PROGRAMMING)

CB-CR data input CB-CR scaler

ALTERNATIVE

INPUT

FUNCTIONS

8-BIT

OUTPUT

MODES

D1 scaler output

output

qualiﬁer output

ready input

output

16-BIT OUTPUT

MODES (ONLY

FOR I2C-BUS

PROGRAMMING)

output

Y scaler output ICODE[93H[7]]

ALTERNATIVE

OUTPUT

FUNCTIONS

clock input ICKS[1:0] 80H[1:0]

gated clock output

extended H-gate, horizontal pulses

CONFIGURATION

PROGRAMMING

ICODE[93H[7]] ISWP[1:0] 85H[7:6] I8_16[93H[6]] IPE[1:0] 87H[1:0] + pin ITRI

ISWP[1:0] 85H[7:6] I8_16[93H[6]] IPE[1:0] 87H[1:0] + pin ITRI

IPE[1:0] 87H[1:0] + pin ITRI

ICKS[3:2] 80H[3:2] IDQP[85H[0]] IPE[1:0] 87H[1:0] + pin ITRI

IDH[1:0] 84H[1:0] IRHP[85H[1]] IPE[1:0] 87H[1:0] + pin ITRI

I/O

BITS

Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive

comb ﬁlter and component video input

SAA7118

Page 17

2001 May 30 17

(1)

K14 (90) IGPV V-gate

K13 (89) IGP1 general

L14 (87) IGP0 general

L12 (86) ITRI output

Note

1. Pin numbers for QFP160 in parenthesis.

SYMBOL

8-BIT

INPUT

MODES

16-BIT INPUT

MODES (ONLY

FOR I2C-BUS

PROGRAMMING)

ALTERNATIVE

INPUT

FUNCTIONS

8-BIT

OUTPUT

MODES

output

purpose

enable input

16-BIT OUTPUT

MODES (ONLY

FOR I2C-BUS

PROGRAMMING)

ALTERNATIVE

OUTPUT

FUNCTIONS

V-sync, vertical pulses

I/O

CONFIGURATION

PROGRAMMING

BITS

IDV[1:0] 84H[3:2] IRVP[85H[2]] IPE[1:0] 87H[1:0] + pin ITRI

IDG1[1:0] 84H[5:4] IG1P[85H[3]] IPE[1:0] 87H[1:0] + pin ITRI

IDG0[1:0] 84H[7:6] IG0P[85H[4]] IPE[1:0] 87H[1:0] + pin ITRI

Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive

comb ﬁlter and component video input

SAA7118

Page 18

Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive

SAA7118

comb ﬁlter and component video input

8 FUNCTIONAL DESCRIPTION

8.1 Decoder

8.1.1 ANALOG INPUT PROCESSING The SAA7118 offers sixteen analog signal inputs, four analog main channels with source switch, clamp circuit, analog

amplifier, anti-alias filter and video 9-bit CMOS ADC with a Decimation Filter (DF); see Figs 5 and 8. The anti-alias filters are adapted to the line-locked clock frequency via a filter control circuit. The characteristic is shown

in Fig.4. During the vertical blanking period gain and clamping control are frozen.

MGD138

(dB)

−6

−12

−18

−24

−30

−36

−42

024 68101214

f (MHz)

Fig.4 Anti-alias filter.

2001 May 30 18

Page 19

Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive comb ﬁlter and component video input

gain (dB)

−3

−6

−9

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

−45

−48

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10 10.5 11 11.5 12 12.5 13 13.5

SAA7118

f (MHz)

Fig.5 Decimation filter.

2001 May 30 19

Page 20

Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive comb ﬁlter and component video input

8.1.1.1 Clamping

The clamp control circuit controls the correct clamping of the analog input signals. The coupling capacitor is also used to store and filter the clamping voltage. An internal digital clamp comparator generates the information with respect to clamp-up or clamp-down. The clamping levels for the four ADC channels are fixed for luminance (120), chrominance (256) and for component inputs as component Y (32), components PB and PR (256) or components RGB (32). Clamping time in normaluse is set with the HCL pulse on the back porch of the video signal.

8.1.1.2 Gain control

The gain control circuit receives (via theI2C-bus) the static gain levels for the four analog amplifiers or controls one of theseamplifiersautomaticallyviaabuilt-inAutomaticGain Control (AGC) as part of the Analog Input Control (AICO).

SAA7118

The AGC (automatic gain control for luminance) is used to amplify a CVBS or Y signal to the required signal amplitude, matched to the ADCs input voltage range. Component inputs are gain adjusted manually at a fixed gain. The AGC active time is the sync bottom of the video signal.

Signal (white) peak control limits the gain at signal overshoots. The flow charts (see Figs 9 and 10) show more details of the AGC. The influence of supply voltage variation within the specified range is automatically eliminated by clamp and automatic gain control.

handbook, halfpage

analog line blanking

511

GAIN CLAMP

120

TV line

HCL

HSY

Fig.6 Analog line with clamp (HCL) and gain

range (HSY). Fig.7 Automatic gain range.

MHB726

analog input level

+3 dB

0 dB

(1 V (p-p) 18/56 Ω)

−6 dB

maximum

range 9 dB

minimum

controlled

ADC input level

0 dB

MHB325

2001 May 30 20

Page 21

Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive comb ﬁlter and component video input

handbook, full pagewidth

AI44 AI43 AI42 AI41

AI4D

AI34 AI33 AI32 AI31

AI3D

SOURCE

SWITCH

SOURCE

SWITCH

CLAMP

CIRCUIT

CLAMP

CIRCUIT

ANALOG

AMPLIFIER

DAC9

ANALOG

AMPLIFIER

DAC9

ANTI-ALIAS

FILTER

ANTI-ALIAS

FILTER

BYPASS SWITCH

FUSE[1:0

BYPASS SWITCH

SAA7118

TEST

SELECTOR

AND

BUFFER

DIGITAL

]

AOSL[2:0

ADC4

]

ADC3

TEST

SELECTOR

DOSL[1:0

]

ADPE

AOUT

ADP[8:0

]

AI24 AI23 AI22 AI21

AI2D

AI14 AI13 AI12 AI11

AI1D

SOURCE

SWITCH

SOURCE

SWITCH

MODE

CONTROL

MODE[5:0

]

FUSE[1:0

CLAMP

CIRCUIT

CLAMP

CIRCUIT

CLAMP

CONTROL

HCL

]

CHROMACVBS/Y

ANALOG

AMPLIFIER

DAC9

ANALOG

AMPLIFIER

DAC9

GLIMB GLIMT WIPA SLTCA

GAIN

CONTROL

HSY

HOLDG GAFIX WPOFF GUDL[1:0 GAI[48:40 GAI[38:30 HLNRS UPTCV REFA

ANTI-ALIAS

FILTER

ANTI-ALIAS

CONTROL

VBSL

] ] ]

ANALOG CONTROL

CROSS MULTIPLEXER

BYPASS SWITCH

FUSE[1:0

BYPASS SWITCH

FUSE[1:0

VERTICAL

BLANKING

CONTROL

R/R - Y

]

VBLNK SVREF

G/Y

B/B - Y

ADC2

ADC1

DF DF DF DF

9999

AD1/3BYPAD2/4BYP

Fig.8 Analog input processing using the SAA7118 as differential front-end with 9-bit ADC.

2001 May 30 21

Page 22

Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive comb ﬁlter and component video input

handbook, full pagewidth

NO ACTION

ANALOG INPUT

AMPLIFIER

ANTI-ALIAS FILTER

ADC

VBLK

HOLDG

SAA7118

gain

DAC

LUMA/CHROMA DECODER

HSY

STOP

X = system variable.

Y AGV FGV– GUDL>=

GUDL = gain update level (adjustable). VBLK = vertical blanking pulse. HSY = horizontal sync pulse. AGV = actual gain value. FGV = frozen gain value.

+1/F

496

+1/L

510

X = 0

−1/LLC2

GAIN ACCUMULATOR (18 BITS)

ACTUAL GAIN VALUE 9-BIT (AGV) [−3/+6 dB

AGV

+1/LLC2 −1/LLC2

GAIN VALUE 9-BIT

HSY

UPDATE

510

X = 1

+/− 0

FGV

MHB728

]

Fig.9 Gain flow chart.

2001 May 30 22

Page 23

Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive comb ﬁlter and component video input

ANALOG INPUT

ADC

NO BLANKING ACTIVE

10 10

CLL

+ CLAMP − CLAMP

VBLK

HCL HSY

01 10

NO CLAMP

+ GAIN − GAIN

GAIN -><- CLAMP

SBOT

fast − GAIN

SAA7118

WIPE

slow + GAIN

MGC647

WIPE = white peak level (510). SBOT = sync bottom level (1). CLL = clamp level [120 for CVBS, Y(C), S; 256 for C(Y), PB-PR; 32 for RGB, Y]. HSY = horizontal sync pulse. HCL = horizontal clamp pulse.

Fig.10 Clamp and gain flow chart.

2001 May 30 23

Page 24

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2001 May 30 24

ndbook, full pagewidth

8.1.2 CHROMINANCE AND LUMINANCE PROCESSING

Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive

comb ﬁlter and component video input

CVBS-IN

or CHR-IN

CVBS-IN

or Y-IN

QUADRATURE

DEMODULATOR

SUBCARRIER

GENERATION 1

HUEC

LDEL

YCOMB

SUBCARRIER

GENERATION 2

CHROMINANCE

INCREMENT

DELAY

COMPENSATION

QUADRATURE

MODULATOR

LOW-PASS 1

DOWNSAMPLING

LCBW[2:0

LDEL YCOMB

CHROMINANCE

INCREMENT

DTO RESET

SUBCARRIER

INCREMENT

GENERATION

AND

DIVIDER

]

CHR

CB-C

SUBTRACTOR

INTERPOLATION

LOW-PASS 3

LUBW

ADAPTIVE

COMB FILTER

SET_RAW

SET_VBI

DEMODULATOR

AMPLITUDE

DETECTOR

BURST GATE

ACCUMULATOR

LOOP FILTER

CB-C

CCOMB

YCOMB

LDEL BYPS

PHASE

LUMINANCE-PEAKING

Y-DELAY ADJUSTMENT

LUFI[3:0

CSTD[2:0

CB-C

YDEL[2:0

LOW-PASS,

]

SET_RAW

]

SET_VBI

]

LOW-PASS 2

CHBW

SECAM

PROCESSING

CHROMA

GAIN

CONTROL

CB-C

ADJUSTMENT

Y/CVBS

]

DBRI[7:0 DCON[7:0 DSAT[7:0

RAWG[7:0 RAWO[7:0

CB-C

PAL DELAY LINE

RECOMBINATION

]

] ]

COLO

BRIGHTNESS

CONTRAST

SATURATION

CONTROL

RAW DATA

GAIN AND

OFFSET

CONTROL

SET_RAW

SET_VBI

SECAM

Y-OUT/ CVBS OUT

CB-CR-OUT

HREF-OUT

CDTO

RTCO

CSTD[2:0

INCS

]

FCTC

ACGC

CGAIN[6:0

IDEL[3:0

CODE

] ]

Fig.11 Chrominance and luminance processing.

SECS

SET_RAW

SET_VBI

fH/2 switch signal

DCVF

MHB729

SAA7118

Page 25

Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive comb ﬁlter and component video input

8.1.2.1 Chrominance path

The 9-bit CVBS or chrominance input signal is fed to the inputofa quadrature demodulator, where it is multiplied by twotime-multiplexed subcarrier signalsfromthe subcarrier generation block 1 (0° and 90° phase relationship to the demodulator axis). The frequency is dependent on the chosen colour standard.

The time-multiplexed output signals of the multipliers are low-pass filtered (low-pass 1). Eight characteristics are programmable via LCWB3 to LCWB0 to achieve the desired bandwidth for the colour difference signals (PAL, NTSC) or the 0° and 90° FM signals (SECAM).

Thechrominance low-pass 1characteristicalso influences the grade of cross-luminance reduction during horizontal colour transients (large chrominance bandwidth means strong suppression of cross-luminance). If the Y-comb filterisdisabledbyYCOMB = 0 the filter influences directly the width of the chrominance notch within the luminance path (a large chrominance bandwidth means wide chrominance notch resulting in a lower luminance bandwidth).

The low-pass filtered signals are fed to the adaptive comb filter block. The chrominance components are separated from the luminance via a two line vertical stage (four lines for PAL standards) and a decision logic between the filtered and the non-filtered output signals. This block is bypassed for SECAM signals. The comb filter logic can be enabled independently for the succeeding luminance and chrominance processing by YCOMB (subaddress 09H, bit 6) and/or CCOMB (subaddress 0EH, bit 0). It is always bypassed during VBI or raw data lines programmable by the LCRn registers (subaddresses 41H to 57H); see Section 8.3.

The separated CB-CR components are further processed by a second filter stage (low-pass 2) to modify the chrominance bandwidth without influencing the luminance path. It’s characteristic is controlled by CHBW (subaddress 10H, bit 3). For the complete transfer characteristic of low-passes 1 and 2 see Figs 12 and 13.

SAA7118

The succeeding chrominance gain control block amplifies or attenuates the CB-CR signal according to the required ITU 601/656 levels. It is controlled by the output signal from the amplitude detection circuit within the burst processing block.

The burst processing block provides the feedback loop of the chrominance PLL and contains the following:

• Burst gate accumulator

• Colour identification and colour killer

• Comparisonnominal/actual burstamplitude(PAL/NTSC

standards only)

• Loop filter chrominance gain control (PAL/NTSC standards only)

• Loop filter chrominance PLL (only active for PAL/NTSC standards)

• PAL/SECAM sequence detection, H/2-switch generation.

The increment generation circuit produces the Discrete Time Oscillator (DTO) increment for both subcarrier generation blocks. It contains a division by the increment of the line-locked clock generator to create a stable phase-locked sine signal under all conditions (e.g. for non-standard signals).

The PAL delay line block eliminates crosstalk between the chrominance channels in accordance with the PAL standard requirements. For NTSC colour standards the delay line can be used as an additional vertical filter. If desired, it can be switched off by DCVF = 1. It is always disabledduringVBIorrawdata lines programmable by the LCRn registers (subaddresses 41H to 57H); see Section 8.3. The embedded line delay is also used for SECAM recombination (cross-over switches).

The SECAM processing (bypassed for QAM standards) contains the following blocks:

• Baseband ‘bell’ filters to reconstruct the amplitude and phase equalized 0° and 90° FM signals

• Phase demodulator and differentiator (FM-demodulation)

• De-emphasis filter to compensate the pre-emphasized input signal, including frequency offset compensation (DB or DR white carrier values are subtracted from the signal, controlled by the SECAM switch signal).

2001 May 30 25

Page 26

Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive comb ﬁlter and component video input

(dB)

−3

−6

−9

(1) LCBW[2:0] = 000. (2) LCBW[2:0] = 010. (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110.

(5) LCBW[2:0] = 001. (6) LCBW[2:0] = 011. (7) LCBW[2:0] = 101. (8) LCBW[2:0] = 111.

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

−45

−48

−51

−54

−57

−60

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0

(dB)

−3

−6

−9

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

−45

−48

−51

−54

−57

−60

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0

(1) (2) (3) (4)

(5) (6) (7) (8)

SAA7118

MHB533

f (MHz)

Fig.12 Transfer characteristics of the chrominance low-pass at CHBW = 0.

2001 May 30 26

Page 27

Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive comb ﬁlter and component video input

(dB)

−3

−6

−9

(1) LCBW[2:0] = 000. (2) LCBW[2:0] = 010. (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110.

(5) LCBW[2:0] = 001. (6) LCBW[2:0] = 011. (7) LCBW[2:0] = 101. (8) LCBW[2:0] = 111.

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

−45

−48

−51

−54

−57

−60

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0

(dB)

−3

−6

−9

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

−45

−48

−51

−54

−57

−60

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0

(1) (2) (3) (4)

(5) (6) (7) (8)

SAA7118

MHB534

f (MHz)

Fig.13 Transfer characteristics of the chrominance low-pass at CHBW = 1.

2001 May 30 27

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Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive comb ﬁlter and component video input

8.1.2.2 Luminance path

The rejection of the chrominance components within the 9-bit CVBS or Y input signal isachieved by subtracting the remodulated chrominance signal from the CVBS input.

The comb filtered CB-CR components are interpolated (upsampled) by the low-pass 3 block. It’s characteristic is controlled by LUBW (subaddress 09H, bit 4) to modify the width of the chrominance ‘notch’ without influencing the chrominance path. The programmable frequency characteristics available, in conjunction with the LCBW2 to LCBW0 settings, can be seen in Figs 14 to 17. It should be noted that these frequency curves are only valid for Y-comb disabled filter mode (YCOMB = 0). In comb filter modethe frequency response is flat. The centre frequency of the notch is automatically adapted to the chosen colour standard.

The interpolated CB-CR samples are multiplied by two time-multiplexed subcarrier signals from the subcarrier generation block 2. This second DTO is locked to the first subcarrier generator by an increment delay circuit matchedtotheprocessingdelay,which is different for PAL and NTSC standards according to the chosen comb filter algorithm. The two modulated signals are finally added to build the remodulated chrominance signal.

SAA7118

The frequency characteristic of the separated luminance signal can be further modified by the succeeding luminance filter block. It can be configured as peaking (resolution enhancement) or low-pass block by LUFI3 to LUFI0 (subaddress 09H, bits 3 to 0). The 16 resulting frequency characteristics can be seen in Fig.18. The LUFI3 to LUFI0 settings can be used as a user programmable sharpness control.

The luminance filter block also contains the adjustable Y-delay part; programmable by YDEL2 to YDEL0 (subaddress 11H, bits 2 to 0).

2001 May 30 28

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Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive comb ﬁlter and component video input

(dB)

−3

−6

(1) LCBW[2:0] = 000. (2) LCBW[2:0] = 010. (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110.

(5) LCBW[2:0] = 001. (6) LCBW[2:0] = 011. (7) LCBW[2:0] = 101. (8) LCBW[2:0] = 111.

−9

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

−45

−48

−51

−54

−57

−60

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0

(dB)

−3

−6

−9

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

−45

−48

−51

−54

−57

−60

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0

(1) (2) (3) (4)

(5) (6) (7) (8)

SAA7118

MHB535

f (MHz)

Fig.14 Transfer characteristics of the luminance notch filter in 3.58 MHz mode (Y-comb filter disabled) at

LUBW = 0.

2001 May 30 29

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Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive comb ﬁlter and component video input

(dB)

−3

−6

(1) LCBW[2:0] = 000 (2) LCBW[2:0] = 010 (3) LCBW[2:0] = 100 (4) LCBW[2:0] = 110

(5) LCBW[2:0] = 001 (6) LCBW[2:0] = 011 (7) LCBW[2:0] = 101 (8) LCBW[2:0] = 111

−9

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

−45

−48

−51

−54

−57

−60

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0

(dB)

−3

−6

−9

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

−45

−48

−51

−54

−57

−60

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0

(1) (2) (3) (4)

(5) (6) (7) (8)

SAA7118

MHB536

f (MHz)

Fig.15 Transfer characteristics of the luminance notch filter in 3.58 MHz mode (Y-comb filter disabled) at

LUBW = 1.

2001 May 30 30

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Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive comb ﬁlter and component video input

(dB)

−3

−6

−9

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

−45

−48

(1) LCBW[2:0] = 000. (2) LCBW[2:0] = 010. (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110.

(5) LCBW[2:0] = 001. (6) LCBW[2:0] = 011. (7) LCBW[2:0] = 101. (8) LCBW[2:0] = 111.

−51

−54

−57

−60

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0

(dB)

−3

−6

−9

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

−45

−48

−51

−54

−57

−60

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0

SAA7118

MHB537

(1) (2) (3) (4)

f (MHz)

(5) (6) (7) (8)

f (MHz)

Fig.16 Transfer characteristics of the luminance notch filter in 4.43 MHz mode (Y-comb filter disabled) at

LUBW = 0.

2001 May 30 31

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Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive comb ﬁlter and component video input

(dB)

−3

−6

−9

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

−45

−48

(1) LCBW[2:0] = 000. (2) LCBW[2:0] = 010. (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110.

(5) LCBW[2:0] = 001. (6) LCBW[2:0] = 011. (7) LCBW[2:0] = 101. (8) LCBW[2:0] = 111.

−51

−54

−57

−60

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0

(dB)

−3

−6

−9

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

−45

−48

−51

−54

−57

−60

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0

SAA7118

MHB538

(1) (2) (3) (4)

f (MHz)

(5) (6) (7) (8)

f (MHz)

Fig.17 Transfer characteristics of the luminance notch filter in 4.43 MHz mode (Y-comb filter disabled) at

LUBW = 1.

2001 May 30 32

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Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive comb ﬁlter and component video input

(dB)

(1) LUFI[3:0] = 0001. (2) LUFI[3:0] = 0010. (3) LUFI[3:0] = 0011. (4) LUFI[3:0] = 0100. (5) LUFI[3:0] = 0101. (6) LUFI[3:0] = 0110. (7) LUFI[3:0] = 0111. (8) LUFI[3:0] = 0000.

(9) LUFI[3:0] = 1000. (10) LUFI[3:0] = 1001. (11) LUFI[3:0] = 1010. (12) LUFI[3:0] = 1011. (13) LUFI[3:0] = 1100. (14) LUFI[3:0] = 1101. (15) LUFI[3:0] = 1110. (16) LUFI[3:0] = 1111.

−1 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

(dB)

−3

−6

−9

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

(1) (2) (3) (4) (5) (6) (7) (8)

(9) (10) (11) (12) (13) (14) (15) (16)

SAA7118

MHB539

f (MHz)

Fig.18 Transfer characteristics of the luminance peaking/low-pass filter (sharpness).

2001 May 30 33

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Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive

SAA7118

comb ﬁlter and component video input

8.1.2.3 Brightness Contrast Saturation (BCS) control and decoder output levels

The resulting Y (CVBS) and CB-CR signals are fed to the BCS block, which contains the following functions:

• Chrominance saturation control by DSAT7 to DSAT0

• Luminance contrast and brightness control by DCON7 to DCON0 and DBRI7 to DBRI0

• Raw data (CVBS) gain and offset adjustment by RAWG7 to RAWG0 and RAWO7 to RAWO0

• Limiting Y-CB-CR or CVBS to the values 1 (minimum) and 254 (maximum) to fulfil

handbook, full pagewidth

+255 +235

+128

white

LUMINANCE 100%

+255 +240

+212 +212

+128

blue 100%

blue 75%

colourless

+255 +240

+128

“ITU Recommendation 601/656”

red 100% red 75%

colourless

CB-COMPONENT

yellow 75% yellow 100%

+44 +16

+16

+44

black

+16

a. Y output range. b. CB output range. c. CR output range.

“ITU Recommendation 601/656”

Equations for modification to the Y-CB-CR levels via BCS control I2C-bus bytes DBRI, DCON and DSAT. Luminance:

Chrominance:

It should be noted that the resulting levels are limited to 1 to 254 in accordance with

OUT

CRCB()

OUT

digital levels with default BCS (decoder) settings DCON[7:0] = 44H, DBRI[7:0] = 80H and DSAT[7:0] = 40H.

DCON

Int

-----------------

Int

DSAT

--------------- 64

Y 128–()× DBRI+=

CRCB, 128–()× 128+=

“ITU Recommendation 601/656”

Fig.19 Y-CB-CR range for scaler input and X-port output.

CR-COMPONENT

cyan 75% cyan 100%

MHB730

2001 May 30 34

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Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive comb ﬁlter and component video input

+255 +209

+71

+60

LUMINANCE

SYNC

white

black black shoulder

sync bottom

a. Sources containing 7.5 IRE black level offset

(e.g. NTSC M).

+255

+199

+60

SAA7118

white

LUMINANCE

black shoulder = black

SYNC

b. Sources not containing black level offset.

sync bottom

MGD700

CVBS levels with default settings RAWG[7:0] = 64 and RAWO[7:0] = 128. Equation for modification of the raw data levels via bytes RAWG and RAWO:

CVBS

OUT

It should be noted that the resulting levels are limited to 1 to 254 in accordance with “

Int

RAWG

-----------------64

CVBS

nom

128–()× RAWO+=

ITU Recommendation 601/656”

Fig.20 CVBS (raw data) range for scaler input, data slicer and X-port output.

8.1.3 SYNCHRONIZATION The prefiltered luminance signal is fed to the synchronization stage. Its bandwidth is further reduced to 1 MHz in a

low-pass filter. The sync pulses are sliced and fed to the phase detectors where they are compared with the sub-divided clockfrequency.Theresultingoutputsignalisappliedtotheloopfiltertoaccumulateallphasedeviations.Internalsignals (e.g. HCL and HSY) are generated in accordance with analog front-end requirements. The loop filter signal drives an oscillator to generate the line frequency control signal LFCO; see Fig.21.

The detection of ‘pseudo syncs’ as part of the macrovision copy protection standard is also achieved within the synchronization circuit.

The result is reported as flag COPRO within the decoder status byte at subaddress 1FH.

2001 May 30 35

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Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive comb ﬁlter and component video input

8.1.4 CLOCK GENERATION CIRCUIT The internal CGC generates all clock signals required for

the video input processor. The internal signal LFCO is a digital-to-analog converted

signal provided by the horizontal PLL. It is the multiple of the line frequency:

6.75 MHz = 429 × fH (50 Hz), or

6.75 MHz = 432 × fH (60 Hz).

The LFCO signal is multiplied by a factor of 2 and 4 in the internalPLL circuit (including phase detector, loop filtering, VCO and frequency divider) to obtain the output clock signals. The rectangular output clocks have a 50% duty factor.

SAA7118

Table 3 Decoder clock frequencies

CLOCK FREQUENCY (MHz)

XTALO 24.576 or 32.110 LLC 27 LLC2 13.5 LLC4 (internal) 6.75 LLC8 (virtual) 3.375

LFCO

BAND PASS

FC = LLC/4

ZERO

CROSS

DETECTION

PHASE

DETECTION

LOOP

FILTER

DIVIDER

1/2

OSCILLATOR

DIVIDER

1/2

MHB330

LLC

LLC2

Fig.21 Block diagram of the clock generation circuit.

8.1.5 POWER-ON RESET AND CHIP ENABLE (CE) INPUT Amissing clock, insufficient digital or analog V

supplyvoltages (below 2.8 V) will start the reset sequence; all outputs

DDA0

are forced to 3-state (see Fig.22). The indicator output RES is LOW for approximately 128 LLC after the internal reset and can be applied to reset other circuits of the digital TV system.

It is possible to force a reset by pulling the Chip Enable pin (CE) to ground. After the rising edge of CE and sufficient power supply voltage, the outputs LLC, LLC2 and SDA return from 3-state to active, while the other signals have to be activated via programming.

2001 May 30 36

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Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive comb ﬁlter and component video input

POC V

DDA

ANALOG

CLOCK

PLL

LLC

POC

LOGIC

RESINT

POC V

DIGITAL

POC

DELAY

CLK0

SAA7118

DDD

RES

XTALO

LLCINT

RESINT

LLC

RES

(internal

reset)

POC = Power-on Control. CE = chip enable input. XTALO = crystal oscillator output. LLCINT = internal system clock. RESINT = internal reset. LLC = line-locked clock output. RES = reset output.

some ms

20 to 200 µs

PLL-delay

1 ms

896 LCC

digital delay

128 LCC

MHB331

Fig.22 Power-on control circuit.

2001 May 30 37

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Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive comb ﬁlter and component video input

8.2 Component video processing

handbook, full pagewidth

FSW

G/Y

B/C

R/C

RGB/Y-CB-C

MATRIX

bypass

FSW DELAY

DOWN

FOMATTER

and

BCS

and

COMPONENT

DELAY

BCS

CB-C

MIXER

Y-CB-CR decoder

to X-port

CB-C

MHB731

SAA7118

Fig.23 Component video processing.

8.2.1 RGB-TO-(Y-CB-CR) MATRIX The matrix converts the RGB signals from the analog-to-digital converters/downsamplers to the Y-CB-CRrepresentation.

The input and output word widths are 9 bits. The matrix has a gain factor of 1. The block provides a delay compensated bypass for component input signals.

The matrix is represented by the following equations:

Y = 0.299 × R + 0.587 × G = 0.114 × B C

= 0.5772 × (B − Y)

CR= 0.7296 × (R − Y)

2001 May 30 38

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Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive comb ﬁlter and component video input

8.2.2 DOWNFORMATTER The block mainly consists of 2 parts: the colour difference

signal downsampler and the Y-path. The colour difference signals are first passed through

low-pass filters which reduce alias effects due to the lower data rate. The ITU sampling scheme requires that both colour difference samples fit to the first Y sample of the current time slot. Thus the CRsignal is delayed by 1 clock before it is fed to the multiplexer. The switch signal defines the data multiplex phase at the output: a ‘0’ marks the first clock of a time slot, this is a CB sample. The output is fed through a register, so that the multiplexer runs with the opposite phase.

handbook, full pagewidth

LOW-PASS

SAA7118

The delay compensation for the Y signal already provides most of the registers required for a small high-pass filter. It can be used to compensate high frequency losses in the analog part. It provides 2 dB gain at 6.75 MHz.

The Y high-pass filter frequency response is shown in Fig.26. The DC gain of the filteris 1, so a limiter is required at the filter output. The current implementation clips at the maximum values of 0 and 511. The entire filter can be controlled by the I2C-bus bit CMFI in subaddress 29H.

(CR-CB)

OUT

switch

CMFI

delay compensation

HIGH-PASS

bypass

Fig.24 Downformatter block diagram.

OUT

MHB732

2001 May 30 39

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Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive comb ﬁlter and component video input

handbook, halfpage

(dB)

−1 024 8

SAA7118

MHB788

f (MHz)

Fig.25 CB-CR low-pass filter frequency response.

MHB787

f (MHz)

handbook, halfpage

(dB)

−20

−40

−60

024 8

Fig.26 Y high-pass filter frequency response.

2001 May 30 40

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Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive

SAA7118

comb ﬁlter and component video input

8.2.3 COMPONENT VIDEO BCS CONTROL The resulting Y and CB-CRsignals are fed to the Component BCS (CBCS) block, which contains the following functions:

• Chrominance saturation control by CSAT7 to CSAT0

• Luminance contrast and brightness control by CCON7 to CCON0 and CBRI7 to CBRI0

• Limiting Y-CB-CR or CVBS to the values 1 (minimum) and 254 (maximum) to fulfil

handbook, full pagewidth

+255 +235

+128

white

LUMINANCE 100%

+255 +240

+212 +212

+128

CB-COMPONENT

blue 100%

blue 75%

colourless

+255 +240

+128

“ITU Recommendation 601/656”

red 100% red 75%

colourless

CR-COMPONENT

yellow 75% yellow 100%

+44 +16

+16

+44

black

+16

a. Y output range. b. CB output range. c. CR output range.

“ITU Recommendation 601/656”

Equations for modification to the Y-CB-CR levels via CBCS control I2C-bus bytes CBRI, CCON and CSAT.

Luminance:

Chrominance:

It should be noted that the resulting levels are limited to 1 to 254 in accordance with

OUT

CBCR()

OUT

digital levels with default CBCS (decoder) settings CCON[7:0] = 44H, CBRI[7:0] = 80H and CSAT[7:0] = 40H.

CCON

Int

-----------------

Int

CSAT

--------------- 64

Y 128–()× CBRI+=

CBCR, 128–()× 128+=

“ITU Recommendation 601/656”

Fig.27 Components Y-CB-CR range.

cyan 75% cyan 100%

MHB730

2001 May 30 41

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Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive

SAA7118

comb ﬁlter and component video input

8.3 Decoder output formatter

The output interface block of thedecoder part contains the ITU 656formatterfor the expansion port data output XPD7 to XPD0 (for a detailed description see Section 9.5.1) and the control circuit for the signals needed for the internal paths to the scaler and data slicer part. It also controls the selection of the reference signals for the RT port (RTCO, RTS0 and RTS1) and the expansion port (XRH, XRV and XDQ).

The generation of the decoder data type control signals SET_RAW and SET VBI is also done within this block. These signals are decoded from the requested data type for the scaler input and/or the data slicer, selectable by the control registers LCR2 to LCR24 (see also Chapter 15; subaddresses 41H to 57H).

Table 4 Data formats at decoder output

DATA TYPE NUMBER DATA TYPE DECODER OUTPUT DATA FORMAT

0 teletext EuroWST, CCST raw 1 European closed caption raw 2 Video Programming Service (VPS) raw 3 wide screen signalling bits raw 4 US teletext (WST) raw 5 US closed caption (line 21) raw 6 video component signal, VBI region Y-CB-CR 4:2:2 7 CVBS data raw 8 teletext raw

9 VITC/EBU time codes (Europe) raw 10 VITC/SMPTE time codes (USA) raw 11 reserved raw 12 US NABTS raw 13 MOJI (Japanese) raw 14 Japanese format switch (L20/22) raw 15 video component signal, active video region Y-CB-CR 4:2:2

For each LCR value from 2 to 23 the data type can be programmed individually. LCR2 to LCR23 refer to line numbers. The selection in LCR24 values is valid for the rest of the corresponding field. The upper nibble contains the value for field 1 (odd), the lower nibble for field 2 (even). The relationship between LCR values and line numbers can be adjusted via VOFF8 to VOFF0, located in subaddresses 5BH (bit 4) and 5AH (bits 7 to 0) and FOFF subaddress 5BH (bit D7). The recommended values are VOFF[8:0] = 03H for 50 Hz sources (with FOFF = 0) and VOFF[8:0] = 06H for 60 Hz sources (with FOFF = 1), to accommodate line number conventions as used for PAL, SECAM and NTSC standards; see Tables 5 to 8.

2001 May 30 42

Page 43

2001 May 30 43

Table 5 Relationship of LCR to line numbers in 525 lines/60 Hz systems (part 1) Vertical line offset, VOFF[8:0] = 06H (subaddresses 5BH[4] and 5AH[7:0]); horizontal pixel offset, HOFF[10:0] = 347H (subaddresses 5BH[2:0] and

59H[7:0]); FOFF = 1 (subaddress 5BH[7])

Linenumber (1st ﬁeld)

Linenumber (2nd ﬁeld)

LCR 24 23456789

Table 6 Relationship of LCR to line numbers in 525 lines/60 Hz systems (part 2)

Vertical line offset, VOFF[8:0] = 06H (subaddresses 5BH[4] and 5AH[7:0]); horizontal pixel offset, HOFF[10:0] = 347H (subaddresses 5BH[2:0] and 59H[7:0]); FOFF = 1 (subaddress 5BH[7])

Linenumber (1st ﬁeld)

Linenumber (2nd ﬁeld)

LCR 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Table 7 Relationship of LCR to line numbers in 625 lines/50 Hz systems (part 1)

Vertical line offset, VOFF[8:0] = 03H (subaddresses 5BH[4] and 5AH[7:0]); horizontal pixel offset, HOFF[10:0] = 347H (subaddresses 5BH[2:0] and 59H[7:0]); FOFF = 0 (subaddress 5BH[7])

Linenumber (1st ﬁeld)

Linenumber (2nd ﬁeld)

LCR 24 2345

521 522 523 524 525 1 2 3 4 5 6 7 8 9

active video equalization pulses serration pulses equalization pulses

259 260 261 262 263 264 265 266 267 268 269 270 271 272

active video equalization pulses serration pulses equalization pulses

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

nominal VBI-lines F1 active video

273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288

nominal VBI-lines F2 active video

62162262362462512345

active video equalization pulses serration pulses equalization pulses

309 310 311 312 313 314 315 316 317 318

active video equalization pulses serration pulses equalization pulses

Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive

comb ﬁlter and component video input

Table 8 Relationship of LCR to line numbers in 625 lines/50 Hz systems (part 2) Vertical line offset, VOFF[8:0] = 03H (subaddresses 5BH[4] and 5AH[7:0]); horizontal pixel offset, HOFF[10:0] = 347H (subaddresses 5BH[2:0] and

59H[7:0]); FOFF = 0 (subaddress 5BH[7])

Linenumber (1st ﬁeld)

Linenumber (2nd ﬁeld)

LCR 67891011121314151617181920212223 24

678910111213141516171819202122232425

nominal VBI-lines F1 active video

319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338

nominal VBI-lines F2 active video

SAA7118

Page 44

Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive comb ﬁlter and component video input

625

ITU counting

single field counting

CVBS

HREF

F_ITU656

(1)

V123

VGATE

FID

ITU counting

single field counting

CVBS

623

622

310

309

VSTO[8:0] = 134H

310

309

310

309

624 311

311 311

312

312 312

313 313

(a) 1st field

31413152316331743185319

SAA7118

...

VSTA[8:0] = 15H

...

22 22

335

23 23

336

HREF

F_ITU656

(1)

V123

VGATE

FID

VSTO[8:0] = 134H

(b) 2nd field

(1) The inactive going edge of the V123 signal indicates whether the field is odd or even. If HREF is active during

the falling edge of V123, the field is ODD (field 1). If HREF is inactive during the falling edge of V123, the field is EVEN. The specific position of the slope is dependent on the internal processing delay and may change a few clock cycles from version to version.

The control signals listed above are available on pins RTS0, RTS1, XRH and XRV according to the following table:

NAME RTS0 RTS1 XRH XRV

HREF X X X − F_ITU656 −−−X V123 X X − X VGATE X X −− FID X X −−

For further information see Section 15.2: Tables 56, 57 and 58.

VSTA[8:0] = 15H

MHB540

Fig.28 Vertical timing diagram for 50 Hz/625 line systems.

2001 May 30 44

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Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive comb ﬁlter and component video input

ITU counting

single field counting

CVBS

HREF

F_ITU656

(1)

V123

VGATE

FID

ITU counting

single field counting

CVBS

525

262

VSTO[8:0] = 101H

263

262

263

262

2 2

264

265

266326742685269627072718272

(a) 1st field

SAA7118

9910

...

VSTA[8:0] = 011H

...

21 21

284

22 22

285

HREF

F_ITU656

(1)

V123

VGATE

FID

VSTO[8:0] = 101H

(b) 2nd field

(1) The inactive going edge of the V123 signal indicates whether the field is odd or even. If HREF is active during

The control signals listed above are available on pins RTS0, RTS1, XRH and XRV according to the following table:

NAME RTS0 RTS1 XRH XRV

HREF X X X − F_ITU656 −−−X V123 X X − X VGATE X X −− FID X X −−

For further information see Section 15.2: Tables 56, 57 and 58.

VSTA[8:0] = 011H

MHB541

Fig.29 Vertical timing diagram for 60 Hz/525 line systems.

2001 May 30 45

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Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive comb ﬁlter and component video input

CVBS input

processing delay ADC to expansion port:

140 × 1/LLC

expansion port

data output

HREF (50 Hz)

720 × 2/LLC

CREF

SAA7118

burst

sync clipped

12 × 2/LLC

144 × 2/LLC

CREF2

HS (50 Hz)

programming range

(step size: 8/LLC)

HREF (60 Hz)

CREF

CREF2

HS (60 Hz)

programming range

(step size: 8/LLC)

108

107

5 × 2/LLC

720 × 2/LLC

1 × 2/LLC

2 × 2/LLC

16 × 2/LLC

138 × 2/LLC

2 × 2/LLC

−107

−106

MHB542

The signals HREF, HS, CREF2 and CREF are available on pins RTS0 and/or RTS1 (see Section 15.2.19 Tables 56 and 57); their polarity can be inverted via RTP0 and/or RTP1.

The signals HREF and HS are available on pin XRH (see Section 15.2.20 Table 58).

Fig.30 Horizontal timing diagram (50/60 Hz).

2001 May 30 46

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Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive comb ﬁlter and component video input

8.4 Scaler

TheHigh Performance video Scaler (HPS) is based onthe system as implemented in the SAA7140, but with some aspects enhanced. Vertical upsampling is supported and the processing pipeline buffer capacity is enhanced, to allow more flexible video stream timing at the image port, discontinuoustransfers,and handshake. The internal data flow from block to block is discontinuous dynamically, due to the scaling process itself.

The flow is controlled by internal data valid and data request flags (internal handshake signalling) between the sub-blocks; therefore the entire scaler acts as a pipeline buffer. Depending on the actually programmed scaling parameters the effective buffer can exceed to an entire line. The access/bandwidth requirements to the VGA frame buffer are reduced significantly.

The high performance video scaler in the SAA7118 has the following major blocks:

• Acquisition control (horizontal and vertical timer) and task handling (the region/field/frame based processing)

• Prescaler, for horizontal down-scaling by an integer factor, combined with appropriate band limiting filters, especially anti-aliasing for CIF format

• Brightness,saturation, contrast control for scaled output data

• Line buffer, with asynchronous read and write, to support vertical up-scaling (e.g. for videophone application, converting 240 into 288 lines, Y-CB-C 4:2:2)

• Vertical scaling, with phase accurate Linear Phase Interpolation (LPI) for zoom and downscale, or phase accurate Accumulation Mode (ACM) for large downscaling ratios and better alias suppression

• Variable Phase Delay (VPD), operates as horizontal phase accurate interpolation for arbitrary non-integer scaling ratios, supporting conversion between square and rectangular pixel sampling

• Output formatter for scaled Y-CB-CR4:2:2, Y-CB-CR4:1:1 and Yonly (format also for raw data)

• FIFO, 32-bit wide, with 64 pixel capacity in Y-CB-C formats

• Output interface, 8 or 16-bit (only if extended by H-port) data pins wide, synchronous or asynchronous operation, with stream events on discretepins, or coded in the data stream.

SAA7118

The overall H and V zooming (HV_zoom) is restricted by the input/output data rate relationships. With a safety margin of 2% for running in and running out, the maximum HV_zoom is equal to:

0.98

-------------------------------------------------------------------------------------------------------------------------------------in_pixel in_lines× out_cycle_per_pix× T_out_clk×

For example:

1. Input from decoder: 50 Hz, 720 pixel, 288 lines, 16-bit data at 13.5 MHz data rate, 1 cycle per pixel; output: 8-bit data at 27 MHz, 2 cycles per pixel; the maximum HV_zoom is equal to:

0.98

2. Input from X-port: 60 Hz, 720 pixel, 240 lines, 8-bit data at 27 MHz data rate (ITU 656), 2 cycles per pixel; output via I + H-port: 16-bit data at 27 MHz clock, 1 cycle per pixel; the maximum HV_zoom is equal to:

0.98

The video scaler receives its input signal from the video decoder or from the expansion port (X-port). It gets 16-bit Y-CB-CR 4:2:2 input data at a continuous rate of

13.5 MHz from the decoder. Discontinuous data stream

can be accepted from the expansion port (X-port), normally 8-bit wide ITU 656 like Y-CB-CRdata, accompanied by a pixel qualifier on XDQ.

Theinputdatastreamissortedinto two data paths, one for luminance (or raw samples) and one for time multiplexed chrominance CBand CR samples. An Y-CB-CR 4:1:1 input format is converted to 4 :2:2 for the horizontal prescaling and vertical filter scaling operation.

Thescaler operation is defined by twoprogrammingpages A and B, representing two different tasks, that can be applied field alternating or to define two regions in a field (e.g.with different scaling range, factors and signal source during odd and even fields).

Each programming page contains control:

• For signal source selection and formats

• For task handling and trigger conditions

• For input and output acquisition window definition

• For H-prescaler, V-scaler and H-phase scaling.

Raw VBI-data is handled as specific input format and needs its own programming page (equals own task).

T_input_field T_v_blanking–

20 ms 24 64 µs×–

-------------------------------------------------------720 288× 2× 37 ns×

16.666 ms 22 64 µs×–

-------------------------------------------------------------720 240× 1× 37 ns×

1.18=×

2.34=×

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Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive comb ﬁlter and component video input

In VBI pass through operation the processing of prescaler and vertical scaling has to be set to no-processing, however, the horizontal fine scaling VPD can be activated. Upscaling (oversampling, zooming), free of frequency folding, up to a factor of 3.5 can be achieved, as required by some software data slicing algorithms.

These raw samples are transported through the image port as valid data and can be output as Y only format. The lines are framed by SAV and EAV codes.

8.4.1 ACQUISITION CONTROL AND TASK HANDLING (SUBADDRESSES 80H, 90H, 91H, 94H TO 9FH

AND C4H TO CFH)

The acquisition control receives horizontal and vertical synchronization signals from the decoder section or from the X-port. The acquisition window is generated via pixel and line counters at the appropriate places in the data path. From X-port only qualified pixels and lines (lines with qualified pixel) are counted.

The acquisition window parameters are as follows:

• Signal source selection regarding input video stream

and formats from the decoder, or from X-port (programming bits SCSRC[1:0] 91H[5:4] and FSC[2:0] 91H[2:0])

Remark: The input of raw VBI-data from the internal decoder should be controlled via the decoder output formatter and the LCR registers (see Section 8.3)

• Vertical offset defined in lines of the video source,

parameter YO[11:0] 99H[3:0] 98H[7:0]

• Vertical length defined in lines of the video source,

parameter YS[11:0] 9BH[3:0] 9AH[7:0]

• Vertical length defined in number of target lines, as a

result of vertical scaling, parameter YD[11:0] 9FH[3:0] 9EH[7:0]

• Horizontal offset defined in number of pixels of thevideo

source, parameter XO[11:0] 95H[3:0] 94H[7:0]

• Horizontal length defined in number of pixels of the

video source, parameter XS[11:0] 97H[3:0] 96H[7:0]

• Horizontal destination size, defined in target pixels after

fine scaling, parameter XD[11:0] 9DH[3:0] 9CH[7:0].

SAA7118

The task handling is controlled by subaddress 90H (see Section 8.4.1.2).

8.4.1.1 Input ﬁeld processing

The trigger event for the field sequence detection from external signals (X-port) are defined in subaddress 92H. From the X-port the state of the scalers H-reference signal at the time of the V-reference edge is taken as field sequence identifier FID. For example, if the falling edge of the XRV input signal is the reference and the state of XRH input is logic 0 at that time, the detected field ID is logic 0.

The bits XFDV[92H[7]] and XFDH[92H[6]] define the detection event and state of the flag from the X-port. For the default setting of XFDV and XFDH at ‘00’ the state of the H-input at the falling edge of the V-input is taken.

The scaler directly gets a corresponding field ID information from the SAA7118 decoder path.

The FID flag is used to determine whether the first or second field of a frame is going to be processed within the scaler and it is used as trigger condition for the task handling (see bits STRC[1:0] 90H[1:0]).

According to ITU 656, when FID is at logic 0 means first field of a frame. To ease the application, the polarities of the detection results on the X-port signals and the internal decoder ID can be changed via XFDH.

As the V-sync from the decoder path has a half line timing (due to the interlaced video signal), but the scaler processing only knows about full lines, during 1st fields fromthedecoder the line count of the scaler possibly shifts by one line, compared to the 2nd field. This can be compensated for by switching the V-trigger event, as defined by XDV0, to the opposite V-sync edge or by using theverticalscalers phase offsets. The vertical timing of the decoder can be seen in Figs 28 and 29.

As the H and V reference events inside the ITU 656 data stream (from X-port) and the real-time reference signals from the decoder path are processed differently, the trigger events for the input acquisition also have to be programmed differently.

The source start offset (XO11 to XO0 and YO11 to YO0) opens the acquisition window, and the target size (XD11 to XD0, YD11 to YD0) closes the window, but the window is cut vertically, if there are less output lines than expected. The trigger events for the pixel and line counts are the horizontal and vertical reference edges as defined in subaddress 92H.

2001 May 30 48

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Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive

SAA7118

comb ﬁlter and component video input

Table 9 Processing trigger and start

DESCRIPTION

Internal decoder: The processing triggers at the falling edge of the V123 pulse

(see Figs 28 (50 Hz) and 29 (60 Hz)), and starts earliest with the rising edge of the decoder HREF at line number:

4/7 (50/60 Hz, 1st field), respectively 3/6 (50/60 Hz, 2nd field) (decoder count) 0 1 0 2/5 (50/60 Hz, 1st field), respectively 2/5 (50/60 Hz, 2nd field) (decoder count) 0 0 0

External ITU 656 stream: The processing starts earliest with SAV at line number 23 (50 Hz system), respectively line 20 (60 Hz system) (according to ITU 656 count)

8.4.1.2 Task handling

The task handler controls the switching between the two programming register sets. It is controlled by subaddresses 90H and C0H. A task is enabled via the global control bits TEA[80H[4]] and TEB[80H[5]].

The handler is then triggered by events, which can be defined for each register set.

In the event of a programming error the task handling and the complete scaler can be reset to the initial states by setting the software reset bit SWRST[88H[5]] to logic 0. Especiallyif the programming registers, relatedacquisition windowand scale are reprogrammed whileatask is active, a software reset must be performed after programming.

Contrary to the disabling/enabling of a task, which is evaluated at the end of a running task, when SWRST is at logic 0 it sets the internal state machines directly to their idle states.

The start condition for the handler is defined by bits STRC[1:0]90H[1:0]andmeans:startimmediately,waitfor next V-sync, next FID at logic 0 or next FID at logic 1. The FID is evaluated, if the vertical and horizontal offsets are reached.

When RPTSK[90H[2]] is at logic 1 the actual running task is repeated (under the defined trigger conditions), before handing control over to the alternate task.

To support field rate reduction, the handler is also enabled to skip fields (bits FSKP[2:0] 90H[5:3]) before executing thetask.ATOGGLEflagisgenerated(usedforthecorrect output field processing), which changes state at the beginning of a task, every time a task is activated. Examples are given in Section 8.4.1.3.

Remarks:

• To activate a task the start condition must be

fulfilled and the acquisition window offsets must be reached.

For example, in case of ‘start immediately’, and two regions are defined for one field, the offset of the lower region must be greater than (offset + length) the upper region, if not, the actual counted H and V position at the end of the upper task is beyond the programmed offsets and the processing will ‘wait for next V’.

• Basicallythetrigger conditions are checked, when a task is activated. It is important to realize, that they are

not checked while a task is inactive. So you can not trigger to next logic 0 or logic 1 with overlapping offset and active video ranges between the tasks (e.g. task A STRC[2:0] = 2, YO[11:0] = 310 and task B STRC[2:0] = 3, YO[11:0] = 310 results in output field rate of50⁄3Hz).

• After power-on or software reset (via SWRST[88H[5]]) task B gets priority over task A.

8.4.1.3 Output ﬁeld processing

As a reference for the output field processing, two signals are available for the back-end hardware.

These signals are the input field ID from the scaler source and a TOOGLE flag, which shows that an active task is used an odd (1, 3, 5...) or even (2, 4, 6...) number of times. Usingasingleorbothtasks and reducing the field or frame rate with the task handling functionality, the TOGGLE information can be used, to reconstruct an interlaced scaled picture at a reduced frame rate. The TOGGLE flag isn’t synchronized to the input field detection, as it is only dependent on the interpretation of this information by the external hardware, whether the output of the scaler is processed correctly (see Section 8.4.3).

With OFIDC = 0, the scalers input field ID is available as output field ID on bit D6 of SAV and EAV, respectively on pin IGP0 (IGP1), if FID output is selected.

When OFIDC[90H[6]] = 1, the TOGGLE information is available as output field ID on bit D6 of SAV and EAV, respectively on pin IGP0 (IGP1), if FID output is selected.

XDV1

92H[5]

000

XDV0

92H[4]

XDH

92H[2]

2001 May 30 49

Page 50

2001 May 30 50

Additionally the bit D7 of SAV and EAV can be defined via CONLH[90H[7]]. CONLH[90H[7]] = 0 (default) sets D7 to logic 1, a logic 1 inverts the SAV/EAV bit D7. So it is possible to mark the output of the both tasks by different SAV/EAV codes. This bit can also be seen as ‘task flag’ on the pins IGP0 (IGP1), if TASK output is selected.

Table 10 Examples for ﬁeld processing

FIELD SEQUENCE FRAME/FIELD

SUBJECT

EXAMPLE 1

(1)

EXAMPLE 2

(2)(3)

EXAMPLE 3

(2)(4)(5)

EXAMPLE 4

(2)(4)(6)

1/1 1/2 2/1 1/1 1/2 2/1 2/2 1/1 1/2 2/1 2/2 3/1 3/2 1/1 1/2 2/1 2/2 3/1 3/2

Processed by task A A A B A B A B B A B B A B B A B B A State of detected

0100101010101 0 101 01

ITU 656 FID TOGGLE ﬂag 1 0 1 1 1 0 0 1 0 1 1 0 0 0 Bit D6 of SAV/EAV byte 0 1 0 0 1 0 1 1 0 1 1 0 0 0 Required sequence

conversion at the vertical

(8)

scaler

(9)

Output

↓

OOOOOOOOOOOOONOOONOOO

(7) (7)

↓

111 111

↓

(7) (7)

↓

Notes

1. Single task every field; OFIDC = 0; subaddress 90H at 40H; TEB[80H[5]] = 0.

2. Tasks are used to scale to different output windows, priority on task B after SWRST.

3. Both tasks at1⁄2frame rate; OFIDC = 0; subaddresses 90H at 43H and C0H at 42H.

4. In examples 3 and 4 the association between input FID and tasks can be flipped, dependent on which time the SWRST is de-asserted.

5. Task B at2⁄3frame rate constructed from neighbouring motion phases; task A at1⁄3frame rate of equidistant motion phases; OFIDC = 1; subaddresses 90H at 41H and C0H at 45H.

6. Task A and B at1⁄3frame rate of equidistant motion phases; OFIDC = 1; subaddresses 90H at 41H and C0H at 49H.

7. State of prior field.

8. It is assumed that input/output FID = 0 (= upper lines); UP = upper lines; LO = lower lines.

9. O = data output; NO = no output.

00 00

↓

Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive

comb ﬁlter and component video input

SAA7118

Page 51

Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive comb ﬁlter and component video input

8.4.2 HORIZONTAL SCALING Theoverall horizontal required scaling factorhasto be split

into a binary and a rational value according to the equation:

H-scale ratio

wherethe parameter of prescaler XPSC[5:0] = 1 to 63 and the parameter of VPD phase interpolation XSCY[12:0] = 300 to 8191 (0 to 299 are only theoretical values). For example,1⁄ binary factor is processed by the prescaler, the arbitrary non-integer ratio is achieved via the variable phase delay VPD circuitry, called horizontal fine scaling. The latter calculates horizontally interpolated new samples with a 6-bit phase accuracy, which relates to less than 1 ns jitter for regular sampling scheme. Prescaler and fine scaler create the horizontal scaler of the SAA7118.

Using the accumulation length function of the prescaler (XACL[5:0] A1H[5:0]), application and destination dependent (e.g. scale for display or for a compression machine), a compromise between visible bandwidth and alias suppression can be determined.

output pixel

-----------------------------input pixel

--------------------------- -

XPSC[5:0]

3.5

1024

×=

------------------------------XSCY[12:0]

is to split in1⁄4× 1.14286. The

SAA7118

• The bit XC2_1[A2H[3]], which defines the weighting of the incoming pixels during the averaging process:

– XC2_1 = 0 ⇒ 1 + 1...+ 1 +1 – XC2_1 = 1 ⇒ 1 + 2...+ 2 +1

Theprescaler creates a prescaledependentFIR low-pass, with up to (64 + 7) filter taps. The parameter XACL[5:0] can be used to vary the low-pass characteristic for a given integer prescale of1⁄

XPSC[5:0]

decide between signal bandwidth (sharpness impression) and alias.

Equation for XPSC[5:0] calculation is:

XPSC[5:0] lower integer of

where,

the range is 1 to 63 (value 0 is not allowed); Npix_in = number of input pixel, and Npix_out = number of desired output pixel over the

complete horizontal scaler.

The use of the prescaler results in a XACL[5:0] and XC2_1 dependent gain amplification. The amplification

can be calculated according to the equation: DC gain = [(XACL[5:0] − XC2_1) + 1] × (XC2_1 + 1)

. The user can therefore

Npix_in

----------------------Npix_out

8.4.2.1 Horizontal prescaler (subaddresses A0H to A7H and D0H to D7H)

The prescaling function consists of an FIR anti-alias filter stage and an integer prescaler, which creates an adaptive prescale dependent low-pass filter to balance sharpness and aliasing effects.

The FIR prefilter stage implements different low-pass characteristics to reduce alias for downscales in the range of 1 to1⁄2. A CIF optimized filter is built-in, which reduces artefacts for CIF output formats (to be used in combination with the prescaler set to1⁄2scale); see Table 11.

The function of the prescaler is defined by:

• An integer prescaling ratio XPSC[5:0] A0H[5:0] (equals

1 to 63), which covers the integer downscale range 1 to1⁄

• An averaging sequence length XACL[5:0] A1H[5:0]

(equals 0 to 63); range 1 to 64

• A DC gain renormalization XDCG[2:0] A2H[2:0];

1 down to1⁄

128

It is recommended to use sequence lengths and weights,

which results in a 2

DC gain amplification, as these

amplitudes can be renormalized by the XDCG[2:0] controlled shifter of the prescaler.

The renormalization range of XDCG[2:0] is 1, to1⁄

128

------

⁄2... down

Other amplifications have to be normalized by using the following BCS control circuitry. In these cases the prescaler has to be set to an overall gain of ≤1, e.g. for an accumulation sequence of ‘1 + 1 + 1’ (XACL[5:0] = 2 and XC2_1 = 0),XDCG[2:0] must be setto‘010’, this equals1⁄ and the BCS has to amplify the signal to4⁄3 (SATN[7:0] and CONT[7:0] value = lower integer of4⁄3× 64).

The use of XACL[5:0] is XPSC[5:0] dependent. XACL[5:0] must be <2 × XPSC[5:0].

XACL[5:0] can be used to find a compromise between bandwidth (sharpness) and alias effects.

2001 May 30 51

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Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive comb ﬁlter and component video input

Remark: Due to bandwidth considerations XPSC[5:0] and XACL[5:0] can be chosen different to the previously mentioned equations or Table 12, as the H-phase scaling is able to scale in the range from zooming up by factor 3 to downscale by a factor of

Figs 33 and 34 show some resulting frequency characteristics of the prescaler.

Table 12 shows the recommended prescaler programming. Other programmings, other than given in Table 12, may result in better alias suppression, but the resulting DC gain amplification needs to be compensated by the BCS control, according to the equation:

CONT[7:0] SATN[7:0] lower integer of

Where:

XDCG[2:0]

2 DC gain = (XC2_1 + 1) × XACL[5:0] + (1 − XC2_1).

≥ DC gain

1024

⁄

8191

XDCG[2:0]

---------------------------------DC gain 64×

SAA7118

For example, if XACL[5:0] = 5, XC2_1 = 1, then the DC gain = 10 and the required XDCG[2:0] = 4.

The horizontal source acquisition timing and the prescalingratio is identical for both the luminance path and chrominance path, but the FIR filter settings can be defined differently in the two channels.

Fade-in and fade-out of the filters is achieved by copying an original source sample each as first and last pixel after prescaling.

Figs 31 and 32 show the frequency characteristics of the selectable FIR filters.

Table 11 FIR preﬁlter functions

PFUV[1:0] A2H[7:6]

PFY[1:0] A2H[5:4]

00 bypassed bypassed 01 121 121 10 −1 1 1.75 4.5 1.75 1 −1 381083 11 12221 12221

LUMINANCE FILTER COEFFICIENTS CHROMINANCE COEFFICIENTS

2001 May 30 52

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Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive comb ﬁlter and component video input

(dB)

−3

−6

−9

−12

(1) PFY[1:0] = 01. (2) PFY[1:0] = 10. (3) PFY[1:0] = 11.

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

(3)

SAA7118

MHB543

(1)

(2)

f_sig/f_clock

(1) PFUV[1:0] = 01. (2) PFUV[1:0] = 10. (3) PFUV[1:0] = 11.

Fig.31 Luminance prefilter characteristic.

(dB)

−3

−6

−9

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

0 0.025 0.05 0.075 0.1 0.125 0.15 0.175 0.2 0.225 0.25

(1)

(2)

(3)

f_sig/f_clock

MHB544

Fig.32 Chrominance prefilter characteristic.

2001 May 30 53

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Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive comb ﬁlter and component video input

(dB)

−3

−6

−9

−12

−15

−18

−21

−24

−27

−30

−33

XC2_1 = 0; Zero’s at

×=

------------------------ XACL 1+

with XACL = (1), (2), (3), (4) or (5)

−36

−39

−42

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

SAA7118

MHB545

(1)(2)(3)(4)(5)

f_sig/f_clock

Fig.33 Examples for prescaler filter characteristics: effect of increasing XACL[5:0].

(1) XC2_1 = 0 and XACL[5:0] = 1. (2) XC2_1 = 1 and XACL[5:0] = 2. (3) XC2_1 = 0 and XACL[5:0] = 3. (4) XC2_1 = 1 and XACL[5:0] = 4. (5) XC2_1 = 0 and XACL[5:0] = 7. (6) XC2_1 = 1 and XACL[5:0] = 8.

(dB)

−3

−6

−9

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

(1)

(2)

(3)(4)(5)(6)

3 dB at 0.25

6 dB at 0.33

f_sig/f_clock

MHB546

Fig.34 Examples for prescaler filter characteristics: setting XC2_1 =1.

2001 May 30 54

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Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive

SAA7118

comb ﬁlter and component video input

Table 12 XACL[5:0] example of usage

RECOMMENDED VALUES

PRESCALE

RATIO

110 0 0 0 0 0 0to2

⁄

XPSC

[5:0]

FOR LOWER BANDWIDTH

REQUIREMENTS

FOR HIGHER BANDWIDTH

REQUIREMENTS

PREFILTER

PFY (PB-PR)

XACL[5:0] XC2_1 XDCG[2:0] XACL[5:0] XC2_1 XDCG[2:0]

2 2 1 2 1 0 1 0 to 2

(1 2 1) ×1⁄

(1)

(1 1) ×1⁄

(1)

34 1 3 3 0 2 2

(12221)×1⁄

(1)

(1 1 1 1) ×1⁄

(1)

47 0 3 4 1 3 2

(11111111)×1⁄

(1)

(12221)×1⁄

(1)

58 1 4 7 0 3 2

(122222221)×1⁄

(1)

(11111111)×1⁄

(1)

68 1 4 7 0 3 3

(122222221)×1⁄

(1)

(11111111)×1⁄

(1)

78 1 4 7 0 3 3

(122222221)×1⁄

(1)

(11111111)×1⁄

(1)

815 0 4 8 1 4 3

(1111111111111111)×1⁄

(1)

(122222221)×1⁄

(1)

915 0 4 8 1 4 3

(1111111111111111)×1⁄

(1)

(122222221)×1⁄

(1)

10 16 1 5 8 1 4 3

(12222222222222221)×1⁄

(1)

(122222221)×1⁄

(1)

13 16 1 5 16 1 5 3 15 31 0 5 16 1 5 3 16 32 1 6 16 1 5 3 19 32 1 6 32 1 6 3 31 32 1 6 32 1 6 3 32 63 1 7 32 1 6 3 35 63 1 7 63 1 7 3

FIR

Note

1. Resulting FIR function.

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Philips Semiconductors Preliminary speciﬁcation

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8.4.2.2 Horizontal ﬁne scaling (variable phase delay ﬁlter; subaddresses A8H to AFH and D8H to DFH)

Thehorizontal fine scaling (VPD) should operateatscaling ratios between1⁄2and 2 (0.8 and 1.6), but can also be used for direct scaling in the range from1⁄ (theoretical) zoom 3.5 (restriction due to the internal data path architecture), without prescaler.

In combination with the prescaler a compromise between sharpness impression and alias can be found, which is a signal source and application dependent.

For the luminance channel a filter structure with 10 taps is implemented, and for the chrominance a filter with 4 taps.

Luminance and chrominance scale increments (XSCY[12:0] A9H[4:0]A8H[7:0] and XSCC[12:0] ADH[4:0]ACH[7:0]) are defined independently, but must be set in a 2 : 1 relationship in the actual data path implementation. The phase offsets XPHY[7:0] AAH[7:0] and XPHC[7:0] AEH[7:0] can be used to shift the sample phases slightly. XPHY[7:0] and XPHC[7:0] covers the phase offset range 7.999T to1⁄32T. The phase offsets should also be programmed in a 2 : 1 ratio.

The underlying phase controlling DTO has a 13-bit resolution.

According to the equations

Npix_in

XSCY[12:0] 1024

XSCC[12:0]

the VPD covers the scale range from 0.125 to zoom 3.5. VPD acts equivalent to a polyphase filter with 64 possible phases. In combination with the prescaler, it is possible to get very accurate samples from a highly anti-aliased integer downscaled input picture.

--------------------------- XPSC[5:0]

XSCY[12:0]

------------------------------2

×=

----------------------Npix_out

7.999

and

SAA7118

8.4.3.1 Line FIFO buffer(subaddresses 91H, B4H and C1H, E4H)

The line FIFO buffer is a dual ported RAM structure for 768 pixels, with asynchronous write and read access. The line buffer can be used for various functions, but not all functions may be available simultaneously.

Theline buffer can buffer acompleteunscaled active video line or more than one shorter lines (only for non-mirror mode), for selective repetition for vertical zoom-up.

For zooming up 240 lines to 288 lines e.g., every fourth line is requested (read) twice from the vertical scaling circuitry for calculation.

For conversion of a 4 : 2 : 0 or 4:1:0 input sampling scheme (MPEG, video phone, Indeo YUV-9) to ITU like sampling scheme 4:2:2, the chrominance line buffer is read twice or four times, before being refilled again by the source. It has to be preserved by means of the input acquisition window definition, so that the processing starts with a line containing luminance and chrominance information for 4:2:0 and 4:1:0 input. The bits FSC[2:1] 91H[2:1] define the distance between the Y/C lines. In the event of 4:2:2and4:1:1FSC2and FSC1 have to be set to ‘00’.

The line buffer can also be used for mirroring, i.e. for flippingthe image left to right, for the vanity picture in video phoneapplications (bit YMIR[B4H[4]]). Inmirrormode only one active prescaled line can be held in the FIFO at a time.

The line buffer can be utilized as an excessive pipeline buffer for discontinuous and variable rate transfer conditions at the expansion port or image port.

8.4.3 VERTICAL SCALING The vertical scaler of the SAA7118 consists of a line FIFO

bufferforlinerepetition and the vertical scaler block, which implements the vertical scaling on the input data stream in 2 different operational modes from theoretical zoom by 64 down to icon size1⁄64. The vertical scaler is located between the BCS and horizontal fine scaler, so that the BCScan be used to compensate theDC gainamplification of the ACM mode (see Section 8.4.3.2) as the internal RAMs are only 8-bit wide.

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Philips Semiconductors Preliminary speciﬁcation

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8.4.3.2 Vertical scaler (subaddresses B0H to BFH and E0H to EFH)

Vertical scaling of any ratio from 64 (theoretical zoom) to1⁄63 (icon) can be applied.

The vertical scaling block consists of another line delay, and the vertical filter structure, that can operate in two different modes; Linear Phase Interpolation (LPI) and accumulation (ACM) mode. These are controlled by YMODE[B4H[0]]:

• LPI mode: In LPI mode (YMODE = 0) two neighbouring

lines of the source video stream are added together, but weighted by factors corresponding to the vertical position (phase) of the target output line relative to the source lines. This linear interpolation has a 6-bit phase resolution, which equals 64 intra line phases. It interpolates between two consecutive input lines only. LPI mode should be applied for scaling ratios around 1 (down to1⁄2), it must be applied for vertical zooming.

• ACM mode: The vertical Accumulation (ACM) mode

(YMODE = 1) represents a vertical averaging window over multiple lines, sliding over the field. This mode also generates phase correct output lines. The averaging windowlengthcorrespondstothescalingratio,resulting in an adaptive vertical low-pass effect, to greatly reduce aliasing artefacts. ACM can be applied for downscales only from ratio 1 down to1⁄64. ACM results in a scale dependent DC gain amplification, which has to be precorrected by the BCS control of the scaler part.

The phase and scale controlling DTO calculates in 16-bit resolution, controlled by parameters YSCY[15:0] B1H[7:0] B0H[7:0]and YSCC[15:0]B3H[7:0]B2H[7:0], continuously over the entire filed. A start offset can be applied to the phase processing by means of the parameters YPY3[7:0] to YPY0[7:0] in BFH[7:0] to BCH[7:0] and YPC3[7:0] to YPC0[7:0]inBBH[7:0] to B8H[7:0]. The start phase covers the range of

By programming appropriate, opposite, vertical start phase values (subaddresses B8H to BFH and E8H to EFH)depending on odd/even field ID of the source video stream and A/B-page cycle, frame ID conversion andfieldrateconversionaresupported(i.e.de-interlacing, re-interlacing).

255

⁄32to1⁄32 lines offset.

SAA7118

Remark: The vertical start phase, as well as scaling ratio are defined independently for luminance and chrominance channel, but must be set to the same values in the actual implementation for accurate 4:2:2 output processing.

The vertical processing communicates on its input side with the line FIFO buffer. The scale related equations are:

• Scaling increment calculation for ACM and LPI mode, downscale and zoom: YSCY[15:0] and YSCC[15:0]

------------------------Nline_out

1024

Nline_in

64×

, or

64×

lower integer of= 1024

• BCS value to compensate DC gain in ACM mode (contrast and saturation have to be set): CONT[7:0] A5H[7:0] respectively SATN[7:0] A6H[7:0]

lower integer of

 

Nline_out



-------------------------



Nline_in



-------------------------------



YSCY[15:0]

8.4.3.3 Use of the vertical phase offsets

Asdescribed in Section 8.4.1.3, thescalerprocessing may run randomly over the interlaced input sequence. Additionally the interpretation and timing between ITU 656 field ID and real-time detection by means of the state of H-sync at the falling edge of V-sync may result in different field ID interpretation.

A vertically scaled interlaced output also gets a larger vertical sampling phase error, if the interlaced input fields are processed, without regard to the actual scale at the starting point of operation (see Fig.35).

For correct interlaced processing the vertical scaler must beused with respect to the interlace propertiesof the input signal and, if required, for conversion of the field sequences.

Four events should be considered, they are illustrated in Fig.36.

Figs 35 and 36 and Tables 13 and 14 describe the use of the offsets.

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Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive comb ﬁlter and component video input

unscaled input

ﬁeld 1 ﬁeld 2 ﬁeld 1 ﬁeld 2 ﬁeld 1 ﬁeld 2

scale dependent start offset

scaled output,

no phase offset

mismatched vertical line distances

SAA7118

scaled output,

with phase offset

correct scale dependent position

Fig.35 Basic problem of interlaced vertical scaling (example: downscale3⁄5).

ﬁeld 1 ﬁeld 2 upper

Offset

1024

32 1 line shift===

------------ 32

1024

input line shift 16==

-- 2

input line shift 16==

-- -

input line shift

-- -

------------ - 32

32 1 line shift===

-- 2

MHB547

ﬁeld 1 ﬁeld 2

lower

scale increment+

YSCY[15:0]

------------------------------ 64

case UP-UP

scale increment

-- 2

D = no offset = 0

input line shift

-- - 2

scale increment

16+==

-- - 2

D = no offset = 0

case LO-LO

ﬁeld 1 ﬁeld 2

case UP-LO

YSCY[15:0]

------------------------------ 64

scale increment+

-- - 2

YSCY[15:0]

------------------------------ - 64

case LO-UP

MHB548

YSCY[15:0]

------------------------------ - 64

16+==

Fig.36 Derivation of the phase related equations (example: interlace vertical scaling down to3⁄5, with field

conversion).

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Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive comb ﬁlter and component video input

In Tables 13 and 14 PHO is a usable common phase offset.

It should be noted that the equations of Fig.36 produce an interpolated output, also for the unscaled case, as the geometrical reference position for all conversions is the position of the first line of the lower field (see Table 13).

If there is no need for UP-LO and LO-UP conversion and the input field ID is the reference for the back-end operation, then it is UP-LO = UP-UP and LO-UP = LO-LO and the1⁄2line phase shift (PHO + 16) that can be skipped. This case is listed in Table 14.

The SAA7118 supports 4 phase offset registers per task and component (luminance and chrominance). The value of 20H represents a phase shift of one line.

Table 13 Examples for vertical phase offset usage: global equations

INPUT FIELD UNDER

PROCESSING

Upper input lines upper output lines UP-UP PHO + 16 Upper input lines lower output lines UP-LO

Lower input lines upper output lines LO-UP PHO Lower input lines lower output lines LO-LO

OUTPUT FIELD

INTERPRETATION

USED ABBREVIATION

The registers are assigned to the following events; e.g. subaddresses B8H to BBH:

• B8H: 00 = input field ID 0, task status bit 0 (toggle status, see Section 8.4.1.3)

• B9H: 01 = input field ID 0, task status bit 1

• BAH: 10 = input field ID 1, task status bit 0

• BBH: 11 = input field ID 1, task status bit 1.

Depending on the input signal (interlaced or non-interlaced) and the task processing 50 Hz or field reduced processing with one or two tasks (see examples in Section 8.4.1.3), other combinations may also be possible, but the basic equations are the same.

EQUATION FOR PHASE OFFSET

CALCULATION (DECIMAL VALUES)

PHO

YSCY[15:0]

------------------------------64

YSCY[15:0]

------------------------------64

SAA7118

16++

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Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive comb ﬁlter and component video input

Table 14 Vertical phase offset usage; assignment of the phase offsets

DETECTED INPUT

FIELD ID

0 = upper lines 0 YPY0[7:0] and

0 = upper lines 1 YPY1[7:0] and

1 = lower lines 0 YPY2[7:0] and

1 = lower lines 1 YPY3[7:0] and

TASK STATUS BIT

VERTICAL PHASE

OFFSET

YPC0[7:0]

YPC1[7:0]

YPC2[7:0]

YPC3[7:0]

SAA7118

CASE EQUATION TO BE USED

(1)

case 1 case 2 case 3 case 1 UP-UP (PHO) case 2 UP-LO case 3 UP-UP case 1

case 2 LO-UP case 3 LO-LO case 1

case 2 LO-LO case 3 LO-UP

UP-UP (PHO)

(2)

UP-UP

(3)

UP-LO

LO-LO



PHO





PHO



YSCY[15:0]

------------------------------64

YSCY[15:0]

------------------------------64

16–+

Notes

1. Case 1: OFIDC[90H[6]] = 0; scaler input field ID as output ID; back-end interprets output field ID at logic 0 as upper output lines.

2. Case 2: OFIDC[90H[6]] = 1; task status bit as output ID; back-end interprets output field ID at logic 0 as upper output lines.

3. Case 3: OFIDC[90H[6]] = 1; task status bit as output ID; back-end interprets output field ID at logic 1 as upper output lines.

8.5 VBI-data decoder and capture

(subaddresses 40H to 7FH)

The SAA7118 contains a versatile VBI-data decoder. The implementation and programming model is in

accordance with the VBI-data slicer built into the multimedia video data acquisition circuit SAA5284.

The circuitry recovers the actual clock phase during the clock run-in period, slices the data bits with the selected data rate, and groups them into bytes. The result is buffered into a dedicated VBI-data FIFO with a capacity of 2 × 56 bytes (2 × 14 Dwords). The clock frequency, signal source, field frequency and accepted error count must be defined in subaddress 40H.

The supported VBI-data standards are shown in Table 15. For lines 2 to 24 of a field, per VBI line, 1 of 16 standards

canbe selected (LCR24_[7:0] to LCR2_[7:0]in57H[7:0] to 41H[7:0]: 23 × 2 × 4 bit programming bits).

The definition for line 24 is valid for the rest of the corresponding field, normally no text data (video data) should be selected there (LCR24_[7:0] = FFH) to stop the activity of the VBI-data slicer during active video.

To adjust the slicers processing to the input signal source, there are offsets in the horizontal and vertical direction available: parameters HOFF[10:0] 5BH[2:0] 59H[7:0], VOFF[8:0] 5BH[4] 5AH[7:0] and FOFF[5BH[7]]).

Contrary to the scalers counting, the slicers offsets define the position of the H and V trigger events related to the processed video field. The trigger events are the falling edge of HREF and the falling edge of V123 from the decoder processing part.

The relationship of these programming values to the input signal and the recommended values can be seen in Tables 5 to 8.

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Multistandard video decoder with adaptive

SAA7118

comb ﬁlter and component video input

Table 15 Data types supported by the data slicer block

DT[3:0]

62H[3:0]

0000 teletext EuroWST, CCST 6.9375 27H WST625 always 0001 European closed caption 0.500 001 CC625 0010 VPS 5 9951H VPS 0011 wide screen signalling bits 5 1E3C1FH WSS 0100 US teletext (WST) 5.7272 27H WST525 always 0101 US closed caption (line 21) 0.503 001 CC525 0110 (video data selected) 5 none disable 0111 (raw data selected) 5 none disable 1000 teletext 6.9375 programmable general text optional 1001 VITC/EBU time codes (Europe) 1.8125 programmable VITC625 1010 VITC/SMPTE time codes (USA) 1.7898 programmable VITC525 1011 reserved 1100 US NABTS 5.7272 programmable NABTS optional 1101 MOJI (Japanese) 5.7272 programmable (A7H) Japtext 1110 Japanese format switch (L20/22) 5 programmable open 1111 no sliced data transmitted

STANDARD TYPE

(video data selected)

DATA RATE

(Mbits/s)

5 none disable

FRAMING CODE

WINDOW

HAM

CHECK

8.6 Image port output formatter

(subaddresses 84H to 87H)

The output interface consists of a FIFO for video and for sliced text data, an arbitration circuit, which controls the mixed transfer of video and sliced text data over the I-port and a decoding and multiplexing unit, which generates the 8 or 16-bit wide output data stream and the accompanied reference and supporting information.

The clock for the output interface can be derived from an internal clock, decoder, expansion port, or an externally providedclock which is appropriate fore.g.VGA and frame buffer.The clock can be up to33 MHz.Thescaler provides the following video related timing reference events (signals), which are available on pins as defined by subaddresses 84H and 85H:

• Output field ID

• Start and end of vertical active video range

• Start and end of active video line

• Data qualifier or gated clock

• Actually activated programming page (if CONLH is

used)

• Threshold controlled FIFO filling flags (empty, full, filled)

• Sliced data marker.

The disconnected data stream at the scaler output is accompanied by a data valid flag (or data qualifier), or is transported via a gated clock. Clock cycles with invalid data on the I-port data bus (including the HPD pins in 16-bit output mode) are marked with code 00H.

The output interface also arbitrates the transfer between scaled video data and sliced text data over the I-port output.

The bits VITX1 and VITX0 (subaddress 86H) are used to control the arbitration.

Asafurtheroperation the serialization of the internal 32-bit Dwords to 8-bit or optional 16-bit output, as well as the insertion of the extended ITU 656 codes (SAV/EAV for video data, ANC or SAV/EAV codes for sliced text data) are done here.

For handshake with the VGA controller, or other memory or bus interface circuitry, programmable FIFO flags are provided (see Section 8.6.2).

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Multistandard video decoder with adaptive

SAA7118

comb ﬁlter and component video input

8.6.1 SCALER OUTPUT FORMATTER

(SUBADDRESSES 93H AND C3H)

The output formatter organizes the packing into the output FIFO. The following formats are available: Y-CB-CR4:2:2, Y-CB-CR4:1:1, Y-CB-CR4:2:0, Y-CB-CR4:1:0, Yonly (e.g. for raw samples). The formatting is controlled by FSI[2:0] 93H[2:0], FOI[1:0] 93H[4:3] and FYSK[93H[5]].

The data formats are defined on Dwords,or multiples, and are similar to the video formats as recommended for PCI multimedia applications (compares to SAA7146A), but planar formats are not supported.

Table 16 Byte stream for different output formats

OUTPUT FORMAT BYTE SEQUENCE FOR 8-BIT OUTPUT MODES

Y-CB-CR4:2:2 CB0Y0CR0Y1CB2Y2CR2Y3CB4Y4CR4Y5 CB6Y6 Y-CB-CR4:1:1 CB0Y0CR0Y1CB4Y2CR4Y3Y4 Y5Y6 Y7 CB8Y8 Yonly Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13

FSI[2:0] defines the horizontal packing of the data, FOI[1:0] defines how many Y only lines are expected, before a Y/C line will be formatted. If FYSK is set to logic 0 preceding Y only lines will be skipped, and the output will always start with a Y/C line.

Additionallythe output formatter limits the amplitude range of the video data (controlled by ILLV[85H[5]]); see Table 18.

Table 17 Explanation to Table 16

NAME EXPLANATION

CBnC Yn Y (luminance) component, pixel number n = 0, 1, 2, 3 to 719 CRnC

Table 18 Limiting range on I-port

LIMIT STEP

ILLV[85H[5]]

0 1 to 254 01 to FE 00 FF 1 8 to 247 08 to F7 00 to 07 F8 to FF

8.6.2 VIDEO FIFO (SUBADDRESS 86H)

The video FIFO at the scaler output contains 32 Dwords. That corresponds to 64 pixels in 16-bit Y-CB-CR 4:2:2 format.Butastheentirescaler can act as a pipeline buffer, the actual available buffer capacity for the image port is much higher, and can exceed beyond a video line.

The image port, and the video FIFO, can operate with the video source clock (synchronous mode) or with an externally provided clock (asynchronous and burst mode), as appropriate for the VGA controller or attached frame buffer.

The video FIFO provides 4 internal flags, reporting to what extent the FIFO is actually filled.

(B − Y) colour difference component, pixel number n = 0, 2, 4 to 718

(R − Y) colour difference component, pixel number n = 0, 2, 4 to 718

VALID RANGE SUPPRESSED CODES (HEXADECIMAL VALUE)

DECIMAL VALUE HEXADECIMAL VALUE LOWER RANGE UPPER RANGE

These are:

• The FIFO Almost Empty (FAE) flag

• The FIFO Combined Flag (FCF) or FIFO filled, which is

set at almost full level and reset, with hysteresis, only after the level crosses below the almost empty mark

• The FIFO Almost Full (FAF) flag

• The FIFO Overflow (FOVL) flag.

The trigger levels for FAE and FAF are programmable by FFL[1:0] 86H[3:2] (16, 24, 28, full) and FEL[1:0] 86H[1:0] (16, 8, 4, empty).

The state of this flag can be seen on the pins IGP0 or IGP1. The pin mapping is defined by subaddresses 84H and 85H (see Section 9.6).

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Multistandard video decoder with adaptive comb ﬁlter and component video input

8.6.3 TEXT FIFO

The data of the terminal VBI-data slicer is collected in the text FIFO before the transmission over the I-port is requested (normally before the video window starts). It is partitioned into two FIFO sections. A complete line is filled into the FIFO before a data transfer is requested. So normally, one line of text data is ready for transfer, while the next text line is collected. Thus sliced text data is delivered as a block of qualified data, without any qualification gaps in the byte stream of the I-port.

The decoded VBI-data is collected in the dedicated VBI-data FIFO. After capture of a line is completed, the FIFO can be streamed through the image port, preceded by a header, telling line number and standard.

The VBI-data period can be signalled via the sliced data flagon pin IGP0 or IGP1. The decoded VBI-datais lead by the ITU ancillary data header (DID[5:0] 5DH[5:0] at value <3EH) or by SAV/EAV codes selectable by DID[5:0] at value 3EH or 3FH. Pin IGP0 or IGP1 is set, if the first byte of the ANC header is valid on the I-port bus. It is reset if an SAV occurs. So it may frame multiple lines of text data output, in case video processing starts with a distance of several video lines to the region of text data. Valid sliced data from the text FIFO is availableon the I-port as long as the IGP0 or IGP1 flag is set and the data qualifier is active on pin IDQ.

The decoded VBI-data are presented in two different data formats, controlled by bit RECODE.

• RECODE = 1: values 00H and FFH will be recoded to

even parity values 03H and FCH

• RECODE = 0: values 00H and FFH may occur in the

data stream as detected.

SAA7118

Ifthevideo data is transferred without any interrupt and the video FIFO does not need to buffer any output pixel, the text data is inserted after the end of a scaled video line, normally during the blanking interval of the video.

8.6.5 DATA STREAM CODING AND REFERENCE SIGNAL

GENERATION (SUBADDRESSES 84H, 85H AND 93H)

As H and V reference signals are logic 1, active gate signalsaregenerated,whichframethe transfer of the valid output data. As an alternative to the gates, H and V trigger pulses are generated on the rising edges of the gates.

Dueto the dynamic FIFO behaviour of the completescaler path, the output signal timing has no fixed timing relationship to the real-time input video stream. So fixed propagation delays, in terms of clock cycles, related to the analog input cannot be defined.

The data stream is accompanied by a data qualifier. Additionally invalid data cycles are marked with code 00H.

If ITU 656 like codes are not wanted, they can be suppressed in the output stream.

As a further option, it is possible to provide the scaler with an external gating signal on pin ITRDY. Thereby making it possible to hold the data output for a certain time and to get valid output data in bursts of a guaranteed length.

The sketched reference signals and events can be mapped to the I-port output pins IDQ, IGPH, IGPV, IGP0 and IGP1. For flexible use the polarities of all the outputs can be modified. The default polarity for the qualifier and reference signals is logic 1 (active).

Table 19shows the relevant and supported SAV and EAV coding.

8.6.4 VIDEO AND TEXT ARBITRATION (SUBADDRESS 86H)

Slicedtext data and scaled video data are transferredover the same bus, the I-port. The mixed transfer is controlled by an arbitration circuit.

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2001 May 30 64

Table 19 SAV/EAV codes on I-port

EVENT DESCRIPTION

FIELD ID = 0 FIELD ID = 1 FIELD ID = 0 FIELD ID = 1

Next pixel is FIRST pixel of any active line

Previous pixel was LAST pixel of any active line, but not the last

Next pixel is FIRST pixel of any V-blanking line

Previous pixel was LAST pixel of the last active line or of any V-blanking line

No valid data, don’t capture and don’t increment pointer

Notes

1. The leading byte sequence is: FFH-00H-00H.

2. The MSB of the SAV/EAV code byte is controlled by: a) Scaler output data: task A ⇒ MSB = CONLH[90H[7]]; task B ⇒ MSB = CONLH[C0H[7]]. b) VBI-data slicer output data: DID[5:0] 5DH[5:0] = 3EH ⇒ MSB = 1; DID[5:0] 5DH[5:0] = 3FH ⇒ MSB = 0.

SAV/EAV CODES ON I-PORT

(2)

OF SAV/EAV BYTE = 0 MSB

(1)

(HEX)

(2)

OF SAV/EAV BYTE = 1

COMMENTMSB

0E 49 80 C7 HREF = active;

VREF = active

13 54 9D DA HREF = inactive;

VREF = active

25 62 AB EC HREF = active;

VREF = inactive

38 7F B6 F1 HREF = inactive;

VREF = inactive

00 IDQ pin inactive

Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive

comb ﬁlter and component video input

invalid data

end of raw VBI line

00 00 FF 00 00 SAV SDID DC IDI1 IDI2 D

...

FF 00 00 EAV

ANC header active for DID (subaddress 5DH) <3EH

timing reference code

ANC header internal header sliced data

00 FF FF DID SDID DC IDI1 IDI2 D

sliced data invalid dataand filling data

1_3D1_4D2_1

1_2

1_1

1_3D1_4

DC_3DDC_4

CS BC 00 00...

Fig.37 Sliced data formats on the I-port in 8-bit mode.

timing reference codeinternal header

CS BC FF 00 00 EAV 00 00... ...

ANC data output is only filled up to the Dword boundary

...

MHB549

SAA7118

Page 65

Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive

SAA7118

comb ﬁlter and component video input

Table 20 Explanation to Fig.37

NAME EXPLANATION

SAV start of active data; see Table 21

(1)

SDID sliced data identiﬁcation: NEP

5EH, D5 to D0, e. g. to be used as source identiﬁer

(1)

DC Dword count: NEP

(2)

, EP

, DC5 to DC0. DC describes the number of succeeding 32-bit words:

• For SAV/EAV mode DC is fixed to 11 Dwords (byte value 4BH)

• For ANC mode it is: DC =1⁄4(C + n), where C = 2 (the two data identification bytes IDI1 and IDI2) and

n = number of decoded bytes according to the chosen text standard.

It should be noted that the number of valid bytes inside the stream can be seen in the BC byte.

IDI1 internal data identiﬁcation 1: OP

LineNumber8 to LineNumber3 = Dword 1 byte 1; see Table 21

IDI2 internal data identiﬁcation 2: OP

DataType3 to DataType0 = Dword 1 byte 2; see Table 21 D D

n_m DC_4

Dword number n, byte number m

last Dword byte 4, note: for SAV/EAV framing DC is ﬁxed to 0BH, missing data bytes are ﬁlled up; the ﬁll

value is A0H CS the check sum byte, the check sum is accumulated from the SAV (respectively DID) byte to the D BC number of valid sliced bytes counted from the IDI1 byte EAV end of active data; see Table 21

(2)

, EP

, SDID5 to SDID0, freely programmable via I2C-bus subaddress

(3)

, FID (ﬁeld 1 = 0, ﬁeld 2 = 1),

(3)

, LineNumber2 to LineNumber0,

DC_4

byte

Notes

1. Inverted EP (bit 7); for EP see note 2.

2. Even parity (bit 6) of bits 5 to 0.

3. Odd parity (bit 7) of bits 6 to 0.

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SAA7118

comb ﬁlter and component video input

Table 21 Bytes stream of the data slicer

NICK

NAME

DID, SAV, EAV

SDID programmable via

(8)

DC IDI1 OP IDI2 OP LN2 CS check sum byte CS6 CS6 CS5 CS4 CS3 CS2 CS1 CS0 BC valid byte count OP 0 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0

COMMENT D7 D6 D5 D4 D3 D2 D1 D0

subaddress

NEP

(1)

(2)

0 1 0 FID

(3)

(4)

5DH = 00H subaddress 5DH;

NEP EP 0 D4[5DH] D3[5DH] D2[5DH] D1[5DH] D0[5DH]

D5=1 subaddress 5DH

1 FID

(3)

(6)

(7)

P3 P2 P1 P0

D5 = 3EH; note 5 subaddress 5DH

0 FID

(3)

(6)

(7)

P3 P2 P1 P0

D5 = 3FH; note 5

NEP EP D5[5EH] D4[5EH] D3[5EH] D2[5EH] D1[5EH] D0[5EH]

subaddress 5EH

FID

(2)

(3)

(10)

DC5 DC4 DC3 DC2 DC1 DC0 LN8 LN1

(10) (10)

LN7 LN0

(10) (10)

LN6 DT3

(10) (11)

LN5

DT2

(10) (11)

LN4 DT1

(10) (11)

NEP EP

(9)

LN3 DT0

(4)

(10) (11)

Notes

1. NEP = inverted EP (see note 2).

2. EP = Even Parity of bits 5 to 0.

3. FID = 0: field 1; FID = 1: field 2.

4. I1 = 0 and I0 = 0: before line 1; I1 = 0 and I0 = 1: lines 1 to 23; I1 = 1 and I0 = 0: after line 23; I1 = 1 and I0 = 1: line 24 to end of field.

5. Subaddress 5DH at 3EH and 3FH are used for ITU 656 like SAV/EAV header generation; recommended value.

6. V = 0: active video; V = 1: blanking.

7. H = 0: start of line; H = 1: end of line.

8. DC = Data Count in Dwords according to the data type.

9. OP = Odd Parity of bits 6 to 0.

10. LN = Line Number.

11. DT = Data Type according to table.

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Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive comb ﬁlter and component video input

8.7 Audio clock generation

(subaddresses 30H to 3FH)

TheSAA7118 incorporates the generationofa field-locked audio clock as an auxiliary function for video capture. An audio sample clock, that is locked to the field frequency, ensures that there is always the same predefined number of audio samples associated with a field, or a set of fields. That ensures synchronous playback of audio and video after digital recording (e.g. capture to hard disk), MPEG or other compression, or non-linear editing.

8.7.1 MASTER AUDIO CLOCK

The audio clock is synthesized from the same crystal frequency as the line-locked video clock is generated. The master audio clock is defined by the parameters:

• Audio master Clocks Per Field, ACPF[17:0] 32H[1:0]

31H[7:0] 30H[7:0] according to the equation:

audio frequency

ACPF[17:0] round



------------------------------------------



field frequency

SAA7118

Remark: For standard applications the synthesized audio clock AMCLK can be used directly as master clock and as input clock for port AMXCLK (short cut) to generate ASCLK and ALRCLK. For high-end applications it is recommended to use an external analog PLL circuit to enhance the performance of the generated audio clock.

• Audio master Clocks Nominal Increment, ACNI[21:0]

36H[5:0] 35H[7:0] 34H[7:0] according to the equation:

audio frequency

ACNI[21:0] round

See Table 22 for examples.

Table 22 Programming examples for audio master clock generation

XTALO

(MHz)

AMCLK = 256 × 48 kHz (12.288 MHz)

32.11

24.576

AMCLK = 256 × 44.1 kHz (11.2896 MHz)

32.11

24.576

AMCLK = 256 × 32 kHz (8.192 MHz)

32.11

24.576



---------------------------------------------



crystal frequency

FIELD

(Hz)

50 245760 3C000 3210190 30FBCE

59.94 205005 320CD 3210190 30FBCE 50 −−−−

59.94 −−−−

50 225792 37200 2949362 2D00F2

59.94 188348 2DFBC 2949362 2D00F2 50 225792 37200 3853517 3ACCCD

59.94 188348 2DFBC 3853517 3ACCCD

50 163840 28000 2140127 20A7DF

59.94 136670 215DE 2140127 20A7DF 50 163840 28000 2796203 2AAAAB

59.94 136670 215DE 2796203 2AAAAB

ACPF ACNI

DECIMAL HEX DECIMAL HEX

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Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive

SAA7118

comb ﬁlter and component video input

8.7.2 SIGNALS ASCLK AND ALRCLK Two binary divided signals ASCLK and ALRCLK are provided for slower serial digital audio signal transmission and for

channel-select. The frequencies of these signals are defined by the following parameters:

• SDIV[5:0] 38H[5:0] according to the equation: f

ASCLK

AMXCLK

= SDIV[5:0]

------------------------------------- SDIV 1+()2×

⇒

• LRDIV[5:0] 39H[5:0] according to the equation: ⇒

See Table 23 for examples.

Table 23 Programming examples for ASCLK/ALRCLK clock generation

AMXCLK

(MHz)

12.288

11.2896

8.192

ASCLK

(kHz)

DECIMAL HEX DECIMAL HEX

1536 3 03

768 7 07 8 08

1411.2 3 03

2822.4 1 01 32 10 1024 3 03 2048 1 01 32 10

AMXCLK

-------------------2f

ASCLK

SDIV

1–=

ALRCLK

ASCLK

= LRDIV[5:0]

-------------------------- LRDIV 2×

ALRCLK

(kHz)

44.1

ASCLK

---------------------- 2f

ALRCLK

LRDIV

16 10

8.7.3 OTHER CONTROL SIGNALS Further control signals are available to define reference clock edges and vertical references:

APLL[3AH[3]]; Audio PLL mode:

0: PLL closed 1: PLL open

AMVR[3AH[2]]; Audio Master clock Vertical Reference:

0: internal V 1: external V

LRPH[3AH[1]]; ALRCLK Phase

0: invert ASCLK, ALRCLK edges triggered by falling edge of ASCLK 1: don’t invert ASCLK, ALRCLK edges triggered by rising edge of ASCLK

SCPH[3AH[0]]; ASCLK Phase:

0: invert AMXCLK, ASCLK edges triggered by falling edge of AMXCLK 1: don’t invert AMXCLK, ASCLK edges triggered by rising edge of AMXCLK.

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Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive comb ﬁlter and component video input

9 INPUT/OUTPUT INTERFACES AND PORTS

The SAA7118 has 5 different I/O interfaces:

• Analog video input interface, for analog CVBS and/or Y and C input signals and/or component video signals

• Audio clock port

• Digital real-time signal port (RT port)

• Digitalvideoexpansionport(X-port),forunscaleddigital

video input and output

• Digital image port (I-port) for scaled video data output and programming

• Digital host port (H-port) for extension of the image port or expansion port from 8 to 16-bit.

9.1 Analog terminals

The SAA7118 has 16 analog inputs AI41 to AI44, AI31 to AI34, AI21 to AI24 and AI11 to AI14 for composite video CVBS or S-video Y/C signal pairs or component video input signals RGB plus separate sync (or Y-PB-P plus separate sync).

SAA7118

Component signals with e.g. sync-on-Y or sync-on-green arealso supported; they are fed to two ADC channels, one for the video contents, the other for sync conversion. Additionally, there are four differential reference inputs, which must be connected to ground via a capacitor equivalent to the decoupling capacitors at the 16 inputs. There are no peripheral components required other than these decoupling capacitors and 18 Ω/56 Ω termination resistors, one set per connected input signal (see also application example in Fig.47). Four anti-alias filters are integrated.

Clamp and gain control for the four ADCs are also integrated. An analog video output (pin AOUT) is provided for testing purposes.

Table 24 Analog pin description

SYMBOL PIN

AI11 to AI14 J2, K1, K2 and L3

(27, 29, 31 and 34)

AI21 to AI24 G4, G3, H2 and J3

(19, 21, 23 and 26)

AI31 to AI34 E3, F2, F3 and G1

(11, 13, 15 and 18)

AI41 to AI44 B1, D2, D1 and E1

(2, 5, 7 and 10) AOUT M1 (36) O analog video output, for test purposes AOSL2 to AOSL0 AI1D, AI2D,

AI3D and AI4D

Note

1. Pin numbers for QFP160 in parenthesis.

K3, H1, F1 and D3

(30, 22, 14 and 6)

(1)

I/O DESCRIPTION BIT

I analog video signal inputs, e.g. 16 CVBS signals or

eight Y/C pairs, or four RGB plus separate sync (or Y-PB-PR plus separate sync) signal groups can be connected simultaneously to this device; many combinations are possible; see Figs 51 to 91

I analog reference pins for differential ADC operation;

connect to ground via 47 nF

MODE5 to MODE0

−

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Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive comb ﬁlter and component video input

9.2 Audio clock signals

The SAA7118 also synchronizes the audio clock and sampling rate to the video frame rate, via a very slow PLL. Thisensures that the multimediacaptureand compression processes always gather the same predefined number of samples per video frame.

Table 25 Audio clock pin description

SYMBOL PIN

AMCLK P11

AMXCLK M12

ASCLK N11

ALRCLK P12

(1)

I/O DESCRIPTION BIT

O audio master clock output ACPF[17:0] 32H[1:0] 31H[7:0] 30H[7:0] and

(72)

I external audio master clock input for the clock

(76)

(74)

(75)

division circuit, can be directly connected to output AMCLK for standard applications

O serial audio clock output, can be synchronized

to rising or falling edge of AMXCLK

O audio channel (left/right) clock output, can be

synchronized to rising or falling edge of ASCLK

SAA7118

An audio master clock AMCLK and two divided clocks ASCLK and ALRCLK are generated;

• ASCLK: can be used as audio serial clock

• ALRCLK: audio left/right channel clock.

The ratios are programmable; see also Section 8.7.

ACNI[21:0] 36H[5:0] 35H[7:0] 34H[7:0]

−

SDIV[5:0] 38H[5:0] and SCPH[3AH[0]]

LRDIV[5:0] 39H[5:0] and LRPH[3AH[1]]

Note

1. Pin numbers for QFP160 in parenthesis.

9.3 Clock and real-time synchronization signals

For the generation of the line-locked video (pixel) clock LLC, and of the frame-locked audio serial bit clock, a crystal accurate frequency reference is required. An oscillator is built-in for fundamental or third harmonic crystals. The supported crystal frequencies are

32.11 or 24.576 MHz (defined during reset by strapping pin ALRCLK).

Alternatively pin XTALI can be driven from an external single-ended oscillator.

The crystal oscillation can be propagated as a clock to other ICs in the system via pin XTOUT.

The Line-Locked Clock (LLC) is the double pixel clock of nominal 27 MHz. It is locked to the selected video input, generating baseband video pixels according to

recommendation 601”

circuits, a direct pixel clock (LLC2) is also provided. The pins for line and field timing reference signals are

RTCO, RTS1 and RTS0. Various real-time status information can be selected for the RTS pins. The signals are always available (output) and reflect the synchronization operation of the decoder part in the SAA7118. The function of the RTS1 and RTS0 pins can be defined by bits RTSE1[3:0] 12H[7:4] and RTSE0[3:0] 12H[3:0].

. In order to support interfacing

“ITU

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Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive comb ﬁlter and component video input

Table 26 Clock and real-time synchronization signals

(155)

(156)

(158)

(46)

(48)

(71)

(69)

(70)

(1)

I/O DESCRIPTION BIT

I input for crystal oscillator or reference clock −

O output of crystal oscillator −

O reference (crystal) clock output drive (optional) XTOUTE[14H[3]]

O line-locked clock, nominal 27 MHz, double pixel clock locked to the

selected video input signal

O line-locked pixel clock, nominal 13.5 MHz −

O real-time control output, transfers real-time status information

supporting RTC level 3.1 (see document available on request)

O real-time status information line 0, can be programmed to carry various

real-time information (see Table 56)

O real-time status information line 1, can be programmed to carry various

real-time information (see Table 57)

SYMBOL PIN Crystal oscillator

XTALI B4

XTALO A3

XTOUT A2

Real-time signals (RT port)

LLC P4

LLC2 N5

RTCO L10

RTS0 M10

RTS1 N10

“RTCFunctional Description”

SAA7118

−

RTSE0[3:0] 12H[3:0]

RTSE1[3:0] 12H[7:4]

Note

1. Pin numbers for QFP160 in parenthesis.

9.4 Interrupt handling

9.4.1 INTERRUPT FLAGS The pin INT_A is an open-drain output (active LOW). All

flagscanbe independently enabled. For the default setting all flags are disabled after reset. For the description of interrupt mask registers see Section 15.4.

9.4.1.1 Power state

PRDON: a power fail has been detected during normal operation, the device needs re-programming.

9.4.1.2 Video decoder

INTL: interlaced/non-interlaced source detected. HLCK: horizontal PLL state changed (locked ↔ unlocked). HLVLN: vertical lock state changed (locked ↔ unlocked). FIDT: detected field frequency has changed

(50 Hz ↔ 60 Hz). RDCAP: ready for capture (true ↔ false).

DCSTD[1:0]: detected colour standard has changed or colour lost.

COPRO, COLSTR and TYPE3: various levels of copy protection have changed.

9.4.1.3 VBI data slicer

VPSV: VPS identification found or lost. PPV: PALplus identification found or lost. CCV: Closed caption identification found or lost.

9.4.1.4 Scaler

ERROF: scaler output formatting error detected.

9.4.2 STATUS READING CONDITIONS The status information read after an interrupt will always

be the LATEST state, that means the status will not be ‘frozen’ when an interrupt is being generated. Therefore, if there is a long time between interrupt generation and status reading, the original trigger condition might have been overridden by the present state.

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Multistandard video decoder with adaptive

SAA7118

comb ﬁlter and component video input

9.4.3 ERASING CONDITIONS The status flags are grouped into four 8-bit registers. The interrupt flag will only be cleared on a read access to

the status register in which the signal is located which causedthe interrupt. This implies that itissufficientto clear the interrupt by reading only those registers which have been enabled by their corresponding masks.

Priority: If a new trigger condition occurs at the SAME time (clock) on which a status is being read, the flag will NOT be cleared.

9.5 Video expansion port (X-port)

The expansion port is intended for transporting video streams image data from other digital video circuits such

Table 27 Signals dedicated to the expansion port

SYMBOL PIN

XPD7 to XPD0

XCLK A7 (143) I/O clock at expansion port: if output, then copy of LLC;

XDQ B7 (144) I/O data valid ﬂag of the expansion port input (qualiﬁer):

XRDY A6 (146) O data request ﬂag = ready to receive, to work with optional

XRH C7 (141) I/O horizontal reference signal for the X-port:

XRV D8 (140) I/O vertical reference signal for the X-port:

XTRI B11 (126) I port control: switches X-port input 3-state XPE[1:0]

C11, A11, B10, A10,

B9, A9, B8 and A8

(127, 128, 130, 131,

134, 135, 138 and 139)

(1)

I/O DESCRIPTION BIT

I/O X-portdata: in output mode controlled by decoder section,

data format see Table 28; in input mode Y-CB-CR4:2:2 serial input data or luminance part of a 16-bit Y-CB-CR4:2:2 input

as input normally a double pixel clock of up to 32 MHz or a gated clock (clock gated with a qualiﬁer)

if output, then decoder (HREF and VGATE) gate (see Fig.30)

buffer in external device, to prevent internal buffer overﬂow; second function: input related task ﬂag A/B

as output: HREF or HS from the decoder (see Fig.30); as input: a reference edge for horizontal input timing and a polarity for input ﬁeld ID detection can be deﬁned

as output: V123 or ﬁeld ID from the decoder, see Figs 28 and 29; as input: a reference edge for vertical input timing and for input ﬁeld ID detection can be deﬁned

as MPEG encoder/decoder and video phone codec, to the image port (I-port).

The expansion port consists of two groups of signals/pins:

• 8-bit data, I/O, regularly components video Y-CB-C 4:2:2, i.e. CB-Y-CR-Y, byte serial, exceptionally raw video samples (e.g. ADC test). In input mode the data bus can be extended to 16-bit by pins HPD7 to HPD0.

• Clock, synchronization and auxiliary signals, accompanying the data stream, I/O.

As output, these are direct copies of the decoder signals. The data transfers through the expansion port represent a

single D1 port, with half duplex mode. The SAV and EAV codes may be inserted optionally for data input (controlled by bit XCODE[92H[3]]). The input/output direction is switched for complete fields only.

OFTS[2:0] 13H[2:0], 91H[7:0] and C1H[7:0]

XCKS[92H[0]]

−

XRQT[83H[2]]

XRHS[13H[6]], XFDH[92H[6]] and XDH[92H[2]]

XRVS[1:0] 13H[5:4], XFDV[92H[7]] and XDV[1:0] 92H[5:4]

83H[1:0]

Note

1. Pin numbers for QFP160 in parenthesis.

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Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive comb ﬁlter and component video input

9.5.1 X-PORT CONFIGURED AS OUTPUT If data output is enabled at the expansion port, then the

data stream from the decoder is presented. The data format of the 8-bit data bus is dependent on the chosen data type, selectable by the line control registers LCR2 to LCR24; see Table 4. In contrast to the image port, the sliced data format is not available on the expansion port. Instead, raw CVBS samples are always transferred if any sliced data type is selected.

Some details of data types on the expansion port are as follows:

• Active video (data type 15): contains component Y-CB-CR 4:2:2 signal, 720 active pixels per line. The amplitude and offsets are programmable via DBRI7 to DBRI0, DCON7 to DCON0, DSAT7 to DSAT0, OFFU1, OFFU0, OFFV1 and OFFV0. For nominal levels see Fig.19.

• Test line (data type 6): is similar to the active video format, with some constraints within the data processing:

– adaptive chrominance comb filter, vertical filter

(chrominance comb filter for NTSC standards, PAL phase error correction) within the chrominance processing are disabled

– adaptive luminance comb filter, peaking and

chrominance trap are bypassed within the luminance processing.

This data type is defined for future enhancements. It could be activated for lines containing standard test signals within the vertical blanking period. Currently the most sources do not contain test lines. For nominal levels see Fig.19.

• Raw samples (data types 0 to 5 and 7 to 14): CB-C samples are similar to data type 6, but CVBS samples aretransferred instead ofprocessedluminance samples within the Y time slots.

SAA7118

The amplitude and offset of the CVBS signal is programmable via RAWG7 to RAWG0 and RAWO7 to RAWO0;seeChapter 15,Tables 63 and 64. For nominal levels see Fig.20.

The relationship of LCR programming to line numbers is described in Section 8.3, see Tables 5 to 8.

The data type selections by LCR are overruled by setting OFTS2 = 1 (subaddress 13H bit 2). This setting is mainly intended for device production test. The VPO-bus carries theupper or lower 8 bits of the two ADCs dependingonthe OFTS[1:0] 13H[1:0] settings; see Table 58. The output configurationis done via MODE[5:0]02H[5:0]settings; see Table 40. If a Y/C mode is selected, the expansion port carriesthemultiplexed output signals of both ADCs, and in CVBS mode the output of only one ADC. No timing reference codes are generated in this mode.

Remark: The LSBs (bit 0) of the ADCs are also available on pin RTS0; see Table 56.

The SAV/EAV timing reference codes define the start and end of valid data regions. The ITU-blanking code sequence ‘- 80 - 10 - 80 - 10 -...’ is transmitted during the horizontal blanking period between EAV and SAV.

The position of the F-bit is constant in accordance with ITU 656; see Tables 30 and 31.

The V-bit can be generated in two different ways (see Tables 30 and 31)controlledviaOFTS1 and OFTS0; see Table 58.

The F and V bits change synchronously with the EAV code.

Table 28 Data format on the expansion port

BLANKING

PERIOD

... 80 10 FF 00 00 SAV CB0Y0CR0Y1CB2 Y2 ... CR718 Y719 FF 00 00 EAV 80 10 ...

Notes

1. The generation of the timing reference codes can be suppressed by setting OFTS[2:0] to ‘010’, see Table 58. In this

event the code sequence is replaced by the standard ‘- 80 - 10 -’ blanking values.

2. If raw samples or sliced data are selected by the line control registers (LCR2 to LCR24), the Y samples are replaced

by CVBS samples.

2001 May 30 73

TIMING

REFERENCE

CODE (HEX)

(1)

720 PIXELS Y-CB-CR4:2:2 DATA

(2)

TIMING

REFERENCE

CODE (HEX)

(1)

BLANKING

PERIOD

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Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive

SAA7118

comb ﬁlter and component video input

Table 29 SAV/EAV format on expansion port XPD7 to XPD0

BIT 7

1 ﬁeld bit vertical blanking bit format reserved; evaluation not

Table 30 525 lines/60 Hz vertical timing

LINE NUMBER F (ITU 656)

1 to 3 1 1 according to selected VGATE

4to19 0 1

20 0 0 21 0 0

22 to 261 0 0

262 0 0 263 0 0

264 and 265 0 1

266 to 282 1 1

283 1 0 284 1 0

285 to 524 1 0

525 1 0

BIT 6

(F)

1st field: F = 0 2nd field: F = 1

for vertical timing see Tables 30 and 31

BIT 5

(V)

VBI: V = 1 active video: V = 0

OFTS[2:0] = 000 (ITU 656) OFTS[2:0] = 001

BIT 4

(H)

H = 0 in SAV format H = 1 in EAV format

BIT 3

BIT 2

(P3)

recommended (protection bits according to ITU 656)

position type via VSTA and VSTO (subaddresses 15H to 17H); see Tables 60 to 62

(P2)

BIT 1

(P1)

BIT 0

(P0)

Table 31 625 lines/50 Hz vertical timing

LINE NUMBER F (ITU 656)

OFTS[2:0] = 000 (ITU 656) OFTS[1:0] = 10

1 to 22 0 1 according to selected VGATE

23 0 0

24 to 309 0 0

310 0 0

311 and 312 0 1

313 to 335 1 1

336 1 0

337 to 622 1 0

623 1 0

624 and 625 1 1

2001 May 30 74

position type via VSTA and VSTO (subaddresses 15H to 17H); see Tables 60 to 62

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Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive comb ﬁlter and component video input

9.5.2 X-PORT CONFIGURED AS INPUT

If data input mode is selected at the expansion port, then the scaler can choose its input data stream from the on-chip video decoder, or from the expansion port (controlled by bit SCSRC[1:0] 91H[5:4]). Byte serial Y-CB-CR4:2:2,orsubsetsfor other sampling schemes, or raw samples from an external ADC may be input (see also bits FSC[2:0] 91H[2:0]). The input stream must be accompanied by an external clock (XCLK), qualifier XDQ and reference signals XRH and XRV. Instead of the reference signal, embedded SAV and EAV codes according to ITU 656 are also accepted. The protection bits are not evaluated.

XRH and XRV carry the horizontal and vertical synchronization signals for the digital video stream through the expansion port. The field ID of the input video stream is carried in the phase (edge) of XRV and state of XRH, or directly as FS (frame sync, odd/even signal) on the XRV pin (controlled by XFDV[92H[7]], XFDH[92H[6]] and XDV1[92H[5]]).

The trigger events on XRH (rising/falling edge) and XRV (rising/falling/both edges) for the scalers acquisition window are defined by XDV[1:0] 92H[5:4] and XDH[92H[2]]. The signal polarity of the qualifier can also be defined (bit XDQ[92H[1]]). Alternatively to a qualifier, the input clock can be applied to a gated clock (means clock gated with a data qualifier, controlled by bit XCKS[92H[0]]). In this event, all input data will be qualified.

As the VBI data slicer may have different requirements for its input reference signals from X-port XRV, XRH, XDQ, XCLK and XPD7 to XPD0, a second set of parameters is available for defining the meaning of the X-port input signals and polarities for the VBI data slicer input path. These bits are defined in subaddresses 81H and 82H.

9.6 Image port (I-port)

The image port transfers data from the scaler as well as from the VBI-data slicer, if selected (maximum 33 MHz). The reference clock is available at the ICLK pin, as an output,oras an input (maximum 33 MHz). As output, ICLK is derived from the line-locked decoder or expansion port input clock. The data stream from the scaler output is normally discontinuous. Therefore valid data during a clock cycle is accompanied by a data qualifying (data valid) flag on pin IDQ. For pin constrained applications the IDQ pin can be programmed to function as a gated clock output (bit ICKS2[80H[2]]).

SAA7118

The data formats at the image port are defined in Dwords of 32 bits (4 bytes), such as the related FIFO structures. However the physical data stream at the imageport is only 16-bit or 8-bit wide; in 16-bit mode data pins HPD7 to HPD0 are used for chrominance data. The four bytes of the Dwords are serialized in words or bytes.

Available formats are as follows:

• Y-CB-CR 4:2:2

• Y-CB-CR 4:1:1

• Raw samples

• Decoded VBI-data.

For handshake with the receiving VGA controller, or other memory or bus interface circuitry, F, H and V reference signals and programmable FIFO flags are provided. The information is provided on pins IGP0, IGP1, IGPH and IGPV. The functionality on these pins is controlled via subaddresses 84H and 85H.

VBI-data is collected over an entire line in its own FIFO, and transferred as an uninterrupted block of bytes. Decoded VBI-data can be signed by the VBI flag on pin IGP0 or IGP1.

As scaled video data and decoded VBI-data may come from different and asynchronous sources, an arbitration scheme is needed. Normally the VBI-data slicer has priority.

The image port consists of the pins and/or signals, as listed in Table 32.

Forpin constrained applications, orinterfaces,the relevant timing and data reference signals can also get encoded into the data stream. Therefore the corresponding pins do not need to be connected. The minimum image port configuration requires 9 pins only, i.e. 8 pins for data including codes, and 1 pin for clock or gated clock. The inserted codes are defined in close relationship to the ITU-R BT.656 (D1) recommendation, where possible.

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The following deviations from are implemented at the SAA7118s image port interface:

• SAV and EAV codes are only present in those lines, where data is to be transferred, i.e. active video lines, or VBI raw samples, no codes for empty lines

• There may be more or less than 720 pixels between SAV and EAV

• Data content and the number of clock cycles during horizontal and vertical blanking is undefined, and may not be constant

• Data stream may be interleaved with not-valid data codes, 00H, but SAV and EAV 4-byte codes are not interleaved with not-valid data codes

• There may be an irregular pattern of not-valid data, or IDQ, and as a result, CB-Y-CR-Y is not in a fixed phase to a regular clock divider

• VBI raw sample streams are enveloped with SAV and EAV, like normal video

“ITU 656 recommendation”

SAA7118

• Decoded VBI-data is transported as Ancillary (ANC) data, two modes:

– direct decoded VBI-data bytes (8-bit) are directly

placed in the ANC data field, 00H and FFH codes may appear in data block (violation to ITU-R BT.656)

– recoded VBI-data bytes (8-bit) directly placed in ANC

data field, 00H and FFH codes will be recoded to even parity codes 03H and FCH to suppress invalid ITU-R BT.656 codes.

There are no empty cycles in the ancillary code and its data field. The data codes 00H and FFH are suppressed (changed to 01H or FEH respectively) in the active video stream, as well as in the VBI raw sample stream (VBI pass-through). Optionally, the number range can be further limited.

Table 32 Signals dedicated to the image port

SYMBOL PIN

IPD7 to IPD0

ICLK M14 (84) I/O continuous reference clock at image port, can

IDQ L13 (85) O data valid ﬂag at image port, qualiﬁer, with

IGPH K12 (91) O horizontal reference output signal, copy of the

IGPV K14 (90) O vertical reference output signal, copy of the

IGP1 K13 (89) O general purpose output signal for I-port IDG12[86H[4]],IDG1[1:0]84H[5:4],

IGP0 L14 (87) O general purpose output signal for I-port IDG02[86H[5]], IDG0[1:0] 84H[7:6],

ITRDY N12 (77) I target ready input signals − ITRI L12 (86) I port control, switches I-port into 3-state IPE[1:0] 87H[1:0]

K11, J13, J14,

H13,H14, H11,

G12 and G14

(92 to 94, 97 to

100 and 102)

(1)

I/O DESCRIPTION BIT

I/O I-port data ICODE[93H[7]], ISWP[1:0]

85H[7:6] and IPE[1:0] 87H[1:0]

ICKS[1:0] 80H[1:0] and IPE[1:0] be input or output, as output decoder LLC or XCLK from X-port

programmable polarity; secondary function: gated clock

H-gate signal of the scaler,with programmable polarity; alternative function: HRESET pulse

V-gate signal of the scaler, with programmable polarity; alternative function: VRESET pulse

87H[1:0]

ICKS2[80H[2]], IDQP[85H[0]] and

IPE[1:0] 87H[1:0]

IDH[1:0] 84H[1:0], IRHP[85H[1]]

and IPE[1:0] 87H[1:0]

IDV[1:0] 84H[3:2], IRVP[85H[2]]

and IPE[1:0] 87H[1:0]

IG1P[85H[3]] and IPE[1:0] 87H[1:0]

IG0P[85H[4]] and IPE[1:0] 87H[1:0]

Note

1. Pin numbers for QFP160 in parenthesis.

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comb ﬁlter and component video input

9.7 Host port for 16-bit extension of video data I/O (H-port)

The H-port pins HPD can be used for extension of the data I/O paths to 16-bit. The I-port has functional priority. If I8_16[93H[6]] is set to logic 1 the output drivers of the H-port are enabled depending

on the I-port enable control. For I8_16 = 0, the HPD output is disabled.

Table 33 Signals dedicated to the host port

SYMBOL PIN

HPD7 to HPD0 G13, F14, F13, E14, E12,

E13, E11 and D14 (103,

105, 107 and 109 to 113)

Note

1. Pin numbers for QFP160 in parenthesis.

9.8 Basic input and output timing diagrams I-port and X-port

9.8.1 I-PORT OUTPUT TIMING

The following diagrams illustrate the output timing via the I-port. IGPH and IGPV are logic 1 active gate signals. If reference pulses are programmed, these pulses are generated on the rising edge of the logic 1 active gates. Valid data is accompanied by the output data qualifier on pin IDQ. In addition invalid cycles are marked with output code 00H.

The IDQ output pin may be defined to be a gated clock output signal (ICLK AND internal IDQ).

(1)

I/O DESCRIPTION BIT

I/O 16-bit extension for digital I/O

(chrominance component)

IPE[1:0] 87H[1:0], ITRI[8FH[6]] and I8_16[93H[6]]

9.8.2 X-PORT INPUT TIMING At the X-port the input timing requirements are the same

as those for the I-port output. But different to those below:

• It is not necessary to mark invalid cycles with a 00H code

• No constraints on the input qualifier (can be a random pattern)

• XCLK may be a gated clock (XCLK AND external XDQ).

Remark: All timings illustrated in Figs 38 to 44 are given for an uninterrupted output stream (no handshake with the external hardware).

ICLK

IDQ

IPD[7:0

IGPH

]

00 FF 00 00 SAV 00

Fig.38 Output timing I-port for serial 8-bit data at start of a line (ICODE = 1).

2001 May 30 77

Y00

MHB550

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Multistandard video decoder with adaptive comb ﬁlter and component video input

ICLK

IDQ

IPD[7:0

IGPH

]

Y00

SAA7118

Y00

MHB551

ICLK

IDQ

IPD[7:0

IGPH

Fig.39 Output timing I-port for serial 8-bit data at start of a line (ICODE = 0).

]

Y00

Y00FF0000EAV00

MHB552

Fig.40 Output timing I-port for serial 8-bit data at end of a line (ICODE = 1).

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ICLK

IDQ

IPD[7:0

IGPH

]

Y00

SAA7118

MHB553

ICLK

IDQ

IPD[7:0

HPD[7:0

IGPH

Fig.41 Output timing I-port for serial 8-bit data at end of a line (ICODE = 0).

]

00 FF 00 00 Y0 Y1 00 Y2 Y3

]

00 00 SAV 00 00

n−1

00 FF 00 00

00 00 EAV 00

MHB554

Fig.42 Output timingfor 16-bit data output via I-port and H-port with codes (ICODE = 1), timing is like 8-bit output,

but packages of 2 bytes per valid cycle.

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IDQ

IGPH

IGPV

SAA7118

MHB555

handbook, full pagewidth

ICLK

IDQ

]

IPD[7:0

]

HPD[7:0

sliced data

flag on IGP0

or IGP1

Fig.43 H-gate and V-gate output timing.

00 00 FF FF DID SDID XX YY ZZ CS

00 FF 00 SAV00 00 00BC FF EAV

00 00 00

MHB733

Fig.44 Output timing for sliced VBI-data in 8-bit serial output mode (dotted graphs for SAV/EAV mode).

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10 BOUNDARY SCAN TEST

The SAA7118 has built-in logic and 5 dedicated pins to support boundary scan testing which allows board testing withoutspecial hardware (nails). The SAA7118 follows the

“IEEE Std. 1149.1 - Standard Test Access Port and Boundary-Scan Architecture”

Group (JTAG) chaired by Philips. The 5 special pins are Test Mode Select (TMS), Test

Clock (TCK), Test Reset (TRST), Test Data Input (TDI) and Test Data Output (TDO).

The Boundary Scan Test (BST) functions BYPASS, EXTEST, INTEST, SAMPLE, CLAMP and IDCODE are all supported (see Table 34). Details about the JTAG BST-TEST can be found in specification “

1149.1”

Description Language (BSDL) description of the SAA7118 is available on request.

Table 34 BST instructions supported by the SAA7118

. A file containing the detailed Boundary Scan

INSTRUCTION DESCRIPTION

BYPASS This mandatory instruction provides a

minimum length serial path (1 bit) between TDI and TDO when no test operation of the component is required.

EXTEST This mandatory instruction allows

testing of off-chip circuitry and board level interconnections.

SAMPLE This mandatory instruction can be

used to take a sample of the inputs during normal operation of the component. It can also be used to preload data values into the latched outputs of the boundary scan register.

CLAMP This optional instruction is useful for

testing when not all ICs have BST. This instruction addresses the bypass register while the boundary scan register is in external test mode.

set by the Joint Test Action

IEEE Std.

SAA7118

INSTRUCTION DESCRIPTION

IDCODE This optional instruction will provide

information on the components manufacturer, part number and version number.

INTEST This optional instruction allows testing

of the internal logic (no customer support available).

USER1 This private instruction allows testing

by the manufacturer (no customer support available).

10.1 Initialization of boundary scan circuit

The TAP (Test Access Port) controller of an IC should be in the reset state (TEST_LOGIC_RESET) when the IC is in functional mode. This reset state also forces the instruction register into a functional instruction such as IDCODE or BYPASS.

To solve the power-up reset, the standard specifies that the TAP controller will be forced asynchronously to the TEST_LOGIC_RESET state by setting the TRST pin LOW.

10.2 Device identiﬁcation codes

A device identification register is specified in

1149.1b-1994”

for the specification of the IC manufacturer, the IC part number and the IC version number. Its biggest advantage is the possibility to check for the correct ICs mounted after production and determination of the version number of ICs during field service.

When the IDCODE instruction is loaded into the BST instruction register, the identification register will be connected between TDI and TDO of the IC. The identification register will load a component specific code duringthe CAPTURE_DATA_REGISTER state of theTAP controller and this code can subsequently be shifted out. At board level this code can be used to verify component manufacturer, type and version number. The device identification register contains 32 bits, numbered 31 to 0, where bit 31 is the most significant bit (nearest to TDI) and bit 0 is the least significant bit (nearest to TDO); see Fig.45.

. It is a 32-bit register which contains fields

“IEEE Std.

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comb ﬁlter and component video input

handbook, full pagewidth

11 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134); all ground pins connected together and all supply pins connected together.

MSB LSB

28 27 12 11 1 0

TDI TDO

nnnn

4-bit

version

code

000000101010111000100011000

16-bit part number 11-bit manufacturer

identification

MHB734

Fig.45 32 bits of identification code.

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V V V V V

DDD DDA IA OA ID

digital supply voltage −0.5 +4.6 V analog supply voltage −0.5 +4.6 V input voltage at analog inputs −0.5 V output voltage at analog output −0.5 V input voltage at digital inputs and outputs outputs in 3-state;

−0.5 +5.5 V

DDA DDA

(1)

+ 0.5 + 0.5 V

note 2 V ∆V T T V

SS stg amb esd

output voltage at digital outputs outputs active −0.5 V voltage difference between V

SSAn

and V

SSDn

− 100 mV

+ 0.5 V

DDD

storage temperature −65 +150 °C ambient temperature 0 70 °C electrostatic discharge voltage at all pins note 3 −2000 +2000 V

Notes

1. Maximum 4.6 V.

2. Except pin XTALI.

3. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ resistor.

12 THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

th(j-a)

thermal resistance from junction to ambient in free air

SAA7118E 37.5 K/W SAA7118H 34.3 K/W

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Multistandard video decoder with adaptive

SAA7118

comb ﬁlter and component video input

13 CHARACTERISTICS

= 3.0 to 3.6 V; V

DDD

Fig.46; unless otherwise speciﬁed.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

DDD

digital supply voltage

DDD

digital supply current

power dissipation digital part

DDA

analog supply voltage

DDA

analog supply current

power dissipation analog part

tot(A+D)

total power dissipation analog and digital part

tot(A+D)(pd)

total power dissipation analog and digital part in power-down mode

tot(A+D)(ps)

total power dissipation analog and digital part in power-save mode

Analog part

clamp

i(p-p)

clamping current VI=1VDC −±8 −µA input voltage

(peak-to-peak value)

Zi input impedance clamping current off 200 −− kΩ C

input capacitance −−10 pF channel crosstalk fi< 5 MHz −−−50 dB

= 3.1 to 3.5 V; T

DDA

=25°C; timings and levels refer to drawings and conditions illustrated in

amb

3.0 3.3 3.6 V

X-port 3-state; 8-bit I-port − 85 − mA

− 280 − mW

3.1 3.3 3.5 V

AOSL1 and AOSL0 = 0

CVBS mode − 75 − mA Y/C mode − 130 − mA

component mode − 250 − mA CVBS mode − 248 − mW Y/C mode − 430 − mW component mode − 825 − mW CVBS mode − 533 − mW Y/C mode − 710 − mW component mode − 1105 1350 mW CE pulled down to ground − 5 − mW

I2C-buscontrolled via subaddress

− 75 − mW

88H = 0FH

for normal video levels 1 V (p-p),

− 0.7 − V

−3 dB termination 18/56 Ω and

AC coupling required; coupling capacitor is 47 nF

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SAA7118

comb ﬁlter and component video input

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

9-bit analog-to-digital converters

B analog bandwidth at −3dB − 7 − MHz φ

diff

clk(ADC)

dc(d)

dc(i)

∆G

ADC

Digital inputs

IL(SCL,SDA)

IH(SCL,SDA)

IL(XTALI)

IH(XTALI)

IL(n)

IH(n)

LI/O

differential phase ampliﬁer plus anti-alias ﬁlter

− 2 − deg

bypassed

differential gain ampliﬁer plus anti-alias ﬁlter

− 2 − %

bypassed

ADC clock

25.4 − 28.6 MHz

frequency DC differential

− 0.7 − LSB

linearity error DC integral

− 1 − LSB

linearity error ADC gain

inequality

maximum deviation



---------------------------------------------------



minimum deviation

1–

100×

− 3 − %

;

note 1

LOW-level input

note 2 −0.5 − +0.3V

DD(I2C)

V voltage pins SDA and SCL

HIGH-level input

note 2 0.7V

DD(I2C)

− V

DD(I2C)

+ 0.5 V voltage pins SDA and SCL

LOW-level CMOS

−0.3 − +0.8 V input voltage pin XTALI

HIGH-levelCMOS

2.0 − V

+ 0.3 V

DDD

input voltage pin XTALI

LOW-level input

−0.3 − +0.8 V voltage all other inputs

HIGH-level input

2.0 − 5.5 V voltage all other inputs

input leakage

−−1 µA current

I/O leakage

−−10 µA current

input capacitance I/O at high-impedance −−8pF

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SAA7118

comb ﬁlter and component video input

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Digital outputs; note 3

OL(SDA)

OL(clk)

OH(clk)

OL(n)

OH(n)

Clock output timing (LLC and LLC2); note 4 C

δ duty factors for

d(LLC-LLC2)

Horizontal PLL

hor(n)

∆f

hor/fhor(n)

Subcarrier PLL

sc(n)

∆f

LOW-level output

SDA at 3 mA sink current −−0.4 V

voltage pin SDA LOW-level output

−0.5 − +0.6 V voltage for clocks

HIGH-level output

2.4 − V

+ 0.5 V

DDD

voltage for clocks LOW-level output

0 − 0.4 V voltage all other digital outputs

HIGH-level output

2.4 − V

+ 0.5 V

DDD

voltage all other digital outputs

output load

15 − 50 pF capacitance

cycle time pin LLC 35 − 39 ns

pin LLC2 70 − 78 ns CL=40pF 40 − 60 %

LLCH/tLLC

LLC2H/tLLC2

rise time LLC and

and

0.2VtoV

− 0.2 V −−5ns

DDD

LLC2 fall time LLC and

− 0.2 V to 0.2 V −−5ns

DDD

LLC2 delay time

measured at 1.5 V; CL=25pF −4 − +8 ns between LLC and LLC2 output

nominal line frequency

permissible static

50 Hz ﬁeld − 15625 − Hz

60 Hz ﬁeld − 15734 − Hz

−−5.7 %

deviation

nominalsubcarrier frequency

PAL BGHI − 4433619 − Hz

NTSC M − 3579545 − Hz

PAL M − 3575612 − Hz

PAL N − 3582056 − Hz lock-in range ±400 −− Hz

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Multistandard video decoder with adaptive

SAA7118

comb ﬁlter and component video input

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Crystal oscillator for 32.11 MHz; note 5

xtal(nom)

∆f

xtal(nom)

∆f

xtal(nom)(T)

CRYSTAL SPECIFICATION (X1) T

amb(X1)

Crystal oscillator for 24.576 MHz; note 5 f

xtal(n)

∆f

xtal(n)

∆f

xtal(n)(T)

CRYSTAL SPECIFICATION (X1) T

amb(X1)

nominal frequency 3rd harmonic − 32.11 − MHz permissible

−−±70 × 10

−6

nominalfrequency deviation

permissible

−−±30 × 10

−6

nominalfrequency deviation with temperature

ambient

0 − 70 °C

temperature load capacitance 8 −− pF series resonance

− 40 80 Ω

resistor motional

− 1.5 ±20% − fF

capacitance parallel

− 4.3 ±20% − pF

capacitance

nominal frequency 3rd harmonic − 24.576 − MHz permissible

−−±50 × 10

−6

nominalfrequency deviation

permissible

−−±20 × 10

−6

nominalfrequency deviation with temperature

ambient

0 − 70 °C

temperature load capacitance 8 −− pF series resonance

− 40 80 Ω

resistor motional

− 1.5 ±20% − fF

capacitance parallel

− 3.5 ±20% − pF

capacitance

2001 May 30 86

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Multistandard video decoder with adaptive

SAA7118

comb ﬁlter and component video input

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Clock input timing (XCLK)

δ duty factors for

Data and control signal input timing X-port, related to XCLK input

SU;DAT

HD;DAT

Clock output timing

δ duty factors for

Data and control signal output timing X-port, related to XCLK output (for XPCK[1:0]83H[5:4] = 00 is default);

note 4 C

OHD;DAT

Control signal output timing RT port, related to LLC output

OHD;DAT

cycle time 31 − 45 ns

40 50 60 %

LLCH/tLLC

rise time −−5ns fall time −−5ns

input data set-up

− 10 − ns

time input data hold

− 3 − ns

time

output load

15 − 50 pF

capacitance cycle time 35 − 39 ns

35 − 65 %

XCLKH/tXCLKL

rise time 0.6 to 2.6 V −−5ns fall time 2.6 to 0.6 V −−5ns

output load

15 − 50 pF

capacitance output data hold

CL=15pF − 14 − ns time

propagation delay

CL=15pF − 24 − ns from positive edge of XCLK output

output load

15 − 50 pF

capacitance output hold time CL=15pF − 14 − ns propagation delay

CL=15pF − 24 − ns from positive edge of LLC output

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Multistandard video decoder with adaptive

SAA7118

comb ﬁlter and component video input

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

ICLK output timing

δ duty factors for

Data and control signal output timing I-port, related to ICLK output (for IPCK[1:0] 87H[5:4] = 00 is default)

OHD;DAT

o(d)

ICLK input timing

Notes

1. ADC1 is not taken into account, since component video is always converted by ADC2, ADC3 and ADC4.

2. V

DD(I2C)

IL(SCL,SDA)(max)

3. The levels must be measured with load circuits; 1.2 kΩ at 3 V (TTL load); CL= 50 pF.

4. The effects of rise and fall times are included in the calculation of t drawings and conditions illustrated in Fig.46.

5. The crystal oscillator drive level is typical 0.28 mW.

output load

15 − 50 pF

capacitance cycle time 31 − 45 ns

35 − 65 %

ICLKH/tICLKL

rise time 0.6 to 2.6 V −−5ns fall time 2.6 to 0.6 V −−5ns

output load

15 − 50 pF capacitance at all outputs

output data hold

CL=15pF − 12 − ns

time output delay time CL=15pF − 22 − ns

cycle time 31 − 100 ns

is the supply voltage of the I2C-bus. For V

= 1.5 V. For V

DD(I2C)

= 3.3 V is V

IH(SCL,SDA)(min)

DD(I2C)

= 3.3 V is V

= 2.3 V; for V

OHD;DAT

IL(SCL,SDA)(max)

DD(I2C)

= 1 V; for V

=5VisV

DD(I2C)

IH(SCL,SDA)(min)

and tPD. Timings and levels refer to

=5V is

= 3.5 V.

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handbook, full pagewidth

clock input

XCLK

data and

control inputs

(X port)

SU;DAT

XCLKH

HD;DAT

SAA7118

2.4 V

1.5 V

0.6 V

not valid

2.0 V

0.8 V

input XDQ

data and

control outputs

X port, I port

clock outputs

LLC, LLC2, XCLK, ICLK

and ICLK input

OHD;DAT

X(I)CLKH

o(d)

SU;DAT

HD;DAT

2.0 V

0.8 V

−2.4 V

−0.6 V

X(I)CLKL

−2.6 V

−1.5 V

−0.6 V

MHB735

Fig.46 Data input/output timing diagram (X-port, RT port and I-port).

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Multistandard video decoder with adaptive comb ﬁlter and component video input

14 APPLICATION INFORMATION

56 Ω

(3×)

BAT83

DGND

10 µF

AGND

DDD

680 Ω

BF840

2.2 µH

DNC0 to

DNC18

TRST

M3, K4, H4, F4, D4

V V

100

DDA0

DDA4

(1)

TCK

L1,

J1, G2, E2

DDA1A

DDA4A

DGND

100

TMS

A13,

B2, B12, B13, B14,

C3,

C4, C12, C13, C14, D13,

N1,

N2,

N3, N13, N14,

P2, P13

D7,

D10, F11,

J11,

L5,

∆t

FSW

47 nF

AI11 AI12 AI13 AI14

AI1D

AGND

AI21 AI22 AI23 AI24

AI2D

AI31 AI32 AI33 AI34

AI3D

AGNDA

AI41 AI42 AI43 AI44

AI4D

EXMCLR

AOUT

100

AGND

boundary scan

TDO TDI

A5 B5 C6 B6 D6 A12,

M13

J2 K1 K2 L3 K3 C2 G4 G3 H2 J3 H1

E3 F2 F3 G1 F1 L2 B1 D2 D1 E1 D3

M2,

J4,

H3, E4, C1

SSA0

SSA4

AGND

100

0 Ω

handbook, full pagewidth

150 pF

680 Ω

75 Ω

18 Ω (3×)

CVBS1 CVBS2

18 Ω (4×)

VSB1 VSB2

18 Ω (4×)

Y1 Y2

18 Ω (4×)

C1 C2

AOUT

DDA

DDD

10 µF

DGND

56 Ω

(4×)

56 Ω

(4×)

56 Ω

(4×)

or V

DDD

DDD2 DDD4 DDD6 DDD8 DDD10 DDD12

DGND

100

SSD

4.7 kΩ

D5,

D9, D11, G11,

L4,

L8,

L11

audio clock

SSD1

SSD3

SSD5

SSD7

SSD9

SSD11

SSD13

I2C-bus port

C5,

C9, D12, H12,

M4, M8,

M11 A4 B3 A2 A3 B4

DDD1

DDD3

DDD5

DDD7

DDD9

DDD11

DDD13

DGND

100

DGND

C11, A11, B10, A10,

B9, A9, B8, A8

G13, F14, F13, E14, E12, E13, E11, D14

K11, J13, J14, H13,

H14, H11, G12, G14

P6, M6, L6, N7, P7,

L7, M7, P8, N8

SS(xtal)

DD(xtal)

XTOUT

100

for crystal strapping

AMCLK

AMXCLK

M12 P11 P12 N11 P10 N9 P9 N4 P5

SAA7118E

C8, C10, F12, J12,

M5, M9

SSD2

SSD4

SSD6

SSD8

SSD10

SSD12

100

DDD

4.7 kΩ

CEINT_ASCLSDAASCLKALRCLK

RES

L10

N10

M10

N5 P4

B11

D8 C7 A6 B7 A7

L12

K13

L14 K14 K12 N12

L13

M14

XTALO XTALI

24.576 MHz

(3rd harmonic)

10pF10

SAA7118

or V

DDD

SSD

for I

C-bus

slave address

strapping

4.7 kΩ

RTCO RTS1 RTS0 LLC2 LLC

XTRI XRV XRH XRDY XDQ XCLK

]

XPD[7:0

]

HPD[7:0

ITRI IGP1 IGP0 IGPV IGPH ITRDY IDQ ICLK

]

IPD[7:0

CLKEXT

]

ADP[8:0

10 µH

1 nF

AD port scaled image port host port expansion port real-time

(1) For board design without boundary scan implementation this pin should be connected to ground.

Fig.47 Application example with 24.576 MHz crystal (BGA156 package).

2001 May 30 90

Page 91

Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive comb ﬁlter and component video input

56 Ω

(3×)

BAT83

DGND

10 µF

AGND

DDD

680 Ω

BF840

2.2 µH

DNC0 to

DNC22

TRST

37, 32, 24, 16,

V V

100

DDA0

DDA4

(1)

TCK

33, 25, 17,

DDA1A

DDA4A

DGND

100

TMS

115, 116, 123, 124, 125,

1, 117, 118, 159, 160, 119, 120,

39, 40, 42, 79, 80, 41, 81,

82, 121, 122

51,

67,

96, 108, 133, 145

V V

V V V V

∆t

FSW

47 nF

AI11 AI12 AI13 AI14

AI1D

AGND

AI21 AI22 AI23 AI24

AI2D

AI31 AI32 AI33 AI34

AI3D

AGNDA

AI41 AI42 AI43 AI44

AI4D

EXMCLR

AOUT

100

AGND

boundary scan

TDO TDI

150 152 147 148 149 78,

27 29 31 34 30 3 19 21 23 26 22

11 13 15 18 14 35 2 5 7 10 6

38,

28,

20, 12,

SSA0

SSA4

AGND

100

0 Ω

handbook, full pagewidth

150 pF

680 Ω

75 Ω

18 Ω (3×)

CVBS1 CVBS2

18 Ω (4×)

VSB1 VSB2

18 Ω (4×)

Y1 Y2

18 Ω (4×)

C1 C2

AOUT

DDA

DDD

10 µF

DGND

56 Ω

(4×)

56 Ω

(4×)

56 Ω

(4×)

or V

DDD

DDD2 DDD4 DDD6 DDD8 DDD10 DDD12

DGND

100

SSD

4.7 kΩ

47, 63,

88, 104, 129, 137,

153

audio clock

SSD1

SSD3

SSD5

SSD7

SSD9

SSD11

SSD13

I2C-bus port

45, 59,

73, 101, 114, 136,

151 154 157 158 156 155

DDD1

DDD3

DDD5

DDD7

DDD9

DDD11

DDD13

DGND

100

DGND

127, 128, 130, 131, 134, 135, 138, 139

103, 105, 107, 109, 110, 111, 112, 113

98, 99, 100, 102

53, 54, 55, 56, 57,

SS(xtal)

DD(xtal)

XTOUT

100

92, 93, 94, 97,

58, 60, 61, 62

for crystal strapping

AMCLK

AMXCLK

76 72 75 74 68 66 64 44 49

SAA7118H

50, 65,

95, 106, 132,

142

SSD2

SSD4

SSD6

SSD8

SSD10

SSD12

100

DDD

4.7 kΩ

CEINT_ASCLSDAASCLKALRCLK

RES

71 70 69 48 46

126 140 141 146 144 143

86 89 87 90 91 77 85 84

XTALO XTALI

24.576 MHz

(3rd harmonic)

10pF10

SAA7118

or V

DDD

SSD

for I2C-bus

slave address

strapping

4.7 kΩ

RTCO RTS1 RTS0 LLC2 LLC

XTRI XRV XRH XRDY XDQ XCLK

]

XPD[7:0

]

HPD[7:0

ITRI IGP1 IGP0 IGPV IGPH ITRDY IDQ ICLK

]

IPD[7:0

CLKEXT

]

ADP[8:0

10 µH

1 nF

AD port scaled image port host port expansion port real-time

(1) For board design without boundary scan implementation this pin should be connected to ground.

Fig.48 Application example with 24.576 MHz crystal (QFP160 package).

2001 May 30 91

Page 92

Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive comb ﬁlter and component video input

handbook, full pagewidth

B4 (155)

XTALI XTALO

4.7 µH

1 nF

(1a) With 3rd harmonic quartz. Crystal load = 8 pF.

handbook, full pagewidth

B4 (155)

XTALI XTALO

SAA7118

32.11 MHz

15 pF

SAA7118

24.576 MHz

A3 (156)

15 pF

A3 (156)

B4 (155)

SAA7118

XTALI XTALO

32.11 MHz

33 pF

(1b) With fundamental quartz. Crystal load = 20 pF.

SAA7118

XTALI XTALO

24.576 MHz

A3 (156)

33 pF

A3 (156)

SAA7118

B4 (155)

XTALI XTALO

32.11 MHz

(1c) With fundamental quartz. Crystal load = 8 pF

SAA7118

B4 (155)

XTALI XTALO

24.576 MHz

10 pF

A3 (156)

4.7 µH

1 nF

(2a) With 3rd harmonic quartz. Crystal load = 8 pF.

18 pF

SAA7118

B4 (155)

XTALI XTALO

32.11 MHz or

24.576 MHz

(3a) With direct clock.

Pin numbers for QFP160 in parenthesis.

A3 (156)

n.c.

clock

39 pF

(2b) With fundamental quartz. Crystal load = 20 pF.

15 pF

(2c) With fundamental quartz. Crystal load = 8 pF.

15 pF

SAA7118

B4 (155)

XTALI XTALO

(3b) With fundamental quartz and restricted drive level. When P is too high a resistance R

Note: The decreased crystal amplitude results in a lower drive level but on the other hand the jitter performance will decrease.

A3 (156)

of the internal oscillator

can be placed in series with the output of the oscillator XTALO.

drive

Fig.49 Oscillator application.

2001 May 30 92

Page 93

Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive comb ﬁlter and component video input

15 I2C-BUS DESCRIPTION

The SAA7118 supports the ‘fast mode’ I2C-bus specification extension (data rate up to 400 kbits/s).

15.1 I

C-bus format

ACK-s ACK-s

SUBADDRESS

DATASLAVE ADDRESS W

data transferred

(n bytes + acknowledge)

a. Write procedure.

ACK-s ACK-s ACK-s ACK-mSLAVE ADDRESS R

SUBADDRESSSLAVE ADDRESS WS

DATA

data transferred

(n bytes + acknowledge)

PSr

MHB340

SAA7118

PS ACK-s

MHB339

b. Read procedure (combined).

Fig.50 I2C-bus format.

Table 35 Description of I

C-bus format

CODE DESCRIPTION

S START condition Sr repeated START condition SLAVE ADDRESS W ‘0100 0010’ (42H, default) or ‘0100 0000’ (40H; note 1) SLAVE ADDRESS R ‘0100 0011’ (43H, default) or ‘0100 0001’ (41H; note 1) ACK-s acknowledge generated by the slave ACK-m acknowledge generated by the master SUBADDRESS subaddress byte; see Tables 36 and 37 DATA data byte; see Table 37; if more than one byte DATA is transmitted the subaddress pointer is

automatically incremented P STOP condition X read/write control bit (LSB slave address); X = 0, order to write (the circuit is slave receiver);

X = 1, order to read (the circuit is slave transmitter)

Note

1. If pin RTCO strapped to supply voltage via a 3.3 kΩ resistor.

2001 May 30 93

Page 94

Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive

SAA7118

comb ﬁlter and component video input

Table 36 Subaddress description and access

SUBADDRESS DESCRIPTION ACCESS (READ/WRITE)

00H chip version read only F0H to FFH reserved −

Video decoder: 01H to 2FH

01H to 05H front-end part read and write 06H to 19H decoder part read and write 1AH to 1EH reserved − 1FH video decoder status byte read only 20H to 2FH reserved −

Audio clock generation: 30H to 3FH

30H to 3AH audio clock generator read and write 3BH to 3FH reserved −

General purpose VBI-data slicer: 40H to 7FH

40H to 5EH VBI-data slicer read and write 5FH reserved − 60H to 62H VBI-data slicer status read only 63H to 7FH reserved −

X-port, I-port and the scaler: 80H to EFH

80H to 8FH task independent global settings read and write 90H to BFH task A deﬁnition read and write C0H to EFH task B deﬁnition read and write

2001 May 30 94

Page 95

2001 May 30 95

Table 37 I2C-bus receiver/transmitter overview

SUB

Chip version: register 00H

Chip version (read only) 00 ID7 ID6 ID5 ID4 −−−−

Video decoder: registers 01H to 1FH

FRONT-END PART: REGISTERS 01H TO 05H Increment delay 01

Analog input control 1 02 FUSE1 FUSE0 MODE5 MODE4 MODE3 MODE2 MODE1 MODE0 Analog input control 2 03 Analog input control 3 04 GAI17 GAI16 GAI15 GAI14 GAI13 GAI12 GAI11 GAI10 Analog input control 4 05 GAI27 GAI26 GAI25 GAI24 GAI23 GAI22 GAI21 GAI20

DECODER PART: REGISTERS 06H TO 1FH Horizontal sync start 06 HSB7 HSB6 HSB5 HSB4 HSB3 HSB2 HSB1 HSB0

Horizontal sync stop 07 HSS7 HSS6 HSS5 HSS4 HSS3 HSS2 HSS1 HSS0 Sync control 08 AUFD FSEL FOET HTC1 HTC0 HPLL VNOI1 VNOI0 Luminance control 09 BYPS YCOMB LDEL LUBW LUFI3 LUFI2 LUFI1 LUFI0 Luminance brightness control 0A DBRI7 DBRI6 DBRI5 DBRI4 DBRI3 DBRI2 DBRI1 DBRI0 Luminance contrast control 0B DCON7 DCON6 DCON5 DCON4 DCON3 DCON2 DCON1 DCON0 Chrominance saturation control 0C DSAT7 DSAT6 DSAT5 DSAT4 DSAT3 DSAT2 DSAT1 DSAT0 Chrominance hue control 0D HUEC7 HUEC6 HUEC5 HUEC4 HUEC3 HUEC2 HUEC1 HUEC0 Chrominance control 1 0E CDTO CSTD2 CSTD1 CSTD0 DCVF FCTC AUTO0 CCOMB Chrominance gain control 0F ACGC CGAIN6 CGAIN5 CGAIN4 CGAIN3 CGAIN2 CGAIN1 CGAIN0 Chrominance control 2 10 OFFU1 OFFU0 OFFV1 OFFV0 CHBW LCBW2 LCBW1 LCBW0 Mode/delay control 11 COLO RTP1 HDEL1 HDEL0 RTP0 YDEL2 YDEL1 YDEL0 RT signal control 12 RTSE13 RTSE12 RTSE11 RTSE10 RTSE03 RTSE02 RTSE01 RTSE00 RT/X-port output control 13 RTCE XRHS XRVS1 XRVS0 HLSEL OFTS2 OFTS1 OFTS0 Analog/ADC/compatibility

control VGATE start, FID change 15 VSTA7 VSTA6 VSTA5 VSTA4 VSTA3 VSTA2 VSTA1 VSTA0 VGATE stop 16 VSTO7 VSTO6 VSTO5 VSTO4 VSTO3 VSTO2 VSTO1 VSTO0

ADDR.

(HEX)

14 CM99 UPTCV AOSL1 AOSL0 XTOUTE AUTO1 APCK1 APCK0

D7 D6 D5 D4 D3 D2 D1 D0

(1)

WPOFF GUDL1 GUDL0 IDEL3 IDEL2 IDEL1 IDEL0

HLNRS VBSL CPOFF HOLDG GAFIX GAI28 GAI18

Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive

comb ﬁlter and component video input

SAA7118

Page 96

2001 May 30 96

SUB

ADDR.

D7 D6 D5 D4 D3 D2 D1 D0

(HEX)

Miscellaneous, VGATE

17 LLCE LLC2E LATY2 LATY1 LATY0 VGPS VSTO8 VSTA8

conﬁguration and MSBs Raw data gain control 18 RAWG7 RAWG6 RAWG5 RAWG4 RAWG3 RAWG2 RAWG1 RAWG0 Raw data offset control 19 RAWO7 RAWO6 RAWO5 RAWO4 RAWO3 RAWO2 RAWO1 RAWO0 Reserved 1A to 1D Status byte 1 video decoder

1E − HLCK SLTCA GLIMT GLIMB WIPA DCSTD1 DCSTD0

(1) (1) (1) (1) (1) (1) (1) (1)

(read only) Status byte 2 video decoder

1F INTL HLVLN FIDT − TYPE3 COLSTR COPRO RDCAP

(read only)

Component processing and interrupt masking part: registers 20H to 2FH

Reserved 20 to 22 Analog input control 5 23 AOSL2 ADPE EXCLK REFA

(1) (1) (1) (1) (1) (1) (1) (1)

(1)

EXMCE GAI48 GAI38 Analog input control 6 24 GAI37 GAI36 GAI35 GAI34 GAI33 GAI32 GAI31 GAI30 Analog input control 7 25 GAI47 GAI46 GAI45 GAI44 GAI43 GAI42 GAI41 GAI40 Reserved 26 to 28

(1) (1) (1) (1) (1) (1) (1) (1)

Component delay 29 FSWE FSWI FSWDL1 FSWDL0 CMFI CPDL2 CPDL1 CPDL0 Component brightness control 2A CBRI7 CBRI6 CBRI5 CBRI4 CBRI3 CBRI2 CBRI1 CBRI0 Component contrast control 2B CCON7 CCON6 CCON5 CCON4 CCON3 CCON2 CCON1 CCON0 Component saturation control 2C CSAT7 CSAT6 CSAT5 CSAT4 CSAT3 CSAT2 CSAT1 CSAT0 Interrupt mask 1 2D Interrupt mask 2 2E

(1) (1) (1) (1)

MHLCK

(1) (1) (1) (1)

Interrupt mask 3 2F MINTL MHLVLN MFIDT

MVPSV MPPV MCCV

(1)

MTYPE3 MCOLSTR MCOPRO MRDCAP

(1)

MDCSTD1 MDCSTD0

Audio clock generator part: registers 30H to 3FH

Audio master clock cycles per ﬁeld

Reserved 33 Audio master clock nominal

increment

30 ACPF7 ACPF6 ACPF5 ACPF4 ACPF3 ACPF2 ACPF1 ACPF0 31 ACPF15 ACPF14 ACPF13 ACPF12 ACPF11 ACPF10 ACPF9 ACPF8 32

(1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1)

ACPF17 ACPF16

34 ACNI7 ACNI6 ACNI5 ACNI4 ACNI3 ACNI2 ACNI1 ACNI0 35 ACNI15 ACNI14 ACNI13 ACNI12 ACNI11 ACNI10 ACNI9 ACNI8 36

(1) (1)

ACNI21 ACNI20 ACNI19 ACNI18 ACNI17 ACNI16

MERROF

Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive

comb ﬁlter and component video input

SAA7118

Page 97

2001 May 30 97

SUB

ADDR.

D7 D6 D5 D4 D3 D2 D1 D0

(HEX)

Reserved 37 Clock ratio AMXCLK to ASCLK 38 Clock ratio ASCLK to ALRCLK 39 Audio clock generator basic

(1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1)

SDIV5 SDIV4 SDIV3 SDIV2 SDIV1 SDIV0

LRDIV5 LRDIV4 LRDIV3 LRDIV2 LRDIV1 LRDIV0

APLL AMVR LRPH SCPH

setup Reserved 3B to 3F

(1) (1) (1) (1) (1) (1) (1) (1)

General purpose VBI-data slicer part: registers 40H to 7FH

Slicer control 1 40

(1)

HAM_N FCE HUNT_N

(1) (1) (1) (1)

LCR2 to LCR24 (n = 2 to 24) 41 to 57 LCRn_7 LCRn_6 LCRn_5 LCRn_4 LCRn_3 LCRn_2 LCRn_1 LCRn_0 Programmable framing code 58 FC7 FC6 FC5 FC4 FC3 FC2 FC1 FC0 Horizontal offset for slicer 59 HOFF7 HOFF6 HOFF5 HOFF4 HOFF3 HOFF2 HOFF1 HOFF0 Vertical offset for slicer 5A VOFF7 VOFF6 VOFF5 VOFF4 VOFF3 VOFF2 VOFF1 VOFF0 Field offset and MSBs for

5B FOFF RECODE

(1)

VOFF8

(1)

HOFF10 HOFF9 HOFF8

horizontal and vertical offset Reserved (for testing) 5C Header and data identiﬁcation

5D FVREF

(1) (1) (1) (1) (1) (1) (1) (1)

(1)

DID5 DID4 DID3 DID2 DID1 DID0

(DID) code control Sliced data identiﬁcation (SDID)

(1) (1)

SDID5 SDID4 SDID3 SDID2 SDID1 SDID0

code Reserved 5F

(1) (1) (1) (1) (1) (1) (1) (1)

Slicer status byte 0 (read only) 60 − FC8V FC7V VPSV PPV CCV −− Slicer status byte 1 (read only) 61 −−F21_N LN8 LN7 LN6 LN5 LN4 Slicer status byte 2 (read only) 62 LN3 LN2 LN1 LN0 DT3 DT2 DT1 DT0 Reserved 63 to 7F

(1) (1) (1) (1) (1) (1) (1) (1)

X-port, I-port and the scaler part: registers 80H to EFH

Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive

comb ﬁlter and component video input

TASK INDEPENDENT GLOBAL SETTINGS: 80H TO 8FH Global control 1 80

Reserved 81 and

(1) (1) (1) (1) (1) (1) (1) (1) (1)

SMOD TEB TEA ICKS3 ICKS2 ICKS1 ICKS0

SAA7118

Page 98

2001 May 30 98

SUB

ADDR.

D7 D6 D5 D4 D3 D2 D1 D0

(HEX)

X-port I/O enable and output

(1) (1)

XPCK1 XPCK0

(1)

XRQT XPE1 XPE0

clock phase control I-port signal deﬁnitions 84 IDG01 IDG00 IDG11 IDG10 IDV1 IDV0 IDH1 IDH0 I-port signal polarities 85 ISWP1 ISWP0 ILLV IG0P IG1P IRVP IRHP IDQP I-port FIFO ﬂag control and

86 VITX1 VITX0 IDG02 IDG12 FFL1 FFL0 FEL1 FEL0

arbitration I-port I/O enable, output clock

87 IPCK3 IPCK2 IPCK1 IPCK0

(1) (1)

IPE1 IPE0

and gated clock phase control Power save/ADC-port control 88 DOSL1 DOSL0 SWRST DPROG SLM3 Reserved 89 to 8E

(1) (1) (1) (1) (1) (1) (1) (1)

(1)

SLM1 SLM0

Status information scaler part 8F XTRI ITRI FFIL FFOV PRDON ERROF FIDSCI FIDSCO TASK A DEFINITION: REGISTERS 90H TO BFH

Basic settings and acquisition window deﬁnition

Task handling control 90 CONLH OFIDC FSKP2 FSKP1 FSKP0 RPTSK STRC1 STRC0 X-port formats and conﬁguration 91 CONLV HLDFV SCSRC1 SCSRC0 SCRQE FSC2 FSC1 FSC0 X-port input reference signal

92 XFDV XFDH XDV1 XDV0 XCODE XDH XDQ XCKS

deﬁnition I-port output formats and

93 ICODE I8_16 FYSK FOI1 FOI0 FSI2 FSI1 FSI0

conﬁguration Horizontal input window start 94 XO7 XO6 XO5 XO4 XO3 XO2 XO1 XO0

(1) (1) (1) (1)

XO11 XO10 XO9 XO8

Horizontal input window length 96 XS7 XS6 XS5 XS4 XS3 XS2 XS1 XS0

(1) (1) (1) (1)

XS11 XS10 XS9 XS8

Vertical input window start 98 YO7 YO6 YO5 YO4 YO3 YO2 YO1 YO0

(1) (1) (1) (1)

YO11 YO10 YO9 YO8

Vertical input window length 9A YS7 YS6 YS5 YS4 YS3 YS2 YS1 YS0

(1) (1) (1) (1)

YS11 YS10 YS9 YS8

Horizontal output window length 9C XD7 XD6 XD5 XD4 XD3 XD2 XD1 XD0

(1) (1) (1) (1)

XD11 XD10 XD9 XD8

Vertical output window length 9E YD7 YD6 YD5 YD4 YD3 YD2 YD1 YD0

(1) (1) (1) (1)

YD11 YD10 YD9 YD8

Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive

comb ﬁlter and component video input

SAA7118

Page 99

2001 May 30 99

SUB

ADDR.

D7 D6 D5 D4 D3 D2 D1 D0

(HEX)

FIR ﬁltering and prescaling

Horizontal prescaling A0 Accumulation length A1 Prescaler DC gain and FIR

A2 PFUV1 PFUV0 PFY1 PFY0 XC2_1 XDCG2 XDCG1 XDCG0

(1) (1) (1) (1)

XPSC5 XPSC4 XPSC3 XPSC2 XPSC1 XPSC0

XACL5 XACL4 XACL3 XACL2 XACL1 XACL0

preﬁlter control Reserved A3

(1) (1) (1) (1) (1) (1) (1) (1)

Luminance brightness control A4 BRIG7 BRIG6 BRIG5 BRIG4 BRIG3 BRIG2 BRIG1 BRIG0 Luminance contrast control A5 CONT7 CONT6 CONT5 CONT4 CONT3 CONT2 CONT1 CONT0 Chrominance saturation control A6 SATN7 SATN6 SATN5 SATN4 SATN3 SATN2 SATN1 SATN0 Reserved A7

(1) (1) (1) (1) (1) (1) (1) (1)

Horizontal phase scaling

Horizontal luminance scaling increment

Horizontal luminance phase

A8 XSCY7 XSCY6 XSCY5 XSCY4 XSCY3 XSCY2 XSCY1 XSCY0 A9

(1) (1) (1)

XSCY12 XSCY11 XSCY10 XSCY9 XSCY8

AA XPHY7 XPHY6 XPHY5 XPHY4 XPHY3 XPHY2 XPHY1 XPHY0

offset Reserved AB Horizontal chrominance scaling

increment Horizontal chrominance phase

AC XSCC7 XSCC6 XSCC5 XSCC4 XSCC3 XSCC2 XSCC1 XSCC0 AD

AE XPHC7 XPHC6 XPHC5 XPHC4 XPHC3 XPHC2 XPHC1 XPHC0

(1) (1) (1) (1) (1) (1) (1) (1)

(1) (1) (1)

XSCC12 XSCC11 XSCC10 XSCC9 XSCC8

offset Reserved AF

(1) (1) (1) (1) (1) (1) (1) (1)

Vertical scaling

Vertical luminance scaling increment

Vertical chrominance scaling increment

Vertical scaling mode control B4 Reserved B5 to B7 Vertical chrominance phase

B0 YSCY7 YSCY6 YSCY5 YSCY4 YSCY3 YSCY2 YSCY1 YSCY0 B1 YSCY15 YSCY14 YSCY13 YSCY12 YSCY11 YSCY10 YSCY9 YSCY8 B2 YSCC7 YSCC6 YSCC5 YSCC4 YSCC3 YSCC2 YSCC1 YSCC0 B3 YSCC15 YSCC14 YSCC13 YSCC12 YSCC11 YSCC10 YSCC9 YSCC8

(1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1)

YMIR

(1) (1) (1)

B8 YPC07 YPC06 YPC05 YPC04 YPC03 YPC02 YPC01 YPC00

offset ‘00’

YMODE

Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive

comb ﬁlter and component video input

SAA7118

Page 100

2001 May 30 100

SUB

Vertical chrominance phase offset ‘01’

Vertical chrominance phase offset ‘10’

Vertical chrominance phase offset ‘11’

Vertical luminance phase offset ‘00’

Vertical luminance phase offset ‘01’

Vertical luminance phase offset ‘10’

Vertical luminance phase offset ‘11’

TASK B DEFINITION REGISTERS C0H TO EFH

ADDR.

(HEX)

B9 YPC17 YPC16 YPC15 YPC14 YPC13 YPC12 YPC11 YPC10

BA YPC27 YPC26 YPC25 YPC24 YPC23 YPC22 YPC21 YPC20

BB YPC37 YPC36 YPC35 YPC34 YPC33 YPC32 YPC31 YPC30

BC YPY07 YPY06 YPY05 YPY04 YPY03 YPY02 YPY01 YPY00

BD YPY17 YPY16 YPY15 YPY14 YPY13 YPY12 YPY11 YPY10

BE YPY27 YPY26 YPY25 YPY24 YPY23 YPY22 YPY21 YPY20

BF YPY37 YPY36 YPY35 YPY34 YPY33 YPY32 YPY31 YPY30

D7 D6 D5 D4 D3 D2 D1 D0

Basic settings and acquisition window deﬁnition

Task handling control C0 CONLH OFIDC FSKP2 FSKP1 FSKP0 RPTSK STRC1 STRC0 X-port formats and conﬁguration C1 CONLV HLDFV SCSRC1 SCSRC0 SCRQE FSC2 FSC1 FSC0 Input reference signal deﬁnition C2 XFDV XFDH XDV1 XDV0 XCODE XDH XDQ XCKS I-port formats and conﬁguration C3 ICODE I8_16 FYSK FOI1 FOI0 FSI2 FSI1 FSI0 Horizontal input window start C4 XO7 XO6 XO5 XO4 XO3 XO2 XO1 XO0

Horizontal input window length C6 XS7 XS6 XS5 XS4 XS3 XS2 XS1 XS0

Vertical input window start C8 YO7 YO6 YO5 YO4 YO3 YO2 YO1 YO0

Vertical input window length CA YS7 YS6 YS5 YS4 YS3 YS2 YS1 YS0

Horizontal output window length CC XD7 XD6 XD5 XD4 XD3 XD2 XD1 XD0

(1) (1) (1) (1)

XO11 XO10 XO9 XO8

XS11 XS10 XS9 XS8

YO11 YO10 YO9 YO8

YS11 YS10 YS9 YS8

XD11 XD10 XD9 XD8

Philips Semiconductors Preliminary speciﬁcation

Multistandard video decoder with adaptive

comb ﬁlter and component video input

SAA7118

Datasheet SAA7118E, SAA7118H Datasheet (Philips)

Specifications and Main Features

Frequently Asked Questions

User Manual