Datasheet SAA7114H-V1 Datasheet (Philips)

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Page 1

DATA SH EET

Preliminary speciﬁcation File under Integrated Circuits, IC22

2000 Mar 15

INTEGRATED CIRCUITS

SAA7114H

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler

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2000 Mar 15 2

Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

CONTENTS

1 FEATURES

1.1 Video decoder

1.2 Video scaler

1.3 Vertical Blanking Interval (VBI) data decoder and slicer

1.4 Audio clock generation

1.5 Digital I/O interfaces

1.6 Miscellaneous

2 APPLICATIONS 3 GENERAL DESCRIPTION 4 QUICK REFERENCE DATA 5 ORDERING INFORMATION 6 BLOCK DIAGRAM 7 PINNING 8 FUNCTIONAL DESCRIPTION

8.1 Decoder

8.2 Decoder output formatter

8.3 Scaler

8.4 VBI-data decoder and capture (subaddresses 40H to 7FH)

8.5 Image port output formatter (subaddresses 84H to 87H)

8.6 Audio clock generation (subaddresses 30H to 3FH)

9 INPUT/OUTPUT INTERFACES AND PORTS

9.1 Analog terminals

9.2 Audio clock signals

9.3 Clock and real-time synchronization signals

9.4 Video expansion port (X-port)

9.5 Image port (I-port)

9.6 Host port for 16-bit extension ofvideodata I/O (H-port)

9.7 Basic input and output timing diagrams I-port and X-port

10 BOUNDARY SCAN TEST

10.1 Initialization of boundary scan circuit

10.2 Device identification codes 11 LIMITING VALUES 12 THERMAL CHARACTERISTICS 13 CHARACTERISTICS 14 APPLICATION INFORMATION 15 I2C-BUS DESCRIPTION

15.1 I2C-bus format

15.2 I2C-bus details

15.3 Programming register audio clock generation

15.4 Programming register VBI-data slicer

15.5 Programming register interfaces and scaler part

16 PROGRAMMING START SET-UP

16.1 Decoder part

16.2 Audio clock generation part

16.3 Data slicer and data type control part

16.4 Scaler and interfaces

17 PACKAGE OUTLINE 18 SOLDERING

18.1 Introduction to soldering surface mount packages

18.2 Reflow soldering

18.3 Wave soldering

18.4 Manual soldering

18.5 Suitability of surface mount IC packages for wave and reflow soldering methods

19 DEFINITIONS 20 LIFE SUPPORT APPLICATIONS 21 PURCHASE OF PHILIPS I2C COMPONENTS

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Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

1 FEATURES

1.1 Video decoder

• Six analog inputs, internal analog source selectors, e.g. 6 × CVBS or (2 × Y/C and 2 × CVBS) or (1 × Y/C and 4 × CVBS)

• Two analog preprocessing channels in differential CMOS style inclusive built-in analog anti-alias filters

• Fully programmable static gain or Automatic Gain Control (AGC) for the selected CVBS or Y/C channel

• Automatic Clamp Control (ACC) for CVBS, Y and C

• Switchable white peak control

• Two 9-bit video CMOS Analog-to-Digital Converters

(ADCs), digitized CVBS or Y/C signals are available on the expansion port

• On-chip line-locked clock generation according

“ITU 601”

• Digital PLL for synchronization and clock generation from all standards and non-standard video sources e.g. consumer grade VTR

• Requires only one crystal (32.11 or 24.576 MHz) for all standards

• Horizontal and vertical sync detection

• Automatic detection of 50 and 60 Hz field frequency,

and automatic switching between PAL and NTSC standards

• Luminance and chrominance signal processing for PAL BGDHIN, combination PAL N, PAL M, NTSC M, NTSC-Japan, NTSC 4.43 and SECAM

• Adaptive 2/4-line comb filter for two dimensional chrominance/luminance separation

– Increasedluminanceandchrominancebandwidthfor

all PAL and NTSC standards

– Reduced cross colour and cross luminance artefacts

• PAL delay line for correcting PAL phase errors

• Independent Brightness Contrast Saturation (BCS)

adjustment for decoder part

• User programmable sharpness control

• Independent gain and offset adjustment for raw data

path.

1.2 Video scaler

• Horizontal and vertical down-scaling and up-scaling to randomly sized windows

• Horizontal and vertical scaling range: variable zoom to

⁄64(icon); it should be noted that the H and V zoom are

restricted by the transfer data rates

• Anti-alias and accumulating filter for horizontal scaling

• Vertical scaling with linear phase interpolation and

accumulating filter for anti-aliasing (6-bit phase accuracy)

• Horizontal phase correct up and down scaling for improved signal quality of scaled data, especially for compression and video phone applications, with 6-bit phase accuracy (1.2 ns step width)

• Two independent programming sets for scaler part, to define two ‘ranges’ per field or sequences over frames

• Fieldwise switching between decoder part and expansion port (X-port) input

• Brightness, contrast and saturation controls for scaled outputs.

1.3 Vertical Blanking Interval (VBI) data decoder

and slicer

• Versatile VBI-data decoder, slicer, clock regeneration and byte synchronization e.g. for World Standard Teletext (WST), North-American Broadcast Text System(NABTS),closecaption,WideScreen Signalling (WSS) etc.

1.4 Audio clock generation

• Generation of a field locked audio master clock to support a constant number of audio clocks per video field

• Generation of an audio serial and left/right (channel) clock signal.

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Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

1.5 Digital I/O interfaces

• Real-time signal port (R port), inclusive continuous line-locked reference clock and real-time status information supporting RTC level 3.1 (refer to external document

“RTC Functional Specification”

for details)

• Bi-directional expansion port (X-port) with half duplex functionality (D1), 8-bit YUV

– Output from decoder part, real-time and unscaled – Input to scaler part, e.g. video from MPEG decoder

(extension to 16-bit possible)

• Video image port (I-port) configurable for 8-bit data (extension to 16-bit possible) in master mode (own clock), or slave mode (external clock), with auxiliary timing and hand shake signals

• Discontinuous data streams supported

• 32-word × 4-byte FIFO register for video output data

• 28-word × 4-byte FIFO register for decoded VBI output

data

• Scaled 4:2:2, 4:1:1, 4:2:0, 4:1:0 YUV output

• Scaled 8-bit luminance only and raw CVBS data output

• Sliced, decoded VBI-data output.

1.6 Miscellaneous

• Power-on control

• 5 V tolerant digital inputs and I/O ports

• Software controlled power saving standby modes

supported

• Programming via serial I2C-bus, full read-back ability by an external controller, bit rate up to 400 kbits/s

• Boundary scan test circuit complies with the

“IEEE Std.

1149.b1 - 1994”

2 APPLICATIONS

• Desktop video

• Multimedia

• Digital television

• Image processing

• Video phone applications.

3 GENERAL DESCRIPTION

The SAA7114H is a video capture device for applications at the image port of VGA controllers.

The SAA7114H is a combination of a two-channel analog preprocessing circuit including source selection, anti-aliasing filter and ADC, an automatic clamp and gain control, a Clock Generation Circuit (CGC), a digital multi-standard decoder containing two-dimensional chrominance/luminance separation by an adaptive comb filter and a high performance scaler, including variable horizontal and vertical up and down scaling and a brightness, contrast and saturation control circuit.

It is a highly integrated circuit for desktop video applications. The decoder is based on the principle of line-lockedclock decoding and is abletodecode the colour of PAL, SECAM and NTSC signals into ITU 601 compatible colour component values. The SAA7114H accepts as analog inputs CVBS or S-video (Y/C) from TV or VCR sources, including weak and distorted signals. An expansion port (X-port) for digital video (bi-directional halfduplex,D1 compatible) is also supported to connect to MPEG or video phone codec. At the so called image port (I-port) the SAA7114H supports 8 or 16-bit wide output data with auxiliary reference data for interfacing to VGA controllers.

The target application for SAA7114H is to capture and scale video images, to be provided as digital video stream through the image port of a VGA controller, for display via VGA’s frame buffer, or for capture to system memory.

In parallel SAA7114H incorporates also provisions for capturing the serially coded data in the vertical blanking interval (VBI-data). Two principal functions are available:

1. To capture raw video samples, after interpolation to the required output data rate, via the scaler

2. A versatile data slicer (data recovery) unit.

SAA7114H incorporates also a field locked audio clock generation. This function ensures that there is always the same number of audio samples associated with a field, or a set of fields. This prevents the loss of synchronization between video and audio, during capture or playback.

The circuit is I2C-bus controlled (full write/read capability for all programming registers, bit rate up to 400 kbits/s).

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Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

4 QUICK REFERENCE DATA

Note

1. Power dissipation is measured in CVBS input mode (only one ADC active) and 8-bit image port output mode, expansion port is 3-stated.

5 ORDERING INFORMATION

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

DDD

digital supply voltage 3.0 3.3 3.6 V

DDDC

digital core supply voltage 3.0 3.3 3.6 V

DDA

analog supply voltage 3.1 3.3 3.5 V

amb

operating ambient temperature 0 − 70 °C

A+D

analog and digital power dissipation; note 1 − 0.45 − W

TYPE

NUMBER

PACKAGE

NAME DESCRIPTION VERSION

SAA7114H LQFP100 plastic low proﬁle quad ﬂat package; 100 leads; body 14 × 14 × 1.4 mm SOT407-1

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2000 Mar 15 6

Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC

comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

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6 BLOCK DIAGRAM

ll pagewidth

MHB528

FIR-PREFILTER

PRESCALER

AND

SCALER BCS

GENERAL PURPOSE

VBI-DATA SLICER

VIDEO/TEXT

ARBITER

TEXT FIFO

VIDEO

FIFO

PROGRAMMING

ARRAY

A/B

MUX

EVENT CONTROLLER

IMAGE PORT PIN MAPPING

X PORT I/O FORMATTING

EXPANSION PORT PIN MAPPING I/O CONTROL I2C-BUSREAL-TIME OUTPUT

LLC

AI2D

LINE FIFO

BUFFER

VERTICAL

SCALING

HORIZONTAL

FINE

(PHASE)

SCALING

to 8(16) MUX

ITRI

AGND

AI1D

AOUT

AI24

AI23

AI22

AI21

AI12

AI11

XTALO

XTALI

XTOUT

TCK

TMS

TDI

DD(XTAL)

SS(XTAL)

DDD(ICO1)

DDD(ICO6)

33, 43, 58, 68, 83, 93

DDD(EP1)

DDD(EP4)

1, 25, 51, 75

DDA0

DDA2

23, 17, 11

SSD(ICO1)

SSD(ICO3)

38, 63, 88

SSD(EP1)

SSD(EP4)

26, 50, 76, 100

SSA0

SSA2

24, 15, 9

AMXCLK

TDO

AMCLK

ALRCLK

ASCLK

LLC2

RTCO

RTS0

RTS1

XCLK

XDQ

81, 82, 84 to 87 89, 90

XRH

XRV

XRDY

SDA32SCL

TEST5

TEST4

TEST3

TEST2

TEST1

TEST0

64 to 67, 69 to 72

XTRI

chrominance of 16-bit input

BOUNDARY

SCAN

TEST

CLOCK GENERATION

AND

POWER-ON CONTROL

ANALOG

DUAL

ADC

DIGITAL

DECODER

WITH

ADAPTIVE

COMB

FILTER

AUDIO CLOCK

GENERATION

ITRDY

ICLK

IGP1

IGP0

IGPV

IGPH

IDQ

54 to 57, 59 to 62

IPD[7:0

]

HPD[7:0

]

XPD[7:0

]

RES

SAA7114H

TRST

(1)

Fig.1 Block diagram.

(1) The pins RTCO and ALRCLK are used for configuration of the I2C-bus interface

and the definition of the crystal oscillator frequency at RESET (pin strapping).

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Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

7 PINNING

SYMBOL PIN TYPE DESCRIPTION

DDD(EP1)

1 P external digital pad supply voltage 1 (+3.3 V) TDO 2 O test data output for boundary scan test; note 1 TDI 3 I test data input for boundary scan test; note 1 XTOUT 4 O crystal oscillator output signal; auxiliary signal V

SS(XTAL)

5 P ground for crystal oscillator XTALO 6 O 24.576 MHz (32.11 MHz) crystal oscillator output; not connected if TTL clock

input of XTALI is used

XTALI 7 I input terminal for 24.576 MHz (32.11 MHz) crystal oscillator or connection of

external oscillator with TTL compatible square wave clock signal

DD(XTAL)

8 P supply voltage for crystal oscillator V

SSA2

9 P ground for analog inputs AI2n AI24 10 I analog input 24 V

DDA2

11 P analog supply voltage for analog inputs AI2n (+3.3 V) AI23 12 I analog input 23 AI2D 13 I differential input for ADC channel 2 (pins AI24, AI23, AI22 and AI21) AI22 14 I analog input 22 V

SSA1

15 P ground for analog inputs AI1n AI21 16 I analog input 21 V

DDA1

17 P analog supply voltage for analog inputs AI1n (+3.3 V) AI12 18 I analog input 12 AI1D 19 I differential input for ADC channel 1 (pins AI12 and AI11) AI11 20 I analog input 11 AGND 21 P analog ground connection AOUT 22 O do not connect; analog test output V

DDA0

23 P analog supply voltage (+3.3 V) for internal Clock Generation Circuit (CGC) V

SSA0

24 P ground for internal clock generation circuit V

DDD(EP2)

25 P external digital pad supply voltage 2 (+3.3 V) V

SSD(EP1)

26 P external digital pad supply ground 1 CE 27 I chip enable or reset input (with internal pull-up) LLC 28 O line-locked system clock output (27 MHz nominal) LLC2 29 O line-locked

⁄2clock output (13.5 MHz nominal)

RES 30 O reset output (active LOW) SCL 31 I(/O) serial clock input (I

C-bus) with inactive output path

SDA 32 I/O serial data input/output (I

C-bus)

DDD(ICO1)

33 P internal digital core supply voltage 1 (+3.3 V) RTS0 34 O real-time status or sync information, controlled by subaddresses 11H and 12H;

see Section 15.2.18, 15.2.19 and 15.2.20

RTS1 35 O

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Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

RTCO 36 (I/)O real-time control output; contains information about actual system clock

frequency, ﬁeld rate, odd/even sequence, decoder status, subcarrier frequency and phase and PAL sequence (see external document

“RTC Functional

Description”

, available on request); the RTCO pin is enabled via I2C-bus

bit RTCE; see notes 2, 3 and Table 34 AMCLK 37 O audio master clock output, up to 50% of crystal clock V

SSD(ICO1)

38 P internal digital core supply ground 1 ASCLK 39 O audio serial clock output ALRCLK 40 (I/)O audio left/right clock output; can be strapped to supply via a 3.3kΩ resistor to

indicate that the default 24.576 MHz crystal (ALRCLK = 0; internal pull-down)

has been replaced by a 32.110 MHz crystal (ALRCLK = 1); see notes 2 and 4 AMXCLK 41 I audio master external clock input ITRDY 42 I target ready input, image port (with internal pull-up) V

DDD(ICO2)

43 P internal digital core supply voltage 2 (+3.3 V) TEST0 44 O do not connect; reserved for future extensions and for testing: scan output ICLK 45 I/O clock output signal for image port, or optional asynchronous back-end clock

input IDQ 46 O output data qualiﬁer for image port (optional: gated clock output) ITRI 47 I(/O) imageportoutput control signal, effects all input portpins inclusive ICLK, enable

and active polarity is under software control (bits IPE in subaddress 87H); output

path used for testing: scan output IGP0 48 O general purpose output signal 0; image port (controlled by subaddresses

84H and 85H) IGP1 49 O general purpose output signal 1; image port (controlled by subaddresses

84H and 85H) V

SSD(EP2)

50 P external digital pad supply ground 2

DDD(EP3)

51 P external digital pad supply voltage 3 (+3.3 V)

IGPV 52 O multi purpose vertical reference output signal; image port (controlled by

subaddresses 84H and 85H) IGPH 53 O multi purpose horizontal reference output signal; image port (controlled by

subaddresses 84H and 85H) IPD7 to IPD4 54 to 57 O image port data outputs V

DDD(ICO3)

58 P internal digital core supply voltage 3 (+3.3 V) IPD3 to IPD0 59 to 62 O image port data output V

SSD(ICO2)

63 P internal digital core supply ground 2 HPD7 to HPD4 64 to 67 I/O host port data I/O, carries UV chrominance information in 16-bit video I/O modes V

DDD(ICO4)

68 P internal digital core supply voltage 4 (+3.3 V) HPD3 to HPD0 69 to 72 I/O host port data I/O, carries UV chrominance information in 16-bit video I/O modes TEST1 73 I do not connect; reserved for future extensions and for testing: scan input TEST2 74 I do not connect; reserved for future extensions and for testing: scan input V

DDD(EP4)

75 P external digital pad supply voltage 4 (+3.3 V) V

SSD(EP3)

76 P external digital pad supply ground 3 TEST3 77 I do not connect; reserved for future extensions and for testing: scan input

SYMBOL PIN TYPE DESCRIPTION

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Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

Notes

1. In accordance with the

“IEEE1149.1”

standard the pads TDI, TMS, TCK and TRST are input pads with an internal

pull-up transistor and TDO is a 3-state output pad.

2. Pin strapping is done by connecting the pin to supply via a 3.3 kΩ resistor. During the power-up reset sequence the corresponding pins are switched to input mode to read the strapping level. For the default setting no strapping resistor is necessary (internal pull-down).

3. Pin RTCO: operates as I2C-bus slave address pin; RTCO = 0 slave address 42H/43H (default); RTCO = 1 slave address 40H/41H.

4. Pin ALRCLK: 0 = 24.576 MHz crystal (default); 1 = 32.110 MHz crystal.

5. For board design without boundary scan implementation connect the TRST pin to ground.

6. This pin provides easy initialization of the Boundary Scan Test (BST) circuit. TRST can be used to force the Test Access Port (TAP) controller to the TEST_LOGIC_RESET state (normal operation) at once.

TEST4 78 O do not connect; reserved for future extensions and for testing: scan output TEST5 79 I do not connect; reserved for future extensions and for testing: scan input XTRI 80 I X-port output control signal, affects all X-port pins (XPD7 to XPD0, XRH, XRV,

XDQ and XCLK), enable and active polarity is under software control (bits XPE

in subaddress 83H) XPD7 81 I/O expansion port data XPD6 82 I/O expansion port data V

DDD(ICO5)

83 P internal digital core supply voltage 5 (+3.3 V) XPD5 to XPD2 84 to 87 I/O expansion port data V

SSD(ICO3)

88 P internal digital core supply ground 3 XPD1 89 I/O expansion port data XPD0 90 I/O expansion port data XRV 91 I/O vertical reference I/O expansion port XRH 92 I/O horizontal reference I/O expansion port V

DDD(ICO6)

93 P internal digital core supply voltage 6 (+3.3 V) XCLK 94 I/O clock I/O expansion port XDQ 95 I/O data qualiﬁer I/O expansion port XRDY 96 O task ﬂag or ready signal from scaler, controlled by XRQT TRST 97 I test reset input (active LOW), for boundary scan test (with internal pull-up);

notes 5 and 6 TCK 98 I test clock for boundary scan test; note 1 TMS 99 I test mode select input for boundary scan test or scan test; note 1 V

SSD(EP4)

100 P external digital pad supply ground 4

SYMBOL PIN TYPE DESCRIPTION

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2000 Mar 15 10

Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

Fig.2 Pin configuration.

handbook, full pagewidth

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52

8079787776

XTRI

TEST5

TEST4

TEST3

SSD(EP3)

DDD(EP4)

TEST2 TEST1 HPD0 HPD1 HPD2 HPD3 V

DDD(ICO4)

HPD4 HPD5 HPD6 HPD7 V

SSD(ICO2)

IPD0 IPD1 IPD2 IPD3 V

DDD(ICO3)

IPD4 IPD5 IPD6 IPD7 IGPH IGPV V

DDD(EP3)

DDD(EP1)

TDO

TDI

XTOUT

SS(XTAL)

XTALO

XTALI

DD(XTAL)

SSA2

AI24

DDA2

AI23

AI2D

AI22

SSA1

AI21

DDA1

AI12

AI1D

AI11

AGND

AOUT

DDA0

SSA0

DDD(EP2)

SSD(EP4)

TMS

TCK

XRDY

XDQ

XCLK

DDD(ICO6)

XRH

XRV

XPD0

XPD1

SSD(ICO3)

XPD2

XPD3

XPD4

XPD5

DDD(ICO5)

XPD6

XPD7

SCL

SDA

DDD(ICO1)

RTS0

RTS1

RTCO

AMCLK

SSD(ICO1)

ASCLK

ALRCLK

AMXCLK

ITRDY

DDD(ICO2)

TEST0

ICLK

IDQ

ITRI

IGP0

IGP1

SSD(EP2)

SSD(EP1)

LLC

LLC2

100

99989796959493929190898887868584838281

31323334353637383940414243444546474849

SAA7114H

RES

TRST

MHB529

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2000 Mar 15 11

Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC

comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

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Table 1 8-bit/16-bit and alternative pin functional conﬁgurations

PIN SYMBOL

8-BIT

INPUT

MODES

16-BIT INPUT

MODES (ONLY

FOR I2C-BUS

PROGRAMMING)

ALTERNATIVE

INPUT

FUNCTIONS

8-BIT

OUTPUT

MODES

16-BIT OUTPUT

MODES (ONLY

FOR I2C-BUS

PROGRAMMING)

ALTERNATIVE

OUTPUT

FUNCTIONS

I/O

CONFIGURATION

PROGRAMMING

BITS

81, 82, 84 to 87, 89, 90

XPD7 to XPD0

D1 data input

Y data input D1

decoder output

XCODE[92H[3]] XPE[1:0]83H[1:0] + pin XTRI

94 XCLK clock

input

gated clock input

decoder clock output

XPE[1:0]83H[1:0] + pin XTRI XPCK[1:0]83H[5:4] XCKS[92H[0]]

95 XDQ data

qualiﬁer input

data qualiﬁer output (HREFand VREF gate)

XDQ[92H[1]] XPE[1:0]83H[1:0] + pin XTRI

96 XRDY input

ready output

active task A/B ﬂag

XRQT[83H[2]] XPE[1:0]83H[1:0] + pin XTRI

92 XRH horizontal

reference input

decoder horizontal reference output

XDH[92H[2]] XPE[1:0]83H[1:0] + pin XTRI

91 XRV vertical

reference input

decoder vertical reference output

XDV[1:0]92H[5:4] XPE[1:0]83H[1:0] + pin XTRI

80 XTRI output

enable input

XPE[1:0]83H[1:0]

64 to 67, 69 to 72

HPD7 to HPD0

UV data input UV scaler output ICODE[93H[7]]

ISWP[1:0]85H[7:6] I8_16[93H[6]] IPE[1:0]87H[1:0] + pin ITRI

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2000 Mar 15 12

Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC

comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

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54 to 57, 59 to 62

IPD7 to IPD0

D1 scaler output

Y scaler output ICODE[93H[7]]

ISWP[1:0]85H[7:6] I8_16[93H[6]] IPE[1:0]87H[1:0] + pin ITRI

45 ICLK clock

output

clock input ICKS[1:0]80H[1:0]

IPE[1:0]87H[1:0] + pin ITRI

46 IDQ data

qualiﬁer output

gated clock output

ICKS[3:2]80H[3:2] IDQP[85H[0]] IPE[1:0]87H[1:0] + pin ITRI

42 ITRDY target

ready input

53 IGPH H-gate

output

extended H-gate, horizontal pulses

IDH[1:0]84H[1:0] IRHP[85H[1]] IPE[1:0]87H[1:0] + pin ITRI

52 IGPV V-gate

output

V-sync, vertical pulses

IDV[1:0]84H[3:2] IRVP[85H[2]] IPE[1:0]87H[1:0] + pin ITRI

49 IGP1 general

purpose

IDG1[1:0]84H[5:4] IG1P[85H[3]] IPE[1:0]87H[1:0] + pin ITRI

48 IGP0 general

purpose

IDG0[1:0]84H[7:6] IG0P[85H[4]] IPE[1:0]87H[1:0] + pin ITRI

47 ITRI output

enable input

PIN SYMBOL

8-BIT

INPUT

MODES

16-BIT INPUT

MODES (ONLY

FOR I

C-BUS

PROGRAMMING)

ALTERNATIVE

INPUT

FUNCTIONS

8-BIT

OUTPUT

MODES

16-BIT OUTPUT

MODES (ONLY

FOR I2C-BUS

PROGRAMMING)

ALTERNATIVE

OUTPUT

FUNCTIONS

I/O

CONFIGURATION

PROGRAMMING

BITS

Page 13

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Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

8 FUNCTIONAL DESCRIPTION

8.1 Decoder

8.1.1 ANALOG INPUT PROCESSING The SAA7114H offers six analog signal inputs, two analog

main channels with source switch, clamp circuit, analog amplifier, anti-alias filter and video 9-bit CMOS ADC; see Fig.6.

8.1.2 ANALOG CONTROL CIRCUITS The anti-alias filters are adapted to the line-locked clock

frequency via a filter control circuit. The characteristics are shown in Fig.3. During the vertical blanking period, gain and clamping control are frozen.

Fig.3 Anti-alias filter.

handbook, full pagewidth

(dB)

−42 024 68101214

f (MHz)

MGD138

−6

−12

−18

−24

−30

−36

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Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

8.1.2.1 Clamping

The clamp control circuit controls the correct clamping of the analog input signals. The coupling capacitor is also used to store and filter the clamping voltage. An internal digital clamp comparator generates the information with respect to clamp-up or clamp-down. The clamping levels for the two ADC channels are fixed for luminance (60) and chrominance (128). Clamping time in normal use is set with the HCL pulse at the back porch of the video signal.

8.1.2.2 Gain control

The gain control circuit receives (via the I2C-bus) the static gain levels for the two analog amplifiers or controls one of theseamplifiersautomaticallyviaabuilt-inAutomaticGain Control (AGC) as part of the Analog Input Control (AICO).

The AGC (automatic gain control for luminance) is used to amplify a CVBS or Y signal to the required signal amplitude, matched to the ADCs input voltage range. The AGCactive time is the sync bottom ofthe video signal.

Signal (white) peak control limits the gain at signal overshoots.Theflow charts (see Figs 7 and 8) show more details of the AGC. The influence of supply voltage variation within the specified range is automatically eliminated by clamp and automatic gain control.

Fig.4 Analog line with clamp (HCL) and gain

range (HSY).

handbook, halfpage

HCL

MGL065

HSY

analog line blanking

TV line

255

GAIN CLAMP

Fig.5 Automatic gain range.

handbook, halfpage

analog input level

controlled

ADC input level

maximum

minimum

range 9 dB

0 dB

MHB325

+3 dB

−6 dB

(1 V (p-p) 18/56 Ω)

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2000 Mar 15 15

Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC

comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

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dbook, full pagewidth

MHB530

HOLDG GAFIX WPOFF GUDL0-GUDL2 GAI20-GAI28 GAI10-GAI18 HLNRS UPTCV

MODE 3 MODE 2 MODE 1 MODE 0

HSY

HCL

GLIMB GLIMT WIPA SLTCA

ANALOG CONTROL

VBSL

SOURCE

SWITCH

CLAMP

CIRCUIT

ANALOG

AMPLIFIER

DAC9

ANTI-ALIAS

FILTER

BYPASS

SWITCH

ADC2

SOURCE

SWITCH

CLAMP

CIRCUIT

ANALOG

AMPLIFIER

DAC9

ANTI-ALIAS

FILTER

BYPASS

SWITCH

ADC1

VBLNK SVREF

CROSS MULTIPLEXER

VERTICAL BLANKING CONTROL

CLAMP

CONTROL

GAIN

CONTROL

ANTI-ALIAS

CONTROL

MODE

CONTROL

FUSE [1:0

]

FUSE [1:0

]

AOSL [1:0

]

AGND

CVBS/CHRCVBS/LUM

AD1BYPAD2BYP

9999

AOUT

18 19 20

15 9

13 10, 12,

14, 16

17 11

AI2D

AI12

AI24 to AI21

AI1D AI11

TEST

SELECTOR

AND

BUFFER

DDA1

SSA2

DDA2

SSA1

Fig.6 Analog input processing using the SAA7114H as differential front-end with 9-bit ADC.

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Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

Fig.7 Gain flow chart.

handbook, full pagewidth

ANALOG INPUT

AMPLIFIER

ANTI-ALIAS FILTER

ADC

LUMA/CHROMA DECODER

HSY

254

248

X = 0

X = 1

−1/LLC2

+1/LLC2 −1/LLC2

+/− 0

+1/F

+1/L

GAIN ACCUMULATOR (18 BITS)

ACTUAL GAIN VALUE 9-BIT (AGV) [−3/+6 dB

]

STOP

HSY

UPDATE

FGV

MHB531

AGV

GAIN VALUE 9-BIT

VBLK

NO ACTION

DAC

gain

HOLDG

X = system variable. Y = (IAGV − FGVI) > GUDL. VBLK = vertical blanking pulse. HSY = horizontal sync pulse. AGV = actual gain value. FGV = frozen gain value.

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Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

Fig.8 Clamp and gain flow chart.

WIPE = white peak level (254). SBOT = sync bottom level (1). CLL = clamp level [60 Y (128 C)]. HSY = horizontal sync pulse. HCL = horizontal clamp pulse.

handbook, full pagewidth

+ CLAMP − CLAMP

NO CLAMP

10 10

01 10

MGC647

fast − GAIN

slow + GAIN

+ GAIN − GAIN

HCL HSY

ADC

SBOT

WIPE

CLL

ANALOG INPUT

GAIN -><- CLAMP

VBLK

NO BLANKING ACTIVE

Page 18

2000 Mar 15 18

Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC

comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

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8.1.3 CHROMINANCE AND LUMINANCE PROCESSING

dbook, full pagewidth

MHB532

CVBS-IN

or CHR-IN

CODE

SECS

HUEC

DCVF

QUADRATURE

DEMODULATOR

PAL DELAY LINE

SECAM

RECOMBINATION

PHASE

DEMODULATOR

AMPLITUDE DETECTOR

BURST GATE

ACCUMULATOR

LOOP FILTER

LOW-PASS 1

DOWNSAMPLING

SUBCARRIER

GENERATION 2

FCTC

ACGC

CGAIN[6:0

]

IDEL[3:0

]

INCS

RTCO

UV-

ADJUSTMENT

SECAM

PROCESSING

fH/2 switch signal

ADAPTIVE

COMB FILTER

CCOMB YCOMB

LDEL BYPS

LUFI[3:0

]

CSTD[2:0

]

YDEL[2:0

]

LOW-PASS 2

CHBW

CHROMA

GAIN

CONTROL

INTERPOLATION

LOW-PASS 3

LUBW

QUADRATURE

MODULATOR

CDTO

CSTD[2:0

]

SUBCARRIER

GENERATION 1

CHROMINANCE

INCREMENT

DTO-RESET

SUBCARRIER

INCREMENT

GENERATION

AND

DIVIDER

CHROMINANCE

INCREMENT

DELAY

LDEL YCOMB

SUBTRACTOR

DELAY

COMPENSATION

CVBS-IN

or Y-IN

CHR

LUMINANCE-PEAKING

LOW-PASS,

Y-DELAY ADJUSTMENT

LCBW[2:0

]

Y/CVBS

DBRI[7:0

]

DCON[7:0

]

DSAT[7:0

]

RAWG[7:0

]

RAWO[7:0

]

COLO

BRIGHTNESS

CONTRAST

SATURATION

CONTROL

RAW DATA

GAIN AND

OFFSET

CONTROL

LDEL

YCOMB

Y-OUT/ CVBS OUT

UV-OUT

HREF-OUT

SET_RAW

SET_VBI

SET_RAW

SET_VBI

SET_RAW

SET_VBI

SET_RAW

SET_VBI

Fig.9 Chrominance and luminance processing.

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Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

8.1.3.1 Chrominance path

The 9-bit CVBS or chrominance input signal is fed to the inputofa quadrature demodulator, where it is multiplied by twotime-multiplexed subcarrier signalsfromthe subcarrier generation block 1 (0° and 90° phase relationship to the demodulator axis). The frequency is dependent on the chosen colour standard.

The time-multiplexed output signals of the multipliers are low-pass filtered (low-pass 1). Eight characteristics are programmable via LCWB3 to LCWB0 to achieve the desired bandwidth for the colour difference signals (PAL, NTSC) or the 0° and 90° FM signals (SECAM).

Thechrominance low-pass 1characteristicalso influences the grade of cross-luminance reduction during horizontal colour transients (large chrominance bandwidth means strong suppression of cross-luminance). If the Y-comb filterisdisabledbyYCOMB = 0thefilterinfluencesdirectly the width of the chrominance notch within the luminance path (large chrominance bandwidth means wide chrominance notch resulting to lower luminance bandwidth).

The low-pass filtered signals are fed to the adaptive comb filter block. The chrominance components are separated from the luminance via a two line vertical stage (four lines for PAL standards) and a decision logic between the filtered and the non-filtered output signals. This block is bypassed for SECAM signals. The comb filter logic can be enabled independently for the succeeding luminance and chrominance processing by YCOMB (subaddress 09H, bit 6) and/or CCOMB (subaddress 0EH, bit 0). It is always bypassed during VBI or raw data lines programmable by the LCRn registers (subaddresses 41H to 57H), see Section 8.2.

TheseparatedUV-componentsarefurtherprocessedbya secondfilterstage(low-pass 2)tomodifythechrominance bandwidth without influence to the luminance path. It’s characteristic is controlled by CHBW (subaddress 10H, bit 3). For the complete transfer characteristic of low-passes 1 and 2 see Figs 10 and 11.

The SECAM processing (bypassed for QUAM standards) contains the following blocks:

• Baseband ‘bell’ filters to reconstruct the amplitude and phase equalized 0° and 90° FM signals

• Phase demodulator and differentiator (FM-demodulation)

• De-emphasis filter to compensate the pre-emphasized input signal, including frequency offset compensation (DB or DR white carrier values are subtracted from the signal, controlled by the SECAM switch signal).

The succeeding chrominance gain control block amplifies or attenuates the UV-signal according to the required ITU 601/656 levels. It is controlled by the output signal from the amplitude detection circuit within the burst processing block.

The burst processing block provides the feedback loop of the chrominance PLL and contains:

• Burst gate accumulator

• Colour identification and killer

• Comparison nominal/actual burst amplitude

(PAL/NTSC standards only)

• Loop filter chrominance gain control (PAL/NTSC standards only)

• Loop filter chrominance PLL (only active for PAL/NTSC standards)

• PAL/SECAM sequence detection, H/2-switch generation.

The increment generation circuit produces the Discrete Time Oscillator (DTO) increment for both subcarrier generation blocks. It contains a division by the increment of the line-locked clock generator to create a stable phase-locked sine signal under all conditions (e.g. for non-standard signals).

The PAL delay line block eliminates crosstalk between the chrominance channels in accordance with the PAL standard requirements. For NTSC colour standards the delay line can be used as an additional vertical filter. If desired, it can be switched off by DCVF = 1. It is always disabledduringVBIorrawdata lines programmable by the LCRn registers (subaddresses 41H to 47H), see Section 8.2. The embedded line delay is also used for SECAM recombination (cross-over switches).

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Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

handbook, full pagewidth

MHB533

−60

−57

−54

−51

−48

−45

−42

−39

−36

−33

−30

−27

−24

−21

−18

−15

−12

−9

−6

−3

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0

(dB)

f (MHz)

−60

−57

−54

−51

−48

−45

−42

−39

−36

−33

−30

−27

−24

−21

−18

−15

−12

−9

−6

−3

(dB)

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0

f (MHz)

(1) (2) (3) (4)

(5) (6) (7) (8)

Fig.10 Transfer characteristics of the chrominance low-pass at CHBW = 0.

(1) LCBW[2:0] = 000. (2) LCBW[2:0] = 010. (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110.

(5) LCBW[2:0] = 001. (6) LCBW[2:0] = 011. (7) LCBW[2:0] = 101. (8) LCBW[2:0] = 111.

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2000 Mar 15 21

Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

handbook, full pagewidth

MHB534

−60

−57

−54

−51

−48

−45

−42

−39

−36

−33

−30

−27

−24

−21

−18

−15

−12

−9

−6

−3

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0

(dB)

f (MHz)

−60

−57

−54

−51

−48

−45

−42

−39

−36

−33

−30

−27

−24

−21

−18

−15

−12

−9

−6

−3

(dB)

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0

f (MHz)

(1) (2) (3) (4)

(5) (6) (7) (8)

Fig.11 Transfer characteristics of the chrominance low-pass at CHBW = 1.

(1) LCBW[2:0] = 000. (2) LCBW[2:0] = 010. (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110.

(5) LCBW[2:0] = 001. (6) LCBW[2:0] = 011. (7) LCBW[2:0] = 101. (8) LCBW[2:0] = 111.

Page 22

2000 Mar 15 22

Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

8.1.3.2 Luminance path

The rejection of the chrominance components within the 9-bit CVBS or Y input signal is done by subtracting the re-modulated chrominance signal from the CVBS input.

The comb filtered UV-components are interpolated (upsampled) by the low-pass 3 block. It’s characteristic is controlled by LUBW (subaddress 09H, bit 4) to modify the width of the chrominance ‘notch’ without influence to the chrominance path. The programmable frequency characteristics available in conjunction with the LCBW2 to LCBW0 settings can be seen in Figs 12 to 15. Notethatthesefrequencycurves are only valid for Y-comb disabled filter mode (YCOMB = 0). in comb filter mode the frequency response is flat. The centre frequency of the notch is automatically adapted to the chosen colour standard.

The interpolated UV-samples are multiplied by two time-multiplexed subcarrier signals from the subcarrier generation block 2. This second DTO is locked to the first subcarrier generator by an increment delay circuit matched to the processing delay, which is different for PAL and NTSC standards according to the chosen comb filter algorithm. The two modulated signals are finally added to build the re-modulated chrominance signal.

The frequency characteristic of the separated luminance signal can be further modified by the succeeding luminance filter block. It can be configured as peaking (resolution enhancement) or low-pass block by LUFI3 to LUFI0 (subaddress 09H, bits 3 to 0). The 16 resulting frequency characteristics can be seen in Fig.16. The LUFI3 to LUFI0 settings can be used as a user programmable sharpness control.

The luminance filter block also contains the adjustable Y-delay part; programmable by YDEL2 to YDEL0 (subaddress 11H, bits 2 to 0).

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Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

handbook, full pagewidth

MHB535

−60

−57

−54

−51

−48

−45

−42

−39

−36

−33

−30

−27

−24

−21

−18

−15

−12

−9

−6

−3

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0

(dB)

f (MHz)

−60

−57

−54

−51

−48

−45

−42

−39

−36

−33

−30

−27

−24

−21

−18

−15

−12

−9

−6

−3

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0

(dB)

f (MHz)

(5) (6) (7) (8)

(1) (2) (3) (4)

Fig.12 Transfer characteristics of the luminance notch filter in 3.58 MHz mode (Y-comb filter disabled) at

LUBW = 0.

(1) LCBW[2:0] = 000. (2) LCBW[2:0] = 010. (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110.

(5) LCBW[2:0] = 001. (6) LCBW[2:0] = 011. (7) LCBW[2:0] = 101. (8) LCBW[2:0] = 111.

Page 24

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Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

handbook, full pagewidth

MHB536

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0

−60

−57

−54

−51

−48

−45

−42

−39

−36

−33

−30

−27

−24

−21

−18

−15

−12

−9

−6

−3

(dB)

f (MHz)

−60

−57

−54

−51

−48

−45

−42

−39

−36

−33

−30

−27

−24

−21

−18

−15

−12

−9

−6

−3

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0

(dB)

f (MHz)

(5) (6) (7) (8)

(1) (2) (3) (4)

Fig.13 Transfer characteristics of the luminance notch filter in 3.58 MHz mode (Y-comb filter disabled) at

LUBW = 1.

(1) LCBW[2:0] = 000 (2) LCBW[2:0] = 010 (3) LCBW[2:0] = 100 (4) LCBW[2:0] = 110

(5) LCBW[2:0] = 001 (6) LCBW[2:0] = 011 (7) LCBW[2:0] = 101 (8) LCBW[2:0] = 111

Page 25

2000 Mar 15 25

Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

handbook, full pagewidth

MHB537

−60

−57

−54

−51

−48

−45

−42

−39

−36

−33

−30

−27

−24

−21

−18

−15

−12

−9

−6

−3

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0

(dB)

f (MHz)

−60

−57

−54

−51

−48

−45

−42

−39

−36

−33

−30

−27

−24

−21

−18

−15

−12

−9

−6

−3

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0

(dB)

f (MHz)

(5) (6) (7) (8)

(1) (2) (3) (4)

Fig.14 Transfer characteristics of the luminance notch filter in 4.43 MHz mode (Y-comb filter disabled) at

LUBW = 0.

(1) LCBW[2:0] = 000. (2) LCBW[2:0] = 010. (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110.

(5) LCBW[2:0] = 001. (6) LCBW[2:0] = 011. (7) LCBW[2:0] = 101. (8) LCBW[2:0] = 111.

Page 26

2000 Mar 15 26

Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

handbook, full pagewidth

MHB538

−60

−57

−54

−51

−48

−45

−42

−39

−36

−33

−30

−27

−24

−21

−18

−15

−12

−9

−6

−3

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0

(dB)

f (MHz)

−60

−57

−54

−51

−48

−45

−42

−39

−36

−33

−30

−27

−24

−21

−18

−15

−12

−9

−6

−3

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0

(dB)

f (MHz)

(5) (6) (7) (8)

(1) (2) (3) (4)

Fig.15 Transfer characteristics of the luminance notch filter in 4.43 MHz mode (Y-comb filter disabled) at

LUBW = 1.

(1) LCBW[2:0] = 000. (2) LCBW[2:0] = 010. (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110.

(5) LCBW[2:0] = 001. (6) LCBW[2:0] = 011. (7) LCBW[2:0] = 101. (8) LCBW[2:0] = 111.

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Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

handbook, full pagewidth

MHB539

−1

(dB)

f (MHz)

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

f (MHz)

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

(8)

(7)

(6)

(5)

(4)

(3)

(2)

(1)

(9) (10) (11) (12) (13) (14) (15) (16)

−39

−36

−33

−30

−27

−24

−21

−18

−15

−12

−9

−6

−3

Fig.16 Transfer characteristics of the luminance peaking/low-pass filter (sharpness).

(1) LUFI[3:0] = 0001. (2) LUFI[3:0] = 0010. (3) LUFI[3:0] = 0011. (4) LUFI[3:0] = 0100. (5) LUFI[3:0] = 0101. (6) LUFI[3:0] = 0110. (7) LUFI[3:0] = 0111. (8) LUFI[3:0] = 0000.

(9) LUFI[3:0] = 1000. (10) LUFI[3:0] = 1001. (11) LUFI[3:0] = 1010. (12) LUFI[3:0] = 1011. (13) LUFI[3:0] = 1100. (14) LUFI[3:0] = 1101. (15) LUFI[3:0] = 1110. (16) LUFI[3:0] = 1111.

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SAA7114H

8.1.3.3 Brightness Contrast Saturation (BCS) control and decoder output levels

The resulting Y (CVBS) and UV-signals are fed to the BCS block, which contains the following functions:

• Chrominance saturation control by DSAT7 to DSAT0

• Luminance contrast and brightness control by DCON7 to DCON0 and DBRI7 to DBRI0

• Raw data (CVBS) gain and offset adjustment by RAWG7 to RAWG0 and RAWO7 to RAWO0

• Limiting YUV or CVBS to the values 1 (minimum) and 254 (maximum) to fulfil

“ITU Recommendation 601/656”

Fig.17 YUV range for scaler input and X-port output.

“ITU Recommendation 601/656”

digital levels with default BCS (decoder) settings DCON[7:0] = 44H, DBRI[7:0] = 80H and DSAT[7:0] = 40H.

Equations for modification to the YUV levels via BCS control I2C-bus bytes DBRI, DCON and DSAT. Luminance:

Chrominance: It should be noted that the resulting levels are limited to 1 to 254 in accordance with

“ITU Recommendation 601/656”

OUT

Int

DCON

-----------------

Y 128–()× DBRI+=

OUT

Int

DSAT

--------------- -

CRCB, 128–()× 128+=

dbook, full pagewidth

LUMINANCE 100%

+255 +235

+128

+16

white

black

U-COMPONENT

+255 +240

+212 +212

+128

+16

+44

blue 100% blue 75%

yellow 75% yellow 100%

colourless

V-COMPONENT

+255 +240

+128

+16

+44

red 100% red 75%

cyan 75%

cyan 100%

colourless

MGC634

a. Y output range. b. U output range (CB). c. V output range (CR).

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SAA7114H

Fig.18 CVBS (raw data) range for scaler input, data slicer and X-port output.

CVBS levels with default settings RAWG[7:0] = 64 and RAWO[7:0] = 128. Equation for modification of the raw data levels via bytes RAWG and RAWO:

It should be noted that the resulting levels are limited to 1 to 254 in accordance with “

ITU Recommendation 601/656”

CVBS

OUT

Int

RAWG

------------------

CVBS

nom

128–()× RAWO+=

handbook, full pagewidth

LUMINANCE

+255 +209

+71

+60

white

sync bottom

black shoulder

black

SYNC

LUMINANCE

+255

+199

+60

white

sync bottom

black shoulder = black

SYNC

MGD700

a. Sources containing 7.5 IRE black level offset (e.g. NTSC M).

b. Sources not containing black level offset.

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SAA7114H

8.1.4 SYNCHRONIZATION The prefiltered luminance signal is fed to the

synchronization stage. Its bandwidth is further reduced to 1 MHz in a low-pass filter. The sync pulses are sliced and fed to the phase detectors where they are compared with the sub-divided clock frequency. The resulting output signal is applied to the loop filter to accumulate all phase deviations. Internal signals (e.g. HCL and HSY) are generated in accordance with analog front-end requirements. The loop filter signal drives an oscillator to generate the line frequency control signal LFCO, see Fig.19.

The detection of ‘pseudo syncs’ as part of the macrovision copy protection standard is also done within the synchronization circuit.

The result is reported as flag COPRO within the decoder status byte at subaddress 1FH.

8.1.5 CLOCK GENERATION CIRCUIT The internal CGC generates all clock signals required for

the video input processor.

The internal signal LFCO is a digital-to-analog converted signal provided by the horizontal PLL. It is the multiple of the line frequency:

6.75 MHz = 429 × fH (50 Hz), or

6.75 MHz = 432 × fH (60 Hz).

Internally the LFCO signal is multiplied by a factor of 2 and 4 in the PLL circuit (including phase detector, loop filtering, VCO and frequency divider) to obtain the output clock signals. The rectangular output clocks have a 50% duty factor.

Table 2 Decoder clock frequencies

CLOCK FREQUENCY (MHz)

XTALO 24.576 or 32.110 LLC 27 LLC2 13.5 LLC4 (internal) 6.75 LLC8 (virtual) 3.375

Fig.19 Block diagram of the clock generation circuit.

handbook, full pagewidth

BAND PASS

FC = LLC/4

ZERO

CROSS

DETECTION

PHASE

DETECTION

LOOP

FILTER

DIVIDER

1/2

DIVIDER

1/2

OSCILLATOR

MHB330

LLC2

LLC

LFCO

8.1.6 POWER-ON RESET AND CHIP ENABLE (CE) INPUT A missing clock, insufficient digital or analog V

DDA0

supply voltages (below 2.7 V) will start the reset sequence; all outputs are forced to 3-state (see Fig.20). The indicator output RES is LOW for about 128 LLC after the internal resetandcan be applied to reset other circuits of the digital TV system.

It is possible to force a reset by pulling the Chip Enable (CE) to ground. After the rising edge of CE and sufficient power supply voltage, the outputs LLC, LLC2 and SDA return from 3-state to active, while the other signals have to be activated via programming.

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SAA7114H

Fig.20 Power-on control circuit.

POC = Power-on Control. CE = chip enable input. XTALO = crystal oscillator output. LLCINT = internal system clock. RESINT = internal reset. LLC = line-locked clock output. RES = reset output

handbook, full pagewidth

MHB331

128 LCC

896 LCC

digital delay

some ms

20 to 200 µs

PLL-delay

1 ms

RES

(internal

reset)

LLC

RESINT

LLCINT

XTALO

POC V

DDA

POC

LOGIC

ANALOG

POC V

DDD

DIGITAL

POC

DELAY

CLOCK

PLL

LLC

CLK0

RESINT

RES

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SAA7114H

8.2 Decoder output formatter

The output interface block of the decoder part contains the ITU 656 formatter for the expansion port data output XPD7 to XPD0 (for a detailed description see Section 9.4.1) and the control circuit for the signals needed for the internal paths to the scaler and data slicer part. It also controls the selection of the reference signals for the RT port (RTCO, RTS0 and RTS1) and the expansion port (XRH, XRV and XDQ).

The generation of the decoder data type control signals SET_RAW and SET VBI is also done within this block. These signals are decoded from the requested data type for the scaler input and/or the data slicer, selectable by the control registers LCR2 to LCR24 (see also Chapter 15 “I2C-bus description”, subaddresses 41H to 57H).

For each LCR value from 2 to 23 the data type can be programmed individually. LCR2 to LCR23 refer to line numbers. The selection in LCR24 values is valid for the rest of the corresponding field. The upper nibble contains the value for field 1 (odd), the lower nibble for field 2 (even). The relationship between LCR values and line numbers can be adjusted via VOFF8 to VOFF0, locatedin subaddresses 5BH (bit 4) and 5AH (bits 7 to 0) and FOFF subaddress 5BH (bit D7). The recommended values are VOFF[8:0] = 03H for 50 Hz sources (with FOFF = 0) and VOFF[8:0] = 06H for 60 Hz sources (with FOFF = 1), to accommodate line number conventions as used for PAL, SECAM and NTSC standards; see Tables 4 to 7.

Table 3 Data formats at decoder output

DATA TYPE NUMBER DATA TYPE DECODER OUTPUT DATA FORMAT

0 teletext EuroWST, CCST raw 1 European closed caption raw 2 Video Programming Service (VPS) raw 3 Wide screen signalling bits raw 4 US teletext (WST) raw 5 US closed caption (line 21) raw 6 video component signal, VBI region YUV4:2:2 7 CVBS data raw 8 teletext raw

9 VITC/EBU time codes (Europe) raw 10 VITC/SMPTE time codes (USA) raw 11 reserved raw 12 US NABTS raw 13 MOJI (Japanese) raw 14 Japanese format switch (L20/22) raw 15 video component signal, active video region YUV4:2:2

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comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

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Table 4 Relationship of LCR to line numbers in 525 lines/60 Hz systems (part 1) Vertical line offset, VOFF[8:0]= 06H (subaddresses 5BH[4] and 5AH[7:0]); horizontal pixel offset, HOFF[10:0] = 347H (subaddresses 5BH[2:0] and 59H[7:0]); FOFF = 1 (subaddress 5BH[7])

Table 5 Relationship of LCR to line numbers in 525 lines/60 Hz systems (part 2) Vertical line offset, VOFF[8:0]= 06H (subaddresses 5BH[4] and 5AH[7:0]); horizontal pixel offset, HOFF[10:0] = 347H (subaddresses 5BH[2:0] and 59H[7:0]); FOFF = 1 (subaddress 5BH[7])

Table 6 Relationship of LCR to line numbers in 625 lines/50 Hz systems (part 1) Vertical line offset, VOFF[8:0]= 03H (subaddresses 5BH[4] and 5AH[7:0]); horizontal pixel offset, HOFF[10:0] = 347H (subaddresses 5BH[2:0] and 59H[7:0]); FOFF = 1 (subaddress 5BH[7])

Table 7 Relationship of LCR to line numbers in 625 lines/50 Hz systems (part 2) Vertical line offset, VOFF[8:0]= 03H (subaddresses 5BH[4] and 5AH[7:0]); horizontal pixel offset, HOFF[10:0] = 347H (subaddresses 5BH[2:0] and 59H[7:0]); FOFF = 1 (subaddress 5BH[7])

Linenumber (1st ﬁeld)

521 522 523 524 525 1 2 3 4 5 6 7 8 9

active video equalization pulses serration pulses equalization pulses

Linenumber (2nd ﬁeld)

259 260 261 262 263 264 265 266 267 268 269 270 271 272

active video equalization pulses serration pulses equalization pulses

LCR 24 23456789

Linenumber (1st ﬁeld)

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

nominal VBI-lines F1 active video

Linenumber (2nd ﬁeld)

273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288

nominal VBI-lines F2 active video

LCR 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Linenumber (1st ﬁeld)

62162262362462512345

active video equalization pulses serration pulses equalization pulses

Linenumber (2nd ﬁeld)

309 310 311 312 313 314 315 316 317 318

active video equalization pulses serration pulses equalization pulses

LCR 24 2345

Linenumber (1st ﬁeld)

678910111213141516171819202122232425

nominal VBI-lines F1 active video

Linenumber (2nd ﬁeld)

319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338

nominal VBI-lines F2 active video

LCR 67891011121314151617181920212223 24

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SAA7114H

Fig.21 Vertical timing diagram for 50 Hz/625 line systems.

(1) The inactive going edge of the V123 signal indicates whether the field is odd or even. If HREF is active during

the falling edge of V123, the field is ODD (field 1). If HREF is inactive during the falling edge of V123, the field is EVEN. The specific position of the slope is dependent on the internal processing delay and may change a few clock cycles from version to version.

The control signals listed above are available on pins RTS0, RTS1, XRH and XRV according to the following table:

For further information see Section 15.2: Tables 55, 56 and 57.

NAME RTS0 (PIN 34) RTS1 (PIN 35) XRH (PIN 92) XRV (PIN 91)

HREF XXX F_ITU656 −−−X V123 XX−X VGATE XX− FID XX−−

handbook, full pagewidth

MHB540

VGATE

VSTO[8:0] = 134H

VSTA[8:0] = 15H

(a) 1st field

CVBS

ITU counting

single field counting

1 1

2 2

3 3

4 4

5 5

6 6

7 7

... ...

22 22

625 312

624 311

623 310

622 309

23 23

FID

HREF

F_ITU656

V123

(1)

VGATE

CVBS

ITU counting

single field counting

FID

HREF

F_ITU656

V123

(1)

VSTO[8:0] = 134H

VSTA[8:0] = 15H

(b) 2nd field

313 313

31413152316331743185319

... ...

335

312 312

311 311

310 310

309 309

336

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PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

Fig.22 Vertical timing diagram for 60 Hz/525 line systems.

(1) The inactive going edge of the V123 signal indicates whether the field is odd or even. If HREF is active during

The control signals listed above are available on pins RTS0, RTS1, XRH and XRV according to the following table:

For further information see Section 15.2: Tables 55, 56 and 57.

NAME RTS0 (PIN 34) RTS1 (PIN 35) XRH (PIN 92) XRV (PIN 91)

HREF X X X − F_ITU656 −−−X V123 X X − X VGATE X X −− FID X X −−

handbook, full pagewidth

MHB541

VGATE

VSTO[8:0] = 101H

VSTA[8:0] = 011H

(a) 1st field

CVBS

ITU counting

single field counting

4 4

5 5

6 6

7 7

8 8

9910

... ...

21 21

3 3

2 2

1 1

525 262

22 22

FID

HREF

F_ITU656

V123

(1)

VGATE

CVBS

ITU counting

single field counting

FID

HREF

F_ITU656

V123

(1)

VSTO[8:0] = 101H

VSTA[8:0] = 011H

(b) 2nd field

266326742685269627072718272

... ...

284

265

264

263 263

262 262

285

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Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

Fig.23 Horizontal timing diagram (50/60 Hz).

The signals HREF, HS, CREF2 and CREF are available on pins RTS0 and/or RTS1 (see Section 15.2.19 Tables 55 and 56); their polarity can be inverted via RTP0 and/or RTP1.

The signals HREF and HS are available on pin XRH (see Section 15.2.20 Table 57).

handbook, full pagewidth

108

−107

107

−106

MHB542

CVBS input

140 × 1/LLC

5 × 2/LLC

expansion port

data output

12 × 2/LLC

720 × 2/LLC

144 × 2/LLC

138 × 2/LLC

720 × 2/LLC

burst

processing delay ADC to expansion port:

2 × 2/LLC

HREF (60 Hz)

HS (60 Hz)

sync clipped

16 × 2/LLC

1 × 2/LLC

programming range

(step size: 8/LLC)

programming range

(step size: 8/LLC)

HS (50 Hz)

HREF (50 Hz)

CREF

CREF2

CREF

CREF2

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SAA7114H

8.3 Scaler

TheHigh Performance video Scaler (HPS) is basedon the system as implemented in SAA7140, but enhanced in some aspects. Vertical upsampling is supported and the processing pipeline buffer capacity is enhanced, to allow more flexible video stream timing at the image port, discontinuoustransfers,and handshake. The internal data flow from block to block is discontinuous dynamically, due to the scaling process itself.

The flow is controlled by internal data valid and data request flags (internal handshake signalling) between the sub-blocks. Therefore the entire scaler acts as a pipeline buffer. Depending on the actually programmed scaling parameters the effective buffer can exceed to an entire line. The access/bandwidth requirements to the VGA frame buffer are reduced significantly.

The high performance video scaler in SAA7114H has the following major blocks.

• Acquisition control (horizontal and vertical timer) and task handling (the region/field/frame based processing)

• Prescaler, for horizontal down-scaling by an integer factor, combined with appropriate band limiting filters, especially anti-aliasing for CIF format

• Brightness,saturation,contrast control for scaled output data

• Line buffer, with asynchronous read and write, to support vertical up-scaling (e.g. for videophone application, converting 240 into 288 lines, YUV 4 : 2 : 2)

• Vertical scaling, with phase accurate Linear Phase Interpolation (LPI) for zoom and down-scale, or phase accurate Accumulation Mode (ACM) for large down-scaling ratios and better alias suppression

• Variable Phase Delay (VPD), operates as horizontal phase accurate interpolation for arbitrary non-integer scaling ratios, supporting conversion between square (SQR) and rectangular (CCIR) pixel sampling

• Output formatter for scaled YUV 4 : 2 : 2, YUV4:1:1 and Y only (format also for raw data)

• FIFO, 32-bit wide, with 64 pixel capacity in YUV formats

• Output interface, 8 or 16 (only if extended by H-port)

data pins wide, synchronous or asynchronous operation, with stream events on discrete pins, or coded in the data stream.

The overall H and V zooming (HV_zoom) is restricted by theinput/outputdata rate relations. With a safety margin of 2% for running in and running out, the maximum HV_zoom is equal to:

For example:

1. Input from decoder: 50 Hz, 720 pixel, 288 lines, 16-bit data at 13.5 MHz data rate, 1 cycle per pixel; output: 8-bit data at 27 MHz, 2 cycles per pixel; the maximum HV_zoom is equal to:

2. Input from X-port: 60 Hz, 720 pixel, 240 lines, 8-bit data at 27 MHz data rate (ITU 656), 2 cycles per pixel; output via I + H-port: 16-bit data at 27 MHz clock, 1 cycle per pixel; the maximum HV_zoom is equal to:

The video scaler receives its input signal from the video decoder or from the expansion port (X-port). It gets 16-bit YUV 4:2:2 input data at a continuous rate of 13.5 MHz from the decoder. Discontinuous data stream can be accepted from the expansion port (X-port), normally 8-bit wide ITU 656 like YUV data, accompanied by a pixel qualifier on XDQ.

Theinputdatastreamis sorted into two data paths, one for luminance (or raw samples), and one for time multiplexed chrominance U and V samples. An YUV 4:1:1 input format is converted to 4:2:2forthehorizontal prescaling and vertical filter scaling operation.

The scaler operation is defined by two programming pages A and B, representing two different tasks, that can be applied field alternating or to define two regions in a field (e.g. with different scaling range, factors, and signal source during odd and even fields).

Each programming page contains control:

• For signal source selection and formats

• For task handling and trigger conditions

• For input and output acquisition window definition

• For H-prescaler, V-scaler and H-phase scaling.

0.98

T_input_field T_v_blanking–

in_pixel in_lines× out_cycle_per_pix× T_out_clk×

--------------------------------------------------------------------------------------------------------------------------------------

0.98

20 ms 24 64 µs×–

720 288× 2× 37 ns×

--------------------------------------------------------

1.18=×

0.98

16.666 ms 22 64 µs×– 720 240× 1× 37 ns×

--------------------------------------------------------------

2.34=×

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SAA7114H

Raw VBI-data will be handled as specific input format and need an own programming page (= own task).

In VBI pass through operation the processing of prescaler and vertical scaling has to be set to no-processing, but the horizontal fine scaling VPD can be activated. Upscaling (oversampling, zooming), free of frequency folding, up to factor 3.5 can be achieved, as required by some software data slicing algorithms.

These raw samples are transported through the image port as valid data and can be output as Y only format. The lines are framed by SAV and EAV codes.

8.3.1 ACQUISITION CONTROL AND TASK HANDLING (SUBADDRESSES 80H, 90H, 94H TO 9FH AND C4H TO CFH)

The acquisition control receives horizontal and vertical synchronization signals from the decoder section or from the X-port. The acquisition window is generated via pixel and line counters at the appropriate places in the data path. From X-port only qualified pixels and lines (= lines with qualified pixel) are counted.

The acquisition window parameters are:

• Signal source selection regarding input video stream

and formats from the decoder, or from X-port (programming bits SCSRC[1:0]91H[5:4] and FSC[2:0]91H[2:0])

Remark: The input of raw VBI-data from internal decoder should be controlled via the decoder output formatter and the LCR registers (see Section 8.2 “Decoder output formatter”)

• Vertical offset defined in lines of the video source,

parameter YO[11:0]99H[3:0]98H[7:0]

• Vertical length defined in lines of the video source,

parameter YS[11:0]9BH[11:8]9AH[7:0]

• Vertical length defined in number of target lines, as

result of vertical scaling, parameter YD[11:0]9FH[11:8]9EH[7:0]

• Horizontaloffset defined in number of pixels ofthe video

source, parameter XO[11:0]95H[3:0]94H[7:0]

• Horizontal length defined in number of pixels of the

video source, parameter XS[11:0]97H[3:0]96H[7:0]

• Horizontal destination size, defined in target pixels after

fine scaling, parameter XD[11:0]9DH[3:0]9CH[7:0].

The source start offset (XO11 to XO0, YO11 to YO0) opens the acquisition window, and the target size

(XD11 to XD0, YD11 to YD0) closes the window, but the window is cut vertically, if there are less output lines than expected. The trigger events for the pixel and line counts are the horizontal and vertical reference edges as defined in subaddress 92H.

The task handling is controlled by subaddress 90H (see Section 8.3.1.2).

8.3.1.1 Input ﬁeld processing

The trigger event for the field sequence detection from external signals (X-port) are defined in subaddress 92H. From the X-port the state of the scalers H-reference signal at the time of the V-reference edge is taken as field sequence identifier FID. For example, if the falling edge of the XRV input signal is the reference and the state of XRH input is logic 0 at that time, the detected field ID is logic 0.

The bits XFDV[92H[7]] and XFDH[92H[6]] are defining the detection event and state of the flag from the X-port. For the default setting of XFDV and XFDH at ‘00’ the state of the H-input at the falling edge of the V-input is taken.

The scaler directly gets a corresponding field ID information from the SAA7114H decoder path.

The FID flag is used to determine, whether the first or second field of a frame is going to be processed within the scaler and it is used as trigger condition for the task handling (see bits STRC[1:0]90H[1:0]).

According to ITU 656, FID at logic 0 means first field of a frame. To ease the application, the polarities of the detection results on the X-port signals and the internal decoder ID can be changed via XFDH.

As the V-sync from the decoder path has a half line timing (due to the interlaced video signal), but the scaler processing only knows about full lines, during 1st fields fromthe decoder the line count of the scaler possibly shifts by one line, compared to the 2nd field. This can be compensated by switching the V-trigger event, as defined by XDV0, to the opposite V-sync edge or by using the vertical scalers phase offsets. The vertical timing of the decoder can be seen in Figs 21 and 22.

As the H and V reference events inside the ITU 656 data stream (from X-port) and the real-time reference signals from the decoder path are processed differently, the trigger events for the input acquisition also have to be programmed differently.

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PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

Table 8 Processing trigger and start

DESCRIPTION

XDV1

92H[5]

XDV0

92H[4]

XDH

92H[2]

Internal decoder: The processing triggers at the falling edge of the V123 pulse

(see Figs 21 (50 Hz) and 22 (60 Hz)), and starts earliest with the rising edge of the decoder HREF at line number:

4/7 (50/60 Hz, 1st field), respectively 3/6 (50/60 Hz, 2nd field) (decoder count) 0 1 0 2/5 (50/60 Hz, 1st field), respectively 2/5 (50/60 Hz, 2nd field) (decoder count) 0 0 0

External ITU 656 stream: The processing starts earliest with SAV at line number 23 (50 Hz system), respectively line 20 (60 Hz system) (according ITU 656 count)

000

8.3.1.2 Task handling

The task handler controls the switching between the two programming register sets. It is controlled by subaddresses 90H and C0H. A task is enabled via the global control bits TEA[80H[4]] and TEB[80H[5]].

The handler is then triggered by events, which can be defined for each register set.

In case of a programming error the task handling and the complete scaler can be reset to the initial states by the software reset bit SWRST[88H[5]] at logic 0.

Especiallyif the programming registers, related acquisition window and scale are reprogrammed, while a task is active, a software reset must be done after programming.

Contrary to the disabling/enabling of a task, which is evaluated at the end of a running task, SWRST at logic 0 sets the internal state machines directly to their idle states.

The start condition for the handler is defined by bits STRC[1:0]90H[1:0] and means: start immediately, wait for next V-sync, next FID at logic 0 or next FID at logic 1. The FID is evaluated, if the vertical and horizontal offsets are reached.

With RPTSK[90H[2]] at logic 1 the actual running task is repeated (under the defined trigger conditions), before handing control over to the alternate task.

To support field rate reduction, the handler is also enabled toskip fields (bits FSKP[2:0]90H[5:3])beforeexecuting the task. A TOGGLE flag is generated (used for the correct output field processing), which changes state at the beginning of a task, every time a task is activated. Examples can be seen in Section 8.3.1.3.

Remarks:

• To activate a task the start condition must be

fulfilled and the acquisition window offsets must be reached. For example, in case of ‘start immediately’,

and two regions are defined for one field, the offset of thelower region must be greater than (offset + length) of upper region, if not, the actual counted H and V position at the end of the upper task is beyond the programmed offsets and the processing will ‘wait for next V’.

• Basicallythe trigger conditions are checked, when a task is activated. It is important to realize, that they are

not checked, while a task is inactive. So you can not trigger to next logic 0 or logic 1 with overlapping offset and active video ranges between the tasks (e.g. task A STRC[2:0] = 2, YO[11:0] = 310 and task B STRC[2:0] = 3, YO[11:0] = 310 results in output field rate of50⁄3Hz).

• After power-on or software reset (via SWRST[88H[5]]) task B gets priority over task A.

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SAA7114H

8.3.1.3 Output ﬁeld processing

As reference for the output field processing, two signals are available for the back-end hardware.

These signals are the input field ID from the scaler source and a TOOGLE flag, which shows, that an active task is used an odd (1, 3, 5...) or even (2, 4, 6...) number of times. Usingasingleorboth tasks and reducing the field or frame rate with the task handling functionality, the TOGGLE information can be used, to reconstruct an interlaced scaled picture at a reduced frame rate. The TOGGLE flag isn’t synchronized to the input field detection, as it is only dependent on the interpretation of this information by the external hardware, whether the output of the scaler is processed correctly (see Section 8.3.3).

With OFIDC = 0, the scalers input field ID is available as output field ID on bit D6 of SAV and EAV, respectively on pin IGP0 (IGP1), if FID output is selected.

When OFIDC[90H[6]] = 1, the TOGGLE information is available as output field ID on bit D6 of SAV and EAV, respectively on pin IGP0 (IGP1), if FID output is selected.

Additionally the bit D7 of SAV and EAV can be defined via CONLH[90H[7]]. CONLH[90H[7]] = 0 (default) sets D7 to logic 1, a logic 1 inverts the SAV/EAV bit D7. So it’s possible to mark the output of the both tasks by different SAV/EAV codes. This bit can also beseen as ‘task flag’ on the pins IGP0 (IGP1), if TASK output is selected.

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comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

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Table 9 Examples for ﬁeld processing

Notes

1. Single task every field; OFIDC= 0; subaddress 90H at 40H; TEB[80H[5]] = 0.

2. Tasks are used to scale to different output windows, priority on task B after SWRST.

3. Both tasks at1⁄2 frame rate; OFIDC = 0; subaddresses 90H at 43H and C0H at 42H.

4. In examples 3and 4 the association between input FID and tasks can be flipped, dependent on which time the SWRST is de-asserted.

5. TaskB at2⁄3 frame rate constructed from neighbouring motion phases; task A at1⁄3 frame rate of equidistant motion phases; OFIDC = 1; subaddresses 90H at 41H and C0H at 45H.

6. TaskA and B at1⁄3 frame rate of equidistant motion phases; OFIDC = 1; subaddresses 90H at 41H and C0H at 49H.

7. State of prior field.

8. It is assumed that input/output FID = 0 (= upper lines); UP = upper lines; LO = lower lines.

9. O= data output; NO = no output.

SUBJECT

FIELD SEQUENCE FRAME/FIELD

EXAMPLE 1

(1)

EXAMPLE 2

(2)(3)

EXAMPLE 3

(2)(4)(5)

EXAMPLE 4

(2)(4)(6)

1/1 1/2 2/1 1/1 1/2 2/1 2/2 1/1 1/2 2/1 2/2 3/1 3/2 1/1 1/2 2/1 2/2 3/1 3/2

Processed by task A A A B A B A B B A B B A B B A B B A State of detected

ITU 656 FID

0100101010101010101

TOGGLE ﬂag 1 0 1 1 1 0 0 1 0 1 1 0 0 0

(7)

111

(7)

Bit D6 of SAV/EAV byte 0 1 0 0 1 0 1 1 0 1 1 0 0 0

(7)

111

(7)

Required sequence conversion at the vertical scaler

(8)

↓

Output

(9)

OOOOOOOOOOOOONOOONOOO

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SAA7114H

8.3.2 HORIZONTAL SCALING Theoverall horizontal required scaling factorhasto be split

into a binary and a rational value according to the equation:

where, parameter of prescaler XPSC[5:0] = 1 to 63 and parameter of VPD phase interpolation XSCY[12:0] = 300 to 8191 (0 to 299 are only theoretical values). For example,1⁄

3.5

is to split in1⁄4× 1.14286. The binary factor is processed by the prescaler, the arbitrary non-integer ratios is achieved via the variable phase delay VPD circuitry, called horizontal fine scaling. Latter calculates horizontally interpolated new samples with a 6-bit phase accuracy, which relates to less than 1 ns jitter forregularsamplingscheme. Prescaler and fine scaler are building the horizontal scaler of the SAA7114H.

Using the accumulation length function of the prescaler (XACL[5:0]A1H[5:0]), application and destination dependent (e.g. scale for display or for a compression machine), a compromise between visible bandwidth and alias suppression can be found.

8.3.2.1 Horizontal prescaler (subaddresses

A0H to A7H and D0H to D7H)

The prescaling function consists of an FIR anti-alias filter stage and an integer prescaler, which is building an adaptive prescale dependent low-pass filter, to balance sharpness and aliasing effects.

The FIR prefilter stage implements different low-pass characteristicsto reduce alias for down-scales intherange of 1 to1⁄2. A CIF optimized filter is build in, which reduces artefacts for CIF output formats (to be used in combination with the prescaler set to1⁄2 scale). See Table 10.

The functionality of the prescaler is defined by:

• An integer prescaling ratio XPSC[5:0]A0H[5:0]

(= 1 to 63), which covers the integer down-scale range 1 to1⁄

• An averaging sequence length XACL[5:0]A1H[5:0]

(= 0 to 63); range 1 to 64

• A DC gain renormalization XDCG[2:0]A2H[2:0];

1 down to1⁄

128

• The bit XC2_1[A2H[3]], which defines the weighting of the incoming pixels during the averaging process

– XC2_1 = 0 ⇒ 1 + 1...+ 1 +1 – XC2_1 = 1 ⇒ 1 + 2...+ 2 +1

The prescaler builds a prescale dependent FIR low-pass, with up to (64 + 7) filter taps. The parameter XACL[5:0] can be used to vary the low-pass characteristic for a given integer prescale of1⁄

XPSC[5:0]

. The user can therewith decide between signal bandwidth (= sharpness impression) and alias.

Equation for XPSC[5:0] calculation is:

where,

the range is 1 to 63 (value 0 is not allowed!); Npix_in = number of input pixel, and Npix_out = number of desired output pixel over the

complete horizontal scaler.

The use of the prescaler results in a XACL[5:0] and XC2_1 dependent gain amplification. The amplification

can be calculated according to the equation: DC gain = ((XACL − XC2_1) + 1) × (XC2_1 + 1) It is recommended to use sequence lengths and weights,

which results in a 2

DC gain amplification, as these

amplitudes can be renormalized by the XDCG[2:0] controlled shifter of the prescaler.

Therenormalization range of XDCG[2:0] is 1,1⁄2...down to

⁄

128

Other amplifications have to be normalized by using the following BCS control circuitry. In these cases the prescaler has to be set to an overall gain ≤1, e.g. for an accumulation sequence of ‘1 + 1 + 1’ (XACL[5:0] = 2 and XC2_1 = 0), XDCG[2:0] must be set to ‘010’, equals1⁄

and the BCS has to amplify the signal to4⁄

(SATN[7:0] and CONT[7:0] value = lower integer of

⁄3× 64).

The use of XACL[5:0] is XPSC[5:0] dependent. XACL[5:0] must be ≤2 × XPSC[5:0].

XACL[5:0] can be used to find a compromise between bandwidth (= sharpness) and alias effects.

H-scale ratio

output pixel

input pixel

------------------------------

H-scale ratio

XPSC[5:0]

--------------------------- -

1024

XSCY[12:0]

-------------------------------

×=

XPSC[5:0] lower integer of

Npix_in

Npix_out

-----------------------

------

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SAA7114H

Remark: Due to bandwidth considerations XPSC[5:0] and XACL[5:0] can be chosen different to the previous mentioned equations or Table 11, as the H-phase scaling is able to scale in the range from zooming up by factor 3 to down-scale by a factor of

1024

⁄

8191

Figs 26 and 27 show some resulting frequency characteristics of the prescaler.

Table 11 shows the recommended prescaler programming. Other programmings, than documented in Table 11, may result in better alias suppression, but the resulting DC gain amplification needs to be compensated by the BCS control, according to the equation:

Where:

XDCG[2:0]

≥ DC gain

DC gain = (XC2_1 + 1) × XACL[5:0] + (1 − XC2_1).

For example, if XACL[5:0] = 5, XC2_1 = 1, then DC gain = 10 and the required XDCG[2:0] = 4.

The horizontal source acquisition timing and the prescaling ratio is identical for both luminance path and chrominance path, but the FIR filter settings can be defined differently in the two channels.

Fade-in and fade-out of the filters is achieved by copying an original source sample each as first and last pixel after prescaling.

Figs 24 and 25 show the frequency characteristics of the selectable FIR filters.

CONT[7:0] SATN[7:0] lower integer of

XDG[2:0]

DC gain 64×

----------------------------------

Table 10 FIR preﬁlter functions

PFUV[1:0]A2H[7:6]

PFY[1:0]A2H[5:4]

LUMINANCE FILTER COEFFICIENTS CHROMINANCE COEFFICIENTS

00 bypassed bypassed 01 121 121 10 −1 1 1.75 4.5 1.75 1 −1 381083 11 12221 12221

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MHB543

(dB)

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

f_sig/f_clock

(1)

(2)

(3)

−42

−39

−36

−33

−30

−27

−24

−21

−18

−15

−12

−9

−6

−3

6 3

Fig.24 Luminance prefilter characteristic.

(1) PFY[1:0] = 01. (2) PFY[1:0] = 10. (3) PFY[1:0] = 11.

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handbook, full pagewidth

MHB544

(dB)

0 0.025 0.05 0.075 0.1 0.125 0.15 0.175 0.2 0.225 0.25

f_sig/f_clock

(1)

(2)

(3)

−42

−39

−36

−33

−30

−27

−24

−21

−18

−15

−12

−9

−6

−3

6 3

Fig.25 Chrominance prefilter characteristic.

(1) PFUV[1:0] = 01. (2) PFUV[1:0] = 10. (3) PFUV[1:0] = 11.

handbook, full pagewidth

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(dB)

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

(1)(2)(3)(4)(5)

f_sig/f_clock

−42

−39

−36

−33

−30

−27

−24

−21

−18

−15

−12

−9

−6

−3

6 3

Fig.26 Examples for prescaler filter characteristics: effect of increasing XACL[5:0].

XC2_1 = 0; Zero’s at with XACL = (1), (2), (3), (4) or (5)fn

XACL 1+

------------------------ -

×=

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SAA7114H

Fig.27 Examples for prescaler filter characteristics: setting XC2_1 =1.

(1) XC2_1 = 0 and XACL[5:0] = 1. (2) XC2_1 = 1 and XACL[5:0] = 2. (3) XC2_1 = 0 and XACL[5:0] = 3. (4) XC2_1 = 1 and XACL[5:0] = 4. (5) XC2_1 = 0 and XACL[5:0] = 7. (6) XC2_1 = 1 and XACL[5:0] = 8.

handbook, full pagewidth

MHB546

−42

−39

−36

−33

−30

−27

−24

−21

−18

−15

−12

−9

−6

−3

6 3

(dB)

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

f_sig/f_clock

(1)

(2)

(3)(4)(5)(6)

3 dB at 0.25

6 dB at 0.33

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Philips Semiconductors Preliminary speciﬁcation

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SAA7114H

Table 11 XACL[5:0] usage example

Note

1. Resulting FIR function.

PRESCALE

RATIO

XPS

[5:0]

RECOMMENDED VALUES

FIR

PREFILTER

PFY[1:0]/

PFUV[1:0]

FOR LOWER BANDWIDTH

REQUIREMENTS

FOR HIGHER BANDWIDTH

REQUIREMENTS

XACL[5:0] XC2_1 XDCG[2:0] XACL[5:0] XC2_1 XDCG[2:0]

110 0 0 0 0 0 0to2

⁄

2 2 1 2 1 0 1 0 to 2

(1 2 1) ×

⁄

(1)

(1 1) ×1⁄

(1)

⁄

34 1 3 3 0 2 2

(12221)×

⁄

(1)

(1 1 1 1) ×1⁄

(1)

⁄

48 1 4 4 1 3 2

(122222221)×

⁄

(1)

(12221)×1⁄

(1)

⁄

58 1 4 7 0 3 2

(122222221)×

⁄

(1)

(11111111)×1⁄

(1)

⁄

68 1 4 7 0 3 3

(122222221)×

⁄

(1)

(11111111)×1⁄

(1)

⁄

78 1 4 7 0 3 3

(122222221)×

⁄

(1)

(11111111)×1⁄

(1)

⁄

815 0 4 8 1 4 3

(1111111111111111)×

⁄

(1)

(122222221)×1⁄

(1)

⁄

915 0 4 8 1 4 3

(1111111111111111)×

⁄

(1)

(122222221)×1⁄

(1)

⁄

10 16 1 5 8 1 4 3

(12222222222222221)×

⁄

(1)

(122222221)×1⁄

(1)

⁄

13 16 1 5 16 1 5 3

⁄

15 31 0 5 16 1 5 3

⁄

16 32 1 6 16 1 5 3

⁄

19 32 1 6 32 1 6 3

⁄

31 32 1 6 32 1 6 3

⁄

32 63 1 7 32 1 6 3

⁄

35 63 1 7 63 1 7 3

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Philips Semiconductors Preliminary speciﬁcation

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SAA7114H

8.3.2.2 Horizontal ﬁne scaling (variable phase delay ﬁlter; subaddresses A8H to AFH and D8H to DFH)

Thehorizontal fine scaling (VPD) should operateatscaling ratios between1⁄2and 2 (0.8 and 1.6), but can also be usedfor direct scale in the rangefrom1⁄

7.999

to(theoretical) zoom 3.5 (restriction due to the internal data path architecture), without prescaler.

In combination with the prescaler a compromise between sharpness impression and alias can be found, which is signal source and application dependent.

For the luminance channel a filter structure with 10 taps is implemented, for the chrominance a filter with 4 taps.

Luminance and chrominance scale increments (XSCY[12:0]A9H[4:0]A8H[7:0] and XSCC[12:0]ADH[4:0]ACH[7:0]) are defined independently, but must be set in a 2 : 1 relation in the actual data path implementation. The phase offsets XPHY[7:0]AAH[7:0] and XPHC[7:0]AEH[7:0] can be used to shift the sample phases slightly. XPHY[7:0] and XPHC[7:0] covers the phase offset range 7.999T to1⁄32T. The phase offsets should also be programmed in a 2 : 1 ratio.

The underlying phase controlling DTO has a 13-bit resolution.

According to the equations

and

the VPD covers the scale

range from 0.125 to zoom 3.5. VPD acts equivalent to a polyphase filter with 64 possible phases. In combination with the prescaler, it is possible to get very accurate samples from a highly anti-aliased integer down-scaled input picture.

8.3.3 V

ERTICAL SCALING

The vertical scaler of the SAA7114H consists of a line FIFO buffer for line repetition and the vertical scaler block, which implements the vertical scaling on the input data stream in 2 different operational modes from theoretical zoom by 64 down to icon size1⁄64. The vertical scaler is located between the BCS and horizontal fine scaler, so that the BCS can be used to compensate the DC gain amplification of the ACM mode (see Section 8.3.3.2) as the internal RAMs are only 8-bit wide.

8.3.3.1 Line FIFO buffer(subaddresses 91H, B4H and C1H, E4H)

The line FIFO buffer is a dual ported RAM structure for 768 pixels, with asynchronous write and read access. The line buffer can be used for various functions, but not all functions may be available simultaneously.

Theline buffer can buffer acompleteunscaled active video line or more than one shorter lines (only for non-mirror mode), for selective repetition for vertical zoom-up.

For zooming up 240 lines to 288 lines e.g., every fourth line is requested (read) twice from the vertical scaling circuitry for calculation.

For conversion of a 4 : 2 : 0 or 4:1:0 input sampling scheme (MPEG, video phone, video YUV-9) to CCIR like sampling scheme 4:2:2, the chrominance line buffer is read twice of four times, before being refilled again by the source. By means of the input acquisition window definition it has to be preserved, that the processing starts with a line containing luminance and chrominance information for 4:2:0 and 4:1:0 input. The bits FSC[2:1]91H[2:1] are defining the distance between the Y/C lines. In case of 4 :2:2 and 4 : 1 : 1 FSC2 to FSC1 have to be set to ‘00’.

The line buffer can also be used for mirroring, i.e. for flippingthe image left to right, for the vanity picture invideo phone application (bit YMIR[B4H[4]]). In mirror mode only one active prescaled line can be held in the FIFO at a time.

The line buffer can be utilized as excessive pipeline buffer for discontinuous and variable rate transfer conditions at expansion port or image port.

XSCY[12:0] 1024

Npix_in

XPSC

------------------- -

Npix_out

-----------------------

×=

XSCC[12:0]

XSCY[12:0]

-------------------------------

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SAA7114H

8.3.3.2 Verticalscaler (subaddresses B0H to BFH and E0H to EFH)

Vertical scaling of any ratio from 64 (theoretical zoom) to

⁄63 (icon) can be applied.

The vertical scaling block consists of another line delay, and the vertical filter structure, that can operate in two different modes. Called linear interpolation (LPI) and accumulation (ACM) mode, controlled by YMODE[B4H[0]].

• LPI mode: In Linear Phase Interpolation (LPI) mode

(YMODE = 0)two neighbouring linesofthe source video stream are added together, but weighted by factors corresponding to the vertical position (phase) of the target output line relative to the source lines. This linear interpolation has a 6-bit phase resolution, which equals 64 intra line phases. It interpolates between two consecutive input lines only. LPI mode should be applied for scaling ratios around 1 (down to1⁄2), it must be applied for vertical zooming.

• ACM mode: The vertical Accumulation (ACM) mode

(YMODE = 1) represents a vertical averaging window over multiple lines, sliding over the field. This mode also generates phase correct output lines. The averaging window length corresponds to the scaling ration, resulting in an adaptive vertical low-pass effect, to greatly reduce aliasing artefacts. ACM can be applied for down-scales only from ratio 1 down to1⁄64. ACM results in a scale dependent DC gain amplification, which has to be precorrected by the BCS control of the scaler part.

The phase and scale controlling DTO calculates in 16-bit resolution, controlled by parameters YSCY[15:0]B1H[7:0]B0H[7:0] and YSCC[15:0]B3H[7:0]B2H[7:0], continuously over the entire filed. A start offset can be applied to the phase processing by means of the parameters YPY3[7:0] to YPY0[7:0] in BFH[7:0] to BCH[7:0] and YPC3[7:0] to YPC0[7:0]inBBH[7:0] to B8H[7:0].The start phase covers the range of

255

⁄32to1⁄32 lines offset.

By programming appropriate, opposite, vertical start phase values (subaddresses B8H to BFH and E8H to EFH)depending on odd/even field ID of the source video stream and A/B-page cycle, frame ID conversion

andfieldrateconversionaresupported(i.e.de-interlacing, re-interlacing).

Figs 28 and 29 and Tables 12 and 13 are describing the use of the offsets.

Remark: The vertical start phase, as well as scaling ratio are defined independently for luminance and chrominance channel, but must be set to the same values in the actual implementation for accurate 4:2:2 output processing.

The vertical processing communicates on it’s input side with the line FIFO buffer. The scale related equations are:

• Scaling increment calculation for ACM and LPI mode, down-scale and zoom:

• BCS value to compensate DC gain in ACM mode (contrast and saturation have to be set): CONT[7:0]A5H[7:0] respectively SATN[7:0]A6H[7:0]

, or

8.3.3.3 Use of the vertical phase offsets

As shown in Section 8.3.1.3, the scaler processing may run randomly over the interlaced input sequence. Additionally the interpretation and timing between ITU 656 field ID and real-time detection by means of the state of H-syncat falling edge of V-sync may result in different field ID interpretation.

Also a vertically scaled interlaced output gets a larger vertical sampling phase error, if the interlaced input fields are processed, without regarding the actual scale at the starting point of operation (see Fig.28).

Four events are to be considered, they are illustrated in Fig.29.

YSCY(C)[15:0] lower integer of 1024

Nline_in

Nline_out

-------------------------





lower integer of

Nline_out

Nline_in

-------------------------

64×





lower integer of

1024

YSCY[15:0]

-------------------------------

64×





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SAA7114H

Fig.28 Basic problem of interlaced vertical scaling (example: down-scale3⁄5).

handbook, full pagewidth

MHB547

mismatched vertical line distances

scale dependent start offset

correct scale dependent position

unscaled input

scaled output,

no phase offset

scaled output,

with phase offset

ﬁeld 1 ﬁeld 2 ﬁeld 1 ﬁeld 2 ﬁeld 1 ﬁeld 2

Fig.29 Derivation of the phase related equations (example: interlace vertical scaling down to3⁄5,

with field conversion).

Offset

1024

------------ -

32 1 line shift===

1 2

-- -

input line shift 16==

D = no offset = 0

1 2

-- -

input line shift

1 2

-- -

scale increment+

YSCY[15:0]

------------------------------ -

16+==

1 2

-- -

scale increment

YSCY[15:0]

------------------------------ -

handbook, full pagewidth

MHB548

ﬁeld 1 ﬁeld 2

upper

lower

ﬁeld 1 ﬁeld 2

case UP-UP

case LO-LO

ﬁeld 1 ﬁeld 2

case UP-LO

case LO-UP

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In Tables 12 and 13 PHO is a usable common phase offset.

Please notice that the equations of Fig.29 are producing an interpolated output also for the unscaled case, as the geometrical reference position for all conversions is the position of the first line of the lower field (see Table 12).

If there is no need for UP-LO and LO-UP conversion and the input field ID is the reference for the back-end operation, then it is UP-LO = UP-UP and LO-UP = LO-LO and the1⁄2line phase shift (PHO + 16) can be skipped. This case is listed in Table 13.

The SAA7114H supports 4 phase offset registers per task and component (luminance and chrominance). The value of 20H represents a phase shift of one line.

The registers are assigned to the following events; e.g. subaddresses B8H to BBH:

• B8H: 00 = input field ID 0, task status bit 0 (toggle status, see Section 8.3.1.3)

• B9H: 01 = input field ID 0, task status bit 1

• BAH: 10 = input field ID 1, task status bit 0

• BBH: 11 = input field ID 1, task status bit 1.

Dependent on the input signal (interlaced or non-interlaced) and the task processing (50 Hz or field reduced processing with one or two tasks, see examples in Section 8.3.1.3), also other combinations may be possible, but the basic equations are the same.

Table 12 Examples for vertical phase offset usage: global equations

INPUT FIELD UNDER

PROCESSING

OUTPUT FIELD

INTERPRETED AS

USED ABBREVIATION

EQUATION FOR PHASE OFFSET

CALCULATION (DECIMAL VALUES)

Upper input lines upper output lines UP-UP PHO + 16 Upper input lines lower output lines UP-LO

Lower input lines upper output lines LO-UP PHO Lower input lines Lower output lines LO-LO

PHO

YSCY[15:0]

-------------------------------

16++

PHO

YSCY[15:0]

-------------------------------

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SAA7114H

Table 13 Vertical phase offset usage; assignment of the phase offsets

Notes

1. Case 1: OFIDC[90H[6]] = 0; scaler input field ID as output ID; back-end interprets output field ID at logic 0 as upper output lines.

2. Case 2: OFIDC[90H[6]] = 1; task status bit as output ID; back-end interprets output field ID at logic 0 as upper output lines.

3. Case 3: OFIDC[90H[6]] = 1; task status bit as output ID; back-end interprets output field ID at logic 1 as upper output lines.

DETECTED INPUT

FIELD ID

TASK STATUS BIT

VERTICAL PHASE

OFFSET

CASE EQUATION TO BE USED

0 = upper lines 0 YPY(C)0[7:0] case 1

(1)

UP-UP (PHO)

case 2

(2)

UP-UP

case 3

(3)

UP-LO

0 = upper lines 1 YPY(C)1[7:0] case 1 UP-UP (PHO)

case 2 UP-LO case 3 UP-UP

1 = lower lines 0 YPY(C)2[7:0] case 1

LO-LO

case 2 LO-UP case 3 LO-LO

1 = lower lines 1 YPY(C)3[7:0] case 1

LO-LO

case 2 LO-LO case 3 LO-UP

PHO

YSCY[15:0]

-------------------------------

16–+





PHO

YSCY[15:0]

-------------------------------

16–+





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PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

8.4 VBI-data decoder and capture

(subaddresses 40H to 7FH)

The SAA7114H contains a versatile VBI-data decoder. The implementation and programming model accords to

the VBI-data slicer built in the multimedia video data acquisition circuit SAA5284.

The circuitry recovers the actual clock phase during the clock run-in period, slices the data bits with the selected data rate, and groups them to bytes. The result is buffered into a dedicated VBI-data FIFO with a capacity of 2 × 56 bytes (2 × 14 Dwords). The clock frequency, signals source, field frequency, accepted error count must be defined in subaddress 40H.

The supported VBI-data standards are shown in Table 14. For lines 2 to 24 of a field, per VBI line, 1 of 16 standards

can be selected (LCR24_[7:0] to LCR2_[7:0] in 57H[7:0] to 41H[7:0]: 23 × 2 × 4 bit programming bits).

The definition for line 24 is valid for the rest of the corresponding field, normally no text data (= video data) should be selected there (LCR24_[7:0] = FFH) to stop the activity of the VBI-data slicer during active video.

To adjust the slicers processing to the input signal source, there are offsets in horizontal and vertical direction available: parameters HOFF[10:0]5BH[2:0]59H[7:0], VOFF[8:0]5BH[4]5AH[7:0] and FOFF[5BH[7]]).

Contrary to the scalers counting, the slicers offsets are defining the position of the H and V trigger events related to the processed video field. The trigger events are the falling edge of HREF and the falling edge of V123 from the decoder processing part.

The relation of these programming values to the input signal and the recommended values can be seen in Tables 4 to 7.

Table 14 Data types supported by the data slicer block

DT[3:0]

62H[3:0]

STANDARD TYPE

DATA RATE

(Mbits/s)

FRAMING CODE

WINDOW

HAM

CHECK

0000 teletext EuroWST, CCST 6.9375 27H WST625 always 0001 European closed caption 0.500 001 CC625 0010 VPS 5 9951H VPS 0011 wide screen signalling bits 5 1E3C1FH WSS 0100 US teletext (WST) 5.7272 27H WST525 always 0101 US closed caption (line 21) 0.503 001 CC525 0110 (video data selected) 5 none disable 0111 (raw data selected) 5 none disable 1000 teletext 6.9375 programmable general text optional 1001 VITC/EBU time codes (Europe) 1.8125 programmable VITC625 1010 VITC/SMPTE time codes (USA) 1.7898 programmable VITC625 1011 reserved 1100 US NABTS 5.7272 programmable NABTS optional 1101 MOJI (Japanese) 5.7272 programmable (A7H) Japtext 1110 Japanese format switch (L20/22) 5 programmable open 1111 no sliced data transmitted

(video data selected)

5 none disable

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SAA7114H

8.5 Image port output formatter

(subaddresses 84H to 87H)

The output interface consists of a FIFO for video and for sliced text data, an arbitration circuit, which controls the mixed transfer of video and sliced text data over the I-port and a decoding and multiplexing unit, which generates the 8 or 16-bit wide output data stream and the accompanied reference and supporting information.

The clock for the output interface can be derived from an internal clock, decoder, expansion port, or an externally providedclock which is appropriate fore.g.VGA and frame buffer.The clock can be up to 33 MHz.Thescaler provides the following video related timing reference events (signals), which are available on pins as defined by subaddresses 84H and 85H:

• Output field ID

• Start and end of vertical active video range,

• Start and end of active video line

• Data qualifier or gated clock

• Actually activated programming page (if CONLH is

used)

• Threshold controlled FIFO filling flags (empty, full, filled)

• Sliced data marker.

The disconnected data stream at the scaler output is accompanied by a data valid flag (or data qualifier), or is transported via a gated clock. Clock cycles with invalid data on the I-port data bus (including the HPD pins in 16-bit output mode) are marked with code 00H.

The output interface also arbitrates the transfer between scaled video data and sliced text data over the I-port output.

The bits VITX1 and VITX0 (subaddress 86H) are used to control the arbitration.

As further operation the serialization of the internal 32-bit Dwords to 8-bit or optional 16-bit output, as well as the insertion of the extended ITU 656 codes (SAV/EAV for video data, ANC or SAV/EAV codes for sliced text data) are done here.

For handshake with the VGA controller, or other memory or bus interface circuitry, programmable FIFO flags are provided (see Section 8.5.2).

8.5.1 SCALER OUTPUT FORMATTER (SUBADDRESSES 93H AND C3H)

The output formatter organizes the packing into the output FIFO. The following formats are available: YUV 4:2:2, YUV4:1:1, YUV4:2:0, YUV4:1:0, Yonly (e.g. for raw samples). The formatting is controlled by FSI[2:0]93H[2:0], FOI[1:0]93H[4:3] and FYSK[93H[5]].

The data formats are defined on Dwords,or multiples, and are similar to the video formats as recommended for PCI multimedia applications (compare SAA7146A), but planar formats are not supported.

FSI[2:0] defines the horizontal packing of the data, FOI[1:0] defines, how many Y only lines are expected, before a Y/C line will be formatted. If FYSK is set to logic 0 preceding Y only lines will be skipped, and output will always start with a Y/C line.

Additionallythe output formatter limits the amplitude range of the video data (controlled by ILLV[85H[5]]); see Table 17.

Table 15 Byte stream for different output formats

Table 16 Explanation to Table 15

OUTPUT FORMAT BYTE SEQUENCE FOR 8-BIT OUTPUT MODES

YUV4:2:2 C

0Y0CR0Y1CB2Y2CR2Y3CB4Y4CR4Y5 CB6Y6

YUV4:1:1 C

0Y0CR0Y1CB4Y2CR4Y3Y4 Y5Y6 Y7 CB8Y8

Yonly Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13

NAME EXPLANATION

n U (B − Y) colour difference component, pixel number n = 0, 2, 4 to 718 Yn Y (luminance) component, pixel number n = 0, 1, 2, 3 to 719 C

n V (R − Y) colour difference component, pixel number n = 0, 2, 4 to 718

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SAA7114H

Table 17 Limiting range on I-port

LIMIT STEP

ILLV[85H[5]]

VALID RANGE SUPPRESSED CODES (HEXADECIMAL VALUE)

DECIMAL VALUE HEXADECIMAL VALUE LOWER RANGE UPPER RANGE

0 1 to 254 01 to FE 00 FF 1 8 to 247 08 to F7 00 to 07 F8 to FF

8.5.2 VIDEO FIFO (SUBADDRESS 86H) The video FIFO at the scaler output contains 32 Dwords.

That corresponds to 64 pixels in 16-bit YUV 4:2:2 format. But as the entire scaler can act as pipeline buffer, the actually available buffer capacity for the image port is much higher, and can exceed beyond a video line.

The image port, and the video FIFO, can operate with the video source clock (synchronous mode) or with externally provided clock (asynchronous, and burst mode), as appropriate for the VGA controller or attached frame buffer.

The video FIFO provides 4 internal flags, reporting to which extent the FIFO is actually filled. These are:

• The FIFO Almost Empty (FAE) flag

• The FIFO Combined Flag (FCF) or FIFO filled, which is

set at almost full level and reset, with hysteresis, only after the level crosses below the almost empty mark

• The FIFO Almost Full (FAF) flag

• The FIFO Overflow (FOVL) flag.

The trigger levels for FAE and FAF are programmable by FFL[1:0]86H[3:2] (16, 24, 28, full) and FEL[1:0]86H[1:0] (16, 8, 4, empty).

The state of this flag can be seen on the pins IGP0 or IGP1. The pin mapping is defined by subaddresses 84H and 85H (see Section 9.5).

8.5.3 TEXT FIFO In the text FIFO the data of the terminal VBI-data slicer are

collected before the transmission over the I-port is requested (normally before the video window starts). It is partitioned into two FIFO sections. A complete line is filled into the FIFO, before a data transfer is requested. So normally, one line text data is ready for transfer, while the next text line is collected. So sliced text data are delivered as a block of qualified data, without any qualification gaps in the byte stream of the I-port.

The decoded VBI-data is collected in the dedicated VBI-data FIFO. After capture of a line is completed, the FIFO can be streamed through the image port, preceded by a header, telling line number and standard.

The VBI-data period can be signalled via the sliced data flagon pin IGP0 or IGP1. The decoded VBI-data is lead by the ITU ancillary data header (DID[5:0]5DH[5:0] at value <3EH) or by SAV/EAV codes selectable by DID[5:0] at value 3EH or 3FH. IGP0 or IGP1 is set, if the first byte of the ANC header is valid on the I-port bus. It is reset, if an SAV occurs. So it may frame multiple lines of text data output, in case video processing starts with a distance of several video lines to the region of text data. Valid sliced data from the text FIFO are available on the I-port as long as the IGP0 or IGP1 flag is set and the data qualifier is active on pin IDQ.

The decoded VBI-data are presented in two different data formats, controlled by bit RECODE.

• RECODE = 1: values 00H and FFH will be recoded to even parity values 03H and FCH

• RECODE = 0: values 00H and FFH may occur in the data stream as detected.

8.5.4 VIDEO AND TEXT ARBITRATION (SUBADDRESS 86H)

Slicedtext data and scaled video data aretransferred over the same bus, the I-port. The mixed transfer is controlled by an arbitration circuitry. If the video data are transferred without any interrupt and the video FIFO does not need to buffer any output pixel, the text data are inserted after an end of a scaled video line, normally during the blanking interval of the video.

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PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

8.5.5 DATA STREAM CODING AND REFERENCE SIGNAL

GENERATION

(SUBADDRESSES 84H, 85H AND 93H)

As H and V reference signals are logic 1, active gate signals are generated, which are framing the transfer of the valid output data. Alternative to the gates, H and V trigger pulses are generated on the rising edges of the gates.

Dueto the dynamic FIFO behaviour of thecomplete scaler path, the output signal timing has no fixed timing relation to the real-time input video stream. So fixed propagation delays, in therms of clock cycles, related to the analog input can not be defined.

The data stream is accompanied by a data qualifier. Additionally invalid data cycles are marked with code 00H.

If ITU 656 like codes are not wanted, these codes can be suppressed in the output stream.

As further option, it is possible to provide the scaler with a gating external signal on pin ITRDY. So it is possible to hold the data output for a certain time and to get valid output data in bursts of a guaranteed length.

The sketched reference signals and events can be mapped to the I-port output pins IDQ, IGPH, IGPV, IGP0 and IGP1. For flexible use the polarities of all the outputs can be modified. The default polarity for the qualifier and reference signals is logic 1 (= active).

Table 18 shows the relevant and supported SAV and EAV coding.

Table 18 SAV/EAV codes on I-port

Notes

1. The leading byte sequence is: FFH-00H-00H.

2. The MSB of the SAV/EAV code byte is controlled by: a) Scaler output data: task A ⇒ MSB =

CONLH (90H[7]); task B ⇒ MSB = CONLH (C0H[7]).

b) VBI-data slicer output data: DID[5:0]5DH[5:0] = 3EH ⇒ MSB = 1; DID[5:0]5DH[5:0] = 3FH ⇒ MSB = 0.

EVENT DESCRIPTION

SAV/EAV CODES ON I-PORT

(1)

(HEX)

COMMENTMSB

(2)

OF SAV/EAV BYTE = 0 MSB

(2)

OF SAV/EAV BYTE = 1

FIELD ID = 0 FIELD ID = 1 FIELD ID = 0 FIELD ID = 1

Nextpixel is FIRST pixelof any active line

0E 49 80 C7 HREF = active;

VREF = active

Previous pixel was LAST pixel of any active line, but not the last

13 54 9D DA HREF = inactive;

VREF = active

Nextpixel is FIRST pixelof any V-blanking line

25 62 AB EC HREF = active;

VREF = inactive

Previous pixel was LAST pixel of the last active line or of any V-blanking line

38 7F B6 F1 HREF = inactive;

VREF = inactive

No valid data, don’t capture and don’t increment pointer

00 IDQ pin inactive

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Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC

comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

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Table 19 Explanation to Fig.30

Notes

1. Inverted EP (bit 7); for EP see note 2.

2. Even parity (bit 6) of bits 5 to 0.

3. Odd parity (bit 7) of bits 6 to 0.

NAME EXPLANATION

SAV start of active data; see Table 20 SDID sliced data identiﬁcation: NEP

(1)

, EP

(2)

, SDID5 to SDID0, freely programmable via I2C-bus subaddress 5EH, D5 to D0, e. g. to be used as

source identiﬁer

DC Dword count: NEP

(1)

, EP

(2)

, DC5 to DC0. DC describes the number of succeeding 32-bit words:

• For SAV/EAV mode DC is fixed to 11 Dwords (byte value 4BH)

• For ANC mode it is: DC =

⁄4(C + n), where C = 2 (the two data identification bytes IDI1 and IDI2) and n = number of decoded bytes

according to the chosen text standard.

Note that the number of valid bytes inside the stream can be seen in the BC byte.

IDI1 internal data identiﬁcation 1: OP

(3)

, FID (ﬁeld 1 = 0, ﬁeld 2 = 1), LineNumber8 to LineNumber3 = Dword 1 byte 1; see Table 20

IDI2 internal data identiﬁcation 2: OP

(3)

, LineNumber2 to LineNumber0, DataType3 to DataType0 = Dword 1 byte 2; see Table 20

n_m

Dword number n, byte number m

DC_4

last Dword byte 4, note: for SAV/EAV framing DC is ﬁxed to 0BH, missing data bytes are ﬁlled up; the ﬁll value is A0H

CS the check sum byte, the checksum is accumulated from the SAV (respectively DID) byte to the D

DC_4

byte BC number of valid sliced bytes counted from the IDI1 byte EAV end of active data; see Table 20

MHB549

00 00 FF 00 00 SAV SDID DC IDI1 IDI2 D

1_3D1_4D2_1

DC_3DDC_4

CS BC FF 00 00 EAV 00 00... ...

...

1_2

1_1

...

FF 00 00 EAV

00 FF FF DID SDID DC IDI1 IDI2 D

1_3D1_4DDC_3DDC_4

CS BC 00 00...

ANC header internal header sliced data

ANC data output is only filled up to the Dword boundary

timing reference code

invalid data

end of raw VBI line

timing reference codeinternal header

sliced data invalid dataand filling data

Fig.30 Sliced data formats on the I-port in 8-bit mode.

ANC header active for DID (subaddress 5DH) <3EH

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SAA7114H

Table 20 Bytes stream of the data slicer

Notes

1. NEP = inverted EP (see note 2).

2. EP = Even Parity of bits 5 to 0.

3. FID = 0: field 1; FID = 1: field 2.

4. I1 = 0 and I0 = 0: before line 1; I1 = 0 and I0 = 1: lines 1 to 23; I1 = 1 and I0 = 0: after line 23; I1 = 1 and I0 = 1: line 24 to end of field.

5. Subaddress 5DH at 3EH and 3FH are used for ITU 656 like SAV/EAV header generation; recommended value.

6. V = 0: active video; V = 1: blanking.

7. H = 0: start of line; H = 1: end of line.

8. DC = Data Count in Dwords according to the data type.

9. OP = Odd Parity of bits 6 to 0.

10. LN = Line Number.

11. DT = Data Type according to table.

NICK

NAME

COMMENT D7 D6 D5 D4 D3 D2 D1 D0

DID, SAV, EAV

subaddress 5DH = 00H

NEP

(1)

(2)

0 1 0 FID

(3)

(4)

subaddress 5DH; D5=1

NEP EP 0 D4[5DH] D3[5DH] D2[5DH] D1[5DH] D0[5DH]

subaddress 5DH D5 = 3EH; note 5

1 FID

(3)

(6)

(7)

P3 P2 P1 P0

subaddress 5DH D5 = 3FH; note 5

0 FID

(3)

(6)

(7)

P3 P2 P1 P0

SDID programmable via

subaddress 5EH

NEP EP D5[5EH] D4[5EH] D3[5EH] D2[5EH] D1[5EH] D0[5EH]

(8)

NEP EP

(2)

DC5 DC4 DC3 DC2 DC1 DC0

IDI1 OP

(9)

FID

(3)

LN8

(10)

LN7

(10)

LN6

(10)

LN5

(10)

LN4

(10)

LN3

(10)

IDI2 OP LN2

(10)

LN1

(10)

LN0

(10)

DT3

(11)

DT2

(11)

DT1

(11)

DT0

(11)

CS check sum byte CS6 CS6 CS5 CS4 CS3 CS2 CS1 CS0 BC valid byte count OP 0 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0

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Philips Semiconductors Preliminary speciﬁcation

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SAA7114H

8.6 Audio clock generation

(subaddresses 30H to 3FH)

SAA7114H incorporates generation of a field locked audio clock, as an auxiliary function for video capture. An audio sample clock, that is locked to the field frequency, makes sure that there is always the same predefined number of audio samples associated with a field, or a set of fields. That ensures synchronous playback of audio and video after digital recording (e.g. capture to hard disk), MPEG or other compression, or non-linear editing.

8.6.1 MASTER AUDIO CLOCK

The audio clock is synthesized from the same crystal frequency as the line-locked video clock is generated. The master audio clock is defined by the parameters:

• Audio master Clocks Per Field,

ACPF[17:0]32H[1:0]31H[7:0]30H[7:0] according to the equation:

• Audio master Clocks Nominal Increment, ACNI[21:0]36H[5:0]35H[7:0]34H[7:0] according to the

equation:

See Table 21 for examples. Remark: For standard applications the synthesized audio

clock AMCLK can be used directly as master clock and as input clock for port AMXCLK (short cut) to generate ASCLK and ALRCLK. For high-end applications it is recommended to use an external analog PLL circuit to enhance the performance of the generated audio clock.

ACPF[17:0] round

audio frequency

field frequency

------------------------------------------





ACNI21:0] round

audio frequency

crystal frequency

---------------------------------------------





Table 21 Programming examples for audio master clock generation

XTALO (MHz) FIELD (Hz)

ACPF ACNI

DECIMAL HEX DECIMAL HEX

AMCLK = 256 × 48 kHz (12.288 MHz)

32.11

50 245760 3C000 3210190 30FBCE

59.94 205005 320CD 3210190 30FBCE

24.576

50 −−−−

59.94 −−−−

AMCLK = 256 × 44.1 kHz (11.2896 MHz)

32.11

50 225792 37200 2949362 2D00F2

59.94 188348 2DFBC 2949362 2D00F2

24.576

50 225792 37200 3853517 3ACCCD

59.94 188348 2DFBC 3853517 3ACCCD

AMCLK = 256 × 32 kHz (8.192 MHz)

32.11

50 163840 28000 2140127 20A7DF

59.94 136670 215DE 2140127 20A7DF

24.576

50 163840 28000 2796203 2AAAAB

59.94 136670 215DE 2796203 2AAAAB

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SAA7114H

8.6.2 SIGNALS ASCLK AND ALRCLK Two binary divided signals ASCLK and ALRCLK are

provided for slower serial digital audio signal transmission and for channel-select. The frequencies of these signals are defined by the parameters:

• SDIV[5:0]38H[5:0] according to the equation: ⇒

• LRDIV[5:0]39H[5:0] according to the equation: ⇒

See Table 22 for examples.

ASCLK

AMXCLK

SDIV 1+()2×

------------------------------------- -

SDIV[5:0]

AMXCLK

ASCLK

--------------------

1–=

ALRCLK

ASCLK

LRDIV 2×

-------------------------- -

= LRDIV[5:0]

ASCLK

ALRCLK

---------------------- -

Table 22 Programming examples for ASCLK/ALRCLK clock generation

AMXCLK

(MHz)

ASCLK

(kHz)

SDIV

ALRCLK

(kHz)

LRDIV

DECIMAL HEX DECIMAL HEX

12.288

1536 3 03

16 10

768 7 07 8 08

11.2896

1411.2 3 03

44.1

16 10

2822.4 1 01 32 10

8.192

1024 3 03

16 10

2048 1 01 32 10

8.6.3 OTHER CONTROL SIGNALS Further control signals are available to define reference

clock edges and vertical references:

APLL[3AH[3]]; Audio PLL mode:

0: PLL closed 1: PLL open

AMVR[3AH[2]]; Audio Master clock Vertical Reference:

0: internal V 1: external V

LRPH[3AH[1]]; ALRCLK Phase

0: invert ASCLK, ALRCLK edges triggered by falling edge of ASCLK

1: don’t invert ASCLK, ALRCLK edges triggered by rising edge of ASCLK

SCPH[3AH[0]]; ASCLK Phase:

0: invert AMXCLK, ASCLK edges triggered by falling edge of AMXCLK

1: don’t invert AMXCLK, ASCLK edges triggered by rising edge of AMXCLK

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9 INPUT/OUTPUT INTERFACES AND PORTS

The SAA7114H has 5 different I/O interfaces:

• Analog video input interface, for analog CVBS and/or Y and C input signals

• Audio clock port

• Digital real-time signal port (RT port)

• Digitalvideoexpansionport(X-port),forunscaleddigital

video input and output

• Digital image port (I-port) for scaled video data output and programming

• Digital host port (H-port) for extension of the image port or expansion port from 8 to 16-bit.

9.1 Analog terminals

The SAA7114H has 6 analog inputs AI21 to AI24, AI11 and AI12 for composite video CVBS or S-video Y/C signal pairs. Additionally, there are two differential reference inputs, which must be connected to ground via a capacitor equivalent to the decoupling capacitors at the 6 inputs. There are no peripheral components required other than these decoupling capacitors and 18 Ω/56 Ω termination resistors, one set per connected input signal (see also application example in Fig.40). Two anti-alias filters are integrated, and self adjusting via the clock frequency.

Clamp and gain control for the two ADC’s are also integrated. An analog video output pin AOUT is provided for testing purposes.

Table 23 Analog pin description

SYMBOL PIN I/O DESCRIPTION BIT

AI24 to AI21 10, 12, 14 and 16 I analog video signal inputs, e.g. 2 CVBS signals and

two Y/C pairs can be connected simultaneously

MODE3 to MODE0 AI12 and AI11 18 and 20 AOUT 22 O analog video output, for test purposes AOSL1 and AOSL0 AI1D and AI2D 19 and 13 I analog reference pins for differential ADC operation −

9.2 Audio clock signals

The SAA7114H also synchronizes the audio clock and sampling rate to the video frame rate, via a very slow PLL. Thisensures that the multimediacaptureand compression processes always gather the same predefined number of samples per video frame.

An audio master clock AMCLK and two divided clocks ASCLK and ALRCLK are generated;

• ASCLK: can be used as audio serial clock

• ALRCLK: audio left/right channel clock.

The ratios are programmable, see also Section 8.6.

Table 24 Audio clock pin description

SYMBOL PIN I/O DESCRIPTION BIT

AMCLK 37 O audio master clock output ACPF[17:0]32H[1:0]31H[7:0]30H[7:0]and

ACNI[21:0]36H[5:0]35H[7:0]34H[7:0]

AMXCLK 41 I external audio master clock input for the clock

division circuit, can be directly connected to output AMCLK for standard applications

−

ASCLK 39 O serial audio clock output, can be synchronized to

rising or falling edge of AMXCLK

SDIV[5:0]38H[5:0] and SCPH[3AH[0]]

ALRCLK 40 O audio channel (left/right) clock output, can be

synchronized to rising or falling edge of ASCLK

LRDIV[5:0]39H[5:0] and LRPH[3AH[1]]

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PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

9.3 Clock and real-time synchronization signals

For the generation of the line-locked video (pixel) clock LLC, and of the frame locked audio serial bit clock, a crystal accurate frequency reference is required. An oscillator is built in, for fundamental or third harmonic crystals. The supported crystal frequencies are 32.11 or

24.576 MHz (defined during reset by strapping pin ALRCLK).

Alternatively pin XTALI can be driven from an external single ended oscillator.

The crystal oscillation can be propagated as clock to other ICs in the system via pin XOUT.

The Line-Locked Clock (LLC) is the double pixel clock of nominal 27 MHz. It is locked to the selected video input, generating baseband video pixels according to

“ITU

recommendation 601”

. In order to support interfacing

circuitries, a direct pixel clock LLC2 is also provided. The pins for line and field timing reference signals are

RTCO, RTS1 and RTS0. Various real-time status information can be selected for the RTS pins. The signals are always available (output) and reflect the synchronization operation of the decoder part in the SAA7114H. The function of the RTS1 and RTS0 pins can be defined by bits RTSE1[3:0]12H[7:4] and RTSE0[3:0]12H[3:0].

Table 25 Clock and real-time synchronization signals

SYMBOL PIN I/O DESCRIPTION BIT Crystal oscillator

XTALI 7 I input for crystal oscillator, or reference clock − XTALO 6 O output of crystal oscillator − XOUT 4 O reference (crystal) clock output drive (optional) XTOUTE[14H[3]]

Real-time signals (RT port)

LLC 28 O line-locked clock, nominal 27 MHz, double pixel clock locked to the

selected video input signal

−

LLC2 29 O line-locked pixel clock, nominal 13.5 MHz − RTCO 36 O real-time control output, transfers real-time status information

supporting RTC level 3.1 (see external document

“RTC Functional

Description”

, available on request)

−

RTS0 34 O real-time status information line 0, can be programmed to carry various

real-time informations (see Table 55)

RTSE0[3:0]12H[3:0]

RTS1 35 O real-time status information line 1, can be programmed to carry various

real-time informations (see Table 56)

RTSE1[3:0]12H[7:4]

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SAA7114H

9.4 Video expansion port (X-port)

The expansion port is intended for transporting video streams image data from other digital video circuits like MPEG encoder/decoder and video phone codec, to the image port (I-port).

The expansion port consists of two groups of signals/pins:

• 8-bit data, I/O, regularly components video YUV4:2:2, i.e. CB-Y-CR-Y, byte serial, exceptionally raw video samples (e.g. ADC test). In input mode the data bus can be extended to 16-bit by the pins HPD7 to HPD0.

• Clock, synchronization and auxiliary signals, accompanying the data stream, I/O.

As output, these are direct copies of the decoder signals. The data transfers through the expansion port represent a

single D1 port, with half duplex mode. The SAV and EAV codes may be inserted optionally for data input (controlled by bit XCODE[92H[3]]). The input/output direction is switched for complete fields, only.

Table 26 Signals dedicated to the expansion port

SYMBOL PIN I/O DESCRIPTION BIT

XPD7 to XPD0

81, 82,

84 to 87,

89 and 90

I/O X-port data: in output mode controlled by decoder

section, data format see Table 27; in input mode YUV4:2:2 serial input data or luminance part of a 16-bit YUV 4 : 2 : 2 input

OFTS[2:0]13H[2:0]; 91H[7:0] and C1H[7:0]

XCLK 94 I/O clock at expansion port: if output, then copy of LLC;

as input normally a double pixel clock of up to 32 MHz or a gated clock (clock gated with a qualiﬁer)

XCKS[92H[0]]

XDQ 95 I/O data valid ﬂag of the expansion port input (qualiﬁer):

if output, then decoder (HREF and VGATE) gate (see Fig.23)

−

XRDY 96 O data request ﬂag = ready to receive, to work with

optional buffer in external device,to preventinternal buffer overﬂow; second function: input related task ﬂag A/B

XRQT[83H[2]]

XRH 92 I/O horizontal reference signal for the X-port: as output:

HREF or HS from the decoder (see Fig.23); as input: a reference edge for horizontal input timing and a polarity for input ﬁeld ID detection can be deﬁned

XRHS[13H[6]], XFDH[92H[6]] and XDH[92H[2]]

XRV 91 I/O vertical reference signal for the X-port: as output:

V123 or ﬁeld ID from the decoder, see Figs 21 and 22; as input: a reference edge for vertical input timing and for input ﬁeld ID detection can be deﬁned

XRVS[1:0]13H[5:4], XFDV[92H[7]] and XDV[1:0]92H[5:4]

XTRI 80 I port control: switches X-port input 3-state XPE[1:0]83H[1:0]

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9.4.1 X-PORT CONFIGURED AS OUTPUT

If data output is enabled at the expansion port, then the data stream from the decoder is presented. The data format of the 8-bit data bus is dependent on the chosen data type, selectable by the line control registers LCR2 to LCR24; see Table 3. In contrast to the image port, the sliced data format is not available on the expansion port. Instead, raw CVBS samples are always transferred if any sliced data type is selected.

Following are some details of data types on the expansion port:

• Active video (data type 15) contains component YUV4:2:2 signal, 720 active pixels per line. The amplitude and offsets are programmable via DBRI7 to DBRI0, DCON7 to DCON0, DSAT7 to DSAT0, OFFU1, OFFU0, OFFV1 and OFFV0. For nominal levels see Fig.17.

• Test line (data type 6) is similar to active video format, with some constraints within the data processing:

– adaptive chrominance comb filter, vertical filter

(chrominance comb filter for NTSC standards, PAL phase error correction) within the chrominance processing are disabled

– adaptive luminance comb filter, peaking and

chrominance trap are bypassed within the luminance processing.

This data type is defined for future enhancements. It could be activated for lines containing standard test signals within the vertical blanking period. Currently the most sources do not contain test lines. For nominal levels see Fig.17.

• Raw samples (data types 0 to 5 and 7 to 14): UV-samples are similar to data type 6, but CVBS samplesare transferred insteadofprocessed luminance samples within the Y time slots.

The amplitude and offset of the CVBS signal is programmable via RAWG7 to RAWG0 and RAWO7 to RAWO0; see Chapter 15 “I2C-bus description”, Tables 62 and 63. For nominal levels see Fig.18.

The relation of LCR programming to line numbers is described in Section 8.2, see Tables 4 to 7.

The data type selections by LCR are overruled by setting OFTS2 (subaddress 13H bit 2) = 1. This setting is mainly intended for device production test. The VPO-bus carries the upper or lower 8 bits of the two ADCs dependent on OFTS[1:0]13H[1:0] settings; see Table 57. The output configuration is done via MODE[3:0]02H[3:0] settings; see Table 39. If a YC mode is selected, the expansion port carries the multiplexed output signals of both ADCs, in CVBS mode the output of only one ADC. No timing reference codes are generated in this mode.

Remark: The LSBs (bit 0) of the ADCs are also available on pin RTS0. For details see Table 55.

The SAV/EAV timing reference codes define start and end of valid data regions. During horizontal blanking period between EAV and SAV the ITU-blanking code sequence ‘- 80 - 10 - 80 - 10 -...’ is transmitted.

The position of the F-bit is constant according to ITU 656 (see Tables 29 and 30).

The V-bit can be generated in two different ways (see Tables 29 and 30) controlled via OFTS1 and OFTS0, see Table 57.

F and V bits change synchronously with the EAV code.

Table 27 Data format on the expansion port

Notes

1. The generation of the timing reference codes can be suppressed by setting OFTS[2:0] to ‘010’, see Table 57. In this

event the code sequence is replaced by the standard ‘- 80 - 10 -’ blanking values.

2. If raw samples or sliced data are selected by the line control registers (LCR2 to LCR24), the Y-samples are replaced

by CVBS samples.

BLANKING

PERIOD

TIMING

REFERENCE

CODE (HEX)

(1)

720 PIXELS YUV 4:2:2 DATA

(2)

TIMING

REFERENCE

CODE (HEX)

(1)

BLANKING

PERIOD

... 80 10 FF 00 00 SAV C

0Y0CR0Y1CB2 Y2 ... CR718 Y719 FF 00 00 EAV 80 10 ...

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SAA7114H

Table 28 SAV/EAV format on expansion port XPD7 to XPD0

Table 29 525 lines/60 Hz vertical timing

Table 30 625 lines/50 Hz vertical timing

BIT 7

BIT 6

(F)

BIT 5

(V)

BIT 4

(H)

BIT 3

(P3)

BIT 2

(P2)

BIT 1

(P1)

BIT 0

(P0)

1 ﬁeld bit vertical blanking bit format reserved; evaluation not

recommended (protection bits according to ITU 656)

1st field: F = 0 2nd field: F = 1

VBI: V = 1 active video: V = 0

H = 0 in SAV format H = 1 in EAV format

for vertical timing see Tables 29 and 30

LINE NUMBER F (ITU 656)

OFTS[2:0] = 000 (ITU 656) OFTS[2:0] = 001

1 to 3 1 1 according to selected VGATE

position type via VSTA and VSTO (subaddresses 15H to 17H); see Tables 59 to 61

4to19 0 1

20 0 0 21 0 0

22 to 261 0 0

262 0 0 263 0 0

264 and 265 0 1

266 to 282 1 1

283 1 0 284 1 0

285 to 524 1 0

525 1 0

LINE NUMBER F (ITU 656)

OFTS[2:0] = 000 (ITU 656) OFTS[1:0] = 10

1 to 22 0 1 according to selected VGATE

position type via VSTA and VSTO (subaddresses 15H to 17H); see Tables 59 to 61

23 0 0

24 to 309 0 0

310 0 0

311 and 312 0 1

313 to 335 1 1

336 1 0

337 to 622 1 0

623 1 0

624 and 625 1 1

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SAA7114H

9.4.2 X-PORT CONFIGURED AS INPUT

If data input mode is selected at the expansion port, then the scaler can choose it’s input data stream from the on-chip video decoder, or from expansion port (controlled by bit SCSRC[1:0]91H[5:4]). Byte serial YUV 4:2:2, or subsets for other sampling schemes, or raw samples from an external ADC may be input (see also bits FSC[2:0]91H[2:0]). The input stream must be accompanied by an external clock XCLK, qualifier XDQ and reference signals XRH and XRV. Instead of the reference signal, embedded SAV and EAV codes according to ITU 656 are also accepted. The protection bits are not evaluated.

XRH and XRV carry the horizontal and vertical synchronization signals for the digital video stream through the expansion port. The field ID of the input video stream is carried in the phase (edge) of XRV and state of XRH, or directly as FS (frame sync, odd/even signal) on the XRV pin (controlled by XFDV[92H[7]], XFDH[92H[6]] and XDV1[92H[5]]).

The trigger events on XRH (rising/falling edge) and XRV (rising/falling/both edges) for the scalers acquisition window are defined by XDV[1:0]92H[5:4] and XDH[92H[2]].Alsothesignalpolarityof the qualifier can be defined (bit XDQ[92H[1]]). Alternatively to a qualifier, the input clock can be applied to a gated clock (means clock gated with a data qualifier, controlled by bit XCKS[92H[0]]). In this event, all input data will be qualified.

9.5 Image port (I-port)

The image port transfers data from the scaler as well as from the VBI-data slicer, if so selected (maximum 33 MHz). The reference clock is available at the ICLK pin, asoutput, or as input (maximum 33 MHz). Asoutput, ICLK is derived from the locked decoder or expansion port input clock. The data stream from the scaler output is normally discontinuous. Therefore valid data during a clock cycle is accompanied by a data qualifying (data valid) flag on pin IDQ. For pin constrained applications the IDQ pin can be programmed to function as gated clock output (bit ICKS2[80H[2]]).

The data formats at the image port are defined in Dwords of 32 bits (4 bytes), like the related FIFO structures. But the physical data stream at the image port is only 16-bit or 8-bit wide; in 16-bit mode data pins HPD7 to HPD0 are used for chrominance data. The four bytes of the Dwords are serialized in words or bytes.

Available formats are:

• YUV4:2:2,

• YUV4:1:1,

• Raw samples

• Decoded VBI-data.

For handshake with the receiving VGA controller, or other memory or bus interface circuitry, F, H and V reference signals and programmable FIFO flags are provided. The informationwillbe provided on pins IGP0, IGP1, IGPH and IGPV. The functionality on this pins is controlled via subaddresses 84H and 85H.

VBI-data is collected over an entire line in its own FIFO, and transferred as an uninterrupted block of bytes. Decoded VBI-data can be signed by the VBI flag on pin IGP0/1.

As scaled video data and decoded VBI-data may come from different and asynchronous sources, an arbitration scheme is needed. Normally VBI-data slicer has priority.

The image port consists of the pins and/or signals, as listed in Table 31.

Forpin constrained applications, orinterfaces,the relevant timing and data reference signals can also get encoded into the data stream. Therefore the corresponding pins do not need to get connected. The minimum image port configuration requires 9 pins only, i.e. 8 pins for data including codes, and 1 pin for clock or gated clock. The inserted codes are defined in close relation to the ITU/CCIR-656 (D1) recommendation, where possible.

The following deviations from

“ITU 656 recommendation”

are implemented at SAA7114H’s image port interface:

• SAV and EAV codes are only present in those lines, where data is to be transferred, i.e. active video lines, or VBI-raw samples, no codes for empty lines

• There may be more or less than 720 pixels between SAV and EAV

• Data content and number of clock cycles during horizontal and vertical blanking is undefined, and may be not constant

• Data stream may be interleaved with not-valid data codes, 00H, but SAV and EAV 4-byte codes are not interleaved with not-valid data codes

• There may be an irregular pattern of not-valid data, or IDQ, and as a result, ‘CB-Y-CR- Y -’ is not in a fixed phase to a regular clock divider

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SAA7114H

• VBI-raw sample streams are enveloped with SAV and EAV, like normal video

• Decoded VBI-data is transported as Ancillary (ANC) data, two modes:

– direct decoded VBI-data bytes (8-bit) are directly

placed in the ANC data field, 00H and FFH codes may appear in data block (violation to CCIR-656)

– recoded VBI-data bytes (8-bit) directly placed in ANC

data field, 00H and FFH codes will be recoded to even parity codes 03H and FCH to suppress invalid CCIR-656 codes.

There are no empty cycles in the ancillary code and its data field. The data codes 00H and FFH are suppressed (changed to 01H or FEH respectively) in active video stream, as well as in VBI-raw sample stream (VBI pass-through).Optionally the number range can be limited further.

Table 31 Signals dedicated to the image port

SYMBOL PIN I/O DESCRIPTION BIT

IPD7 to IPD0

54 to 57

and

59 to 62

I/O I-port data ICODE[93H[7]], ISWP[1:0]85H[7:6]

and IPE[1:0]87[1:0]

ICLK 45 I/O continuous reference clock at image port, can

be input or output, as output decoder LLC or XCLK from X-port

ICKS[1:0]80H[1:0] and IPE[1:0]87H[1:0]

IDQ 46 O data valid ﬂag at image port, qualiﬁer, with

programmable polarity; secondary function: gated clock

ICKS2[80H[2]], IDQP[85H[0]] and IPE[1:0]87H[1:0]

IGPH 53 O horizontal reference output signal, copy of the

H-gate signal of the scaler, with programmable polarity; alternative functions: HRESET pulse

IDH[1:0]84H[1:0], IRHP[85H[1]] and IPE[1:0]87H[1:0]

IGPV 52 O vertical reference output signal, copy of the

V-gate signal of the scaler, with programmable polarity; alternative functions: VRESET pulse

IDV[1:0]84H[3:2], IRVP[85H[2]] and IPE[1:0]87H[1:0]

IGP1 49 O general purpose output signal for I-port IDG12[86H[4]], IDG1[1:0]84H[5:4],

IG1P[85H[3]] and IPE[1:0]87H[1:0]

IGP0 48 O general purpose output signal for I-port IDG02[86H[5]], IDG0[1:0]84H[7:6],

IG0P[85H[4]] and IPE[1:0]87H[1:0] ITRDY 42 I target ready input signals − ITRI 47 I port control, switches I-port into 3-state IPE[1:0]87H[1:0]

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SAA7114H

9.6 Host port for 16-bit extension of video data I/O (H-port)

The H-port pins HPD can be used for extension of the data I/O paths to 16-bit. Functional priority has the I-port. If I8_16[93H[6]] is set to logic 1 the output drivers of the H-port are enabled dependent

on the I-port enable control. For I8_16 = 0, the HPD output is disabled.

Table 32 Signals dedicated to the host port

9.7 Basic input and output timing diagrams I-port and X-port

9.7.1 I-

PORT OUTPUT TIMING

The following diagrams are sketching the output timing via the I-port. IGPH and IGPV are sketched as logic 1 active gate signals. If reference pulses are programmed, these pulses are generated on the rising edge of the logic 1 active gates. Valid data is accompanied by the output data qualifier on pin IDQ. In addition invalid cycles are marked with output code 00H.

The IDQ output pin may be defined to be a gated clock output signal (ICLK AND internal IDQ).

9.7.2 X-PORT INPUT TIMING At the X-port the input timing requirements are the same as sketched for the I-port output. But different to this:

• It is not necessary to mark invalid cycles with a 00H code

• No constraints on the input qualifier (can be a random pattern)

• XCLK may be a gated clock (XCLK AND external XDQ).

Remark: All timings illustrated in Figs 31 to 37 are given for an uninterrupted output stream (no handshake with the external hardware).

SYMBOL PIN I/O DESCRIPTION BIT

HPD7 to HPD0 64 to 67

and

69 to 72

I/O 16-bit extension for digital I/O (chrominance

component)

IPE[1:0]87H[1:0], ITRI[8FH[6]] and I8_16[93H[6]]

Fig.31 Output timing I-port for serial 8-bit data at start of a line (ICODE = 1).

handbook, full pagewidth

IPD[7:0

]

IGPH

IDQ

ICLK

00 FF 00 00 SAV 00

Y00

MHB550

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SAA7114H

Fig.32 Output timing I-port for serial 8-bit data at start of a line (ICODE = 0).

handbook, full pagewidth

IPD[7:0

]

IGPH

IDQ

ICLK

Y00

MHB551

Fig.33 Output timing I-port for serial 8-bit data at end of a line (ICODE = 1).

handbook, full pagewidth

IPD[7:0

]

IGPH

IDQ

ICLK

Y00

Y00FF0000EAV00

MHB552

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SAA7114H

Fig.34 Output timing I-port for serial 8-bit data at end of a line (ICODE = 0).

handbook, full pagewidth

IPD[7:0

]

IGPH

IDQ

ICLK

Y00

MHB553

Fig.35 Output timing for 16-bit data output via I-port andH-port with codes (ICODE = 1),

timing is like 8-bit output, but packages of 2 bytes per valid cycle.

handbook, full pagewidth

IPD[7:0

]

HPD[7:0

]

IGPH

IDQ

ICLK

00 FF 00 00 Y0 Y1 00 Y2 Y3

n−1

00 FF 00 00

MHB554

00 00 SAV 00 00

00 00 EAV 00

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Fig.36 H-gate and V-gate output timing.

handbook, full pagewidth

IGPV

IGPH

IDQ

MHB555

Fig.37 Output timing for sliced VBI-data in 8-bit serial output mode (dotted graphs for SAV/EAV mode).

handbook, full pagewidth

IPD[7:0

]

HPD[7:0

]

ISLD

IDQ

ICLK

00 00 FF FF DID SDID XX YY ZZ CS

00 00 00

MHB556

00 FF 00 SAV00 00 00BC FF EAV

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10 BOUNDARY SCAN TEST

The SAA7114H has built in logic and 5 dedicated pins to support boundary scan testing which allows board testing without special hardware (nails). The SAA7114H follows the

“IEEE Std. 1149.1 - Standard Test Access Port and

Boundary-Scan Architecture”

set by the Joint Test Action

Group (JTAG) chaired by Philips. The 5 special pins are Test Mode Select (TMS), Test

Clock (TCK), Test Reset (TRST), Test Data Input (TDI) and Test Data Output (TDO).

The Boundary Scan Test (BST) functions BYPASS, EXTEST, INTEST, SAMPLE, CLAMP and IDCODEare all supported (see Table 33). Details about the JTAG BST-TEST can be found in the specification “

IEEE

Std. 1149.1”

. A file containing the detailed Boundary Scan Description Language (BSDL) description of the SAA7114H is available on request.

Table 33 BST instructions supported by the SAA7114H

INSTRUCTION DESCRIPTION

BYPASS This mandatory instruction provides a minimum length serial path (1 bit) between TDI and TDO

when no test operation of the component is required.

EXTEST This mandatory instruction allows testing of off-chip circuitry and board level interconnections.

SAMPLE This mandatory instruction can be used to take a sample of the inputs during normal operation of

the component. It can also be used to preload data values into the latched outputs of the boundary scan register.

CLAMP This optional instruction is useful for testing when not all ICs have BST. This instruction addresses

the bypass register while the boundary scan register is in external test mode.

IDCODE This optional instruction will provide information on the components manufacturer, partnumber and

version number.

INTEST This optional instruction allows testing of the internal logic (no customer support available).

USER1 This private instruction allows testing by the manufacturer (no customer support available).

10.1 Initialization of boundary scan circuit

The TAP (Test Access Port) controller of an IC should be in the reset state (TEST_LOGIC_RESET) when the IC is in functional mode. This reset state also forces the instruction register into a functional instruction such as IDCODE or BYPASS.

To solve the power-up reset, the standard specifies that the TAP controller will be forced asynchronously to the TEST_LOGIC_RESET state by setting the TRST pin LOW.

10.2 Device identiﬁcation codes

A device identification register is specified in

“IEEE Std.

1149.1b-1994”

. It is a 32-bit register which contains fields for the specification of the IC manufacturer, the IC part number and the IC version number. Its biggest advantage is the possibility to check for the correct ICs mounted after production and determination of the version number of ICs during field service.

When the IDCODE instruction is loaded into the BST instruction register, the identification register will be connected between TDI and TDO of the IC. The identification register will load a component specific code during the CAPTURE_DATA_REGISTER state of the TAP controller and this code can subsequently be shifted out. At board level this code can be used to verify component manufacturer, type and version number. The device identification register contains 32 bits, numbered 31 to 0, where bit 31 is the most significant bit (nearest to TDI) and bit 0 is the least significant bit (nearest to TDO); see Fig.38.

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Fig.38 32 bits of identification code.

handbook, full pagewidth

MHB557

000000101010111000100010100

nnnn

4-bit

version

code

16-bit part number 11-bit manufacturer

identification

TDI TDO

MSB LSB

28 27 12 11 1 0

11 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134); all ground pins connected together and all supply pins connected together.

Notes

1. Maximum: 4.6 V.

2. Except pin XTALI.

3. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ resistor.

12 THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

DDD

digital supply voltage −0.5 +4.6 V

DDA

analog supply voltage −0.5 +4.6 V

input voltage at analog inputs −0.5 V

DDA

+ 0.5

(1)

output voltage at analog output −0.5 V

DDA

+ 0.5 V

input voltage at digital inputs and outputs outputs in 3-state;

note 2

−0.5 +5.5 V

output voltage at digital outputs outputs active −0.5 V

DDD

+ 0.5 V

∆V

voltage difference between V

SSAn

and V

SSDn

− 100 mV

stg

storage temperature −65 +150 °C

amb

operating ambient temperature 0 70 °C

amb(bias)

operating ambient temperature under bias −10 +80 °C

esd

electrostatic discharge all pins note 3 −2000 +2000 V

SYMBOL PARAMETER CONDITIONS VALUE UNIT

th(j-a)

thermal resistance from junction to ambient in free air 54 K/W

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13 CHARACTERISTICS

DDD

= 3.0 to 3.6 V; V

DDA

= 3.1 to 3.5 V; T

amb

=25°C; timings and levels refer to drawings and conditions illustrated in

Fig.39; unless otherwise speciﬁed.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

DDD

digital supply voltage 3.0 3.3 3.6 V

DDD

digital supply current X-port 3-state; 8-bit I-port − 90 − mA

power dissipation digital part

− 300 − mW

DDA

analog supply voltage 3.1 3.3 3.5 V

DDA

analog supply current AOSL1 to AOSL0 = 0

CVBS mode − 47 − mA Y/C mode − 72 − mA

power dissipation analog part

CVBS mode − 150 − mW Y/C mode − 240 − mW

tot(A+D)

total power dissipation analog and digital part

CVBS mode − 450 − mW Y/C mode − 540 − mW

tot(A+D)(pd)

total power dissipation analog and digital part in power-down mode

CE pulled down to ground − 5 − mW

tot(A+D)(ps)

total power dissipation analog and digital part in power-save mode

I2C-bus controlled via subaddress 88H = 0FH

− 75 − mW

Analog part

clamp

clamping current VI= 0.9 V DC −±8−µA

i(p-p)

input voltage (peak-to-peak value)

for normal video levels 1 V (p-p), −3dB termination 27/47 Ω and AC coupling required; coupling capacitor = 22 nF

− 0.7 − V

Z

 input impedance clamping current off 200 −− kΩ

input capacitance −−10 pF

channel crosstalk fi< 5 MHz −−−50 dB

9-bit analog-to-digital converters

B analog bandwidth at −3dB − 7 − MHz φ

diff

differential phase (ampliﬁer plus anti-alias ﬁlter bypassed)

− 2 − deg

diff

differential gain (ampliﬁer plus anti-alias ﬁlter bypassed)

− 2 − %

clk(ADC)

ADC clock frequency 12.8 − 14.3 MHz

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Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

dc(d)

DC differential linearity error

− 0.7 − LSB

dc(i)

DC integral linearity error − 1 − LSB

Digital inputs

IL(SCL,SDA)

LOW-level input voltage pins SDA and SCL

−0.5 − +0.3V

DDD

IH(SCL,SDA)

HIGH-level input voltage pins SDA and SCL

0.7V

DDD

− V

DDD

+ 0.5 V

IL(XTALI)

LOW-level CMOS input voltage pin XTALI

−0.3 − +0.8 V

IH(XTALI)

HIGH-level CMOS input voltage pin XTALI

2.0 − V

DDD

+ 0.3 V

IL(n)

LOW-levelinput voltage all other inputs

−0.3 − +0.8 V

IH(n)

HIGH-level input voltage all other inputs

2.0 − 5.5 V

input leakage current −−1 µA

LI/O

I/O leakage current −−10 µA

input capacitance I/O at high impedance −−8pF Digital outputs; note 1 V

OL(SDA)

LOW-level output voltage

pin SDA

SDA at 3 mA sink current −−0.4 V

OL(clk)

LOW-level output voltage

for clocks

−0.5 − +0.6 V

OH(clk)

HIGH-level output voltage

for clocks

2.4 − V

DDD

+ 0.5 V

LOW-level output voltage

all other digital outputs

0 − 0.4 V

HIGH-level output voltage

all other digital outputs

2.4 − V

DDD

+ 0.5 V

Clock output timing (LLC and LLC2); note 2 C

output load capacitance 15 − 50 pF T

cycle time pin LLC 35 − 39 ns

pin LLC2 70 − 78 ns

δ duty factors for t

LLCH/tLLC

and t

LLC2H/tLLC2

CL=40pF 40 − 60 %

rise time LLC and LLC2 0.2 V to V

DDD

− 0.2 V −−5ns

fall time LLC and LLC2 V

DDD

− 0.2 V to 0.2 V −−5ns

d(LLC-LLC2)

delay time between LLC

and LLC2 output

measured at 1.5 V; CL=25pF

−4 − +8 ns

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

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Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

Horizontal PLL

hor(n)

nominal line frequency 50 Hz ﬁeld − 15625 − Hz

60 Hz ﬁeld − 15734 − Hz

∆f

hor/fhor(n)

permissible static deviation −−5.7 %

Subcarrier PLL

sc(n)

nominal subcarrier

frequency

PAL BGHI − 4433619 − Hz NTSC M − 3579545 − Hz PAL M − 3575612 − Hz PAL N − 3582056 − Hz

∆f

lock-in range ±400 −− Hz Crystal oscillator for 32.11 MHz; note 3 f

xtal(n)

nominal frequency 3rd harmonic − 32.11 − MHz ∆f

xtal(n)

permissible nominal

frequency deviation

−−±70 × 10

−6

∆f

xtal(n)(T)

permissible nominal

frequency deviation with

temperature

−−±30 × 10

−6

CRYSTAL SPECIFICATION (Y1) T

amb(X1)

operating ambient

temperature

0 − 70 °C

load capacitance 8 −− pF R

series resonance resistor − 40 80 Ω C

motional capacitance − 1.5 ±20% − fF C

parallel capacitance − 4.3 ±20% − pF Crystal oscillator for 24.576 MHz; note 3 f

xtal(n)

nominal frequency 3rd harmonic − 24.576 − MHz ∆f

xtal(n)

permissible nominal

frequency deviation

−−±50 × 10

−6

∆f

xtal(n)(T)

permissible nominal

frequency deviation with

temperature

−−±20 × 10

−6

CRYSTAL SPECIFICATION (Y1) T

amb(X1)

operating ambient

temperature

0 − 70 °C

load capacitance 8 −− pF R

series resonance resistor − 40 80 Ω C

motional capacitance − 1.5 ±20% − fF

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

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Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

parallel capacitance − 3.5 ±20% − pF

Clock input timing (XCLK)

cycle time 31 − 45 ns δ duty factors for t

LLCH/tLLC

40 50 60 %

rise time −−5ns t

fall time −−5ns

Data and control signal input timing X-port, related to XCLK input

SU;DAT

input data set-up time − 10 − ns t

HD;DAT

input data hold time − 3 − ns

Clock output timing

output load capacitance 15 − 50 pF T

cycle time 35 − 39 ns δ duty factors for

XCLKH/tXCLKL

35 − 65 %

rise time 0.6 to 2.6 V −−5ns t

fall time 2.6 to 0.6 V −−5ns

Data and control signal output timing X-port, related to XCLK output (for XPCK[1:0]83H[5:4] = 00 is default);

note 2 C

output load capacitance 15 − 50 pF t

OHD;DAT

output data hold time CL=15pF − 14 − ns t

propagation delay from

positive edge of XCLK

output

CL=15pF − 24 − ns

fall time −−<tbf> ns

Control signal output timing RT port, related to LLC output

output load capacitance 15 − 50 pF t

OHD;DAT

output hold time CL=15pF − 14 − ns t

propagation delay from

positive edge of LLC

output

CL=15pF − 24 − ns

fall time −−<tbf> ns

ICLK output timing

output load capacitance 15 − 50 pF T

cycle time 31 − 45 ns δ duty factors for t

ICLKH/tICLKL

35 − 65 %

rise time 0.6 to 2.6 V −−5ns

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

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Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

Notes

1. The levels must be measured with load circuits; 1.2 kΩ at 3 V (TTL load); CL= 50 pF.

2. The effects of rise and fall times are included in the calculation of t

OHD;DAT

and tPD. Timings and levels refer to

drawings and conditions illustrated in Fig.39.

3. The crystal oscillator drive level is typical 0.28 mW.

fall time 2.6 to 0.6 V −−5ns

Data and control signal output timing I-port, related to ICLK output (for IPCK[1:0]87H[5:4] = 00 is default)

output load capacitance at

all outputs

15 − 50 pF

OHD;DAT

output data hold time CL=15pF − 12 − ns t

o(d)

output delay time CL=15pF − 22 − ns t

dis

port disable time to 3-state CL=25pF −−<tbf> ns t

port enable time from

3-state

CL=25pF −−<tbf> ns

ICLK input timing

cycle time 31 − 100 ns t

, t

LOW and HIGH times −−<tbf> ns t

rise time −−<tbf> ns

Data and control signal output timing I-port, related to ICLK input (for ICKS[1:0]80H[1:0] = 11)

output load capacitance at

all outputs

<tbf> − <tbf> pF

OHD;DAT

output data hold time CL=15pF − <tbf> − ns t

o(d)

output delay time CL=15pF − <tbf> − ns t

dis

port disable time to 3-state CL=25pF −−<tbf> ns t

port enable time from

3-state

CL=25pF −−<tbf> ns

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Page 78

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Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

handbook, full pagewidth

MHB569

XCLKH

HD;DAT

SU;DAT

HD;DAT

X(I)CLKH

X(I)CLKL

clock input

XCLK

data and

control inputs

(X port)

data and

control outputs

X port, I port

clock outputs

XCLK, ICLK

and ICLK-input

input XDQ

2.4 V

1.5 V

0.6 V

−2.6 V

−1.5 V

−0.6 V

2.0 V

0.8 V

OHD;DAT

o(d)

−2.4 V

−0.6 V

2.0 V

0.8 V

not valid

Fig.39 Data input/output timing diagram (X-port, RT port and I-port).

Page 79

2000 Mar 15 79

Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC

comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

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14 APPLICATION INFORMATION

handbook, full pagewidth

100

C24

10 µF

3.3 V (D)

100

C3 100 nF

100

C12 100

C10 100

C11 100

C13

100

C23

µF

3.3 V (A)

R19 open

DGND AGND

AGND

AI11

AI12

AI21

AI22

AI23

AI24

R23

3.3 kΩ

0 Ω

R6 18

Ω

R7 56

Ω

R8 56

Ω

R9 56

Ω

R10

Ω

R11

Ω

R12

Ω

R14

3.3 kΩ

R24

0 Ω

C26

47 nF

C18

47 nF

C25

47 nF

C16

47 nF

C15

47 nF

C14

47 nF

C17

47 nF

C19

AI1D

AI12

AI2D

AI21

AI22

AI23

AI24

AI11

47 nF

R16

18 Ω

DGND

TP1

TP5

TP6

XCON[7:0

]

XPD[7:0

] LLC RTS0 RTS1 RTCO RESON

TP7

TP4TP2

TP3

10 µH

DGND

24.576 MHz

C20 10 pF

1 nF

C22

C21 10 pF

IMCON[7:0

]

IPDL[7:0

]

HPDL[7:0

]

BST2

BST[2:0

]

TDI

TDO

DD(3.3)

3.3 V (D)

3.3 V (A)

L2 2.2 µH

L3 2.2 µH

DDA(3.3)

AOUT

SDA

SCL

R18 0 Ω R21 open R22 open

R15 3.3 kΩ

0 Ω

R17

ACLK

3.3 V (D)

DGND

R20 open

R13 open

Strapping clock frequency

Strapping I

C-bus slave address

Place 0 Ω if BST is not used

AMCLK ASCLK ALRCLK AMXCLK

XTALO XTALI

37 39 40 41

XRH

XRV

XRDY

XDQ

XCLK

XTRI

XTOUT

XCON0

XCON1

XCON2

XCON3

XCON4

XCON5

XCON6

XPD782XPD684XPD585XPD486XPD387XPD289XPD190XPD0

XPD7

XPD6

XPD5

XPD4

XPD3

XPD2

XPD1

XPD0

RTCO

RTS134RTS0

TEST073TEST174TEST2

LLC

LLC2

RES

SSDE1

100

SSDE2

SSDE3

SSDE4

SSX

SSDI3

SSDI2

SSDI1

27CE24

SSA0

SSA1

SSA2

AGND

IGPH

ITRDY

ICLK IDQ ITRI IGP0 IGP1 IGPV

IMCON0

IMCON7

IMCON6 IMCON5 IMCON4 IMCON3 IMCON2 IMCON1

IPD7 IPD6 IPD5 IPD4 IPD3 IPD2 IPD1 IPD0

IPD6 IPD5 IPD4 IPD3 IPD2 IPD1 IPD0

IPD7

45 46 47 48 49 52

98 99 97 3 2

TCK

TMS

TRST

TDI

TDO

BST0

BST1

BST2

23 17 11 25 75511 334358688393

SAA7114H

DDX

DDDE1VDDDI1VDDDI2VDDDI3VDDDI4VDDDI5VDDDI6

DDA0VDDA1VDDA2VDDDE2VDDDE4VDDDE3

72 71 70 69 67 66 65 64 77 31 32 22

HPD5

HPD6

HPD7

TEST3

SCL

SDA

AOUT

78 79

TEST4

TEST5

HPD0

HPD1

HPD2

HPD3

HPD4

HPD5

HPD6

HPD7

HPD0

HPD1

HPD2

HPD3

HPD4

MHB527

Fig.40 Application example with 24.576 MHz crystal.

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Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

15 I2C-BUS DESCRIPTION

The SAA7114H supports the ‘fast mode’ I2C-bus specification extension (data rate up to 400 kbits/s).

15.1 I

C-bus format

handbook, full pagewidth

XTAL

XTALI

MHB558

XTAL

L 10 µH ± 20%

C 10 pF

C 1 nF

quartz (3rd harmonic)

24.576 MHz

XTALI

SAA7114H SAA7114H

Fig.41 Oscillator application.

a. With quartz crystal. b. With external clock.

handbook, full pagewidth

ACK-s ACK-s

DATASLAVE ADDRESS W

data transferred

(n bytes + acknowledge)

MHB339

PS ACK-s

SUBADDRESS

a. Write procedure.

b. Read procedure (combined).

handbook, full pagewidth

ACK-s ACK-mSLAVE ADDRESS R

MHB340

PSr

ACK-s ACK-s

DATA

SUBADDRESSSLAVE ADDRESS WS

data transferred

(n bytes + acknowledge)

Fig.42 I2C-bus format.

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Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

Table 34 Description of I2C-bus format

Note

1. If pin RTCO strapped to ground via a 3.3 kΩ resistor.

Table 35 Subaddress description and access

CODE DESCRIPTION

S START condition Sr repeated START condition Slave address W ‘0100 0010’ (= 42H, default) or ‘0100 0000’ (= 40H; note 1) Slave address R ‘0100 0011’ (= 43H, default) or ‘0100 0001’ (= 41H; note 1) ACK-s acknowledge generated by the slave ACK-m acknowledge generated by the master Subaddress subaddress byte; see Tables 35 and 36 Data data byte; see Table 36; if more than one byte DATA is transmitted the subaddress pointer is

automatically incremented P STOP condition X read/write control bit (LSB slave address); X = 0, order to write (the circuit is slave receiver);

X = 1, order to read (the circuit is slave transmitter)

SUBADDRESS DESCRIPTION ACCESS (READ/WRITE)

00H chip version read only F0H to FFH reserved −

Video decoder: 01H to 2FH

01H to 05H front-end part read and write 06H to 19H decoder part read and write 1AH to 1EH reserved − 1FH video decoder status byte read only 20H to 2FH reserved −

Audio clock generation: 30H to 3FH

30H to 3AH audio clock generator read and write 3BH to 3FH reserved −

General purpose VBI-data slicer: 40H to 7FH

40H to 60H VBI-data slicer read and write 61H to 62H VBI-data slicer status read only 64H to 7FH reserved −

X-port, I-port and the scaler: 80H to EFH

80H to 8FH task independent global settings read and write 90H to BFH task A deﬁnition read and write C0H to EFH task B deﬁnition read and write

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2000 Mar 15 82

Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC

comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

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Table 36 I

C-bus receiver/transmitter overview

SUB

ADDR.

(HEX)

D7 D6 D5 D4 D3 D2 D1 D0

Chip version: register 00H

Chip version (read only) 00 ID07 ID06 ID05 ID04 −−−−

Video decoder: registers 01H to 2FH

RONT-END PART: REGISTERS 01H TO 05H

Horizontal increment delay 01

(1) (1) (1) (1)

IDEL3 IDEL2 IDEL1 IDEL0 Analog input control 1 02 FUSE1 FUSE0 GUDL1 GUDL0 MODE3 MODE2 MODE1 MODE0 Analog input control 2 03

(1)

HLNRS VBSL WPOFF HOLDG GAFIX GAI28 GAI18 Analog input control 3 04 GAI17 GAI16 GAI15 GAI14 GAI13 GAI12 GAI11 GAI10 Analog input control 4 05 GAI27 GAI26 GAI25 GAI24 GAI23 GAI22 GAI21 GAI20

ECODER PART: REGISTERS 06H TO 2FH

Horizontal sync start 06 HSB7 HSB6 HSB5 HSB4 HSB3 HSB2 HSB1 HSB0 Horizontal sync stop 07 HSS7 HSS6 HSS5 HSS4 HSS3 HSS2 HSS1 HSS0 Sync control 08 AUFD FSEL FOET HTC1 HTC0 HPLL VNOI1 VNOI0 Luminance control 09 BYPS YCOMB LDEL LUBW LUFI3 LUFI2 LUFI1 LUFI0 Luminance brightness control 0A DBRI7 DBRI6 DBRI5 DBRI4 DBRI3 DBRI2 DBRI1 DBRI0 Luminance contrast control 0B DCON7 DCON6 DCON5 DCON4 DCON3 DCON2 DCON1 DCON0 Chrominance saturation control 0C DSAT7 DSAT6 DSAT5 DSAT4 DSAT3 DSAT2 DSAT1 DSAT0 Chrominance hue control 0D HUEC7 HUEC6 HUEC5 HUEC4 HUEC3 HUEC2 HUEC1 HUEC0 Chrominance control 1 0E CDTO CSTD2 CSTD1 CSTD0 DCVF FCTC

(1)

CCOMB Chrominance gain control 0F ACGC CGAIN6 CGAIN5 CGAIN4 CGAIN3 CGAIN2 CGAIN1 CGAIN0 Chrominance control 2 10 OFFU1 OFFU0 OFFV1 OFFV0 CHBW LCBW2 LCBW1 LCBW0 Mode/delay control 11 COLO RTP1 HDEL1 HDEL0 RTP0 YDEL2 YDEL1 YDEL0 RT signal control 12 RTSE13 RTSE12 RTSE11 RTSE10 RTSE03 RTSE02 RTSE01 RTSE00 RT/X-port output control 13 RTCE XRHS XRVS1 XRVS0 HLSEL OFTS2 OFTS1 OFTS0 Analog/ADC/compatibility

control

14 CM99 UPTCV AOSL1 AOSL0 XTOUTE OLDSB APCK1 APCK0

VGATE start, FID change 15 VSTA7 VSTA6 VSTA5 VSTA4 VSTA3 VSTA2 VSTA1 VSTA0 VGATE stop 16 VSTO7 VSTO6 VSTO5 VSTO4 VSTO3 VSTO2 VSTO1 VSTO0 Miscellaneous/VGATE MSBs 17 LLCE LLC2E

(1) (1) (1)

VGPS VSTO8 VSTA8

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Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC

comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

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Raw data gain control 18 RAWG7 RAWG6 RAWG5 RAWG4 RAWG3 RAWG2 RAWG1 RAWG0 Raw data offset control 19 RAWO7 RAWO6 RAWO5 RAWO4 RAWO3 RAWO2 RAWO1 RAWO0 Reserved 1A to 1E

(1) (1) (1) (1) (1) (1) (1) (1)

Status byte video decoder (read only, OLDSB = 0)

1F INTL HLVLN FIDT GLIMT GLIMB WIPA COPRO RDCAP

Status byte video decoder (read only, OLDSB = 1)

1F INTL HLCK FIDT GLIMT GLIMB WIPA SLTCA CODE

Reserved 20 to 2F

(1) (1) (1) (1) (1) (1) (1) (1)

Audio clock generator part: registers 30H to 3FH

Audio master clock cycles per ﬁeld

30 ACPF7 ACPF6 ACPF5 ACPF4 ACPF3 ACPF2 ACPF1 ACPF0 31 ACPF15 ACPF14 ACPF13 ACPF12 ACPF11 ACPF10 ACPF9 ACPF8 32

(1) (1) (1) (1) (1) (1)

ACPF17 ACPF16

Reserved 33

(1) (1) (1) (1) (1) (1) (1) (1)

Audio master clock nominal increment

34 ACNI7 ACNI6 ACNI5 ACNI4 ACNI3 ACNI2 ACNI1 ACNI0 35 ACNI15 ACNI14 ACNI13 ACNI12 ACNI11 ACNI10 ACNI9 ACNI8 36

(1) (1)

ACNI21 ACNI20 ACNI19 ACNI18 ACNI17 ACNI16

Reserved 37

(1) (1) (1) (1) (1) (1) (1) (1)

Clock ratio AMCLK to ASCLK 38

(1) (1)

SDIV5 SDIV4 SDIV3 SDIV2 SDIV1 SDIV0

Clock ratio ASCLK to ALRCLK 39

(1) (1)

LRDIV5 LRDIV4 LRDIV3 LRDIV2 LRDIV1 LRDIV0

Audio clock control 3A

(1) (1) (1) (1)

APLL AMVR LRPH SCPH

Reserved 3B to 3F

(1) (1) (1) (1) (1) (1) (1) (1)

General purpose VBI-data slicer part: registers 40H to 7FH

Slicer control 1 40

(1)

HAM_N FCE HUNT_N

(1) (1) (1) (1)

LCR2 to LCR24 (n = 2 to 24) 41 to 57 LCRn_7 LCRn_6 LCRn_5 LCRn_4 LCRn_3 LCRn_2 LCRn_1 LCRn_0 Programmable framing code 58 FC7 FC6 FC5 FC4 FC3 FC2 FC1 FC0 Horizontal offset for slicer 59 HOFF7 HOFF6 HOFF5 HOFF4 HOFF3 HOFF2 HOFF1 HOFF0 Vertical offset for slicer 5A VOFF7 VOFF6 VOFF5 VOFF4 VOFF3 VOFF2 VOFF1 VOFF0 Field offset and MSBs for

horizontal and vertical offset

5B FOFF RECODE

(1)

VOFF8

(1)

HOFF10 HOFF9 HOFF8

Reserved (for testing) 5C

(1) (1) (1) (1) (1) (1) (1) (1)

SUB

ADDR.

(HEX)

D7 D6 D5 D4 D3 D2 D1 D0

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2000 Mar 15 84

Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC

comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

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Header and data identiﬁcation (DID) code control

5D FVREF

(1)

DID5 DID4 DID3 DID2 DID1 DID0

Sliced data identiﬁcation (SDID) code

(1) (1)

SDID5 SDID4 SDID3 SDID2 SDID1 SDID0

Reserved 5F

(1) (1) (1) (1) (1) (1) (1) (1)

Slicer status byte 0 (read only) 60 − FC8V FC7V VPSV PPV CCV −− Slicer status byte 1 (read only) 61 −−F21_N LN8 LN7 LN6 LN5 LN4 Slicer status byte 2 (read only) 62 LN3 LN2 LN1 LN0 DT3 DT2 DT1 DT0 Reserved 63 to 7F

(1) (1) (1) (1) (1) (1) (1) (1)

X-port, I-port and the scaler part: registers 80H to EFH

TASK INDEPENDENT GLOBAL SETTINGS: 80H TO 8FH Global control 1 80

(1)

SMOD TEB TEA ICKS3 ICKS2 ICKS1 ICKS0

Reserved 81 and

(1) (1) (1) (1) (1) (1) (1) (1)

X-port I/O enable and output clock phase control

(1) (1)

XPCK1 XPCK0

(1)

XRQT XPE1 XPE0

I-port signal deﬁnitions 84 IDG01 IDG00 IDG11 IDG10 IDV1 IDV0 IDH1 IDH0 I-port signal polarities 85 ISWP1 ISWP0 ILLV IG0P IG1P IRVP IRHP IDQP I-port FIFO ﬂag control and

arbitration

86 VITX1 VITX0 IDG02 IDG12 FFL1 FFL0 FEL1 FEL0

I-port I/O enable, output clock and gated clock phase control

87 IPCK3 IPCK2 IPCK1 IPCK0

(1) (1)

IPE1 IPE0

Power save control 88 CH4EN CH2EN SWRST DPROG SLM3

(1)

SLM1 SLM0

Reserved 89 to 8E

(1) (1) (1) (1) (1) (1) (1) (1)

Status information scaler part 8F XTRI ITRI FFIL FFOV PRDON ERR_OF FIDSCI FIDSCO TASK A DEFINITION: REGISTERS 90H TO BFH

Basic settings and acquisition window deﬁnition

Task handling control 90 CONLH OFIDC FSKP2 FSKP1 FSKP0 RPTSK STRC1 STRC0 X-port formats and conﬁguration 91 CONLV HLDFV SCSRC1 SCSRC0 SCRQE FSC2 FSC1 FSC0 X-port input reference signal

deﬁnition

92 XFDV XFDH XDV1 XDV0 XCODE XDH XDQ XCKS

SUB

ADDR.

(HEX)

D7 D6 D5 D4 D3 D2 D1 D0

Page 85

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Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC

comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

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I-port format and conﬁguration 93 ICODE I8_16 FYSK FOI1 FOI0 FSI2 FSI1 FSI0 Horizontal input window start 94 XO7 XO6 XO5 XO4 XO3 XO2 XO1 XO0

(1) (1) (1) (1)

XO11 XO10 XO9 XO8

Horizontal input window length 96 XS7 XS6 XS5 XS4 XS3 XS2 XS1 XS0

(1) (1) (1) (1)

XS11 XS10 XS9 XS8

Vertical input window start 98 YO7 YO6 YO5 YO4 YO3 YO2 YO1 YO0

(1) (1) (1) (1)

YO11 YO10 YO9 YO8

Vertical input window length 9A YS7 YS6 YS5 YS4 YS3 YS2 YS1 YS0

(1) (1) (1) (1)

YS11 YS10 YS9 YS8

Horizontal output window length 9C XD7 XD6 XD5 XD4 XD3 XD2 XD1 XD0

(1) (1) (1) (1)

XD11 XD10 XD9 XD8

Vertical output window length 9E YD7 YD6 YD5 YD4 YD3 YD2 YD1 YD0

(1) (1) (1) (1)

YD11 YD10 YD9 YD8

FIR ﬁltering and prescaling

Horizontal prescaling A0

(1) (1)

XPSC5 XPSC4 XPSC3 XPSC2 XPSC1 XPSC0

Accumulation length A1

(1) (1)

XACL5 XACL4 XACL3 XACL2 XACL1 XACL0

Prescaler DC gain and FIR preﬁlter control

A2 PFUV1 PFUV0 PFY1 PFY0 XC2_1 XDCG2 XDCG1 XDCG0

Reserved A3

(1) (1) (1) (1) (1) (1) (1) (1)

Luminance brightness setting A4 BRIG7 BRIG6 BRIG5 BRIG4 BRIG3 BRIG2 BRIG1 BRIG0 Luminance contrast setting A5 CONT7 CONT6 CONT5 CONT4 CONT3 CONT2 CONT1 CONT0 Chrominance saturation setting A6 SATN7 SATN6 SATN5 SATN4 SATN3 SATN2 SATN1 SATN0 Reserved A7

(1) (1) (1) (1) (1) (1) (1) (1)

Horizontal phase scaling

Horizontal luminance scaling increment

A8 XSCY7 XSCY6 XSCY5 XSCY4 XSCY3 XSCY2 XSCY1 XSCY0 A9

(1) (1) (1)

XSCY12 XSCY11 XSCY10 XSCY9 XSCY8

Horizontal luminance phase offset

AA XPHY7 XPHY6 XPHY5 XPHY4 XPHY3 XPHY2 XPHY1 XPHY0

Reserved AB

(1) (1) (1) (1) (1) (1) (1) (1)

SUB

ADDR.

(HEX)

D7 D6 D5 D4 D3 D2 D1 D0

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2000 Mar 15 86

Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC

comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

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Horizontal chrominance scaling increment

AC XSCC7 XSCC6 XSCC5 XSCC4 XSCC3 XSCC2 XSCC1 XSCC0

(1) (1) (1)

XSCC12 XSCC11 XSCC10 XSCC9 XSCC8

Horizontal chrominance phase offset

AE XPHC7 XPHC6 XPHC5 XPHC4 XPHC3 XPHC2 XPHC1 XPHC0

Reserved AF

(1) (1) (1) (1) (1) (1) (1) (1)

Vertical scaling

Vertical luminance scaling increment

B0 YSCY7 YSCY6 YSCY5 YSCY4 YSCY3 YSCY2 YSCY1 YSCY0 B1 YSCY15 YSCY14 YSCY13 YSCY12 YSCY11 YSCY10 YSCY9 YSCY8

Vertical chrominance scaling increment

B2 YSCC7 YSCC6 YSCC5 YSCC4 YSCC3 YSCC2 YSCC1 YSCC0 B3 YSCC15 YSCC14 YSCC13 YSCC12 YSCC11 YSCC10 YSCC9 YSCC8

Vertical scaling mode control B4

(1) (1) (1)

YMIR

(1) (1) (1)

YMODE Reserved B5 to B7

(1) (1) (1) (1) (1) (1) (1) (1)

Vertical chrominance phase offset ‘00’

B8 YPC07 YPC06 YPC05 YPC04 YPC03 YPC02 YPC01 YPC00

Vertical chrominance phase offset ‘01’

B9 YPC17 YPC16 YPC15 YPC14 YPC13 YPC12 YPC11 YPC10

Vertical chrominance phase offset ‘10’

BA YPC27 YPC26 YPC25 YPC24 YPC23 YPC22 YPC21 YPC20

Vertical chrominance phase offset ‘11’

BB YPC37 YPC36 YPC35 YPC34 YPC33 YPC32 YPC31 YPC30

Vertical luminance phase offset ‘00’

BC YPY07 YPY06 YPY05 YPY04 YPY03 YPY02 YPY01 YPY00

Vertical luminance phase offset ‘01’

BD YPY17 YPY16 YPY15 YPY14 YPY13 YPY12 YPY11 YPY10

Vertical luminance phase offset ‘10’

BE YPY27 YPY26 YPY25 YPY24 YPY23 YPY22 YPY21 YPY20

Vertical luminance phase offset ‘11’

BF YPY37 YPY36 YPY35 YPY34 YPY33 YPY32 YPY31 YPY30

ASK B DEFINITION REGISTERS C0H TO EFH

Basic settings and acquisition window deﬁnition

Task handling control C0 CONLH OFIDC FSKP2 FSKP1 FSKP0 RPTSK STRC1 STRC0

SUB

ADDR.

(HEX)

D7 D6 D5 D4 D3 D2 D1 D0

Page 87

2000 Mar 15 87

Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC

comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

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X-port formats and conﬁguration C1 CONLV HLDFV SCSRC1 SCSRC0 SCRQE FSC2 FSC1 FSC0 Input reference signal deﬁnition C2 XFDV XFDH XDV1 XDV0 XCODE XDH XDQ XCKS I-port format and conﬁguration C3 ICODE I8_16 FYSK FOI1 FOI0 FSI2 FSI1 FSI0 Horizontal input window start C4 XO7 XO6 XO5 XO4 XO3 XO2 XO1 XO0

(1) (1) (1) (1)

XO11 XO10 XO9 XO8

Horizontal input window length C6 XS7 XS6 XS5 XS4 XS3 XS2 XS1 XS0

(1) (1) (1) (1)

XS11 XS10 XS9 XS8

Vertical input window start C8 YO7 YO6 YO5 YO4 YO3 YO2 YO1 YO0

(1) (1) (1) (1)

YO11 YO10 YO9 YO8

Vertical input window length CA YS7 YS6 YS5 YS4 YS3 YS2 YS1 YS0

(1) (1) (1) (1)

YS11 YS10 YS9 YS8

Horizontal output window length CC XD7 XD6 XD5 XD4 XD3 XD2 XD1 XD0

(1) (1) (1) (1)

XD11 XD10 XD9 XD8

Vertical output window length CE YD7 YD6 YD5 YD4 YD3 YD2 YD1 YD0

(1) (1) (1) (1)

YD11 YD10 YD9 YD8

FIR ﬁltering and prescaling

Horizontal prescaling D0

(1) (1)

XPSC5 XPSC4 XPSC3 XPSC2 XPSC1 XPSC0

Accumulation length D1

(1) (1)

XACL5 XACL4 XACL3 XACL2 XACL1 XACL0

Prescaler DC gain and FIR preﬁlter control

D2 PFUV1 PFUV0 PFY1 PFY0 XC2_1 XDCG2 XDCG1 XDCG0

Reserved D3

(1) (1) (1) (1) (1) (1) (1) (1)

Luminance brightness setting D4 BRIG7 BRIG6 BRIG5 BRIG4 BRIG3 BRIG2 BRIG1 BRIG0 Luminance contrast setting D5 CONT7 CONT6 CONT5 CONT4 CONT3 CONT2 CONT1 CONT0 Chrominance saturation setting D6 SATN7 SATN6 SATN5 SATN4 SATN3 SATN2 SATN1 SATN0 Reserved D7

(1) (1) (1) (1) (1) (1) (1) (1)

Horizontal phase scaling

Horizontal luminance scaling increment

D8 XSCY7 XSCY6 XSCY5 XSCY4 XSCY3 XSCY2 XSCY1 XSCY0 D9

(1) (1) (1)

XSCY12 XSCY11 XSCY10 XSCY9 XSCY8

Horizontal luminance phase offset

DA XPHY7 XPHY6 XPHY5 XPHY4 XPHY3 XPHY2 XPHY1 XPHY0

SUB

ADDR.

(HEX)

D7 D6 D5 D4 D3 D2 D1 D0

Page 88

2000 Mar 15 88

Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC

comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

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Note

1. All unused control bits must be programmed with logic 0 to ensure compatibility to future enhancements.

Reserved DB

(1) (1) (1) (1) (1) (1) (1) (1)

Horizontal chrominance scaling increment

DC XSCC7 XSCC6 XSCC5 XSCC4 XSCC3 XSCC2 XSCC1 XSCC0 DD

(1) (1) (1)

XSCC12 XSCC11 XSCC10 XSCC9 XSCC8

Horizontal chrominance phase offset

DE XPHC7 XPHC6 XPHC5 XPHC4 XPHC3 XPHC2 XPHC1 XPHC0

Reserved DF

(1) (1) (1) (1) (1) (1) (1) (1)

Vertical scaling

Vertical luminance scaling increment

E0 YSCY7 YSCY6 YSCY5 YSCY4 YSCY3 YSCY2 YSCY1 YSCY0 E1 YSCY15 YSCY14 YSCY13 YSCY12 YSCY11 YSCY10 YSCY9 YSCY8

Vertical chrominance scaling increment

E2 YSCC7 YSCC6 YSCC5 YSCC4 YSCC3 YSCC2 YSCC1 YSCC0 E3 YSCC15 YSCC14 YSCC13 YSCC12 YSCC11 YSCC10 YSCC9 YSCC8

Vertical scaling mode control E4

(1) (1) (1)

YMIR

(1) (1) (1)

YMODE Reserved E5 to E7

(1) (1) (1) (1) (1) (1) (1) (1)

Vertical chrominance phase offset ‘00’

E8 YPC07 YPC06 YPC05 YPC04 YPC03 YPC02 YPC01 YPC00

Vertical chrominance phase offset ‘01’

E9 YPC17 YPC16 YPC15 YPC14 YPC13 YPC12 YPC11 YPC10

Vertical chrominance phase offset ‘10’

EA YPC27 YPC26 YPC25 YPC24 YPC23 YPC22 YPC21 YPC20

Vertical chrominance phase offset ‘11’

EB YPC37 YPC36 YPC35 YPC34 YPC33 YPC32 YPC31 YPC30

Vertical luminance phase offset ‘00’

EC YPY07 YPY06 YPY05 YPY04 YPY03 YPY02 YPY01 YPY00

Vertical luminance phase offset ‘01’

ED YPY17 YPY16 YPY15 YPY14 YPY13 YPY12 YPY11 YPY10

Vertical luminance phase offset ‘10’

EE YPY27 YPY26 YPY25 YPY24 YPY23 YPY22 YPY21 YPY20

Vertical luminance phase offset ‘11’

EF YPY37 YPY36 YPY35 YPY34 YPY33 YPY32 YPY31 YPY30

SUB

ADDR.

(HEX)

D7 D6 D5 D4 D3 D2 D1 D0

Page 89

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Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

15.2 I2C-bus details

15.2.1 SUBADDRESS 00H Table 37 Chip Version (CV) identiﬁcation; 00H[7:4]; read only register

15.2.2 S

UBADDRESS 01H

The programming of the horizontal increment delay is used to match internal processing delays to the delay of the ADC. Use recommended position only.

Table 38 Horizontal increment delay; 01H[3:0]

15.2.3 SUBADDRESS 02H

Table 39 Analog input control 1 (AICO1); 02H[7:0]

FUNCTION

LOGIC LEVELS

ID07 ID06 ID05 ID04

Chip Version (CV) CV0 CV1 CV2 CV3

FUNCTION IDEL3 IDEL2 IDEL1 IDEL0

No update 1 1 1 1 Minimum delay 1 1 1 0

Recommended position 1 0 0 0

Maximum delay 0 0 0 0

BIT DESCRIPTION SYMBOL VALUE FUNCTION

D[7:6] analog function

select (see Fig.6)

FUSE[1:0] 00 ampliﬁer plus anti-alias ﬁlter bypassed

01 10 ampliﬁer active 11 ampliﬁer plus anti-alias ﬁlter active

D[5:4] update

hysteresis for 9-bit gain (see Fig.7)

GUDL[1:0] 00 off

01 ±1 LSB 10 ±2 LSB 11 ±3 LSB

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Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

Note

1. To take full advantage of the Y/C-modes 6 to 9 the I2C-bus bit BYPS (subaddress 09H, bit 7) should be set to logic 1 (full luminance bandwidth).

D[3:0] mode selection MODE[3:0] 0000 Mode 0: CVBS (automatic gain) from AI11 (pin 20); see Fig. 43

0001 Mode 1: CVBS (automatic gain) from AI12 (pin 18); see Fig. 44 0010 Mode 2: CVBS (automatic gain) from AI21 (pin 16); see Fig. 45 0011 Mode 3: CVBS (automatic gain) from AI22 (pin 14); see Fig. 46 0100 Mode 4: CVBS (automatic gain) from AI23 (pin 12); see Fig. 47 0101 Mode 5: CVBS (automatic gain) from AI24 (pin 10); see Fig. 48 0110 Mode 6: Y (automatic gain) from AI11 (pin 20) + C (gain adjustable

via GAI28 to GAI20) from AI21 (pin 16); note 1; see Fig. 49

0111 Mode 7: Y (automatic gain) from AI12 (pin 18) + C (gain adjustable

via GAI28 to GAI20) from AI22 (pin 14); note 1; see Fig. 50

1000 Mode 8: Y (automatic gain) from AI11 (pin 20) + C (gain adapted to

Y gain) from AI21 (pin 16); note 1; see Fig. 51

1001 Mode 9: Y (automatic gain) from AI12 (pin 18) + C (gain adapted to

Y gain) from AI22 (pin 14); note 1; see Fig. 52

1111 Modes 10 to 15: reserved

BIT DESCRIPTION SYMBOL VALUE FUNCTION

Fig.43 Mode 0; CVBS (automatic gain).

handbook, halfpage

MHB559

AI22 AI21

AI12 AI11

AD2

AD1

CHROMA

LUMA

AI24 AI23

Fig.44 Mode 1; CVBS (automatic gain).

handbook, halfpage

MHB560

AI12 AI11

AD2

AD1

CHROMA

LUMA

AI22 AI21

AI24 AI23

Fig.45 Mode 2; CVBS (automatic gain).

handbook, halfpage

MHB561

AI12 AI11

AD2

AD1

CHROMA

LUMA

AI22 AI21

AI24 AI23

Fig.46 Mode 3; CVBS (automatic gain).

handbook, halfpage

MHB562

AI12 AI11

AD2

AD1

CHROMA

LUMA

AI22 AI21

AI24 AI23

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Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

Fig.47 Mode 4; CVBS (automatic gain).

handbook, halfpage

MHB563

AI12 AI11

AD2

AD1

CHROMA

LUMA

AI22 AI21

AI24 AI23

Fig.48 Mode 5; CVBS (automatic gain).

handbook, halfpage

MHB564

AI12 AI11

AD2

AD1

CHROMA

LUMA

AI22 AI21

AI24 AI23

Fig.49 Mode 6; Y + C (gain channel 2 adjusted via

GAI2).

I2C-bus bit BYPS (subaddress 09H, bit 7) should be set to logic 1 (full luminance bandwidth).

handbook, halfpage

MHB565

AI12 AI11

AD2

AD1

CHROMA

LUMA

AI22 AI21

AI24 AI23

Fig.50 Mode 7; Y + C (gain channel 2 adjusted via

GAI2).

I2C-bus bit BYPS (subaddress 09H, bit 7) should be set to logic 1 (full luminance bandwidth).

handbook, halfpage

MHB566

AI12 AI11

AD2

AD1

CHROMA

LUMA

AI22 AI21

AI24 AI23

Fig.51 Mode 8; Y + C (gain channel 2adaptedto Y

gain).

I2C-bus bit BYPS (subaddress 09H, bit 7) should be set to logic 1 (full luminance bandwidth).

handbook, halfpage

MHB567

AI12 AI11

AD2

AD1

CHROMA

LUMA

AI22 AI21

AI24 AI23

Fig.52 Mode 9; Y + C (gain channel 2adaptedto Y

gain).

I2C-bus bit BYPS (subaddress 09H, bit 7) should be set to logic 1 (full luminance bandwidth).

handbook, halfpage

MHB568

AI12 AI11

AD2

AD1

CHROMA

LUMA

AI22 AI21

AI24 AI23

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Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

15.2.4 SUBADDRESS 03H

Table 40 Analog input control 2 (AICO2); 03H[6:0]

15.2.5 SUBADDRESS 04H

Table 41 Analog input control 3 (AICO3): static gain control channel 1; 03H[0] and 04H[7:0]

15.2.6 SUBADDRESS 05H

Table 42 Analog input control 4 (AICO4); static gain control channel 2; 03H[1] and 05H[7:0]

BIT DESCRIPTION SYMBOL VALUE FUNCTION

D6 HL not reference select HLNRS 0 normal clamping if decoder is in unlocked state

1 reference select if decoder is in unlocked state

D5 AGC hold during vertical

blanking period

VBSL 0 short vertical blanking (AGC disabled during equalization

and serration pulses)

1 long vertical blanking (AGC disabled from start of

pre-equalization pulses until start of active video (line 22 for 60 Hz, line 24 for 50 Hz)

D4 white peak off WPOFF 0 white peak control active

1 white peak off

D3 automatic gain control

integration

HOLDG 0 AGC active

1 AGC integration hold (freeze)

D2 gain control ﬁx GAFIX 0 automatic gain controlled by MODE3 to MODE0

1 gain is user programmable via GAI[17:10] and GAI[27:20]

D1 static gain control channel 2

sign bit

GAI28 see Table 42

D0 static gain control channel 1

sign bit

GAI18 see Table 41

DECIMAL

VALUE

GAIN

(dB)

SIGN BIT

03H[0]

CONTROL BITS D7 TO D0

GAI18 GAI17 GAI16 GAI15 GAI14 GAI13 GAI12 GAI11 GAI10

0... −3 0 00000000

...144 0 0 1 0 0 1 0 0 0 0

145... 0 0 1 0 0 1 0 0 0 1 ...511 +6 1 1 1 1 1 1 1 1 1

DECIMAL

VALUE

GAIN

(dB)

SIGN BIT

03H[1]

CONTROL BITS D7 TO D0

GAI28 GAI27 GAI26 GAI25 GAI24 GAI23 GAI22 GAI21 GAI20

0... −3 0 00000000

...144 0 0 1 0 0 1 0 0 0 0

145... 0 0 1 0 0 1 0 0 0 1 ...511 +6 1 1 1 1 1 1 1 1 1

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Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

15.2.7 SUBADDRESS 06H

Table 43 Horizontal sync start; 06H[7:0]

15.2.8 SUBADDRESS 07H

Table 44 Horizontal sync stop; 07H[7:0]

DELAY TIME

(STEP SIZE = 8/LLC)

CONTROL BITS D7 TO D0

HSB7 HSB6 HSB5 HSB4 HSB3 HSB2 HSB1 HSB0

−128...−109 (50 Hz) forbidden (outside available central counter range)

−128...−108 (60 Hz)

−108 (50 Hz)... 1 0 0 1 0 1 0 0

−107 (60 Hz)... 1 0 0 1 0 1 0 1

...108 (50 Hz) 0 1 1 0 1 1 0 0 ...107 (60 Hz) 0 1 1 0 1 0 1 1

109...127 (50 Hz) forbidden (outside available central counter range)

108...127 (60 Hz)

DELAY TIME

(STEP SIZE = 8/LLC)

CONTROL BITS D7 TO D0

HSS7 HSS6 HSS5 HSS4 HSS3 HSS2 HSS1 HSS0

−128...−109 (50 Hz) forbidden (outside available central counter range)

−128...−108 (60 Hz)

−108 (50 Hz)... 1 0 0 1 0 1 0 0

−107 (60 Hz)... 1 0 0 1 0 1 0 1

...108 (50 Hz) 0 1 1 0 1 1 0 0 ...107 (60 Hz) 0 1 1 0 1 0 1 1

109...127 (50 Hz) forbidden (outside available central counter range)

108...127 (60 Hz)

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Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

15.2.9 SUBADDRESS 08H

Table 45 Sync control; 08H[7:0]

BIT DESCRIPTION SYMBOL VALUE FUNCTION

D7 automatic ﬁeld detection AUFD 0 ﬁeld state directly controlled via FSEL

1 automatic ﬁeld detection; recommended setting

D6 ﬁeld selection FSEL 0 50 Hz, 625 lines

1 60 Hz, 525 lines

D5 forced ODD/EVEN toggle FOET 0 ODD/EVEN signal toggles only with interlaced source

1 ODD/EVEN signal toggles ﬁeldwise even if source is

non-interlaced

D[4:3] horizontal time constant

selection

HTC[1:0] 00 TV mode, recommended for poor quality TV signals only; do

not use for new applications

01 VTR mode, recommended if a deﬂection control circuit is

directly connected to the SAA7114H 10 reserved 11 fast locking mode; recommended setting

D2 horizontal PLL HPLL 0 PLL closed

1 PLL open; horizontal frequency ﬁxed

D[1:0] vertical noise reduction VNOI[1:0] 00 normal mode; recommended setting

01 fast mode, applicable for stable sources only; automatic ﬁeld

detection (AUFD) must be disabled 10 free running mode 11 vertical noise reduction bypassed

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Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

15.2.10 SUBADDRESS 09H Table 46 Luminance control; 09H[7:0]

15.2.11 SUBADDRESS 0AH

Table 47 Luminance brightness control: decoder part; 0AH[7:0]

BIT DESCRIPTION SYMBOL VALUE FUNCTION

D7 chrominance trap/comb ﬁlter

bypass

BYPS 0 chrominance trap or luminance comb ﬁlter active;

default for CVBS mode

1 chrominance trap or luminance comb ﬁlter bypassed;

default for S-video mode

D6 adaptive luminance comb ﬁlter YCOMB 0 disabled (= chrominance trap enabled, if BYPS = 0)

1 active, if BYPS = 0

D5 processing delay in non comb

ﬁlter mode

LDEL 0 processing delay is equal to internal pipelining delay

1 one (NTSC standards) or two (PAL standards) video

lines additional processing delay

D4 remodulation bandwidth for

luminance; see Figs 12 to 15

LUBW 0 small remodulation bandwidth

(narrow chroma notch ⇒ higher luminance bandwidth)

1 large remodulation bandwidth

(wider chroma notch ⇒ smaller luminance bandwidth)

D[3:0] sharpness control, luminance

ﬁlter characteristic; see Fig.16

LUFI[3:0] 0001 resolution enhancement ﬁlter 8.0 dB at 4.1 MHz

0010 resolution enhancement ﬁlter 6.8 dB at 4.1 MHz 0011 resolution enhancement ﬁlter 5.1 dB at 4.1 MHz 0100 resolution enhancement ﬁlter 4.1 dB at 4.1 MHz 0101 resolution enhancement ﬁlter 3.0 dB at 4.1 MHz 0110 resolution enhancement ﬁlter 2.3 dB at 4.1 MHz 0111 resolution enhancement ﬁlter 1.6 dB at 4.1 MHz 0000 plain 1000 low-pass ﬁlter 2 dB at 4.1 MHz 1001 low-pass ﬁlter 3 dB at 4.1 MHz 1010 low-pass ﬁlter 3 dB at 3.3 MHz; 4 dB at 4.1 MHz 1011 low-pass ﬁlter 3 dB at 2.6 MHz; 8 dB at 4.1 MHz 1100 low-pass ﬁlter 3 dB at 2.4 MHz; 14 dB at 4.1 MHz 1101 low-pass ﬁlter 3 dB at 2.2 MHz; notch at 3.4 MHz 1110 low-pass ﬁlter 3 dB at 1.9 MHz; notch at 3.0 MHz 1111 low-pass ﬁlter 3 dB at 1.7 MHz; notch at 2.5 MHz

OFFSET

CONTROL BITS D7 TO D0

DBRI7 DBRI6 DBRI5 DBRI4 DBRI3 DBRI2 DBRI1 DBRI0

255 (bright) 11111111

128 (ITU level) 10000000

0 (dark) 00000000

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PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

15.2.12 SUBADDRESS 0BH Table 48 Luminance contrast control; decoder part; 0BH[7:0]

15.2.13 SUBADDRESS 0CH Table 49 Chrominance saturation control: decoder part; 0CH[7:0]

15.2.14 S

UBADDRESS 0DH

Table 50 Chrominance hue control; 0DH[7:0]

GAIN

CONTROL BITS D7 TO D0

DCON7 DCON6 DCON5 DCON4 DCON3 DCON2 DCON1 DCON0

1.984 (maximum) 01111111

1.063 (ITU level) 01000100

1.0 01000000

0 (luminance off) 00000000

−1 (inverse luminance) 11000000

−2 (inverse luminance) 10000000

GAIN

CONTROL BITS D7 TO D0

DSAT7 DSAT6 DSAT5 DSAT4 DSAT3 DSAT2 DSAT1 DSAT0

1.984 (maximum) 01111111

1.0 (ITU level) 01000000 0 (colour off) 00000000

−1 (inverse chrominance) 11000000

−2 (inverse chrominance) 10000000

HUE PHASE (DEG)

CONTROL BITS D7 TO D0

HUEC7 HUEC6 HUEC5 HUEC4 HUEC3 HUEC2 HUEC1 HUEC0

+178.6... 01111111

...0... 00000000

...−180 10000000

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PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

15.2.15 SUBADDRESS 0EH Table 51 Chrominance control 1; 0EH[7:0]

15.2.16 SUBADDRESS 0FH

Table 52 Chrominance gain control; 0FH[7:0]

BIT DESCRIPTION SYMBOL VALUE

FUNCTION

50 Hz/625 LINES 60 Hz/525 LINES

D7 clear DTO CSTDO 0 disabled

1 Every time CDTO is set, the internal subcarrier DTO

phase is reset to 0° and the RTCO output generates a logic 0 at time slot 68 (see external document

“RTC

Functional Description”

, available on request). So an identical subcarrier phase can be generated by an external device (e.g. an encoder).

D[6:4] colour standard selection CSTD[2:0] 000 PAL BGDHI (4.43 MHz) NTSC M (3.58 MHz)

001 NTSC 4.43 (50 Hz) PAL 4.43 (60 Hz) 010 Combination-PAL N

(3.58 MHz)

NTSC 4.43 (60 Hz)

011 NTSC N (3.58 MHz) PAL M (3.58 MHz) 100 reserved NTSC-Japan (3.58 MHz) 101 SECAM reserved 110 reserved; do not use 111 reserved; do not use

D3 disable chrominance

vertical ﬁlter and PAL phase error correction

DCVF 0 chrominance vertical ﬁlter and PAL phase error

correction on (during active video lines)

1 chrominance vertical ﬁlter and PAL phase error

correction permanently off

D2 fast colour time constant FCTC 0 nominal time constant

1 fast time constant for special applications

D0 adaptive chrominance

comb ﬁlter

CCOMB 0 disabled

1 active

BIT DESCRIPTION SYMBOL VALUE FUNCTION

D7 automatic chrominance

gain control

ACGC 0 on

1 programmable gain via CGAIN6 to CGAIN0; need to be

set for SECAM standard

D[6:0] chrominance gain value

(if ACGC is set to logic 1)

CGAIN[6:0] 000 0000 minimum gain (0.5)

010 0100 nominal gain (1.125) 111 1111 maximum gain (7.5)

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PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

15.2.17 SUBADDRESS 10H Table 53 Chrominance control 2; 10H[7:0]

15.2.18 S

UBADDRESS 11H

Table 54 Mode/delay control; 11H[7:0]

BIT DESCRIPTION SYMBOL VALUE FUNCTION

D[7:6] ﬁne offset adjustment B-Y component OFFU[1:0] 00 0 LSB

⁄4LSB

⁄2LSB

⁄4LSB

D[5:4] ﬁne offset adjustment R-Y component OFFV[1:0] 00 0 LSB

⁄4LSB

⁄2LSB

⁄4LSB

D3 chrominance bandwidth; see Figs 10 and 11 CHBW 0 small

1 wide

D[2:0] combined luminance/chrominance bandwidth

adjustment; see Figs 10 to 16

LCBW[2:0] 000 smallest chrominance

bandwidth/largest luminance bandwidth

... ... to ...

111 largest chrominance

bandwidth/smallest luminance bandwidth

BIT DESCRIPTION SYMBOL VALUE FUNCTION

D7 colour on COLO 0 automatic colour killer enabled

1 colour forced on

D6 polarity of RTS1 output signal RTP1 0 non inverted

1 inverted

D[5:4] ﬁne position of HS (steps in 2/LLC) HDEL[1:0] 00 0

01 1 10 2 11 3

D3 polarity of RTS0 output signal RTP0 0 non inverted

1 inverted

D[2:0] luminance delay compensation (steps in 2/LLC) YDEL[2:0] 100 −4...

000 ...0... 011 ...3

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PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

15.2.19 SUBADDRESS 12H Table 55 RT signal control: RTS0 output; 12H[3:0]

The polarity of any signal on RTS0 can be inverted via RTP0[11H[3]].

Note

1. Function of HL is selectable via HLSEL[13H[3]]: a) HLSEL = 0: HL is standard horizontal lock indicator. b) HLSEL = 1: HL is fast horizontal lock indicator (use is not recommended for sources with unstable timebase e.g.

VCRs).

RTS0 OUTPUT RTSE03 RTSE02 RTSE01 RTSE00

3-state 0000 Constant LOW 0 0 0 1 CREF (13.5 MHz toggling pulse; see Fig.23) 0 0 1 0 CREF2 (6.75 MHz toggling pulse; see Fig.23) 0 0 1 1 HL; horizontal lock indicator (note 1): 0 1 0 0

HL = 0: unlocked HL = 1: locked

VL; vertical and horizontal lock: 0 1 0 1

VL = 0: unlocked VL = 1: locked

DL, vertical and horizontal lock and colour detected: 0 1 1 0

DL = 0: unlocked

DL = 1: locked Reserved 0 1 1 1 HREF, horizontal reference signal; indicates 720 pixels valid data on the

expansion port. The positive slope marks the beginning of a new active line. HREF is also generated during the vertical blanking interval (see Fig.23).

1000

HS: 1001

programmable width in LLC8 steps via HSB[7:0]06H[7:0] and

HSS[7:0]07H[7:0]

fine position adjustment in LLC2 steps via HDEL[1:0]11H[5:4]

(see Fig.23) HQ; HREF gated with VGATE 1 0 1 0 Reserved 1 0 1 1 V123; vertical sync (see vertical timing diagrams Figs 21 and 22) 1 1 0 0 VGATE; programmable via VSTA[8:0]17H[0]15H[7:0],

VSTO[8:0]17H[1]16H[7:0] and VGPS[17H[2]]

1101

LSBs of the 9-bit ADC’s 1 1 1 0 FID; position programmable via STA[8:0]17H[0]15H[7:0]; see vertical timing

diagrams Figs 21 and 22

1111

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PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

Table 56 RT signal control: RTS1 output; 12H[7:4] The polarity of any signal on RTS1 can be inverted via RTP1[11H[6]].

Note

VCRs).

RTS1 OUTPUT RTSE13 RTSE12 RTSE11 RTSE10

3-state 0000 Constant LOW 0 0 0 1 CREF (13.5 MHz toggling pulse; see Fig.23) 0 0 1 0 CREF2 (6.75 MHz toggling pulse; see Fig.23) 0 0 1 1 HL; horizontal lock indicator (note 1): 0 1 0 0

HL = 0: unlocked HL = 1: locked

VL; vertical and horizontal lock: 0 1 0 1

VL = 0: unlocked VL = 1: locked

DL, vertical and horizontal lock and colour detected: 0 1 1 0

DL = 0: unlocked

DL = 1: locked Reserved 0 1 1 1 HREF, horizontal reference signal; indicates 720 pixels valid data on the

expansion port. The positive slope marks the beginning of a new active line. HREF is also generated during the vertical blanking interval (see Fig.23).

1000

HS: 1001

programmable width in LLC8 steps via HSB[7:0]06H[7:0] and

HSS[7:0]07H[7:0]

fine position adjustment in LLC2 steps via HDEL[1:0]11H[5:4]

(see Fig.23) HQ; HREF gated with VGATE 1 0 1 0 Reserved 1 0 1 1 V123; vertical sync (see vertical timing diagrams Figs 21 and 22) 1 1 0 0 VGATE; programmable via VSTA[8:0]17H[0]15H[7:0],

VSTO[8:0]17H[1]16H[7:0] and VGPS[17H[2]]

1101

LSBs of the 9-bit ADC’s 1 1 1 0 FID; position programmable via STA[8:0]17H[0]15H[7:0]; see vertical timing

diagrams Figs 21 and 22

1111

Datasheet SAA7114H-V1 Datasheet (Philips)

Specifications and Main Features

Frequently Asked Questions

User Manual