Datasheet SAA7111H-01, SAA7111WP-01 Datasheet (Philips)

DATA SH EET

Product specification
Supersedes data of 1996 Oct 30
File under Integrated Circuits, IC22

1998 May 15

INTEGRATED CIRCUITS

SAA7111

Video Input Processor (VIP)

1998 May 15 2

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

CONTENTS

1 FEATURES
2 APPLICATIONS
3 GENERAL DESCRIPTION
4 QUICK REFERENCE DATA
5 ORDERING INFORMATION
6 BLOCK DIAGRAM
7 PINNING
8 FUNCTIONAL DESCRIPTION

8.1 Analog input processing

8.2 Analog control circuits

8.2.1 Clamping

8.2.2 Gain control

8.3 Chrominance processing

8.4 Luminance processing

8.5 RGB matrix

8.6 VPO-bus (digital outputs)

8.7 Synchronization

8.8 Clock generation circuit

8.9 Power-on reset and CE input

8.10 RTCO output

8.11 The Line-21 text slicer

8.11.1 Suggestions for I2C-bus interface of the display
software reading line-21 data

9 GAIN CHARTS
10 LIMITING VALUES
11 CHARACTERISTICS
12 TIMING DIAGRAMS
13 CLOCK SYSTEM

13.1 Clock generation circuit

13.2 Power-on control

14 OUTPUT FORMATS
15 APPLICATION INFORMATION

15.1 Layout hints

16 I2C-BUS DESCRIPTION

16.1 I2C-bus format

16.2 I2C-bus detail

16.2.1 Subaddress 00

16.2.2 Subaddress 02

16.2.3 Subaddress 03

16.2.4 Subaddress 04

16.2.5 Subaddress 05

16.2.6 Subaddress 06

16.2.7 Subaddress 07

16.2.8 Subaddress 08

16.2.9 Subaddress 09

16.2.10 Subaddress 0A

16.2.11 Subaddress 0B

16.2.12 Subaddress 0C

16.2.13 Subaddress 0D

16.2.14 Subaddress 0E

16.2.15 Subaddress 10

16.2.16 Subaddress 11

16.2.17 Subaddress 12

16.2.18 Subaddress 1A (read-only register)

16.2.19 Subaddress 1B (read-only register)

16.2.20 Subaddress 1C (read-only register)

16.2.21 Subaddress 1F (read-only register)
17 FILTER CURVES

17.1 Anti-alias filter curve

17.2 Luminance filter curves

17.3 Chrominance filter curves
18 I2C START SET-UP
19 PACKAGE OUTLINE
20 SOLDERING

20.1 Introduction

20.2 Reflow soldering

20.3 Wave soldering

20.3.1 PLCC

20.3.2 QFP

20.3.3 Method (PLCC and QFP)

20.4 Repairing soldered joints
21 DEFINITIONS
22 LIFE SUPPORT APPLICATIONS
23 PURCHASE OF PHILIPS I2C COMPONENTS

1998 May 15 3

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

1 FEATURES

• Four analog inputs, internal analog source selectors,

e.g. 4 × CVBS or 2 × Y/C or (1 × Y/C and 2 × CVBS)

• Two analog preprocessing channels

• Fully programmable static gain for the main channels or

automatic gain control for the selected CVBS or Y/C
channel

• Switchable white peak control

• Two built-in analog anti-aliasing filters

• Two 8-bit video CMOS analog-to-digital converters

(ADCs)

• On-chip clock generator

• Line-locked system clock frequencies

• Digital PLL for H-sync processing and clock generation

• Requires only one crystal (24.576 MHz) for all standards

• Horizontal and vertical sync detection

• Automatic detection of 50/60 Hz field frequency and

automatic switching between standards PAL and NTSC

• Luminance and chrominance signal processing for

PAL BGHI, PAL N, PAL M, NTSC M, NTSC N and
NTSC 4.43

• User programmable luminance peaking or aperture

correction

• Cross-colour reduction for NTSC by chrominance comb

filtering

• PAL delay line for correcting PAL phase errors

• Real time status information output (RTCO)

• Brightness Contrast Saturation (BCS) control on-chip

• The YUV (CCIR-601) bus supports a data rate of:

– 864 × f

H

= 13.5 MHz for 625 line sources

– 858 × fH= 13.5 MHz for 525 line sources.

• Data output streams for 16, 12 or 8-bit width with the

following formats:
– 411 YUV (12-bit)
– 422 YUV (16-bit)
– 422 YUV [CCIR-656] (8-bit)
– 565 RGB (16-bit) with dither
– 888 RGB (24-bit) with special application.

• 720 active samples per line on the YUV bus

• One user programmable general purpose switch on an

output pin

• Built in line-21 text slicer

• Power-on control

• Two switchable outputs for the digitized CVBS or Y/C

input signals AD1 (7 to 0) and AD2 (7 to 0) via the
I

2

C-bus

• Chip enable function (reset for the clock generator)

• Compatible with memory-based features (line-locked

clock)

• Boundary scan test circuit complies with the

IEEE Std. 1149.1−1990

(ID-Code = 0 7111 02 B)

• I2C-bus controlled (full read-back ability by an external
controller).

2 APPLICATIONS

• Desktop video

• Multimedia

• Digital television

• Image processing

• Video phone.

3 GENERAL DESCRIPTION

The Video Input Processor (VIP) is a combination of a
two-channel analog preprocessing circuit including source
selection, anti-aliasing filter and ADC, an automatic clamp
and gain control, a Clock Generation Circuit (CGC), a
digital multi-standard decoder (PAL BGHI, PAL M, PAL N,
NTSC M and NTSC N), a brightness/contrast/saturation
control circuit and a colour space matrix (see Fig.1).

The CMOS circuit SAA7111, analog front-end and digital
video decoder, is a highly integrated circuit for desktop
video applications. The decoder is based on the principle
of line-locked clock decoding and is able to decode the
colour of PAL and NTSC signals into CCIR-601
compatible colour component values. The SAA7111
accepts as analog inputs CVBS or S-video (Y/C) from
TV or VTR sources. The circuit is I

2

C-bus controlled.

1998 May 15 4

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

4 QUICK REFERENCE DATA

5 ORDERING INFORMATION

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V

DDD

digital supply voltage 4.5 5.0 5.5 V

V

DDA

analog supply voltage 4.75 5.0 5.25 V

T

amb

operating ambient temperature 0 25 70 °C

P

A+D

analog and digital power 0.77 1.0 1.26 W

TYPE NUMBER

P ACKAGE

NAME DESCRIPTION VERSION

SAA7111WP PLCC68 plastic leaded chip carrier; 68 leads SOT188-2
SAA7111H QFP64 plastic quad flat package; 64 leads (lead length 1.6 mm); body

14 × 14 × 2.7 mm

SOT393-1

1998 May 15 5

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

6 BLOCK DIAGRAM

Fig.1 Block diagram.

handbook, full pagewidth

SDA

XTAL
XTALI

RES

IICSA

TRST

TDI

HSVS

CLOCK

INTERFACE

I C-BUS

SYNCHRONIZATION

CIRCUIT

LUMINANCE

CIRCUIT

SAA7111

CHROMINANCE

CIRCUIT

I C-BUS

CONTROL

CLOCKS

Y

(31) 42

ANALOG

PROCESSING

AND

ANALOG-TO-

DIGITAL

CONVERSION

AI11
AI12

AI21
AI22

21 (12)
19 (10)

17 (8)
15 (6)

AD2 AD1

ANALOG

CONTROL

CON

FORMATTER

OUTPUT

CONTROL

AND

BRIGHTNESS

CONTRAST

SATURATION

BYPASS

GENERATION

CIRCUIT

POWER-ON

CONTROL

(30)41(27)38(17)26(29)40(28)39(60)

3

(15)24(16)25(24)

33

RTS0

(55) 66

(54) 65

(21) 30
(22) 31
(20) 29

LLC2
CREF

(52) 63

45 to 50
53 to 62

(34 to 39)
(42 to 51)

(53) 64

FEI
HREF

VPO
(0 : 15)

GPSW

(63) 6

(62) 5

(61) 4

(23) 32

V

SS

n.c.

7,8,9 (64)

n.c.

10,36,
37

22 (13)

AOUT

23 (14)

RTCO

CE

MGC653

RTS1

LLC

V

SSA0

V

DDA0

V

SS1-5

V

DD1-5

(57,41,33,25,18)
68,52,44,34,27

(56,40,32,26,19)
67,51,43,35,28

V

SSA1-2

V

DDA1-2

18,14 (9,5)
20,16 (11,7)

Y/CVBS

C/CVBS

TCK

2 (59)
13 (4)
1 (58)

11 (2)

12 (3)

TMS

TDO

VREF

YUV-to-RGB

CONVERSION

AND

UV

Y

PROCESSING

Y

LFCO

TEST

CONTROL

BLOCK

FOR
BOUNDARY
SCAN TEST

AND
SCAN TEST

2

2

SCL

The pin numbers given in parenthesis refer to the 64-pin package.

1998 May 15 6

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

7 PINNING

SYMBOL

PINS

I/O DESCRIPTION

PLCC68 QFP64

TRST 1 58 I Test reset input not (active LOW), for boundary scan test;

notes 1, 2, 3 and 4.
TCK 2 59 I Test clock input for boundary scan test; note 3.
RTCO 3 60 O Real time control output: contains information about actual system

clock frequency, subcarrier frequency and phase and PAL sequence.
IICSA 4 61 I I

2

C-bus slave address select input; 0 → 48H for write, 49H for read,

1 → 4AH for write, 4BH for read.
SDA 5 62 I/O I

2

C-bus serial data input/output.

SCL 6 63 I/O I

2

C-bus serial clock input/output.
n.c. 7 64 − Not connected.
n.c. 8 −−Not connected.
n.c. 9 −−Not connected.
n.c. 10 1 − Not connected.
TDO 11 2 O Test data output for boundary scan test; note 3.
TDI 12 3 I Test data input for boundary scan test; note 3.
TMS 13 4 I Test mode select input for boundary scan test or scan test; note 3.
V

SSA2

14 5 GND Ground for analog supply voltage channel 2.
AI22 15 6 I Analog input 22.
V

DDA2

16 7 P Positive supply voltage (+5 V) for analog channel 2.
AI21 17 8 I Analog input 21.
V

SSA1

18 9 GND Ground for analog supply voltage channel 1.
AI12 19 10 I Analog input 12.
V

DDA1

20 11 P Positive supply voltage (+5 V) for analog channel 1.
AI11 21 12 I Analog input 11.
V

SSS

22 13 GND Substrate (connected to analog ground).
AOUT 23 14 O Analog test output; for testing the analog input channels.
V

DDA0

24 15 P Positive supply voltage (+5 V) for internal CGC.
V

SSA0

25 16 GND Ground for internal CGC.
VREF 26 17 O Vertical reference output signal (I

2

C-bit COMPO = 0) or inverse
composite blank signal (I2C-bit COMPO = 1) (enabled via I2C-bit
OEHV).

V

DD5

27 18 P Positive digital supply voltage 5 (+5 V).

V

SS5

28 19 GND Digital ground for positive supply voltage 5.
LLC 29 20 O Line-locked system clock output (27 MHz).
LLC2 30 21 O Line-locked clock

1

⁄2output (13.5 MHz).

CREF 31 22 O Clock reference output: this is a clock qualifier signal distributed by

the CGC for a data rate of LLC2. Using CREF all interfaces on the
VPO-bus are able to generate a bus timing with identical phase.
If CCIR-656 format is selected (OFTS0 = 1 and OFTS1 = 1) an
inverse composite blank signal (pixel qualifier) is provided on this pin.

1998 May 15 7

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

RES 32 23 O Reset output (active LOW); sets the device into a defined state.

All data outputs are in high impedance state. The I2C-bus is reset

(waiting for start condition) note 4.
CE 33 24 I Chip enable; connection to ground forces a reset.
V

DD4

34 25 P Positive digital supply voltage 4 (+5 V).

V

SS4

35 26 GND Digital ground for positive supply voltage 4.
n.c. 36 −−Not connected.
n.c. 37 −−Not connected.
HS 38 27 O Horizontal sync output signal (programmable); the positions of the

positive and negative slopes are programmable in 8 LLC increments
over a complete line (equals 64 µs) via I

2

C-bus bytes HSB and HSS.
Fine position adjustment in 2 LLC increments can be performed via
I2C-bits HDEL1 and HDEL0.

RTS1 39 28 O Two functions output; controlled by I

2

C-bit RTSE1.
RTSE1 = 0: PAL line identifier (LOW = PAL line); indicates the
inverted and non-inverted R − Y component for PAL signals.
RTSE1 = 1: H-PLL locked indicator; a high state indicates that the
internal horizontal PLL has locked.

RTS0 40 29 O Two functions output; controlled by I

2

C-bit RTSE0.
RTSE0 = 0: odd/even field identification (HIGH = odd field).
RTSE0 = 1: vertical locked indicator; a HIGH state indicates that the
internal VNL has locked.

VS 41 30 O Vertical sync output signal (enabled via I

2

C-bit OEHV); this signal
indicates the vertical sync with respect to the YUV output. The HIGH
period of this signal is approximately six lines if the vertical noise
limiter (VNL) function is active. The positive slope contains the phase
information for a deflection controller.

HREF 42 31 O Horizontal reference output signal (enabled via I

2

C-bit OEHV); this
signal is used to indicate data on the digital YUV bus. The positive
slope marks the beginning of a new active line. The HIGH period of
HREF is 720 Y samples long. HREF can be used to synchronize data
multiplexer/demultiplexers. HREF is also present during the vertical
blanking interval.

V

SS3

43 32 GND Digital ground for positive supply voltage 3.

V

DD3

44 33 P Positive digital supply voltage 3 (+5 V).

VPO (15 to 10) 45 to 50 34 to 39 O Digital VPO-bus (Video Port Out) output signal; higher bits of the

16-bit YUV-bus or the 16-bit RGB-bus output signal. The output data
rate, the format and multiplexing scheme of the VPO-bus are
controlled via I

2

C-bits OFTS0 and OFTS1. With I2C-bit VIPB = 1 the
six MSBs of the digitized input signal (AD1 [7 to 2]) are connected to
these outputs.

V

SS2

51 40 GND Digital ground for positive supply voltage 2.

V

DD2

52 41 P Positive digital supply voltage 2 (+5 V).

SYMBOL

PINS

I/O DESCRIPTION

PLCC68 QFP64

1998 May 15 8

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

Notes

1. For board design without boundary scan implementation (pin compatibility with the SAA7110) connect the TRST pin
to ground.

2. This pin provides easy initialization of BST circuit. TRST can be used to force the TAP (Test Access Port) controller
to the Test-Logic-Reset state (normal operation) at once.

3. In accordance with the

IEEE1149.1

standard the pads TCK, TDI, TMS and TRST are input pads with an internal

pull-up transistor and TDO a 3-state output pad.

4. All pin names that carry an ‘overscore’ have been renamed due to Philips pin name conventions. In previous data
sheet versions these pins were marked by the suffix ‘N’, e.g. TRST = TRSTN.

VPO (9 to 0) 53 to 62 42 to 51 O Digital VPO-bus output signal; lower bits of the 16-bit YUV-bus or the

16-bit RGB-bus output signal. The output data rate, the format and
multiplexing schema of the VPO-bus are controlled via I2C-bits
OFTS0 and OFTS1. With I2C-bit VIPB = 1 the digitized input signals
(AD1 [1 and 0] and AD2 [7 to 0]) are connected to these outputs.

FEI 63 52 I Fast enable input signal (active LOW); this signal is used to control

fast switching on the digital YUV-bus. A HIGH at this input forces the
IC to set its Y and UV outputs to the high impedance state; note 4.

GPSW 64 53 O General purpose switch output; the state of this signal is set via

I

2

C-bus control and the levels are TTL compatible.

XTAL 65 54 O Second output terminal of crystal oscillator; not connected if external

clock signal is used.

XTALI 66 55 I Input terminal for 24.576 MHz crystal oscillator or connection of

external oscillator with CMOS compatible square wave clock signal.

V

SS1

67 56 GND Digital ground for positive supply voltage 1.

V

DD1

68 57 P Positive digital supply voltage 1 (+5 V).

SYMBOL

PINS

I/O DESCRIPTION

PLCC68 QFP64

1998 May 15 9

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

Fig.2 Pin configuration (PLCC68).

handbook, full pagewidth

SAA7111

MGC636

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45

VPO15

VPO14

VPO13

VPO12

VPO11

VPO10

VPO9

VPO8

VPO7

VPO6

VPO5

VPO4

VPO3

VPO3

44

27

28

29LLC

LLC2

CREF

RES

CE

HS

VS

RTS1

RTS0

HREF

n.c.

n.c.

30

31

32

33

34

35

36

37

38

39

40

41

42

43

9

8

7

6

5

4

3

2

1

68

67

66 XTALI

XTAL

TRST

TCK

RTCO

IICSA

n.c.

n.c.

n.c.

SDA

SCL

GPSW

FEI

VPO0

VPO1

65

64

63

62

61

n.c.

TDO

TDI

TMS

AI22

AI21

AI12

AI11

AOUT

V

SSA2

V

DD1VSS1

V

DDA2

V

SSA1

V

DDA1

V

SS

V

DDA0

V

DD5

V

SS5

V

DD4

V

SS4

V

SS3

V

DD3

V

SS2

V

DD2

V

SSA0

VREF

1998 May 15 10

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

Fig.3 Pin configuration (QFP64).

handbook, full pagewidth

SAA7111

MBH226

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

TCK

IICSA

SDA

RTCO

n.c.

TDO

n.c.

TDI

TMS

V

SSA2

AI22

V

DDA2

VPO15

VPO14

VPO13

VPO12

VPO11

VPO10

VPO9

VPO8

VPO7

VPO6

VPO5

VPO4

VPO3

VPO2

VPO1

VPO0

FEI

GPSW

XTAL

XTALI

V

SS1

V

DD1

V

DD3

V

DD2

V

SS2

AI21

AI11

AOUT

V

SSA1

V

SSA0

V

SS5

LLC

LLC2

CREF

CE

HS

RTS1

RTS0

VS

HREF

V

SS3

V

SS4

V

DD4

VREF

V

SS

V

DDA1

V

DDA0

V

DD5

AI12

SCL

TRST

RES

1998 May 15 11

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

8 FUNCTIONAL DESCRIPTION

8.1 Analog input processing

The SAA7111 offers four analog signal inputs, two analog
main channels with clamp circuit, analog amplifier,
anti-alias filter and video CMOS ADC (see Fig.6).

8.2 Analog control circuits

The anti-alias filters are adapted to the line-locked clock
frequency with help from a filter control. During the vertical
blanking, time gain and clamping control are frozen.

8.2.1 C

LAMPING

The clamp control circuit controls the correct clamping of
the analog input signals. The coupling capacitor is also
used to store and filter the clamping voltage. An internal
digital clamp comparator generates the information with
respect to clamp-up or clamp-down. The clamping levels
for the two ADC channels are fixed for luminance (60) and
chrominance (128). Clamping time in normal use is set
with the HCL pulse at the back porch of the video signal.

8.2.2 G

AIN CONTROL

Signal (white) peak control limits the gain at signal
overshoots. The flow charts (see Figs 10 and 11) show
more details of the AGC. The influence of supply voltage
variation within the specified range is automatically
eliminated by clamp and automatic gain control.

The gain control circuit receives (via the I2C-bus) the static
gain levels for the two analog amplifiers or controls one of
these amplifiers automatically via a built-in automatic gain

Fig.4 Analog line with clamp (HCL) and gain

range (HSY).

handbook, halfpage

HCL

MGC661

HSY

analog line blanking

TV line

1

60

225

GAIN CLAMP

control (AGC) as part of the Analog Input Control (AICO).
The AGC (automatic gain control for luminance) is used to
amplify a CVBS or Y signal to the required signal
amplitude, matched to the ADCs input voltage range.
The AGC active time is the sync bottom of the video signal.

8.3 Chrominance processing

The 8-bit chrominance signal is fed to the multiplication
inputs of a quadrature demodulator, where two subcarrier
signals from the local oscillator DTO1 are applied
(0 and 90° phase relationship to the demodulator axis).
The frequency is dependent on the present colour
standard. The output signals of the multipliers are
low-pass filtered (four programmable characteristics) to
achieve the desired bandwidth for the colour difference
signals.

The colour difference signals are fed to the
Brightness/Contrast/Saturation block (BCS), which
includes the following five functions;

1. AGC (automatic gain control for chrominance)

2. Chroma amplitude matching [different gain factors for
(R−Y) and (B−Y) to achieve CCIR-601 levels
Cr and Cb]

3. Chroma saturation control

4. Luminance contrast and brightness

5. Limiting YUV to the values 1 (min.) and 254 (max.) to
fulfil CCIR-601 requirements.

Fig.5 Automatic gain range.

handbook, halfpage

analog input level

controlled

ADC input level

maximum

minimum

range 10 dB0 dB

0 dB

MGC660

+4 dB

−6 dB

(1 V(p-p) 75 Ω)

1998 May 15 12

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

The burst processing block provides the feedback loop of
the chroma PLL and contains;

Burst gate accumulator
Colour identification and killer
Comparison nominal/actual burst amplitude
Loop filter chroma gain control
Loop filter chroma PLL
PAL sequence generation
Increment generation for DTO1 with divider to generate

stable subcarrier for non-standard signals.

The chroma comb filter block eliminates crosstalk between
the chrominance channels in accordance with the PAL
standard requirements. For NTSC colour standards the
chroma comb filter can be used to eliminate crosstalk from
luminance to chrominance (cross-colour) for vertical
structures. The comb filter can be switched off if desired.

The resulting signals are fed to the variable Y-delay
compensation, RGB matrix, dithering circuit and output
interface, which contains the VPO output formatter and the
output control logic (see Fig.7).

8.4 Luminance processing

The 8-bit luminance signal, a digital CVBS format or a
luminance format (S-VHS, HI8), is fed through a
switchable prefilter. High frequency components are
emphasized to compensate for loss. The following
chrominance trap filter (f

0

= 4.43 or 3.58 MHz centre
frequency selectable) eliminates most of the colour carrier
signal, therefore, it must be bypassed for S-video
(S-VHS, HI8) signals.

The high frequency components of the luminance signal
can be peaked (control for sharpness improvement via
I2C-bus) in two band-pass filters with selectable transfer
characteristic. This signal is then added to the original
(unpeaked) signal. A switchable amplifier achieves
common DC amplification, because the DC gains are
different in both chrominance trap modes. The improved
luminance signal is fed to the BCS control located in the
chrominance processing block (see Fig.8).

8.5 RGB matrix

Y, Cr and Cb-data are converted after interpolation into
RGB data in accordance with CCIR-601 recommendation.
The realized matrix equations consider the digital
quantization:

R = Y + 1.371 Cr
G=Y−0.336 Cb − 0.698 Cr
B = Y + 1.732 Cb.

After dithering (noise shaping) the RGB data is fed to the
output interface within the VPO-bus output formatter.

8.6 VPO-bus (digital outputs)

The 16-bit VPO-bus transfers digital data from the output
interfaces to a feature box or a field memory, a digital
colour space converter (SAA7192 DCSC), a video
enhancement and digital-to-analog processor
(SAA7165 VEDA2) or a colour graphics board
(Targa-format) as a graphical user interface.

The output data formats are controlled via the I

2

C-bus bits
OFTS0, OFTS1 and RGB888. Timing for the data stream
formats, 411 YUV (12-bit), 422 YUV (16-bit),
565 RGB (16-bit) and 888 RGB (24-bit) with an LLC2 data
rate, is achieved by marking each second positive rising
edge of the clock LLC in conjunction with CREF (clock
reference) (except RGB 888, see special application in
Fig.27). The higher output signals VPO15 to VPO8 in the
YUV format perform the digital luminance signal.
The lower output signals VPO7 to VPO0 in the YUV format
are the bits of the multiplexed colour difference signals
(B−Y) and (R−Y). The arrangement of the RGB 565 and
RGB 888 data stream bits on the VPO-bus is given in
Table 5.

The data stream format 422 YUV (the 8 higher output
signals VPO15 to VPO8) in LLC data rate fulfils the
CCIR-656 standard with its own timing reference code at
the start and end of each video data block.

A pixel in the format tables is the time required to transfer
a full set of samples. In the event of a 4 :2:2format two
luminance samples are transmitted in comparison to one
(B−Y) and one (R−Y) sample within a pixel. The time
frames are controlled by the HREF signal.

1998 May 15 13

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

Fast enable is achieved by setting input FEI to LOW.
The signal is used to control fast switching on the digital
VPO-bus. HIGH on this pin forces the YUV outputs to a
high-impedance state (see Figs 15 and 17).

The digitized analog PAL or NTSC signals AD1 (7 to 0)
and AD2 (7 to 0) are connected directly to the VPO-bus
via I2C-bit VIPB = 1.

AD1 (7 to 0) → VPO (15 to 8) and
AD2 (7 to 0) → VPO (7 to 0)

The selection of the analog input channels are controlled
via I2C-bus subaddress 02 MODE select.

8.7 Synchronization

The prefiltered luminance signal is fed to the
synchronization stage. Its bandwidth is reduced to 1 MHz
in a low-pass filter. The sync pulses are sliced and fed to
the phase detectors where they are compared with the
sub-divided clock frequency. The resulting output signal is
applied to the loop filter to accumulate all phase
deviations. Internal signals (e.g. HCL and HSY) are
generated in accordance with analog front-end
requirements. The output signals HS, VS, and PLIN are
locked to the timing reference, guaranteed between the
input signal and the HREF signal, as further improvements
to the circuit may change the total processing delay. It is
therefore not recommended to use them for applications
which require absolute timing accuracy on the input
signals. The loop filter signal drives an oscillator to
generate the line frequency control signal LFCO
(see Fig.8).

8.8 Clock generation circuit

The internal CGC generates all clock signals required for
the video input processor. The internal signal LFCO is a
digital-to-analog converted signal provided by the
horizontal PLL. It is the multiple of the line frequency
(6.75 MHz = 432 × f

h

). Internally the LFCO signal is
multiplied by a factor of 2 or 4 in the PLL circuit (including
phase detector, loop filtering, VCO and frequency divider)
to obtain the LLC and LLC2 output clock signals.
The rectangular output clocks have a 50% duty factor
(see Fig.22).

8.9 Power-on reset and CE input

A missing clock, insufficient digital or analog V

DDA0

supply
voltages (below 3.5 V) will initiate the reset sequence; all
outputs are forced to 3-state. The indicator output RES is
LOW for approximately 128 LLC after the internal reset
and can be applied to reset other circuits of the digital TV
system.

It is possible to force a reset by pulling the CE
(chip enable) to ground. After the rising edge of CE and
sufficient power supply voltage, the outputs LLC, LLC2,
CREF, RTCO, RTS0, RTS1, GPSW and SDA return from
3-state to active, while HREF, VREF, HS and VS remain in
3-state and have to be activated via I

2

C-bus programming

(see Table 4).

8.10 RTCO output

The real time control and status output signal contains
serial information about the actual system clock
(increment of the HPLL), subcarrier frequency [increment
and phase (via reset) of the FSC-PLL] and PAL sequence
bit. The signal can be used for various applications in
external circuits, e.g. in a digital encoder to achieve clean
encoding (see Fig.16).

8.11 The Line-21 text slicer

The text slicer block detects and acquires Line-21 closed
captioning data from a 525-line CVBS signal. Extended
data services on Line-21 Field 2 are also supported.
If valid data is detected the two data bytes are stored in two
I

2

C-bus registers. A parity check is also performed and the
result is stored in the MSB of the corresponding byte.
A third I2C-bus register is provided for data valid and data
ready flags. The two bits F1VAL and F2VAL indicate that
the input signal carries valid Closed Captioning data on the
corresponding fields. The data ready bits F1RDY and
F2RDY have to be evaluated if asynchronous I2C-bus
reading is used.

8.11.1 S

UGGESTIONS FOR I

2

C-BUS INTERFACE OF THE

DISPLAY SOFTWARE READING LINE

-21 DATA

There are two methods by which the software can acquire
the data;

1. Synchronous reading once per frame (or once per

field): It can use either the rising edge (Line-21 Field 1)
or both edges (Line-21 Field 1 or 2) of the ODD signal
(pin RTSO) to initiate an I2C-bus read transfer of the
three registers 1A, 1B and 1C

2. Asynchronous reading: It can poll either the F1RDY bit

(Line-21 Field 1) or both F1RDY/F2RDY bits (Line-21
Field 1 or 2). After valid data has been read the
corresponding F*RDY bit is set to LOW until new data
has arrived. The polling frequency has to be slightly
higher than the frame or field frequency, respectively.

1998 May 15 14

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

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AI22
AI21

FUSE (1 : 0)

AI12
AI11

FUSE (1 : 0)

AOSL (1 : 0)

HOLDG

ANALOG
CONTROL

GAI10-GAI18

V

SSS

n.c.

VBSL 8 8

64

13

MGC655

14

CHRLUM

VERTICAL
BLANKING
CONTROL

SOURCE

SWITCH

CLAMP

CIRCUIT

ANALOG

AMPLIFIER

ANTI-ALIAS

FILTER

BYPASS
SWITCH

SOURCE

SWITCH

CLAMP

CIRCUIT

ANALOG

AMPLIFIER

ANTI-ALIAS

FILTER

BYPASS
SWITCH

ADC2

ADC1

TEST
AND

SELECTOR

CLAMP

CONTROL

GAIN

CONTROL

CROSS MULTIPLEXER

ANTI-ALIAS

CONTROL

V

DDA1

V

SSA2

AOUT

MODE

CONTROL

MODE 0
MODE 1
MODE 2

GAI20-GAI28

GUDL0-GUDL2

GAFIX
WPOFF

HSY

VBLNK
SVREF

HCL

AD1BYPAD2BYP

BUFFER

DAC9

DAC9

HLNRS
UPTCV

V

DDA2

9
5

6
8

11
7

10
12

V

SSA1

GLIMB
GLIMT
WIPA
SLTCA

Fig.6 Analog input processing.

The pin numbers given in parenthesis refer to the 64-pin package.

1998 May 15 15

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

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CHRLUM

CODE

AD1BYPAD2BYP

BRIG
CONT
SATN

HUEC

DCCF

MGC645

V

DD1-5

V

SS1-5

(57,41,33,
25,18)

68,52,44,
34,27

(56,40,32,26,19)
67,51,43,35,28

(31) 42

(60) 3

(34 to 39),

45 to 50

(42 to 51),

53 to 62

(52) 63

QUADRATURE

DEMODULATOR

COMB

FILTERS

FORMATTER

OUTPUT

AND

INTERFACE

ACCUMULATOR

BURST GATE

LOW-PASS

LOOP FILTER

SUBCARRIER

INCREMENT

GENERATION

SUBCARRIER
GENERATION

DIVIDER

FCTCCSTD 1

RGB MATRIX

interpolation

dithering

DIT CBR

CHBW0
CHBW1

CSTD 0

INCS

RES

TCK

TDI

2 (59)
12 (3)

32 (23)

CONTROL

POWER-ON

CONTROL

TEST

BLOCK

TDO

TRST

11 (2)

1 (58)

TMS

13 (4)

LUM

Y

RTCO

n.c.

10 (1)

CLOCKS

CE

Y

UV

RGB

FEI

HREF

VPO
(9 : 0)

VPO
(15 : 10)

AND

PHASE

DEMOD.
AMPLITUDE
DETECTOR

OFTS0
OFTS1
RGB888
OEYC
OEHV
FECO
VRLN

GPSW
RTSE1
RTSE0
VIPB
VLOF
COLO
COMPO

BRIGHTNESS,

CONTRAST,

AND

SATURATION

CONTROL

GAIN

CONTROL

AND Y-DELAY

COMPENSATION

Fig.7 Chrominance circuit.

The pin numbers given in parenthesis refer to the 64-pin package.

1998 May 15 16

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

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CREF
LLC

XTALI
XTAL

VREF

RTS0

HS

VS

SDASCLIICSA

GPSW

I C BUS CONTROL

CLOCKS

SYNCHRONIZATION CIRCUIT

PREF

BYPS

APER0
APER1
VBLB

AUFD

HSB

HSS
FSEL
VTRC

STTC

FIDT

VNOI0
VNOI1
VTRC

VTRC

CE

RTS1

MGC654

LLC2

HLCK

V

DDA0

V

SSA0

53

61 63 62 30 29 17 27 28

16
24

15

54

55

22
20
21

DAC6

AND

WEIGHTING

ADDING

BAND-PASS

VARIABLE

FILTER

CHROMINANCE

TRAP

PREFILTER

AMPLIFIER

MATCHING

CLOCK

LINE-LOCKED
GENERATOR

2

LOOP FILTER

DETECTOR

PHASE

COARSE

DETECTOR

PHASE

FINE

SYNC SLICER

SYNC

PREFILTER

LINE 21

TEXT

SLICER

CLOCK

CRYSTAL

GENERATOR

TIME

DISCRETE

OSCILLATOR 2

INTERFACE

I C-BUS

PROCESSOR

VERTICAL

COUNTER

GENERATION

CLOCK

CIRCUIT

LUMINANCE CIRCUIT

BPSS0
BPSS1
PREF

LUM

VBLB

VBLB

Y

CLOCK CIRCUIT

INCS

STAGE

HPLL
VTRC
EXFIL

BYTE1
BYTE2

STATUS

2

2

Fig.8 Luminance and sync processing.

The pin numbers given in parenthesis refer to the 64-pin package.

1998 May 15 17

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

9 GAIN CHARTS

Fig.9 Amplifier curve.

handbook, halfpage

0

7.5

5.5

dB

3.5

1.5

−0.5

−4.5

−2.5

256 512

gain value (i)

MGC648

bit [8] = 1

factor

dB

= 20 x log10 gain =

(

512

768 − i

i > 256

bit [8] = 0

factor

dB

= 20 x log10 gain =

(

512

257 + i

(

i < 256

(

Fig.10 Clamp and gain flow.

WIPE = white peak level (254); SBOT = sync bottom level (1); CLL = clamp level [60 Y (128 C)];
HSY = horizontal sync pulse; HCL = horizontal clamp pulse.

handbook, full pagewidth

10

+ CLAMP − CLAMP

NO CLAMP

10 10

01 10

MGC647

fast − GAIN

slow + GAIN

+ GAIN − GAIN

HCL HSY

ADC

SBOT

WIPE

CLL

ANALOG INPUT

GAIN -><- CLAMP

VBLK

NO BLANKING ACTIVE

10

1998 May 15 18

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

handbook, full pagewidth

ANALOG INPUT

AMPLIFIER

ANTI-ALIAS FILTER

ADC

LUMA/CHROMA DECODER

X

HSY

>254

>254

<1

<4

>248

X = 0

X = 1

−

1/LLC2

+1/LLC2 −1/LLC2

+/− 0

+1/F

+1/L

GAIN ACCUMULATOR (18 BITS)

ACTUAL GAIN VALUE 9-BIT (AGV) [−6/+6 dB]

X

STOP

HSY

Y

UPDATE

FGV

MGC652

AGV

GAIN VALUE 9-BIT

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0

1

1

0

1

0

VBLK

1

0

NO ACTION

9

8

DAC

gain

HOLDG

Fig.11 Gain flow chart.

X = system variable; Y = AGV − FGVI > GUDL; VBLK = vertical blanking pulse;
HSY = horizontal sync pulse; AGV = actual gain value; FGV = frozen gain value.

1998 May 15 19

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

10 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

Note

1. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ resistor.

11 CHARACTERISTICS

V

DDD

= 4.5 to 5.5 V; V

DDA

= 4.75 to 5.25 V; T

amb

=25°C; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DDD

digital supply voltage −0.5 +6.5 V

V

DDA

analog supply voltage −0.5 +6.5 V

V

diff

voltage difference between V

SSAall

and

V

SSall

− 100 mV

T

stg

storage temperature −65 +150 °C

T

amb

operating ambient temperature 0 70 °C

T

amb(bias)

operating ambient temperature under bias −10 +80 °C

V

ESD

electrostatic discharge all pins note 1 −2000 +2000 V

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

DDD

digital supply voltage 4.5 5.0 5.5 V

I

DDD

digital supply current 100 130 160 mA

P

D

digital power 0.45 0.65 0.88 W

V

DDA

analog supply voltage 4.75 5.0 5.25 V

I

DDA

analog supply current 60 70 80 mA

P

A

analog power 0.32 0.35 0.38 W

P

A+D

analog and digital power 0.77 1.0 1.26 W

Analog part

I

clamp

clamping current VI= 1.25 V DC − 2 −µA

V

i(p-p)

input voltage (peak-to-peak
value), AC coupling required

coupling
capacitor = 10 nF; note 1

0.55 1.0 1.5 V

|Z

i

| input impedance clamping current off 200 −− kΩ

C

i

input capacitance −− 10 pF

α

cs

channel crosstalk fi= 5 MHz −−50 − dB

Analog-to-digital converters

B bandwidth at −3dB − 15 − MHz
φ

diff

differential phase (amplifier
plus anti-alias filter = bypass)

− 2 − deg

G

diff

differential gain (amplifier plus
anti-alias filter = bypass)

− 2 − %

f

ADC

ADC clock frequency 11 − 16 MHz
DLE DC differential linearity error − 0.5 − LSB
ILE DC integral linearity error − 1 − LSB

1998 May 15 20

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

Digital inputs

V

IL

LOW-level input voltage pins

SDA and SCL

−0.5 − +1.5 V

V

IH

HIGH-level input voltage pins

SDA and SCL

0.7V

DDD

− V

DDD

+ 0.5 V

V

IL(xtalI)

LOW-level CMOS input

voltage pin XTALI

−− 0.3V

DDD

V

V

IH(xtalI)

HIGH-level CMOS input

voltage pin XTALI

0.7V

DDD

−− V

V

ILn

LOW-level input voltage all

other inputs

−0.5 − +0.8 V

V

IHn

HIGH-level input voltage all

other inputs

2.0 − V

DDD

+ 0.5 V

I

LI

input leakage current −− 1 µA
C

i(I/O)

input capacitance inputs and outputs at

high-impedance

−− 8pF

C

i(n)

input capacitance all other

inputs

−− 8pF

Digital outputs

V

OL

LOW-level output voltage pins

SDA and SCL

SDA/SCL at 3 mA sink
current

−− 0.4 V

V

OL

LOW-level output voltage note 2 0 − 0.6 V
V

OH

HIGH-level output voltage note 2 2.4 − V

DDD

V

V

OL(clk)

LOW-level output voltage for

clocks

−0.5 − +0.6 V

V

OH(clk)

HIGH-level output voltage for

clocks

2.6 − V

DDD

+ 0.5 V

FEI input timing

t

SU;DAT

input data set-up time 13 −− ns
t

HD;DAT

input data hold time 3 −− ns

Data and control output timing

C

L

output load capacitance 15 − 50 pF
t

OHD;DAT

output hold time CL=15pF 5 −− ns
t

PD

propagation delay CL=40pF −− 21 ns
t

PDZ

propagation delay to 3-state −− 21 ns

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1998 May 15 21

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

Clock output timing (LLC and LLC2)

C

L(LLC)

output load capacitance 15 − 40 pF
T

cy

cycle time LLC 35 − 39 ns

LLC2 70 − 78 ns

δLLC duty factors for t

LLCH/tLLC

and

t

LLC2H/tLLC2

CL=40pF 40 − 60 %

t

r

rise time Vi= 0.6 to 2.6 V −− 5ns
t

f

fall time Vi= 2.6 to 0.6 V −− 5ns
t

dLLC2

delay time LLC output to LLC2

output

Vi= 1.5 V;
LLC/LLC2 = 40 pF

−1 − +1 ns

Data qualifier output timing (CREF)

t

OHD;CREF

output hold time CL=15pF 4 −− ns
t

PD;CREF

propagation delay from

positive edge of LLC

CL=40pF −− 20 ns

Clock input timing (XTALI)

δXTALI duty factor for t

XTALIH/tXTALI

nominal frequency 40 − 60 %

Horizontal PLL

f

Hn

nominal line frequency 50 Hz field − 15625 − Hz

60 Hz field − 15734 − Hz

∆fH/f

Hn

permissible static deviation −− 5.7 %

Subcarrier PLL

f

SCn

nominal subcarrier frequency PALBGHI and NTSC 443 − 4433619 − Hz

NTSC M − 3579545 − Hz
PAL M − 3575612 − Hz
PAL N − 3582056 − Hz

∆f

SCH/fSCHn

lock-in range ±400 −− Hz

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1998 May 15 22

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

Notes

1. The levels must be measured with load circuits; 1.2 kΩ at 3 V (TTL load); CL= 50 pF.

2. The effects of rise and fall times are included in the calculation of t

OHD;DAT

, tPD and t

PDZ

. Timings and levels refer to

drawings and conditions illustrated in Figs 12 and 13.

Table 1 Processing delay

Crystal oscillator

f

n

nominal frequency 3rd harmonic − 24.576 − MHz
∆f/f

n

permissible nominal

frequency deviation

−− ±50 10

−6

∆f/fn(T) permissible nominal

frequency deviation with

temperature

−− ±20 10

−6

CRYSTAL SPECIFICATION (X1)
T

ambX1

operating ambient

temperature

0 − 70 °C

C

L

load capacitance 8 −− pF
R

s

series resonance resistor − 40 80 Ω
C

1

motional capacitance − 1.5 ±20% − fF
C

0

parallel capacitance − 3.5 ±20% − pF

FUNCTION

TYPICAL ANALOG DELAY

AI22 −> ADCIN (AOUT) (ns)

DIGITAL DELAY

ADCIN → VPO (LLC-CLOCKS)

[YDEL(2 to 0) = 000]

Without amplifier or anti-alias filter 14

139With amplifier, without anti-alias filter 30

With amplifier plus anti-alias filter 72

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1998 May 15 23

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

12 TIMING DIAGRAMS

Fig.12 Clock/data timing (8-bit CCIR-656 format of the VPO-bus).

An explanation of the output formats is given in Table 5.

handbook, full pagewidth

2.4 V

t

LLC

t

f

t

PD

t

OHD;DAT

t

LLCL

t

LLCH

OUTPUTS VPO, HREF,
VREF, VS, HS

CLOCK OUTPUT LLC

t

r

0.6 V

2.6 V

1.5 V

0.6 V

MGC658

Fig.13 Clock/data timing (12/16-bit CCIR-601 format of the VPO-bus).

An explanation of the output formats is given in Table 5. The FEI timing of the VPO-bus is illustrated in Figs 15 and 17.

handbook, full pagewidth

2.4 V

0.6 V

t

LLC

t

f

t

PD

t

OHD;CREF

t

dLLC2

t

r

t

LLCL

t

LLCH

2.4 V

0.6 V

OUTPUTS VPO, HREF,

CLOCK OUTPUT LLC

CLOCK OUTPUT LLC2

1.5 V

0.6 V

2.6 V

1.5 V

0.6 V

2.6 V

VREF, VS, HS

OUTPUT CREF

t

OHD;DAT

t

dLLC2

t

PD

MGC659

t

LLC

t

PD

t

OHD;CREF

1998 May 15 24

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

Fig.14 Clock/data timing for RGB888 output format.

An explanation of the output formats is given in Table 5.

handbook, full pagewidth

MBH227

2.4 V

1.5 V

0.6 V

2.4 V

1.5 V

0.6 V

2.4 V

1.5 V

0.6 V

CLOCK OUTPUT LLC

OUTPUT CREF

RGB (8, 8, 8) data

VPO15 to VPO8

RGB (8, 8, 8) data

VPO7 to VPO0

2.4 V

1.5 V

0.6 V

t

OHD;DAT

t

OHD;DAT

t

OHD;CREF

t

OHD;CREF

t

OHD;CREF

t

PD;CREF

t

PD

t

PD;CREF

R(7 : 3)
G(7 : 5)

G(4 : 2)
B(7 : 3)

R(2 : 0)
G(1 : 0)
B(2 : 0)

t

LLCL

t

LLC

t

LLC

t

f

t

r

t

LLCH

Fig.15 FEI timing diagram (FEI sampling at CREF = HIGH).

I2C-bit FECO = 1.

handbook, full pagewidth

LLC

CREF

HREF

FEI

VPO

to 3-state

from 3-state

MGC656

t

PDZ

t

PD

t

HD;DAT

t

SU;DAT

t

OHD;DAT

1998 May 15 25

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

Fig.16 Real time control output.

(1) Set to zero for one transmission, if a phase reset of the fsc- DTO is applied via I2C-bit CDTO. RTCO sequence is generated in LLC/4.
The HPLL increment represents the actual LFCO frequency (f

LFCO

× 4=f

LLC

); 16 LSB from 20, upper four bits are fixed to 0100b

Where: f

XTAL

= 24.576 MHz, word length DTO2 = 20 bits.

The f

sc

increment represents the actual subcarrier frequency (related to the actual clock); 23 LSB from 24, MSB is 0b.

Where: word length DTO1 = 24 bits.

f

LFCO

INCR

HPLLfXTAL

×

2

word lengthDTO2

------------------------------------------------ -

=

f

sc

INCR

FSCPLLfXTAL

×

2

word lengthDTO1

-------------------------------------------------------

INCR

HPLL

2

19

----------------------------

×=

handbook, full pagewidth

TIME SLOT:

BIT NO.:

transmitted once per line

22

1

21

1920

15

1617

18

7

8

9

11 1012

13

14

SEQUENCE

19

0 67

2

3

6

452

3

0

16

45

RESERVED

16

INCR

FSCPLL

MGC649

63

0

1

RESERVED

128

HIGH

LOW

15

INCR

HPLL

RESERVED

1

68

DTO RESET

(1)

50 Hz fields: 235
60 Hz fields: 232

Fig.17 FEI timing diagram (FEI sampling at CREF = LOW).

Timing is compatible with SAA7110; I2C-bit FECO = 0.

handbook, full pagewidth

LLC

CREF

HREF

VPO

t

SU;DAT

t

HD;DAT

to 3-state

MGC657

from 3-state

t

OHD;DAT

t

PD

t

PDZ

FEI

1998 May 15 26

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

Fig.18 HREF timing diagram.

handbook, full pagewidth

0

LLC

CREF

LLC2

HREF

Yn

UVn

HREF

Yn

UVn

1234

U0 V0 U2 V2 U4

END OF ACTIVE LINE

START OF ACTIVE LINE

719718717716715

U718 V718

MGC646

V716U716V714

1998 May 15 27

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

Fig.19 Horizontal timing diagram.

(1) PLIN is switched to output RTS1 via I2C-bit RTSE1 = 0.
(2) See Table 1.

handbook, full pagewidth

0

108

−107

107

−106

MGC664

CVBS

50 x 2/LLC

139 x 1/LLC

7 x 2/LLC

Y - output

HREF (50 Hz)

12 x 2/LLC

720 x 2/LLC

144 x 2/LLC

3 x 2/LLC

138 x 2/LLC

720 x 2/LLC

burst

RTS1 (PLIN)

(1)

processing delay CVBS->VPO

(2)

0

0

4/LLC

HREF (60 Hz)

HS (60 Hz)

sync clipped

16 x 2/LLC

HS (50 Hz)

programming range

(step size: 8/LLC)

HS (60 Hz)

programming range

(step size: 8/LLC)

HS

113 x 2/LLC

1998 May 15 28

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

Fig.20 Vertical timing diagram for 50 Hz [nominal input signal VNL in normal mode (VNOI = 00b)].

(1) ODD is switched to output RTS0 via I2C-bit RTSE0 = 0.
The luminance peaking and the chrominance trap are bypassed during VREF = 0 if I2C-bit VBLB is set to logic 1.
The chrominance delay line (chroma-comb filter for NTSC, phase error correcting for PAL) is disabled during VREF = 0.

handbook, full pagewidth

313 314

315 316

317

318

319

335 336

1234567822625

HREF

input CVBS

b: 2nd field

a: 1st field

VREF
VREF

VREF

VREF

VRLN = 1

VRLN = 0

624

623

622

23

HREF

input CVBS

312

311

310

VRLN = 0

337

MGC662

503 x 2/LLC

VS

RTS0 (ODD)

(1)

RTS0 (ODD)

(1)

320

VS

71 x 2/LLC

VRLN = 1

1998 May 15 29

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

Fig.21 Vertical timing diagram for 60 Hz [nominal input signal VNL in normal mode (VNOI = 00b)].

(1) ODD is switched to output RTS0 via I2C-bit RTSE0 = 0.
(2) Line numbers in parenthesis refer to CCIR line counting.
The luminance peaking and the chrominance trap are bypassed during VREF = 0 if I2C-bit VBLB is set to logic 1.
The chrominance delay line (chroma-comb filter for NTSC, phase error correcting for PAL) is disabled during VREF = 0.

andbook, full pagewidth

VS

(266) (267) (268) (269) (270) (271) (272) (273) (274)

(4) (5) (6) (7) (8) (9)

(10)

(11)

(20)

(3)

HREF

b: 2nd field

a: 1st field

input CVBS

(2)(1)

(525)

(21)

(22)

(283)

(284)

(265)

(264)

(263)

(262)

VRLN = 1

VRLN = 0

VRLN = 1

VRLN = 0

1234567

8

17

525

524

523

522

18 19

263 264 265 266 267 268 269 270 271

280

281

262

261

260

259

(285)

282

(2)

(2)

MGC663

493 x 2/LLC

RTS0 (ODD)

(1)

61 x 2/LLC

VREF

VREF

VREF

VREF

VS

HREF

input CVBS

RTS0 (ODD)

(1)

1998 May 15 30

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

Table 2 Digital output control

Notes

1. OFTS(1 : 0) = 10 or 01 or 00.

2. OFTS(1 : 0) = 11.

13 CLOCK SYSTEM

13.1 Clock generation circuit

The internal CGC generates the system clocks LLC, LLC2
and the clock reference signal CREF. The internal
generated LFCO (triangular waveform) is multiplied by
2 or 4 via the analog PLL (including phase detector, loop
filter, VCO and frequency divider). The rectangular output
signals have a 50% duty factor.

OEYC FEI

VPO

15 to 0

(1)

15 to 8

(2)

7to0

(2)

00 Z Z Z
1 0 active active Z
01 Z Z Z
1 1 Z active Z

Table 3 Clock frequencies

CLOCK FREQUENCY (MHz)

XTAL 24.576

LLC 27
LLC2 13.5
LLC4 6.75
LLC8 3.375

Fig.22 Block diagram of clock generation circuit.

handbook, full pagewidth

BAND PASS

FC = LLC/4

ZERO

CROSS

DETECTION

PHASE

DETECTION

LOOP

FILTER

DIVIDER

1/2

DIVIDER

1/2

OSCILLATOR

DELAY CREF

MGC632

LLC2

LLC

LFCO

1998 May 15 31

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

13.2 Power-on control

Power-on reset is activated at power-on, chip enable, PLL clock generation failure and if the supply voltage falls below

3.5 V. The RES signal can be applied to reset other circuits of the digital picture processing system.

Fig.23 Power-on control circuit.

ndbook, full pagewidth

MGC633

128 LCC

896 LCC

digital delay

some ms

20 to 200 µs

PLL-delay

<

1 ms

RES

LLC

RESINT

LLCINT

XTAL

CE

POC V

DDA

POC

LOGIC

ANALOG

POC V

DDD

DIGITAL

POC

DELAY

CLOCK

PLL

CE

LLC

CLK0

RES

CE = chip enable input; XTAL = crystal oscillator output; LLCINT = internal system clock;
RESINT = internal reset; LLC = line-locked system clock output; RES = reset output (active LOW).

1998 May 15 32

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

Table 4 Power-on control sequence

14 OUTPUT FORMATS
Table 5 Output formats

Notes

1. Values in accordance with CCIR-601.

2. Before and after the video data, video timing codes are inserted in accordance with CCIR-656.

3. Values not defined during HREF = LOW.

4. CREF = 0 (see Fig.14).

5. CREF = 1 (see Fig.14).

INTERNAL POWER-ON
CONTROL SEQUENCE

PIN OUTPUT STATUS FUNCTION

Directly after power-on
asynchronous reset

VPO15 to VPO0, RTCO, RTS0, RTS1,
GPSW, HREF, VREF, HS, VS, LLC, LLC2
and CREF are in high-impedance state

direct switching to high impedance for
20 to 200 ms

Synchronous reset
sequence

LLC, LLC2, CREF, RTCO, RTS0, RTS1,
GPSW and SDA become active;
VPO15 to VPO0, HREF, VREF, HS and VS
are held in high-impedance state

internal reset sequence

Status after power-on
control sequence

VPO15 to VPO0, HREF, VREF, HS and VS
are held in high-impedance state

after power-on (reset sequence) a complete
I

2

C-bus transmission is required

BUS SIGNAL 411 (12-BIT) 422 (16-BIT)

(1)

CCIR-656 (8-BIT)

(2)

RGB (16-BIT)

(3)

RGB (24-BIT)

(3)

VPO15 Y07Y17Y27Y

37

Y

07

Y

17

U07Y07V07Y

17

R4 R7 R7

VPO14 Y

06Y16Y26Y36

Y

06

Y

16

U06Y06V06Y

16

R3 R6 R6

VPO13 Y

05Y15Y25Y35

Y

05

Y

15

U05Y05V05Y

15

R2 R5 R5

VPO12 Y

04Y14Y24Y34

Y

04

Y

14

U04Y04V04Y

14

R1 R4 R4

VPO11 Y

03Y13Y23Y33

Y

03

Y

13

U03Y03V03Y

13

R0 R3 R3

VPO10 Y

02Y12Y22Y32

Y

02

Y

12

U02Y02V02Y

12

G5 G7 G7

VPO9 Y

01Y11Y21Y31

Y

01

Y

11

U01Y01V01Y

11

G4 G6 G6

VPO8 Y

00Y10Y20Y30

Y

00

Y

10

U00Y00V00Y

10

G3 G5 G5

VPO7 U

07U05U03U01

U

07

V

07

XXXX G2 G4 R2

VPO6 U

06U04U02U00

U

06

V

06

XXXX G1 G3 R1

VPO5 V

07V05V03V01

U

05

V

05

XXXX G0 G2 R0

VPO4 V

06V04V02V00

U

04

V

04

XXXX B4 B7 G1

VPO3 X X X X U

03

V

03

XXXX B3 B6 G0

VPO2 X X X X U

02

V

02

XXXX B2 B5 B2

VPO1 X X X X U

01

V

01

XXXX B1 B4 B1

VPO0 X X X X U

00

V

00

XXXX B0 B3 B0
Pixel order Y 0 1 2 3 0 1 0 1 − note 4 note 5
Pixel order UV 0 0 0 −−
Data rates LLC2 LLC2 LLC LLC2 LLC
I

2

C-bus

control signals

OFTS0 = 0 OFTS0 = 1 OFTS0 = 1 OFTS0 = 0 OFTS0 = 0
OFTS1 = 1 OFTS1 = 0 OFTS1 = 1 OFTS1 = 0 OFTS1 = 0

RGB888 = X RGB888 = X RGB888 = X RGB888 = 0 RGB888 = 1

1998 May 15 33

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

Fig.24 VPO output signal range with default BCS settings.

Equations for modification to the YUV levels via BCS control I2C bytes BRIG, CONT and SATN.
Luminance:

Chrominance:

It should be noted that the resulting levels are limited to 1 to 254 in accordance with CCIR-601/656 standard.

Y

OUT

Int

CONT

71

----------------- -

Y128–()× BRIG+=

UV

OUT

Int

SATN

64

---------------- -

Cr Cb, 128–()× 128+=

handbook, full pagewidth

LUMINANCE 100%

+255
+235

+128

+16

0

white

black

U-COMPONENT

+255
+240

+212 +212

+128

+16

+44

0

blue 100%
blue 75%

yellow 75%
yellow 100%

colourless

V-COMPONENT

+255
+240

+128

+16

+44

0

red 100%
red 75%

cyan 75%

cyan 100%

colourless

MGC634

a. Y output range. b. U output range (Cb). c. V output range (Cr).

CCIR Rec. 602 digital levels.

Fig.25 Oscillator application.

handbook, full pagewidth

XTAL

XTALI

65 (54)

66 (55)

MGC635

XTAL

L = 10 µH ±20%

C =
10 pF

C =
10 pF

C =
1 nF

quartz (3rd harmonic)

24.576 MHz

XTALI

65 (54)

66 (55)

SAA7111 SAA7111

The pin numbers given in parenthesis refer to the 64-pin package.

a. With quartz crystal. b. With external clock.

1998 May 15 34

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

15 APPLICATION INFORMATION

handbook, full pagewidth

Q1(24.576 MHz)

VPO(15 : 0)

SCL

V

DDD

AI22

FEI

SDA

RTCO

VS

HS

AOUT

GPSW

RTS0

RTS1

RES

CREF

LLC2

LLC

HREF

V

SS

V

SS

V

SSA

V

DDA

V

SSA

V

DD

V

SS

V

SS

VREF

V

SS

SAA7111

R4

75 Ω

C4

10 nF

C7

100 nF

100 nF

100 nF

100 nF

C8

C9

C11

C12

C13

C14

C15

R6

1 kΩ

n.c.

n.c.

V

SSA2

V

SS

V

SS1VSS2VSS3VSS4VSS5

IICSA

V

SSA1

V

SSA0

V

DDA0VDDA1VDDA2

V

DD1VDD2VDD3VDD4VDD5

TMS

TDI

TDO

TCK

TRST

n.c.

C17

L1

10
µH

C16
1 nF

10 pF

10 pF

C18

R5

1 kΩ

27

(18)

34

(25)

44

(33)

52

(41)

68

(57)

12
(3)

16
(7)

20

(11)

24

(15)

(34) 45
(35) 46
(36) 47
(37) 48
(38) 49
(39) 50
(42) 53
(43) 54
(44) 55
(45) 56
(46) 57
(47) 58
(48) 59

(31) 42

(27) 38
(30) 41

(60) 3

(14) 23

(53) 64

(28) 39
(29) 40

(20) 29
(21) 30
(22) 31
(23) 32

(17) 26

36

37

9

8

(64)

7

1

(58)

2

(59)

(61)

4

(19)

28

(26)

35

(32)

43

(40)

51

(56)

67

(13)

22

(5)
14

(9)

18

10

(16)

25

11

(2)

13
(4)

15 (6)

6 (63)
5 (62)

63 (52)

33 (24)

66 (55)

65 (54)

XTAL

XTALI

n.c.

n.c.

MGC651

V

SSA

BST

V

SS

n.c.

n.c.

n.c.

n.c.

(49) 60
(50) 61
(51) 62

100 nF

100 nF

100 nF

100 nF

R3

75 Ω

C3

10 nF

V

SSA

AI21

R2

75 Ω

C2

10 nF

V

SSA

17 (8)

AI12

R1

75 Ω

C1

10 nF

V

SSA

19 (10)

AI11

21 (12)

15
14
13
12

11
10
9
8
7
6
5
4
3
2
1
0

Fig.26 Application diagram.

The pin numbers given in parenthesis refer to the QFP64 package.

1998 May 15 35

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

Fig.27 Application diagram for RGB 24-bit output format.

The pin numbers given in parenthesis refer to the QFP64 package.
I2C-bus control bits:
OFTS(1 : 0) = 00 (subaddress 10h, bits D7 and D6).
RGB888 = 1 (subaddress 12h, bit D3).

handbook, full pagewidth

OEN
D7

7
6
5
4
3
2
1
0

D6
D5
D4

e.g.

74HCT574

D3
D2
D1
D0

(44) 55
(45) 56
(46) 57
(47) 58
(48) 59
(49) 60
(50) 61
(51) 62

(31) 42

HREF
(17) 26
(27) 38
(30) 41

(60) 3
(28) 39
(29) 40
(53) 64
(14) 23
(20) 29
(21) 30
(32) 31
(23) 32

V

SS

V

SS

V

SS

CLK

O7

3

R (2 : 0)

R (7 : 0)
O6
O5
O4
O3
O2
O1

00

V

DDVDD

3

3

3

2

G (1 : 0)

G (7 : 0)

3

B (2 : 0)

B (7 : 0)

LLC2N

MGD137

LLC2

e.g. 74F240

B (7 : 3)VPO (4 : 0)

VPO

(7 : 0)

SAA7111

VPO (15 : 11) R (7 : 3)

G (7 : 5)

G (4 : 2)

VPO (10 : 8)

VPO (7 : 5)

5

8

8

VREF
HS
VS
RTCO
RTS1
RTS0
GPSW
AOUT
LLC

CREF
RES

8

15
14
13
12
11
10
9
8

(34) 45
(35) 46
(36) 47
(37) 48
(38) 49
(39) 50
(42) 53
(43) 54

VPO

(15 : 8)

15.1 Layout hints

Use separate ground planes for analog and digital ground.
Connect these planes at one point directly under the
device, by using a zero Ω resistor. Use separate supply
lines for analog and digital supply. Place the supply
decoupling capacitors nearby the supply pins.

Place the coupling (clamp) capacitors close to the analog
input pins. Place the termination resistors close to the
coupling capacitors. Care should be exercised concerning
the hidden layout capacitors around the crystal
application. To avoid reflection effects use serial resistors
in the clock, sync and data lines.

1998 May 15 36

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

16 I2C-BUS DESCRIPTION

16.1 I

2

C-bus format

Table 6 Write procedure

Table 7 Read procedure (combined format)

Table 8 Description of I

2

C-bus format

Notes

1. If more than one byte DATA is transmitted then the auto-increment of the subaddress is performed.

2. During slave transmitter mode the SCL-LOW period may be extended by pulling SCL to LOW (in accordance with
the I

2

C-bus specification).

3. The I2C-bus subaddress 00 has to be initialized with 0 before being read.

S SLAVE ADDRESS W ACK(s) SUBADDRESS ACK(s) DATA (N BYTES) ACK(s) P

S SLAVE ADDRESS W ACK(s) SUBADDRESS ACK(s)

Sr SLAVE ADDRESS R ACK(s) DATA (N BYTES) ACK(m) P

CODE DESCRIPTION

S START condition
Sr repeated START condition
Slave address W 0100 1000b (IICSA = LOW) or 0100 1010b (IICSA = HIGH)
Slave address R 0100 1001b (IICSA = LOW) or 0100 1011b (IICSA = HIGH)
ACK(s) acknowledge generated by the slave
ACK(m) acknowledge generated by the master
Subaddress subaddress byte; see Table 9
Data data byte, see; note 1 and Table 9
P STOP condition
X = LSB slave

address

read/write control bit; X = 0, order to write (the circuit is slave receiver); X = 1, order to read
(the circuit is slave transmitter)

Slave address read = 49H or 4BH; note 2

write = 48H or 4AH
IICSA = 0 or 1

Subaddress 00H chip version read and write; note 3

01H reserved −
02H to 05H front-end part read and write
06H to 12H decoder part read and write
13H to 19H reserved −
1AH to 1CH Line-21 text slicer part read only
1DH to 1EH reserved −
1FH status byte read only

1998 May 15 37

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

Table 9 I2C-bus receiver/transmitter overview

Note

1. All unused control bits must be programmed with 0.

16.2 I

2

C-bus detail

The I2C-bus receiver slave address is 48H/49H. Subaddresses 0F, 1D, 1E and 13 to 19 are reserved; subaddress 01 is
reserved for chip version.

SLAVE ADDRESS

READ WRITE IICSA

49H and 4BH 48H and 4AH 0 and 1

REGISTER
FUNCTION

SUB-

ADDR.

D7 D6 D5 D4 D3 D2 D1 D0

Chip version 00 ID07 ID06 ID05 ID04 ID03 ID02 ID01 ID00
Reserved 01

(1) (1) (1) (1) (1) (1) (1) (1)

Analog input control 1 02 FUSE1 FUSE0 GUDL2 GUDL1 GUDL0 MODE2 MODE1 MODE0
Analog input control 2 03

(1)

HLNRS VBSL WPOFF HOLDG GAFIX GAI28 GAI18
Analog input control 3 04 GAI17 GAI16 GAI15 GAI14 GAI13 GAI12 GAI11 GAI10
Analog input control 4 05 GAI27 GAI26 GAI25 GAI24 GAI23 GAI22 GAI21 GAI20
Horizontal sync start 06 HSB7 HSB6 HSB5 HSB4 HSB3 HSB2 HSB1 HSB0
Horizontal sync stop 07 HSS7 HSS6 HSS5 HSS4 HSS3 HSS2 HSS1 HSS0
Sync control 08 AUFD FSEL EXFIL

(1)

VTRC HPLL VNOI1 VNOI0
Luminance control 09 BYPS PREF BPSS1 BPSS0 VBLB UPTCV APER1 APER0
Luminance brightness 0A BRIG7 BRIG6 BRIG5 BRIG4 BRIG3 BRIG2 BRIG1 BRIG0
Luminance contrast 0B CONT7 CONT6 CONT5 CONT4 CONT3 CONT2 CONT1 CONT0
Chroma saturation 0C SATN7 SATN6 SATN5 SATN4 SATN3 SATN2 SATN1 SATN0
Chroma Hue control 0D HUEC7 HUEC6 HUEC5 HUEC4 HUEC3 HUEC2 HUEC1 HUEC0
Chroma control 0E CDTO CM99 CSTD1 CSTD0 DCCF FCTC CHBW1 CHBW0
Reserved 0F

(1) (1) (1) (1) (1) (1) (1) (1)

Format/delay control 10 OFTS1 OFTS0 HDEL1 HDEL0 VRLN YDEL2 YDEL1 YDEL0
Output control 1 11 GPSW

(1)

FECO COMPO OEYC OEHV VIPB COLO

Output control 2 12 RTSE1 RTSE0

(1)

CBR RGB888 DIT AOSL1 AOSL0

Reserved 13-19

(1) (1) (1) (1) (1) (1) (1) (1)

Text slicer status 1A

(1) (1) (1) (1)

F2VAL F2RDY F1VAL F1RDY

Decoded bytes of the
text slicer

1B P1 BYTE16 BYTE15 BYTE14 BYTE13 BYTE12 BYTE11 BYTE10
1C P2 BYTE26 BYTE25 BYTE24 BYTE23 BYTE22 BYTE21 BYTE20

Reserved 1D-1E

(1) (1) (1) (1) (1) (1) (1) (1)

Status byte 1F STTC HLCK FIDT GLIMT GLIMB WIPA SLTCA CODE

1998 May 15 38

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

16.2.1 SUBADDRESS 00

Table 10 Chip version SA 00, D7 to D0

Note

1. The I

2

C-bus subaddress 00 has to be initialized with 0 prior to reading it.

16.2.2 S

UBADDRESS 02

Table 11 Analog control 1 (mode select; see Figs 28 to 35) SA 02, D2 to D0; note 1

Note

1. For modes 0 to 3 use BYPS (SA 09, D7) = 0 (chrominance trap active) and for modes 4 to 7 use BYPS = 1
(chrominance trap bypassed).

Table 12 Analog control 1 SA 02, D5 to D3 (see Fig.11)

Table 13 Analog control 1 SA 02, D7 and D6

FUNCTION

CONTROL BITS

ID07 ID06 ID05 ID04 ID03 ID02 ID01 ID00

Chip version in read mode

(1)

0000XXXX

chip version number reserved for chip name

FUNCTION

CONTROL BITS D2 TO D0

MODE 2 MODE 1 MODE 0

Mode 0: CVBS (automatic gain) 0 0 0
Mode 1: CVBS (automatic gain) 0 0 1
Mode 2: CVBS (automatic gain) 0 1 0
Mode 3: CVBS (automatic gain) 0 1 1
Mode 4: Y (automatic gain) + C (gain channel 2 fixed to GAI2 level) 1 0 0
Mode 5: Y (automatic gain) + C (gain channel 2 fixed to GAI2 level) 1 0 1
Mode 6: Y (automatic gain) + C (gain channel 2 adapted to Y gain) 1 1 0
Mode 7: Y (automatic gain) + C (gain channel 2 adapted to Y gain) 1 1 1

DECIMAL VALUE UPDATE HYSTERESIS FOR 9-BIT GAIN

CONTROL BITS D5 TO D3

GUDL 2 GUDL 1 GUDL 0

0.... off 0 0 0

....7 ±7 LSB 1 1 1

ANALOG FUNCTION SELECT FUSE

CONTROL BITS D7 AND D6

FUSE 1 FUSE 0

Amplifier plus anti-alias filter bypassed 0 0

01
Amplifier active 1 0
Amplifier plus anti-alias filter active 1 1

1998 May 15 39

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

Fig.28 Mode 0; CVBS (automatic gain).

handbook, halfpage

AI22
AI21

AI12
AI11

CHROMA

LUMA

AD2

AD1

MGC637

Fig.29 Mode 1; CVBS (automatic gain).

handbook, halfpage

MGC638

AI22
AI21

AI12
AI11

CHROMA

LUMA

AD2

AD1

Fig.30 Mode 2; CVBS (automatic gain).

handbook, halfpage

MGC639

AI22
AI21

AI12
AI11

CHROMA

LUMA

AD2

AD1

Fig.31 Mode 3; CVBS (automatic gain).

handbook, halfpage

MGC640

AI22
AI21

AI12
AI11

CHROMA

LUMA

AD2

AD1

Fig.32 Mode 4 Y (automatic gain) + C

(gain channel 2 fixed to GAI1 level).

handbook, halfpage

MGC641

AI22
AI21

AI12
AI11

CHROMA

LUMA

AD2

AD1

Fig.33 Mode 5 Y (automatic gain) + C

(gain channel 2 fixed to GAI1 level).

handbook, halfpage

MGC642

AI22
AI21

AI12
AI11

CHROMA

LUMA

AD2

AD1

Fig.34 Mode 6 Y (automatic gain) + C

(gain channel 2 adapted to Y gain).

handbook, halfpage

MGC643

AI22
AI21

AI12
AI11

CHROMA

LUMA

AD2

AD1

Fig.35 Mode 7 Y (automatic gain) + C

(gain channel 2 adapted to Y gain).

handbook, halfpage

MGC644

AI22
AI21

AI12
AI11

CHROMA

LUMA

AD2

AD1

1998 May 15 40

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

16.2.3 SUBADDRESS 03
Table 14 Analog control 2 (AICO2)

16.2.4 S

UBADDRESS 04

Table 15 Gain control analog (AIC03); static gain control channel 1 GAI1 SA 04, D7 to D0

FUNCTION BIT NAME LOGIC LEVEL CONTROL BIT

Static gain control channel 1 (GAI18)

Sign bit of gain control GAI18 see Table 15 D0

Static gain control channel 2 (GAI28)

Sign bit of gain control GAI28 see Table 16 D1

Gain control fix (GAFIX)

Automatic gain controlled by MODE 1 and MODE 0 GAFIX 0 D2
Gain control is user programmable via GAI1 + GAI2 GAFIX 1 D2

Automatic gain control integration (HOLDG)

AGC active HOLDG 0 D3
AGC integration hold (freeze) HOLDG 1 D3

White peak off (WPOFF)

White peak control active WPOFF 0 D4
White peak off WPOFF 1 D4

Vertical blanking select (VBSL)

Long vertical blanking VBSL 0 D5
Short vertical blanking VBSL 1 D5

HL not reference select (HLNRS)

Normal clamping by HL not HLNRS 0 D6
Reference select by HL not HLNRS 1 D6

DECIMAL

VALUE

GAIN (dB)

SIGN

BIT

CONTROL BITS D7 TO D0

GAI18 GAI17 GAI16 GAI15 GAI14 GAI13 GAI12 GAI11 GAI10

0.... −5.98 000000000

....255 0 011111111

256.... 0 100000000

....511 5.98 111111111

1998 May 15 41

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

16.2.5 SUBADDRESS 05
Table 16 Gain control analog (AIC04); static gain control channel 2 GAI2 SA 05

16.2.6 S

UBADDRESS 06

Table 17 Horizontal sync begin SA 06, D7 to D0

16.2.7 S

UBADDRESS 07

Table 18 Horizontal sync stop SA 07

\DECIMAL

VALUE

GAIN

(dB)

SIGN BIT

(SA 03, D1)

CONTROL BITS D7 to D0

GAI28 GAI27 GAI26 GAI25 GAI24 GAI23 GAI22 GAI21 GAI20

0.... −5.98 0 0 0000000

....255 0 0 1 1111111

256.... 0 1 0 0000000

....511 5.98 1 1 1111111

DELAY TIME

(STEP SIZE = 8/LLC)

CONTROL BITS D7 to D0

HSB7 HSB6 HSB5 HSB4 HSB3 HSB2 HSB1 HSB0

−128...−108 forbidden (outside available central counter range)

−107... 1 0 0 1 0 1 0 1

...108 (50 Hz) 0 1 1 0 1 1 0 0
...107 (60 Hz) 0 1 1 0 1 0 1 1

109...127 (50 Hz)
forbidden (outside available central counter range)

108...127 (60 Hz)

DELAY TIME

(STEP SIZE = 8/LLC)

CONTROL BITS D7 to D0

HSS7 HSS6 HSS5 HSS4 HSS3 HSS2 HSS1 HSS0

−128...−108 forbidden (outside available central counter range)

−107... 1 0 0 1 0 1 0 1

...108 (50 Hz) 0 1 1 0 1 1 0 0
...107 (60 Hz) 0 1 1 0 1 0 1 1

109...127 (50 Hz)
forbidden (outside available central counter range)

108...127 (60 Hz)

1998 May 15 42

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

16.2.8 SUBADDRESS 08

Table 19 Sync control SA 08, D7 to D5, D3 to D0

FUNCTION BIT NAME LOGIC LEVEL CONTROL BIT

Vertical noise reduction (VNOI)

Normal mode VNOI1 0 D1

VNOI0 0 D0

Searching mode VNOI1 0 D1

VNOI0 1 D0

Free running mode VNOI1 1 D1

VNOI0 0 D0

Vertical noise reduction bypassed VNOI1 1 D1

VNOI0 1 D0

Horizontal PLL (HPLL)

PLL closed HPLL 0 D2
PLL open, horizontal frequency fixed HPLL 1 D2

TV/VTR mode select (VTRC)

TV mode
(recommended for poor quality TV signals only)

VTRC 0 D3

VTR mode (recommended as default setting) VTRC 1 D3

Extended loop filter (EXFIL)

Word width of the loop filter (LF2) amplification = 16-bit EXFIL 0 D5
Word width of the loop filter (LF2) amplification = 14-bit EXFIL 1 D5

Field selection (FSEL)

50 Hz and 625 lines FSEL 0 D6
60 Hz and 525 lines FSEL 1 D6

Automatic field detection (AUFD)

Field state directly controlled via FSEL AUFD 0 D7
Automatic field detection AUFD 1 D7

1998 May 15 43

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

16.2.9 SUBADDRESS 09

Table 20 Luminance control

Note

1. Not to be used with bypassed chrominance trap.

FUNCTION BIT NAME LOGIC LEVEL CONTROL BIT

Aperture factor (APER)

Aperture factor = 0 APER1 0 D1

APER0 0 D0

Aperture factor = 0.25 APER1 0 D1

APER0 1 D0

Aperture factor = 0.5 APER1 1 D1

APER0 0 D0

Aperture factor = 1.0 APER1 1 D1

APER0 1 D0

Update time interval for AGC value (UPTCV)

Horizontal update (once per line) UPTCV 0 D2
Vertical update (once per field) UPTCV 1 D2

Vertical blanking luminance bypass (VBLB

Active luminance processing VBLB 0 D3
Luminance bypass during vertical blanking VBLB 1 D3

Aperture band-pass (centre frequency) (BPSS) D5 and D4

Centre frequency = 4.1 MHz BPSS1 0 D5

BPSS0 0 D4

Centre frequency = 3.8 MHz; note 1 BPSS1 0 D5

BPSS0 1 D4

Centre frequency = 2.6 MHz; note 1 BPSS1 1 D5

BPSS0 0 D4

Centre frequency = 2.9 MHz; note 1 BPSS1 1 D5

BPSS0 1 D4

Prefilter active (PREF)

Bypassed PREF 0 D6
Active PREF 1 D6

Chrominance trap bypass (BYPS)

Chrominance trap active; default for CVBS mode BYPS 0 D7
Chrominance trap bypassed; default for S-Video mode BYPS 1 D7

1998 May 15 44

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

16.2.10 SUBADDRESS 0A
Table 21 Luminance brightness control BRIG7 to BRIG0 SA 0A

16.2.11 S

UBADDRESS 0B

Table 22 Luminance contrast control CONT7 to CONT0 SA 0B

16.2.12 S

UBADDRESS 0C

Table 23 Chrominance saturation control SATN7 to SATN0 SA 0C

16.2.13 S

UBADDRESS 0D

Table 24 Chrominance hue control HUEC7 to HUEC0 SA 0D

OFFSET

CONTROL BITS D7 to D0

BRIG7 BRIG6 BRIG5 BRIG4 BRIG3 BRIG2 BRIG1 BRIG0

255 (bright) 1 1 1 1 1 1 1 1

128 (CCIR level) 1 0 0 0 0 0 0 0

0 (dark) 0 0 0 0 0 0 0 0

GAIN

CONTROL BITS D7 to D0

CONT7 CONT6 CONT5 CONT4 CONT3 CONT2 CONT1 CONT0

1.999 (maximum) 0 1 1 1 1 1 1 1

1.109 (CCIR level) 0 1 0 0 0 1 1 1

1.0 01000000

0 (luminance off) 0 0 0 0 0 0 0 0

−1 (inverse luminance) 1 1 0 0 0 0 0 0

−2 (inverse luminance) 1 0 0 0 0 0 0 0

GAIN

CONTROL BITS D7 to D0

SATN7 SATN6 SATN5 SATN4 SATN3 SATN2 SATN1 SATN0

1.999 (maximum) 0 1 1 1 1 1 1 1

1.0 (CCIR level) 0 1 0 0 0 0 0 0
0 (colour off) 0 0 0 0 0 0 0 0

−1 (inverse chroma) 1 1 0 0 0 0 0 0

−2 (inverse chroma) 1 0 0 0 0 0 0 0

HUE PHASE (DEG)

CONTROL BITS D7 to D0

HUEC7 HUEC6 HUEC5 HUEC4 HUEC3 HUEC2 HUEC1 HUEC0

+178.6.... 0 1 1 1 1 1 1 1

....0.... 0 0 0 0 0 0 0 0

....−180 10000000

1998 May 15 45

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

16.2.14 SUBADDRESS 0E

Table 25 Chrominance control SA 0E

FUNCTION BIT NAME LOGIC LEVEL CONTROL BIT

Chroma bandwidth (CHBW0 and CHBW1)

Small bandwidth (≈ 620 kHz) CHBW1 0 D1

CHBW0 0 D0

Nominal bandwidth (≈ 800 kHz) CHBW1 0 D1

CHBW0 1 D0

Medium bandwidth (≈ 920 kHz) CHBW1 1 D1

CHBW0 0 D0

Wide bandwidth (≈ 1000 kHz) CHBW1 1 D1

CHBW0 1 D0

Fast colour time constant (FCTC)

Nominal time constant FCTC 0 D2
Fast time constant FCTC 1 D2

Disable chroma comb filter (DCCF)

Chroma comb filter on (during VREF = 1)
(see Figures 20 and 21)

DCCF 0 D3

Chroma comb filter off DCCF 1 D3

Colour standard (CSTD0 and CSTD1)

Colour standard control automatic switching between
PAL BGHI and NTSC M

CSTD1 0 D5
CSTD0 0 D4

Colour standard control automatic switching between
NTSC 4.43 (50 Hz) and PAL 4.43 (60 Hz)

CSTD1 0 D5
CSTD0 1 D4

Colour standard control automatic switching between
PAL N and NTSC 4.43 (60 Hz)

CSTD1 1 D5
CSTD0 0 D4

Colour standard control automatic switching between
NTSC N and PAL M

CSTD1 1 D5
CSTD0 1 D4

Compatibility to SAA7199 (CM99)

Default value CM99 0 D6
To be set if SAA7199 (digital encoder) is used for

re-encoding in conjunction with RTCO

CM99 1 D6

Clear DTO (CDTO)

Disabled CDTO 0 D7
Every time CDTO is set, the internal subcarrier DTO

phase is reset to 0° and the RTCO output generates a
logic 0 at time slot 68 (see RTCO description Fig.16). So
an identical subcarrier phase can be generated by an
external device (e.g. an encoder).

CDTO 1 D7

1998 May 15 46

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

16.2.15 SUBADDRESS 10

Table 26 Format/delay control SA 10

Table 27 VREF pulse position and length VRLN SA 10 (D3)

Note

1. The numbers given in parenthesis refer to CCIR line counting.

Table 28 Fine position of HS HDEL0 and HDEL1 SA 10

Table 29 Output format selection OFTS0 and OFTS1 SA 10

LUMINANCE DELAY COMPENSATION

(STEPS IN 2/LLC)

CONTROL BITS D2 to D0

YDEL2 YDEL1 YDEL0

−4... 1 0 0

...0... 0 0 0

...3 0 1 1

VRLN

VREF at 60 HZ 525 LINES

(1)

VREF at 50 HZ 625 LINES

0101

Length 240 242 286 288
Line number first last first last first last first last
Field 1 19 (22) 258 (261) 18 (21) 259 (262) 24 309 23 310
Field 2 282 (285) 521 (524) 281 (284) 522 (525) 337 622 336 623

FINE POSITION OF HS WITH A STEP SIZE

OF 2/LLC

CONTROL BITS D5 and D4

HDEL1 HDEL0

000
101
210
311

FORMATS

CONTROL BITS D7 and D6

OFTS1 OFTS0

RGB 565, RGB 888 (dependent on control
bit RGB888) see Table 31

00

YUV 422 16 bits 0 1
YUV 411 12 bits 1 0
YUV CCIR-656 8 bits 1 1

1998 May 15 47

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

16.2.16 SUBADDRESS 11

Table 30 Output control 1 SA 11

Note

1. The pin number given in parenthesis refers to the 64-pin package.

FUNCTION BIT NAME LOGIC LEVEL CONTROL BIT

Colour on (COLO)

Automatic colour killer COLO 0 D0
Colour forced on COLO 1 D0

Decoder VIP bypassed (VIPB)

DMSD data to YUV output VIPB 0 D1
ADC data to YUV output; dependent on mode settings VIPB 1 D1

Output enable horizontal/vertical sync (OEHV)

HS, HREF, VREF and VS high impedance inputs OEHV 0 D2
Outputs HS, HREF, VREF and VS active OEHV 1 D2

Output enable YUV data (OEYC)

VPO-bus high-impedance inputs OEYC 0 D3
Output VPO-bus active OEYC 1 D3

Inverse composite blank (COMPO)

VREF is vertical reference COMPO 0 D4
VREF is inverse composite blank COMPO 1 D4

FEI control (FECO)

FEI sampling at CREF = LOW
(SAA7110 compatible; see Fig.17)

FECO 0 D5

FEI sampling at CREF = HIGH FECO 1 D5

General purpose switch (GPSW)

Switches directly pin 64 (53) GPSW; note 1 GPSW 0 D7

GPSW 1 D7

1998 May 15 48

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

16.2.17 SUBADDRESS 12

Table 31 Output control 2 SA 12

Note

1. The pin number given in parenthesis refers to the 64-pin package.

FUNCTION BIT NAME LOGIC LEVEL CONTROL BIT

Analog test select (AOSL)

AOUT connected to internal test point 1 AOSL1 0 D1

AOSL0 0 D0

AOUT connected to input AD1 AOSL1 0 D1

AOSL0 1 D0

AOUT connected to input AD2 AOSL1 1 D1

AOSL0 0 D0

AOUT connected to internal test point 2 AOSL1 1 D1

AOSL0 1 D0

Dithering (noise shaping) control (DIT)

Dithering off DIT 0 D2
Dithering on DIT 1 D2

RGB output format selection (RGB888)

RGB565 RGB888 0 D3
RGB888 RGB888 1 D3

Chroma interpolation filter function (CBR)

Cubic interpolation (default) CBR 0 D4
Linear interpolation (lower bandwidth) CBR 1 D4

Real time outputs mode select (RTSE0)

ODD switched to output pin 40 (29); note 1 RTSE0 0 D6
VL switched to output pin 40 (29); note 1 RTSE0 1 D6

Real time outputs mode select (RTSE1)

PLIN switched to output pin 39 (28); note 1 RTSE1 0 D7
HL switched to output pin 39 (28); note 1 RTSE1 1 D7

1998 May 15 49

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

16.2.18 SUBADDRESS 1A (READ-ONLY REGISTER)
Table 32 Line-21 text slicer status SA 1A

16.2.19 S

UBADDRESS 1B (READ-ONLY REGISTER)

Table 33 First decoded data byte of the text slicer SA 1B

16.2.20 SUBADDRESS 1C (READ-ONLY REGISTER)
Table 34 Second decoded data byte of the text slicer SA 1C

16.2.21 S

UBADDRESS 1F (READ-ONLY REGISTER)

Table 35 Status byte SA 1F

I

2

C-BUS

STATUS BIT

NAME

FUNCTION STATUS BIT

F1RDY new data on field 1 has been acquired (for asynchronous reading); active HIGH D0

F1VAL Line-21 of field 1 carries valid data; active HIGH D1

F2RDY new data on field 2 has been acquired (for asynchronous reading); active HIGH D2

F2VAL Line-21 of field 2 carries valid data; active HIGH D3

I

2

C-BUS

TEXT DATA

BITS

FUNCTION DATA BITS

BYTE1 (6 to 0) data bit 6 to 0 of first data byte D6 to D0

P1 parity error flag bit; bit goes HIGH when a parity error has occurred D7

I

2

C-BUS

TEXT DATA

BITS

FUNCTION DATA BITS

BYTE2 (6 to 0) data bit 6 to 0 of second data byte D6 to D0

P2 parity error flag bit; bit goes HIGH when a parity error has occurred D7

I2C-BUS

STATUS BIT

NAME

FUNCTION STATUS BIT

CODE colour signal according to selected standard has been detected; active HIGH D0

SLTCA slow time constant active in WIPA-mode; active HIGH D1

WIPA white peak loop is activated; active HIGH D2
GLIMB gain value for active luminance channel is limited [min (bottom)]; active HIGH D3
GLIMT gain value for active luminance channel is limited [max (top)]; active HIGH D4

FIDT identification bit for detected field frequency; LOW = 50 Hz and HIGH = 60 Hz D5
HLCK status bit for locked horizontal frequency; LOW = locked and HIGH = unlocked D6
STTC status bit for horizontal phase loop; LOW = TV time-constant and

HIGH = VTR time-constant

D7

1998 May 15 50

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

17 FILTER CURVES

17.1 Anti-alias filter curve

Fig.36 Anti-alias filter.

handbook, full pagewidth

6

V

(dB)

−42

024 68101214

f (MHz)

MGD138

−6

−12

−18

−24

−30

−36

0

17.2 Luminance filter curves

Fig.37 Luminance control SA 09H, 4.43 MHz Trap/CVBS mode, prefilter on and different aperture band-pass

centre frequencies.

(1) = 43H; (2) = 53H; (3) = 63H; (4) = 73H.

handbook, full pagewidth

f

Y (MHz)

18

−30

024 86

MGD139

6

V

Y

(dB)

−18

−6

(1)
(2)
(4)
(3)

(1)
(2)
(4)
(3)

1998 May 15 51

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

Fig.38 Luminance control SA 09H, 4.43 MHz Trap/CVBS mode, prefilter on and different aperture factors.

(1) = 40H; (2) = 41H; (3) = 42H; (4) = 43H.

handbook, full pagewidth

f

Y (MHz)

18

−30

024 86

MGD140

6

−18

−6

(1)
(2)
(3)
(4)

(4)
(3)
(2)
(1)

V

Y

(dB)

Fig.39 Luminance control SA 09H, 4.43 MHz Trap/CVBS mode, prefilter off and different aperture band-pass

centre frequencies.

(1) = 03H; (2) = 13H; (3) = 23H; (4) = 33H.

handbook, full pagewidth

f

Y (MHz)

18

−30
024 86

MGD141

6

−18

−6

(1)
(2)
(4)
(3)

(1)
(2)
(4)
(3)

V

Y

(dB)

1998 May 15 52

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

Fig.40 Luminance control SA 09H, Y/C mode, prefilter on and different aperture factors.

(1) = C0H; (2) = C1H; (3) = C2H; (4) = C3H.

handbook, full pagewidth

f

Y (MHz)

18

−30
024 86

MGD142

6

−18

−6

(1)
(2)
(3)
(4)

V

Y

(dB)

Fig.41 Luminance control SA 09H, Y/C mode, prefilter off and different aperture factors.

(1) = 80H; (2) = 81H; (3) = 82H; (4) = 83H.

handbook, full pagewidth

f

Y (MHz)

18

−30
024 86

MGD143

6

−18

−6

(1)
(2)
(3)
(4)

V

Y

(dB)

1998 May 15 53

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

Fig.42 Luminance control SA 09H, 3.58 MHz Trap/CVBS mode, prefilter on and different aperture band-pass

centre frequencies.

(1) = 43H; (2) = 53H; (3) = 63H; (4) = 73H.

handbook, full pagewidth

f

Y (MHz)

18

−30
024 86

MGD144

6

−18

−6

(1)
(2)
(4)
(3)

(1)
(2)
(4)
(3)

V

Y

(dB)

Fig.43 Luminance control SA 09H, 3.58 MHz Trap/CVBS mode, prefilter on and different aperture factors.

(1) = 40H; (2) = 41H; (3) = 42H; (4) = 43H.

handbook, full pagewidth

f

Y (MHz)

18

−30
024 86

MGD145

6

−18

−6

(1)
(2)
(3)
(4)

(4)
(3)
(2)
(1)

V

Y

(dB)

1998 May 15 54

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

Fig.44 Luminance control SA 09H, 3.58 MHz Trap/CVBS mode, prefilter off and different aperture band-pass

centre frequencies.

(1) = 03H; (2) = 13H; (3) = 23H; (4) = 33H.

handbook, full pagewidth

f

Y (MHz)

18

−30
024 86

MGD146

6

−18

−6

(1)
(2)
(4)
(3)

(1)
(2)
(4)
(3)

V

Y

(dB)

1998 May 15 55

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

17.3 Chrominance filter curves

18 I

2

C-BUS START SET-UP

• The given values force the following behaviour of the SAA7111:
– The analog input AI11 expects a signal in CVBS format; analog anti-alias filter active
– Automatic field detection
– YUV 422/16-bit output format enabled
– Outputs HS, HREF, VREF and VS active
– Contrast, brightness and saturation control in accordance with CCIR standards
– Chrominance processing with nominal bandwidth (800 kHz).

Fig.45 Chrominance filter.

Transfer characteristics of the chroma low-pass dependent on CHBW[1:0] settings.
(1) CHBW [1 : 0] = 00; (2) CHBW [1 : 0] = 01; (3) CHBW [1 : 0] = 10; (4) CHBW [1 : 0] = 11.

handbook, full pagewidth

2.7

6

0

−6

−12

−18

−24

−30

−36

−42

−48

−54

0 0.54 1.08 1.62 2,16

MGD147

f

(MHz)

V

(dB)

(1)
(2)
(3)
(4)

(4)
(1)
(3)
(2)

1998 May 15 56

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

Table 36 I2C-bus start set-up values

Notes

1. All X values must be set to LOW.

2. The I

2

C-bus subaddress 00 has to be initialized with 0 prior to reading.

SUB

(HEX)

FUNCTION NAME

(1)

VALUES (BIN) (HEX)

76543210START

00 chip version ID0(7 : 0); note 2 0 0 0 0 0 0 0 0 00
01 reserved 0 0 0 0 0 0 0 0 00
02 analog input control 1 FUSE(1 : 0), GUDL(2 : 0) and

MODE(2 : 0)

11000000C0

03 analog input control 2 X, HLNRS, VBSL, WPOFF, HOLDG,

GAFIX, GAI2 and GAI18

0010001133

04 analog input control 3 GAI(17 : 10) 0 0 0 0 0 0 0 0 00
05 analog input control 4 GAI(27 : 20) 0 0 0 0 0 0 0 0 00
06 horizontal sync start HSB(7 : 0) 1 1 1 0 1 0 1 1 EB
07 horizontal sync stop HSS(7 : 0) 1 1 1 0 0 0 0 0 E0
08 sync control AUFD, FSEL, EXFIL, X, VTRC and HPLL

and VNOI(1 : 0)

1000100088

09 luminance control BYPS, PREF, BPSS(1 : 0), VBLB,

UPTCV and APER(1 : 0)

0000000101

0A luminance brightness BRIG(7 : 0) 1 0 0 0 0 0 0 0 80
0B luminance contrast CONT(7 : 0) 0 1 0 0 0 1 1 1 47
0C chrominance saturation SATN(7 : 0) 0 1 0 0 0 0 0 0 40
0D chroma hue control HUEC(7 : 0) 0 0 0 0 0 0 0 0 00
0E chrominance control CDTO, CM99, CSTD(1 : 0), DCCF, FCTC

and CHBW(1 : 0)

0000000101

0F reserved 0 0 0 0 0 0 0 0 00
10 format/delay control OFTS(1 : 0), HDEL(1 : 0), VRLN and

YDEL(2 : 0)

0100000040

11 output control 1 GPSW, X, FECO, COMPO, OEYC,

OEHV, VIPB and COLO

000111001C

12 output control 2 RTSE(1 : 0), X, CBR, RGB888, DIT and

AOSL(1 : 0)

0000000103

13 to19reserved 0 0 0 0 0 0 0 0 00

1A text slicer status 0, 0, 0, 0, F2VAL, F2RDY, F1VAL and

F1RDY

read only register

1B decoded bytes of the

text slicer

P1 and BYTE1(6 : 0)
1C P2 and BYTE2(6 : 0)
1D to1Ereserved 0 0 0 0 0 0 0 0 00

1F status byte STTC, HLCK, FIDT, GLIMT, GLIMB,

WIPA and SLTCA and CODE

read only register

1998 May 15 57

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

19 PACKAGE OUTLINES

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

Note

1. Plastic or metal protrusions of 0.01 inches maximum per side are not included.

SOT188-2

4460

68

1

9

10 26

43

27

61

detail X

(A )

3

b

p

w M

A

1

A

A

4

L

p

b

1

β

k

1

k

X

y

e

E

B

D

H

E

H

v M

B

D

Z

D

A

Z

E

e

v M

A

pin 1 index

112E10 MO-047AC

0 5 10 mm

scale

92-11-17
95-03-11

PLCC68: plastic leaded chip carrier; 68 leads

SOT188-2

UNIT A

A

min. max. max. max. max.

1

A

4

b

p

E

(1)

(1) (1)

eH

E

Z

ywv β

mm

4.57

4.19

0.51

3.30

0.53

0.33

0.021

0.013

1.27

0.51

2.16
45

o

0.18 0.100.18

DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)

D

(1)

24.33

24.13

H

D

25.27

25.02

E

Z

2.16

D

b

1

0.81

0.66

k

1.22

1.07

k

1

0.180

0.165

0.020

0.13

A

3

0.25

0.01

0.05

0.020

0.085

0.007 0.0040.007

L

p

1.44

1.02

0.057

0.040

0.958

0.950

24.33

24.13

0.958

0.950

0.995

0.985

25.27

25.02

0.995

0.985

e

E

e

D

23.62

22.61

0.930

0.890

23.62

22.61

0.930

0.890

0.085

0.032

0.026

0.048

0.042

E

e

inches

D

e

1998 May 15 58

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

UNIT A1A2A3b

p

cE

(1)

eH

E

LL

p

Zywv θ

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

mm

0.25

0.10

2.75

2.55

0.25

0.45

0.30

0.23

0.13

14.1

13.9

0.8

17.45

16.95

1.2

0.8

7
0

o
o

0.16 0.100.161.60

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

1.03

0.73

SOT393-1 MS-022

96-05-21
97-08-04

D

(1) (1)(1)

14.1

13.9

H

D

17.45

16.95

E

Z

1.2

0.8

D

e

θ

E

A

1

A

L

p

detail X

L

(A )

3

B

16

y

c

E

H

A

2

D

Z

D

A

Z

E

e

v M

A

1

64

49

48 33

32

17

X

b

p

D

H

b

p

v M

B

w M

w M

0 5 10 mm

scale

pin 1 index

QFP64: plastic quad flat package; 64 leads (lead length 1.6 mm); body 14 x 14 x 2.7 mm

SOT393-1

A

max.

3.00

1998 May 15 59

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

20 SOLDERING

20.1 Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“IC Package Databook”

(order code 9398 652 90011).

20.2 Reflow soldering

Reflow soldering techniques are suitable for all PLCC and
QFP packages.

The choice of heating method may be influenced by larger
PLCC or QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our

“Quality

Reference Handbook”

(order code 9397 750 00192).

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 50 and 300 seconds depending on heating
method. Typical reflow peak temperatures range from
215 to 250 °C.

20.3 Wave soldering

20.3.1 PLCC
Wave soldering techniques can be used for all PLCC

packages if the following conditions are observed:

• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.

• The longitudinal axis of the package footprint must be
parallel to the solder flow.

• The package footprint must incorporate solder thieves at
the downstream corners.

20.3.2 QFP
Wave soldering is not recommended for QFP packages.

This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

If wave soldering cannot be avoided, for QFP
packages with a pitch (e) larger than 0.5 mm, the
following conditions must be observed:

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)
soldering technique should be used.

• The footprint must be at an angle of 45° to the board

direction and must incorporate solder thieves
downstream and at the side corners.

20.3.3 M

ETHOD (PLCC AND QFP)

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

20.4 Repairing soldered joints

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

CAUTION

Wave soldering is NOT applicable for all QFP
packages with a pitch (e) equal or less than 0.5 mm.

1998 May 15 60

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

21 DEFINITIONS

22 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

23 PURCHASE OF PHILIPS I

2

C COMPONENTS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Purchase of Philips I

2

C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.

1998 May 15 61

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

NOTES

1998 May 15 62

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

NOTES

1998 May 15 63

Philips Semiconductors Product specification

Video Input Processor (VIP) SAA7111

NOTES

Internet: http://www.semiconductors.philips.com

Philips Semiconductors – a worldwide company

© Philips Electronics N.V. 1998 SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

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Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

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For all other countries apply to: Philips Semiconductors,
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Ireland: Newstead, Clonskeagh, DUBLIN 14,
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Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
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Printed in The Netherlands 655102/1200/03/pp64 Date of release: 1998 May 15 Document order number: 9397750 03116