Datasheet SAA7111AHZ-01, SAA7111AHZ-02, SAA7111AHZ-03, SAA7111AH-01, SAA7111AH-03 Datasheet (Philips)

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Page 1

DATA SH EET

Product speciﬁcation Supersedes data of 1997 May 26 File under Integrated Circuits, IC22

1998 May 15

INTEGRATED CIRCUITS

SAA7111A

Enhanced Video Input Processor (EVIP)

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1998 May 15 2

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

CONTENTS

1 FEATURES 2 APPLICATIONS 3 GENERAL DESCRIPTION 4 QUICK REFERENCE DATA 5 ORDERING INFORMATION 6 BLOCK DIAGRAM 7 PINNING 8 FUNCTIONAL DESCRIPTION

8.1 Analog input processing

8.2 Analog control circuits

8.2.1 Clamping

8.2.2 Gain control

8.3 Chrominance processing

8.4 Luminance processing

8.5 RGB matrix

8.6 VBI-data bypass

8.7 VPO-bus (digital outputs)

8.8 Reference signals HREF, VREF and CREF

8.9 Synchronization

8.10 Clock generation circuit

8.11 Power-on reset and CE input

8.12 RTCO output

8.13 The Line-21 text slicer

8.13.1 Suggestions for I2C-bus interface of the display software reading line-21 data

9 BOUNDARY-SCAN TEST

9.1 Initialization of boundary-scan circuit

9.2 Device identification codes

10 GAIN CHARTS 11 LIMITING VALUES 12 CHARACTERISTICS 13 TIMING DIAGRAMS 14 CLOCK SYSTEM

14.1 Clock generation circuit

14.2 Power-on control

15 OUTPUT FORMATS 16 APPLICATION INFORMATION

16.1 Layout hints

17 I2C-BUS DESCRIPTION

17.1 I2C-bus format

17.2 I2C-bus detail

17.2.1 Subaddress 00

17.2.2 Subaddress 02

17.2.3 Subaddress 03

17.2.4 Subaddress 04

17.2.5 Subaddress 05

17.2.6 Subaddress 06

17.2.7 Subaddress 07

17.2.8 Subaddress 08

17.2.9 Subaddress 09

17.2.10 Subaddress 0A

17.2.11 Subaddress 0B

17.2.12 Subaddress 0C

17.2.13 Subaddress 0D

17.2.14 Subaddress 0E

17.2.15 Subaddress 10

17.2.16 Subaddress 11

17.2.17 Subaddress 12

17.2.18 Subaddress 13

17.2.19 Subaddress 15

17.2.20 Subaddress 16

17.2.21 Subaddress 17

17.2.22 Subaddress 1A (read-only register)

17.2.23 Subaddress 1B (read-only register)

17.2.24 Subaddress 1C (read-only register)

17.2.25 Subaddress 1F (read-only register) 18 FILTER CURVES

18.1 Anti-alias filter curve

18.2 TUF-block filter curve

18.3 Luminance filter curves

18.4 Chrominance filter curves 19 I2C-BUS START SET-UP 20 PACKAGE OUTLINES 21 SOLDERING

21.1 Introduction

21.2 Reflow soldering

21.3 Wave soldering

21.4 Repairing soldered joints 22 DEFINITIONS 23 LIFE SUPPORT APPLICATIONS 24 PURCHASE OF PHILIPS I2C COMPONENTS

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Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

1 FEATURES

• Four analog inputs, internal analog source selectors,

e.g. 4 × CVBS or 2 × Y/C or (1 × Y/C and 2 × CVBS)

• Two analog preprocessing channels

• Fully programmable static gain for the main channels or

automatic gain control for the selected CVBS or Y/C channel

• Switchable white peak control

• Two built-in analog anti-aliasing filters

• Two 8-bit video CMOS analog-to-digital converters

• On-chip clock generator

• Line-locked system clock frequencies

• Digital PLL for horizontal-sync processing and clock

generation

• Requires only one crystal (24.576 MHz) for all standards

• Horizontal and vertical sync detection

• Automatic detection of 50 and 60 Hz field frequency,

and automatic switching between PAL and NTSC standards

• Luminance and chrominance signal processing for

PAL BGHI, PAL N, PAL M, NTSC M, NTSC N, NTSC 4.43, NTSC-Japan and SECAM

• User programmable luminance peaking or aperture

correction

• Cross-colour reduction for NTSC by chrominance comb

filtering

• PAL delay line for correcting PAL phase errors

• Real time status information output (RTCO)

• Brightness Contrast Saturation (BCS) control on-chip

• The YUV (CCIR-601) bus supports a data rate of:

– 864 × f

= 13.5 MHz for 625 line sources

– 858 × fH= 13.5 MHz for 525 line sources.

• Data output streams for 16, 12 or 8-bit width with the

following formats: – YUV4:1:1 (12-bit) – YUV4:2:2 (16-bit) – YUV4:2:2 (CCIR-656) (8-bit) – RGB (5, 6, and 5) (16-bit) with dither – RGB (8, 8, and 8) (24-bit) with special application.

• Odd/even field identification by a non interlace CVBS input signal

• Fix level for RGB output format during horizontal blanking

• 720 active samples per line on the YUV bus

• One user programmable general purpose switch on an

output pin

• Built-in line-21 text slicer

• A 27 MHz Vertical Blanking Interval (VBI) data bypass

programmable by I

C-bus for INTERCAST applications

• Power-on control

• Two via I2C-bus switchable outputs for the digitized

CVBS or Y/C input signals AD1 (7 to 0) and AD2 (7 to 0)

• Chip enable function (reset for the clock generator and power save mode up from chip version 3)

• Compatible with memory-based features (line-locked clock)

• Boundary scan test circuit complies with the

‘IEEE Std. 1149.1−1990’

(ID-Code = 0 F111 02 B)

• I2C-bus controlled (full read-back ability by an external controller)

• Low power (<0.5 W), low voltage (3.3 V), small package (LQFP64)

• 5 V tolerant digital I/O ports.

2 APPLICATIONS

• Desktop/Notebook (PCMCIA) video

• Multimedia

• Digital television

• Image processing

• Video phone

• Intercast.

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Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

3 GENERAL DESCRIPTION

The Enhanced Video Input Processor (EVIP) is a combination of a two-channel analog preprocessing circuit including source selection, anti-aliasing filter and ADC, an automatic clamp and gain control, a Clock Generation Circuit (CGC), a digital multi-standard decoder (PAL BGHI, PAL M, PAL N, NTSC M, NTSC-Japan NTSC N and SECAM), a brightness/contrast/saturation control circuit, a colour space matrix (see Fig.1) and a 27 MHz VBI-data bypass.

The pure 3.3 V CMOS circuit SAA7111A, analog front-end and digital video decoder, is a highly integrated circuit for desktop video applications. The decoder is based on the principle of line-locked clock decoding and is able to decode the colour of PAL, SECAM and NTSC signals into CCIR-601 compatible colour component values. The SAA7111A accepts as analog inputs CVBS or S-video (Y/C) from TV or VTR sources. The circuit is I

C-bus controlled. The SAA7111A then supports several

text features as Line 21 data slicing and a high-speed VBI data bypass for Intercast.

4 QUICK REFERENCE DATA

5 ORDERING INFORMATION

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

DDD

digital supply voltage 3.0 3.3 3.6 V

DDA

analog supply voltage 3.1 3.3 3.5 V

amb

operating ambient temperature 0 25 70 °C

A+D

analog and digital power − 0.5 − W

TYPE

NUMBER

PACKAGE

NAME DESCRIPTION VERSION

SAA7111AHZ LQFP64 plastic low proﬁle quad ﬂat package; 64 leads; body 10 × 10 × 1.4 mm SOT314-2 SAA7111AH QFP64 plastic quad ﬂat package; 64 leads (lead length 1.6 mm);

body 14 × 14 × 2.7 mm

SOT393-1

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Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

6 BLOCK DIAGRAM

Fig.1 Block diagram.

handbook, full pagewidth

SDA

XTAL XTALI

RES

IICSA

TRST

TDI

HSVS

CLOCK

GENERATION

CIRCUIT

POWER-ON

CONTROL

INTERFACE

C-BUS

SYNCHRONIZATION

CIRCUIT

LUMINANCE

CIRCUIT

SAA7111A

CHROMINANCE

CIRCUIT

AND

BRIGHTNESS

CONTRAST

SATURATION

CONTROL

VBI DATA BYPASS

UPSAMPLING FILTER

C-BUS

CONTROL

CLOCKS

ANALOG

PROCESSING

AND

ANALOG-TO-

DIGITAL

CONVERSION

AI11 AI12

AI21 AI22

12 10

8 6

AD2 AD1

ANALOG

CONTROL

CON

BYPASS

30 27 17 29 28 60 15 16 24

RTS0

21 22 20

LLC2 CREF

34 to 39 42 to 51

FEI HREF

VPO (0 : 15)

GPSW

SSS

n.c.

AOUT

RTCO

MGG061

RTS1

LLC

SSA0

DDA0

SSD1-5

DDD1-5

57,41,33,25,18

56,40,32,26,19

SSA1-2

DDA1-2

9,5 11,7

Y/CVBS

C/CVBS

TCK

59 4 58

TMS

TDO

VREF

YUV-to-RGB

CONVERSION

AND

OUTPUT

FORMATTER

PROCESSING

LFCO

TEST

CONTROL

BLOCK

FOR BOUNDARY SCAN TEST

AND SCAN TEST

SCL

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Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

7 PINNING

SYMBOL

I/O/P DESCRIPTION

(L)QFP64

n.c. 1 − Do not connect. TDO 2 O Test data output for boundary scan test; note 1. TDI 3 I Test data input for boundary scan test; note 1. TMS 4 I Test mode select input for boundary scan test or scan test; note 1. V

SSA2

5 P Ground for analog supply voltage channel 2. AI22 6 I Analog input 22. V

DDA2

7 P Positive supply voltage for analog channel 2 (+3.3 V). AI21 8 I Analog input 21. V

SSA1

9 P Ground for analog supply voltage channel 1. AI12 10 I Analog input 12. V

DDA1

11 P Positive supply voltage for analog channel 1 (+3.3 V). AI11 12 I Analog input 11. V

SSS

13 P Substrate ground connection. AOUT 14 O Analog test output; for testing the analog input channels. V

DDA0

15 P Positive supply voltage for internal Clock Generator Circuit (CGC) (+3.3 V). V

SSA0

16 P Ground for internal CGC. VREF 17 O Vertical reference output signal (I

C-bit COMPO = 0) or inverse composite blanking

signal (I2C-bit COMPO = 1) (enabled via I2C-bus bit OEHV).

DDD5

18 P Digital supply voltage 5 (+3.3 V). V

SSD5

19 P Ground for digital supply voltage 5. LLC 20 O Line-locked system clock output (27 MHz). LLC2 21 O Line-locked clock

⁄2output (13.5 MHz).

CREF 22 O Clock reference output: this is a clock qualiﬁer signal distributed by the internal CGC

for a data rate of LLC2. Using CREF all interfaces on the VPO bus are able to generate a bus timing with identical phase. If CCIR 656 format is selected (OFTS0 = 1 and OFTS1 = 1) an inverse composite blanking signal (pixel qualiﬁer) is provided on this pin.

RES 23 O Reset output (active LOW); sets the device into a deﬁned state. All data outputs are

in high impedance state. The I2C-bus is reset (waiting for start condition).

CE 24 I Chip enable; connection to ground forces a reset, up from version 3 power save

function additionally available.

DDD4

25 P Digital supply voltage input 4 (+3.3 V). V

SSD4

26 P Ground for digital supply voltage input 4. HS 27 O Horizontal sync output signal (programmable); the positions of the positive and

negative slopes are programmable in 8 LLC increments over a complete line (equals 64 µs) via I

C-bus bytes HSB and HSS. Fine position adjustment in 2 LLC

increments can be performed via I2C-bus bits HDEL1 and HDEL0.

RTS1 28 O Two functions output; controlled by I

C-bus bit RTSE1. RTSE1 = 0: PAL line identiﬁer (LOW = PAL line); indicates the inverted and non-inverted R − Y component for PAL signals. RTSE1 = 1: H-PLL locked indicator; a high state indicates that the internal horizontal PLL has locked.

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Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

RTS0 29 O Two functions output; controlled by I2C-bus bit RTSE0.

RTSE0 = 0: odd/even ﬁeld identiﬁcation (HIGH = odd ﬁeld). RTSE0 = 1: vertical locked indicator; a HIGH state indicates that the internal Vertical Noise Limiter (VNL) has locked.

VS 30 O Vertical sync signal (enabled via I

C-bus bit OEHV); this signal indicates the vertical sync with respect to the YUV output. The HIGH period of this signal is approximately six lines if the VNL function is active. The positive slope contains the phase information for a deﬂection controller.

HREF 31 O Horizontal reference output signal (enabled via I

C-bus bit OEHV); this signal is used to indicate data on the digital YUV bus. The positive slope marks the beginning of a new active line. The HIGH period of HREF is 720 Y samples long. HREF can be used to synchronize data multiplexer/demultiplexer. HREF is also present during the vertical blanking interval.

SSD3

32 P Ground for digital supply voltage input 3.

DDD3

33 P Digital supply voltage 3 (+3.3 V).

VPO (15 to 10)

34 to 39 O Digital VPO-bus (Video Port Out) signal; higher bits of the 16-bit VPO-bus or the

16-bit RGB-bus output signal. The output data rate, the format and multiplexing scheme of the VPO-bus are controlled via I

C-bus bits OFTS0 and OFTS1. If I2C-bus bit VIPB = 1 the six MSBs of the digitized input signal are connected to these outputs, conﬁgured by the I2C-bus ‘MODE’ bits (see Figs 33 to 40): LUMA → VPO15 to VPO8, CHROMA → VPO7 to VPO0.

SSD2

40 P Ground for digital supply voltage input 2.

DDD2

41 P Digital supply voltage 2 (+3.3 V).

VPO (9 to 0)

42 to 51 O Digital VPO-bus output signal; lower bits of the 16-bit YUV-bus or the 16-bit RGB-bus

output signal. The output data rate, the format and multiplexing schema of the VPO-bus are controlled via I

C-bus bits OFTS0 and OFTS1. If I2C-bus bit VIPB = 1 the digitized input signal are connected to these outputs, conﬁgured by the I2C-bus ‘MODE’ bits (see Figs 33 to 40): LUMA → VPO15 to VPO8, CHROMA → VPO7 to VPO0.

FEI 52 I Fast enable input signal (active LOW); this signal is used to control fast switching on

the digital YUV-bus. A HIGH at this input forces the IC to set its Y and UV outputs to the high impedance state.

GPSW 53 O General purpose switch output; the state of this signal is set via I

C-bus control and

the levels are TTL compatible.

XTAL 54 O Second terminal of crystal oscillator; not connected if external clock signal is used. XTALI 55 I Input terminal for 24.576 MHz crystal oscillator or connection of external oscillator

with CMOS compatible square wave clock signal.

SSD1

56 P Ground for digital supply voltage input 1.

DDD1

57 P Digital supply voltage input 1 (+3.3 V). TRST 58 I Test reset input not (active LOW), for boundary scan test; notes 1, 2 and 3. TCK 59 I Test clock for boundary scan test; note 1. RTCO 60 O Real time control output: contains information about actual system clock frequency,

subcarrier frequency and phase and PAL sequence.

SYMBOL

I/O/P DESCRIPTION

(L)QFP64

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Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

Notes

1. In accordance with the ‘

IEEE1149.1

’ standard the pads TCK, TDI, TMS and TRST are input pads with an internal

pull-up transistor and TDO a 3-state output pad.

2. This pin provides easy initialization of BST circuit. TRST can be used to force the TAP (Test Access Port) controller to the Test-Logic-Reset state (normal operation) at once.

3. For board design without boundary scan implementation (pin compatibility with the SAA7110) connect the TRST pin to ground.

IICSA 61 I I

C-bus slave address select; 0 = 48H for write, 49H for read 1 = 4AH for write, 4BH for read.

SDA 62 I/O Serial data input/output (I

C-bus).

SCL 63 I/O Serial clock input/output (I

C-bus).

n.c. 64 − Not connect.

SYMBOL

I/O/P DESCRIPTION

(L)QFP64

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Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

Fig.2 Pin configuration (LQFP64/QFP64).

handbook, full pagewidth

SAA7111A

MGG060

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

TCK

IICSA

SDA

RTCO

n.c.

TDO

TDI

TMS

SSA2

n.c.

AI22

DDA2

VPO15

VPO14

VPO13

VPO12

VPO11

VPO10

VPO9

VPO8

VPO7

VPO6

VPO5

VPO4

VPO3

VPO2

VPO1

VPO0

FEI

GPSW

XTAL

XTALI

SSD1

DDD1

DDD3

DDD2

SSD2

AI21

AI11

AOUT

SSA1

SSA0

SSD5

LLC

LLC2

CREF

RTS1

RTS0

HREF

SSD3

SSD4

DDD4

VREF

SSS

DDA1

DDA0

DDD5

AI12

SCL

TRST

RES

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Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

8 FUNCTIONAL DESCRIPTION

8.1 Analog input processing

The SAA7111A offers four analog signal inputs, two analog main channels with source switch, clamp circuit, analog amplifier, anti-alias filter and video CMOS ADC (see Fig.5).

8.2 Analog control circuits

The anti-alias filters are adapted to the line-locked clock frequency via a filter control circuit. During the vertical blanking time, gain and clamping control are frozen.

8.2.1 C

LAMPING

The clamp control circuit controls the correct clamping of the analog input signals. The coupling capacitor is also used to store and filter the clamping voltage. An internal digital clamp comparator generates the information with respect to clamp-up or clamp-down. The clamping levels for the two ADC channels are fixed for luminance (60) and chrominance (128). Clamping time in normal use is set with the HCL pulse at the back porch of the video signal.

8.2.2 G

AIN CONTROL

Signal (white) peak control limits the gain at signal overshoots. The flow charts (see Figs 13 and 14) show more details of the AGC. The influence of supply voltage variation within the specified range is automatically eliminated by clamp and automatic gain control.

The gain control circuit receives (via the I2C-bus) the static gain levels for the two analog amplifiers or controls one of these amplifiers automatically via a built-in automatic gain control (AGC) as part of the Analog Input Control (AICO).

Fig.3 Analog line with clamp (HCL) and gain

range (HSY).

handbook, halfpage

HCL

MGL065

HSY

analog line blanking

TV line

255

GAIN CLAMP

The AGC (automatic gain control for luminance) is used to amplify a CVBS or Y signal to the required signal amplitude, matched to the ADCs input voltage range. The AGC active time is the sync bottom of the video signal.

8.3 Chrominance processing

The 8-bit chrominance signal is fed to the multiplication inputs of a quadrature demodulator, where two subcarrier signals from the local oscillator DTO1 are applied (0 and 90° phase relationship to the demodulator axis). The frequency is dependent on the present colour standard. The output signals of the multipliers are low-pass filtered (four programmable characteristics) to achieve the desired bandwidth for the colour difference signals (PAL and NTSC) or the 0 and 90° FM-signals (SECAM).

The colour difference signals are fed to the Brightness/Contrast/Saturation block (BCS), which includes the following five functions:

• AGC (Automatic Gain Control for chrominance PAL and NTSC)

• Chrominance amplitude matching (different gain factors for R − Y and B − Y to achieve CCIR-601 levels Cr and Cb for all standards)

• Chrominance saturation control

• Luminance contrast and brightness

• Limiting YUV to the values 1 (min.) and 254 (max.) to

fulfil CCIR-601 requirements.

Fig.4 Automatic gain range.

handbook, halfpage

analog input level

controlled

ADC input level

maximum

minimum

range tbf0 dB

0 dB

MGG063

+4.5 dB

−7.5 dB

(1 V(p-p) 27/47 Ω)

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Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

The SECAM-processing contains the following blocks:

• Baseband ‘bell’ filters to reconstruct the amplitude and phase equalized 0 and 90° FM-signals

• Phase demodulator and differentiator (FM-demodulation)

• De-emphasis filter to compensate the pre-emphasised input signal, including frequency offset compensation (DB or DR white carrier values are subtracted from the signal, controlled by the SECAM-switch signal).

The burst processing block provides the feedback loop of the chroma PLL and contains;

• Burst gate accumulator

• Colour identification and killer

• Comparison nominal/actual burst amplitude (PAL/NTSC

standards only)

• Loop filter chrominance gain control (PAL/NTSC standards only)

• Loop filter chrominance PLL (only active for PAL/NTSC standards)

• PAL/SECAM sequence detection, H/2-switch generation

• Increment generation for DTO1 with divider to generate stable subcarrier for non-standard signals.

The chrominance comb filter block eliminates crosstalk between the chrominance channels in accordance with the PAL standard requirements. For NTSC colour standards the chrominance comb filter can be used to eliminate crosstalk from luminance to chrominance (cross-colour) for vertical structures. The comb filter can be switched off if desired. The embedded line delay is also used for SECAM recombination (cross-over switches).

The resulting signals are fed to the variable Y-delay compensation, RGB matrix, dithering circuit and output interface, which contains the VPO output formatter and the output control logic (see Fig.6).

8.4 Luminance processing

The 8-bit luminance signal, a digital CVBS format or a luminance format (S-VHS, HI8), is fed through a switchable prefilter. High frequency components are emphasized to compensate for loss. The following chrominance trap filter (f

= 4.43 or 3.58 MHz centre frequency selectable) eliminates most of the colour carrier signal, therefore, it must be bypassed for S-video (S-VHS and HI8) signals.

The high frequency components of the luminance signal can be peaked (control for sharpness improvement via I

C-bus) in two band-pass filters with selectable transfer characteristic. This signal is then added to the original (unpeaked) signal. A switchable amplifier achieves common DC amplification, because the DC gains are different in both chrominance trap modes. The improved luminance signal is fed to the BCS control located in the chrominance processing block (see Fig.7).

8.5 RGB matrix

Y, Cr and Cb data are converted after interpolation into RGB data in accordance with CCIR-601 recommendations. The realized matrix equations consider the digital quantization:

R = Y + 1.371 Cr G=Y−0.336 Cb − 0.698 Cr B = Y + 1.732 Cb.

After dithering (noise shaping) the RGB data is fed to the output interface within the VPO-bus output formatter.

8.6 VBI-data bypass

For a 27 MHz VBI-data bypass the offset binary CVBS signal is upsampled behind the ADCs. Upsampling of the CVBS signal from 13.5 to 27 MHz is possible, because the ADCs deliver high performance at 13.5 MHz sample clock. Suppressing of the back folded CVBS frequency components after upsampling is achieved by an interpolation filter (see Fig.42).

The TUF block on the digital top level performs the upsampling and interpolation for the bypassed CVBS signal (see Fig.6).

For bypass details see Figs 8 to 10.

8.7 VPO-bus (digital outputs)

The 16-bit VPO-bus transfers digital data from the output interfaces to a feature box or a field memory, a digital colour space converter (SAA7192 DCSC), a video enhancement and digital-to-analog processor (SAA7165 VEDA2) or a colour graphics board (Targa-format) as a graphical user interface.

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Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

The output data formats are controlled via the I2C-bus bits OFTS0, OFTS1 and RGB888. Timing for the data stream formats, YUV (4 : 1 : 1) (12-bit), YUV (4 : 2 : 2) (16-bit), RGB (5, 6 and 5) (16-bit) and RGB (8, 8 and 8) (24-bit) with an LLC2 data rate, is achieved by marking each second positive rising edge of the clock LLC in conjunction with CREF (clock reference) (except RGB (8, 8 and 8), see special application in Fig.32). The higher output signals VPO15 to VPO8 in the YUV format perform the digital luminance signal. The lower output signals VPO7 to VPO0 in the YUV format are the bits of the multiplexed colour difference signals (B − Y) and (R − Y). The arrangement of the RGB (5, 6 and 5) and RGB (8, 8 and 8) data stream bits on the VPO-bus is given in Table 6.

The data stream format YUV 4:2:2 (the 8 higher output signals VPO15 to VPO8) in LLC data rate fulfils the CCIR-656 standard with its own timing reference code at the start and end of each video data block.

A pixel in the format tables is the time required to transfer a full set of samples. If 16-bit 4 : 2 : 2 format is selected two luminance samples are transmitted in comparison to one (B − Y) and one (R − Y) sample within a pixel. The time frames are controlled by the HREF signal.

Fast enable is achieved by setting input FEI to LOW. The signal is used to control fast switching on the digital VPO-bus. HIGH on this pin forces the VPO outputs to a high-impedance state (see Figs 18 and 19). The I2C-bus bit OEYC has to be set HIGH to use this function.

The digitized PAL, SECAM or NTSC signals AD1 (7 to 0) and AD2 (7 to 0) are connected directly to the VPO-bus via I2C-bus bit VIPB = 1 and MODE = 4, 5, 6 or 7.

AD1 (7 to 0) → VPO (15 to 8) and AD2 (7 to 0) → VPO (7 to 0).

The selection of the analog input channels is controlled via I2C-bus subaddress 02 MODE select.

The upsampled 8-bit offset binary CVBS signal (VBI-data bypass) is multiplexed under control of the I2C-bus to the digital VPO-bus (see Fig.8).

8.8 Reference signals HREF, VREF and CREF

• HREF: The positive slope of the HREF output signal indicates the beginning of a new active video line. The high period is 720 luminance samples long and is also present during the vertical blanking. The description of timing and position from HREF is illustrated in Figs 15, 16, 21 and 23.

• VREF: The VREF output delivers a vertical reference signal or an inverse composite blank signal controlled via the I2C-bus [subaddress 11, inverse composite blank (COMPO)]. Furthermore four different modes of vertical reference signals are selectable via the I2C-bus [subaddress 13, vertical reference output control (VCTR1 and VCTR0)]. The description of VREF timing and position is illustrated in Figs 15, 16, 24 and 25.

• CREF: The CREF output delivers a clock/pixel qualifier signal for external interfaces to synchronize to the VPO-bus data stream.

Four different modes for the clock qualifier signal are selectable via the I2C-bus [subaddress 13, clock reference output control (CCTR1 and CCTR0)]. The description of CREF timing and position is illustrated in Figs 16, 18, 20 and 21.

8.9 Synchronization

The prefiltered luminance signal is fed to the synchronization stage. Its bandwidth is reduced to 1 MHz in a low-pass filter. The sync pulses are sliced and fed to the phase detectors where they are compared with the sub-divided clock frequency. The resulting output signal is applied to the loop filter to accumulate all phase deviations. Internal signals (e. g. HCL and HSY) are generated in accordance with analog front-end requirements. The output signals HS, VS, and PLIN are locked to the timing reference, guaranteed between the input signal and the HREF signal, as further improvements to the circuit may change the total processing delay. It is therefore not recommended to use them for applications which require absolute timing accuracy on the input signals. The loop filter signal drives an oscillator to generate the line frequency control signal LFCO (see Fig.7).

8.10 Clock generation circuit

The internal CGC generates all clock signals required for the video input processor. The internal signal LFCO is a digital-to-analog converted signal provided by the horizontal PLL. It is the multiple of the line frequency

Internally the LFCO signal is multiplied by a factor of 2 or 4 in the PLL circuit (including phase detector, loop filtering, VCO and frequency divider) to obtain the LLC and LLC2 output clock signals. The rectangular output clocks have a 50% duty factor (see Fig.26).

6.75MHz

429 432

--------- -

×=

Page 13

1998 May 15 13

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

8.11 Power-on reset and CE input

A missing clock, insufficient digital or analog V

DDA0

supply voltages (below 2.7 V) will initiate the reset sequence; all outputs are forced to 3-state. The indicator output RES is LOW for approximately 128LLC after the internal reset and can be applied to reset other circuits of the digital TV system.

It is possible to force a reset by pulling the chip enable (CE) to ground. After the rising edge of CE and sufficient power supply voltage, the outputs LLC, LLC2, CREF, RTCO, RTS0, RTS1, GPSW and SDA return from 3-state to active, while HREF, VREF, HS and VS remain in 3-state and have to be activated via I

C-bus programming

(see Table 5).

8.12 RTCO output

The real time control and status output signal contains serial information about the actual system clock (increment of the HPLL), subcarrier frequency [increment and phase (via reset) of the FSC-PLL] and PAL sequence bit. The signal can be used for various applications in external circuits, e.g. in a digital encoder to achieve clean encoding (see Fig.20).

8.13 The Line-21 text slicer

The text slicer block detects and acquires Line-21 Closed Captioning data from a 525-line CVBS signal. Extended data services on Line-21 Field 2 are also supported. If valid data is detected the two data bytes are stored in two I2C-bus registers. A parity check is also performed and the result is stored in the MSB of the corresponding byte. A third I2C-bus register is provided for data valid and data ready flags. The two bits F1VAL and F2VAL indicate that the input signal carries valid Closed Captioning data in the corresponding fields. The data ready bits F1RDY and F2RDY have to be evaluated if asynchronous I2C-bus reading is used.

8.13.1 S

UGGESTIONS FOR I

C-BUS INTERFACE OF THE

DISPLAY SOFTWARE READING LINE

-21 DATA

There are two methods by which the software can acquire the data:

1. Synchronous reading once per frame (or once per field); It can use either the rising edge (Line-21 Field 1) or both edges (Line-21 Field 1 or 2) of the ODD signal (pin RTSO) to initiate an I2C-bus read transfer of the three registers 1A, 1B and 1C.

2. Asynchronous reading; It can poll either the F1RDY bit (Line-21 Field 1) or both F1RDY/F2RDY bits (Line-21 Field 1 or 2). After valid data has been read the corresponding F*RDY bit is set to LOW until new data has arrived. The polling frequency has to be slightly higher than the frame or field frequency, respectively.

Page 14

1998 May 15 14

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

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AI22 AI21

FUSE (1 : 0)

AI12 AI11

FUSE (1 : 0)

AOSL (1 : 0)

HOLDG

ANALOG CONTROL

GAI10-GAI18

SSS

n.c.

VBSL 8 8

MGC655

CHRLUM

VERTICAL

BLANKING

CONTROL

SOURCE

SWITCH

CLAMP

CIRCUIT

ANALOG

AMPLIFIER

ANTI-ALIAS

FILTER

BYPASS SWITCH

SOURCE

SWITCH

CLAMP

CIRCUIT

ANALOG

AMPLIFIER

ANTI-ALIAS

FILTER

BYPASS SWITCH

ADC2

ADC1

TEST

AND

SELECTOR

CLAMP

CONTROL

GAIN

CONTROL

CROSS MULTIPLEXER

ANTI-ALIAS

CONTROL

DDA1

SSA2

AOUT

MODE

CONTROL

MODE 0 MODE 1 MODE 2

GAI20-GAI28

GUDL0-GUDL2

GAFIX WPOFF

HSY

VBLNK SVREF

HCL

AD1BYPAD2BYP

BUFFER

DAC9

HLNRS UPTCV

DDA2

9 5

6 8

11 7

10 12

SSA1

GLIMB GLIMT WIPA SLTCA

Fig.5 Analog input processing.

Page 15

1998 May 15 15

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

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Fig.6 Chrominance circuit.

ewidth

CHRLUM

CODE

AD1BYPAD2BYP

BRIG

CONT

SATN

HUEC

DCCF

fH/2 switch signal

MGG062

DDD1-5

SSD1-5

57,41,33, 25,18

56,40,32,26,19

34 to 39

42 to 51

QUADRATURE

DEMODULATOR

COMB

FILTERS

SECAM

RECOMBINATION

FORMATTER

OUTPUT

AND

INTERFACE

ACCUMULATOR

BURST GATE

LOW-PASS

LOOP FILTER

SUBCARRIER

INCREMENT

GENERATION

AND

DIVIDER

SUBCARRIER GENERATION

FCTCCSTD 1

RGB MATRIX

interpolation

dithering

SECAM

PROCESSING

DIT CBR

CHBW0 CHBW1

CSTD 0

INCS

RES

TCK

TDI

59 3

POWER-ON

CONTROL

TEST

CONTROL

BLOCK

TDO

TRST

TMS

LUM

RTCO

n.c.

CLOCKS

sequential UV signals

RGB

FEI

HREF

VPO (9 : 0)

VPO (15 : 10)

VBI DATA BYPASS

TUF

PHASE

DEMODULATOR

AMPLITUDE

DETECTOR

OFTS0 OFTS1 RGB888 OEYC OEHV FECO VRLN VSTA (8 : 0) VSTO (8 : 0)

GPSW RTSE1 RTSE0 VIPB VLOF COLO COMPO

LEVEL

ADJUSTMENT,

BRIGHTNESS,

CONTRAST,

AND

SATURATION

CONTROL

GAIN

CONTROL

AND Y-DELAY

COMPENSATION

Page 16

1998 May 15 16

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

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CREF LLC

XTALI XTAL

VREF

RTS0

SDASCLIICSA

GPSW

I C BUS CONTROL

CLOCKS

SYNCHRONIZATION CIRCUIT

PREF

BYPS

APER0 APER1 VBLB

AUFD

HSB HSS

FSEL

VTRC

STTC

FIDT

VNOI0 VNOI1 VTRC

VTRC

RTS1

MGC654

LLC2

HLCK

DDA0

SSA0

61 63 62 30 29 17 27 28

16 24

22 20 21

DAC6

AND

WEIGHTING

ADDING

BAND-PASS

VARIABLE

FILTER

CHROMINANCE

TRAP

PREFILTER

AMPLIFIER

MATCHING

CLOCK

LINE-LOCKED GENERATOR

LOOP FILTER

DETECTOR

PHASE

COARSE

DETECTOR

PHASE

FINE

SYNC SLICER

SYNC

PREFILTER

LINE 21

TEXT

SLICER

CLOCK

CRYSTAL

GENERATOR

TIME

DISCRETE

OSCILLATOR 2

INTERFACE

I C-BUS

PROCESSOR

VERTICAL

COUNTER

GENERATION

CLOCK

CIRCUIT

LUMINANCE CIRCUIT

BPSS0 BPSS1 PREF

LUM

VBLB

CLOCK CIRCUIT

INCS

STAGE

HPLL VTRC

EXFIL

BYTE1 BYTE2

STATUS

Fig.7 Luminance and sync processing.

Page 17

1998 May 15 17

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

Fig.8 Multiplexing of the CVBS signal to the VPO-bus.

HREFINT = internal horizontal reference. TBP = upsampled CVBS input data (27 MHz). AD1BYP/AD2BYP = digitized CVBS input data and Y/C input data (13.5 MHz). VBP0 = programmable vertical reference signal. VBP4 = delayed programmable vertical reference signal (4LLC clocks delay).

handbook, full pagewidth

MGG064

CLOCK 0

HREFINT

V_GATE

(programmable)

4 × REG

CLOCK 0

REG

BCHI1 BCHI0 SWHI

0 0 1 1

0 1 0 1

0 VBP0 VBP4

VBP0

AD1BYP

VBP4

MUX

CVBS

MUX

BYP

BCLO1 BCLO0 SWLO

0 0 1 1

0 1 0 1

BCLO1 to 0

C-bus

BCHI1 to 0

C-bus

VIPB I

C-bus

TBP7 to 0

(CVBS)

UV or YUV

Y or YUV

0 VBP0 VBP4

VBP0

VBP4

VBP0

AD2BYP

VBP4

MUX

CVBS

VPO7 to 0

SWHI

SWLO

VPO15 to 8

MUX

BYP

(LUMA see Fig. 37)

(CHROMA see Fig. 37)

Page 18

1998 May 15 18

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

Fig.9 VREF output signal generation.

VREF_CCIR 656 = vertical reference signal referring to the field interval definitions of CCIR656. HREFINT = internal horizontal reference signal. VREFINT = internal vertical reference signal. VBP0 = programmable vertical reference signal. VBP4 = delayed programmable vertical reference signal (4LLC clocks delay).

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MGG065

V C T R 1

0 0 1 1

0 1 0 1

V C T R 0

VREFINT

VREF

CLOCK 0

COMPO

VCTR1 to 0

VREFOUT

VREF CCIR 656 VBP0 VBP4

VBP0 VBP4

VREFINT

HREFINT

VREF CCIR 656

REG

HREF

CLK0

REG

CLOCK 0

REG

MUX

CLOCK 0

REG

Fig.10 CREF output signal generation.

CREFINT = internal clock qualifier signal.

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MGG066

C C T R 1

0 0 1 1

0 1 0 1

C C T R 0

CREFINT

selected

VREF

CCTR1 to 0

CREF

CLOCK 0

CREFOUT

0 if VREF = 0 1 if VREF = 0 1 (always HIGH)

REG

Page 19

1998 May 15 19

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

9 BOUNDARY-SCAN TEST

The SAA7111A has built in logic and 5 dedicated pins to support boundary-scan testing which allows board testing without special hardware (nails). The SAA7111A follows the

‘IEEE Std. 1149.1 - Standard Test Access Port and

Boundary-Scan Architecture

’ set by the Joint Test Action

Group (JTAG) chaired by Philips. The 5 special pins are Test Mode Select (TMS), Test

Clock (TCK), Test Reset (TRST), Test Data Input (TDI) and Test Data Output (TDO).

The BST functions BYPASS, EXTEST, INTEST, SAMPLE, CLAMP and IDCODE are all supported (see Table 1). Details about the JTAG BST-TEST can be found in the specification “

EEE Std. 1149.1”

. A file containing the detailed Boundary-Scan Description Language (BSDL) description of the SAA7111A is available on request.

9.1 Initialization of boundary-scan circuit

The Test Access Port (TAP) controller of an IC should be in the reset state (TEST_LOGIC_RESET) when the IC is in functional mode. This reset state also forces the instruction register into a functional instruction such as IDCODE or BYPASS.

To solve the power-up reset, the standard specifies that the TAP controller will be forced asynchronously to the TEST_LOGIC_RESET state by setting the TRST pin LOW.

9.2 Device identiﬁcation codes

A Device Identification Register (DIR) is specified in

‘IEEE Std. 1149.1-1990 - IEEE Standard Test Access Port and Boundary-Scan Architecture

’ (IEEE Std. 1149.1b-1994). It is a 32-bit register which contains fields for the specification of the IC manufacturer, the IC part number and the IC version number. Its biggest advantage is the possibility to check for the correct ICs mounted after production and determination of the version number of ICs during field service.

When the IDCODE instruction is loaded into the BST instruction register, the identification register will be connected between TDI and TDO of the IC. The identification register will load a component specific code during the CAPTURE_DATA_REGISTER state of the TAP controller and this code can subsequently be shifted out. At board level this code can be used to verify component manufacturer, type and version number. The device identification register contains 32-bits, numbered 31 to 0, where bit 31 is the Most Significant Bit (MSB) (nearest to TDI) and bit 0 is the Least Significant Bit (LSB) (nearest to TDO); see Fig.11.

Table 1 BST instructions supported by the SAA7111A

INSTRUCTION DESCRIPTION

BYPASS This mandatory instruction provides a minimum length serial path (1 bit) between TDI and TDO

when no test operation of the component is required.

EXTEST This mandatory instruction allows testing of off-chip circuitry and board level interconnections.

SAMPLE This mandatory instruction can be used to take a sample of the inputs during normal operation of

the component. It can also be used to preload data values into the latched outputs of the boundary-scan register.

CLAMP This optional instruction is useful for testing when not all ICs have BST. This instruction addresses

the bypass register while the boundary-scan register is in external test mode.

IDCODE This optional instruction will provide information on the components manufacturer, part number and

version number.

INTEST This optional instruction allows testing of the internal logic (no support for customers available).

USER1 This private instruction allows testing by the manufacturer (no support for customers available).

Page 20

1998 May 15 20

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

Fig.11 32 bits of identification code.

handbook, full pagewidth

MGL111

0000001010111110001000100010010

4-bit

version

code

16-bit part number 11-bit manufacturer

indentification

TDI TDO

MSB LSB

28 27 12 11 1 0

Page 21

1998 May 15 21

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

10 GAIN CHARTS

Fig.12 Amplifier curve.

handbook, halfpage

7.5

5.5

3.5

1.5

−0.5

−4.5

−2.5

256 512

gain value (i)

MGC648

bit [8] = 1

factor

= 20 x log10 gain =

(

512

768 − i

i > 256

bit [8] = 0

factor

= 20 x log10 gain =

(

512

257 + i

(

i < 256

(

Fig.13 Clamp and gain flow.

WIPE = white peak level (254); SBOT = sync bottom level (1); CLL = clamp level [60 Y (128 C)]; HSY = horizontal sync pulse; HCL = horizontal clamp pulse.

handbook, full pagewidth

+ CLAMP − CLAMP

NO CLAMP

10 10

01 10

MGC647

fast − GAIN

slow + GAIN

+ GAIN − GAIN

HCL HSY

ADC

SBOT

WIPE

CLL

ANALOG INPUT

GAIN -><- CLAMP

VBLK

NO BLANKING ACTIVE

Page 22

1998 May 15 22

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

Fig.14 Gain flow chart.

X = system variable; Y = IAGV − FGVI > GUDL; VBLK = vertical blanking pulse; HSY = horizontal sync pulse; AGV = actual gain value; FGV = frozen gain value.

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ANALOG INPUT

AMPLIFIER

ANTI-ALIAS FILTER

ADC

LUMA/CHROMA DECODER

HSY

>254

>248

X = 0

X = 1

−

1/LLC2

+1/LLC2 −1/LLC2

+/− 0

+1/F

+1/L

GAIN ACCUMULATOR (18 BITS)

ACTUAL GAIN VALUE 9-BIT (AGV) [−6/+6 dB]

STOP

HSY

UPDATE

FGV

MGC652

AGV

GAIN VALUE 9-BIT

VBLK

NO ACTION

DAC

gain

HOLDG

Page 23

1998 May 15 23

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

11 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134); all ground pins connected together and all supply pins connected together.

Note

1. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ resistor.

12 CHARACTERISTICS

DDD

= 3.0 to 3.6 V; V

DDA

= 3.1 to 3.5 V; T

amb

=25°C; unless otherwise speciﬁed.

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

DDD

digital supply voltage −0.5 +4.6 V

DDA

analog supply voltage −0.5 +4.6 V

i(A)

input voltage at analog inputs −0.5 V

DDA

+ 0.5

(4.6 max.)

o(A)

output voltage at analog output −0.5 V

DDA

+ 0.5 V

i(D)

input voltage at digital inputs and outputs outputs in 3-state −0.5 +5.5 V

o(D)

output voltage at digital outputs outputs active −0.5 V

DDD

+ 0.5 V

∆V

voltage difference between V

SSAall

and V

SSall

− 100 mV

stg

storage temperature −65 +150 °C

amb

operating ambient temperature 0 70 °C

amb(bias)

operating ambient temperature under bias −10 +80 °C

esd

electrostatic discharge all pins note 1 −2000 +2000 V

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

DDD

digital supply voltage 3.0 3.3 3.6 V

DDD

digital supply current − 63 70 mA

digital power − 0.21 − W

DDA

analog supply voltage 3.1 3.3 3.5 V

DDA

analog supply current AOSL = [1:0] = 00b;

AOUT not connected

− 52 − mA

analog power − 0.17 − W

A+D

analog and digital power − 0.38 − W

analog and digital power in power-down mode

CE connected to ground (since version 3)

− 0.02 − W

Analog part

clamp

clamping current VI= 0.9 V DC −±3.5 −µA

i(p-p)

input voltage (peak-to-peak value)

for normal video levels [1 V (p-p)]; −3dB termination 27/47 Ω and AC coupling required; coupling capacitor = 22 nF

0.3 0.7 1.2 V

| input impedance clamping current off 200 −− kΩ

input capacitance −−10 pF

Page 24

1998 May 15 24

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

channel crosstalk fi= 5 MHz −−−50 dB

Analog-to-digital converters

B bandwidth at −3dB − 7 − MHz φ

diff

differential phase (ampliﬁer plus anti-alias ﬁlter = bypass)

− 2 − deg

diff

differential gain (ampliﬁer plus anti-alias ﬁlter = bypass)

− 2 − %

clkADC

ADC clock frequency 12.8 − 14.3 MHz

DLE DC differential linearity

error

− 0.7 − LSB

ILE DC integral linearity error − 1 − LSB

Digital inputs

IL(SCL,SDA)

LOW level input voltage pins SDA and SCL

−0.5 − +0.3V

DDD

HIGH level input voltage pins SDA and SCL

0.7V

DDD

− V

DDD

+ 0.5 V

IL(xtal)

LOW level CMOS input voltage pin XTALI

−0.3 − +0.8 V

IH(xtal)

HIGH level CMOS input voltage pin XTALI

2.0 − V

DDD

+ 0.3 V

ILn

LOW level input voltage all other inputs

−0.3 − +0.8 V

IHn

HIGH level input voltage all other inputs

2.0 − 5.5 V

input leakage current −−1 µA

input capacitance outputs at 3-state −−8pF

i(n)

input capacitance all other inputs

−−5pF

Digital outputs

OL(SCL,SDA)

LOW level output voltage pins SDA and SCL

SDA/SCL at 3 mA (6 mA) sink current

−−0.4 (0.6) V

LOW level output voltage V

DDD

= max; IOL=2mA 0 − 0.4 V

HIGH level output voltage V

DDD

= min, IOH= −2 mA 2.4 − V

DDD

+ 0.5 V

OL(clk)

LOW level output voltage for clocks

−0.5 − +0.6 V

OH(clk)

HIGH level output voltage for clocks

2.4 − V

DDD

+ 0.5 V

output leakage current at 3-state mode −−10 µA

FEI input timing

SU;DAT

input data set-up time 13 −− ns

HD;DAT

input data hold time 3 −− ns

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Page 25

1998 May 15 25

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

Data and control output timing; note 1 C

output load capacitance 15 − 40 pF

OHD;DAT

output hold time CL=15pF 4 −− ns

propagation delay CL=25pF −−20 ns

PDZ

propagation delay to 3-state

−−20 ns

Clock output timing (LLC and LLC2); note 2 C

L(LLC)

output load capacitance 15 − 40 pF

cycle time LLC 35 − 39 ns

LLC2 70 − 78 ns

LLC

duty factors for t

LLCH/tLLC

and t

LLC2H/tLLC2

CL=25pF 40 − 60 %

rise time LLC, LLC2 −−5ns

fall time LLC, LLC2 −−5ns

delay time LLC output to LLC2 output

at 1.5 V; LLC/LLC2 = 25 pF

−4 − +8 ns

Data qualiﬁer output timing (CREF)

OHD;CREF

output hold time CL=15pF 4 −− ns

PD;CREF

propagation delay from positive edge of LLC

CL=25pF −−20 ns

Clock input timing (XTALI)

XTALI

duty factor for t

XTALIH/tXTALI

nominal frequency 40 − 60 %

Horizontal PLL

nominal line frequency 50 Hz ﬁeld − 15625 − Hz

60 Hz ﬁeld − 15734 − Hz

∆f

H/fHn

permissible static deviation −−5.7 %

Subcarrier PLL

SCn

nominal subcarrier frequency

PAL BGHI − 4433619 − Hz NTSC M; NTSC-Japan − 3579545 − Hz PAL M − 3575612 − Hz PAL N − 3582056 − Hz

∆f

lock-in range ±400 −− Hz

Crystal oscillator

nominal frequency 3rd harmonic; note 3 − 24.576 − MHz

∆f/f

permissible nominal frequency deviation

−−±50 10

−6

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Page 26

1998 May 15 26

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

Notes

1. The levels must be measured with load circuits; 1.2 kΩ at 3 V (TTL load); CL= 50 pF.

2. The effects of rise and fall times are included in the calculation of t

OHD;DAT

, tPD and t

PDZ

. Timings and levels refer to

drawings and conditions illustrated in Figs 15 and 16.

3. Order number: Philips 4322 143 05291.

Table 2 Processing delay

Note

1. Digital processing delay (LLC CLOCKS) for VBI data is defined in Fig.23 ‘Horizontal timing diagram’.

Crystal oscillator

nominal frequency 3rd harmonic; note 3 − 24.576 − MHz

∆f/f

permissible nominal frequency deviation

−−±50 10

−6

∆Tf/f

permissible nominal frequency deviation with temperature

−−±20 10

−6

CRYSTAL SPECIFICATION (X1) T

amb(X1)

operating ambient temperature

0 − 70 °C

load capacitance 8 −− pF

series resonance resistor − 40 80 Ω

motional capacitance − 1.5 ±20% − fF

parallel capacitance − 3.5 ±20% − pF

FUNCTION

TYPICAL ANALOG DELAY

AI22 → ADCIN (AOUT) (ns)

DIGITAL DELAY

ADCIN → VPO (LLC CLOCKS)

[YDEL(2 to 0) = 000]; note 1

Without ampliﬁer or anti-alias ﬁlter 15

179With ampliﬁer, without anti-alias ﬁlter 25

With ampliﬁer and anti-alias ﬁlter 75

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Page 27

1998 May 15 27

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

13 TIMING DIAGRAMS

Fig.15 Clock/data timing (8-bit CCIR-656 format of the VPO-bus).

An explanation of the output formats is given in Table 6.

handbook, full pagewidth

2.4 V

LLC

OHD;DAT

LLCL

LLCH

OUTPUTS VPO, HREF, VREF, VS, HS

CLOCK OUTPUT LLC

0.6 V

2.6 V

1.5 V

0.6 V

MGC658

Fig.16 Clock/data timing (12 and 16-bit CCIR-601 format of the VPO-bus).

An explanation of the output formats is given in Table 6. The FEI timing of the VPO-bus is illustrated in Figs 18 and 19.

handbook, full pagewidth

2.4 V

0.6 V

LLC

OHD;CREF

dLLC2

LLCL

LLCH

2.4 V

0.6 V

OUTPUTS VPO, HREF,

CLOCK OUTPUT LLC

CLOCK OUTPUT LLC2

1.5 V

0.6 V

2.6 V

1.5 V

0.6 V

2.6 V

VREF, VS, HS

OUTPUT CREF

OHD;DAT

dLLC2

MGC659

LLC

OHD;CREF

Page 28

1998 May 15 28

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

Fig.17 Clock/data timing for RGB (8, 8 and 8) output format.

An explanation of the output formats is given in Table 6.

handbook, full pagewidth

MBH227

2.4 V

1.5 V

0.6 V

2.4 V

1.5 V

0.6 V

2.4 V

1.5 V

0.6 V

CLOCK OUTPUT LLC

OUTPUT CREF

RGB (8, 8, 8) data

VPO15 to VPO8

RGB (8, 8, 8) data

VPO7 to VPO0

2.4 V

1.5 V

0.6 V

OHD;DAT

OHD;CREF

PD;CREF

R(7 : 3) G(7 : 5)

G(4 : 2) B(7 : 3)

R(2 : 0) G(1 : 0) B(2 : 0)

LLCL

LLC

LLCH

Fig.18 FEI timing diagram (FEI sampling at CREF = HIGH) for OFTS = 0, 1 or 2).

I2C-bus bit FECO = 1.

handbook, full pagewidth

LLC

CREF

HREF

FEI

VPO

to 3-state

from 3-state

MGC656

PDZ

HD;DAT

SU;DAT

OHD;DAT

Page 29

1998 May 15 29

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

Fig.19 FEI timing diagram (FEI sampling at CREF = LOW) for OFTS = 0, 1 or 2).

Timing is compatible with SAA7110; I2C-bus bit FECO = 0.

handbook, full pagewidth

LLC

CREF

HREF

VPO

SU;DAT

HD;DAT

to 3-state

MGC657

from 3-state

OHD;DAT

PDZ

FEI

Fig.20 Real time control output.

(1) Set to zero for one transmission, if a phase reset of the fsc− DTO is applied via I2C-bus bit CDTO. RTCO sequence is generated in LLC/4.

The HPLL increment represents the actual LFCO frequency (f

LFCO

× 4=f

LLC

); 16 LSB from 20, upper four bits are fixed to 0100b.

Where: f

XTAL

= 24.576 MHz, word length DTO2 = 20 bits.

The f

increment represents the actual subcarrier frequency (related to the actual clock); 23 LSB from 24, MSB is 0b.

Where: word length DTO1 = 24 bits.

LFCO

INCR

HPLLfXTAL

word lengthDTO2

------------------------------------------------ -

INCR

FSCPLLfXTAL

word lengthDTO1

-------------------------------------------------------

INCR

HPLL

----------------------------

×=

handbook, full pagewidth

TIME SLOT:

BIT NO.:

transmitted once per line

1920

1617

11 1012

SEQUENCE

0 67

452

RESERVED

INCR

FSCPLL

MGC649

RESERVED

128

HIGH

LOW

INCR

HPLL

RESERVED

DTO RESET

(1)

50 Hz fields: 235 60 Hz fields: 232

Page 30

1998 May 15 30

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

Fig.21 HREF timing diagram.

handbook, full pagewidth

LLC

CREF

LLC2

HREF

UVn

HREF

UVn

1234

U0 V0 U2 V2 U4

END OF ACTIVE LINE

START OF ACTIVE LINE

719718717716715

U718 V718

MGC646

V716U716V714

Fig.22 FEI timing in CCIR 656 mode [OFTS (1 : 0) = 3].

handbook, full pagewidth

MBH766

PDZ

OHD

LLC

FEI

VPO

Page 31

1998 May 15 31

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

Fig.23 Horizontal timing diagram.

(1) PLIN is switched to output RTS1 via I2C-bus bit RTSE1 = 0. (2) See Table 2. (3) HDEL (1 : 0) = 0 0, YDEL (2 : 0) = 0 0 0.

handbook, full pagewidth

108

−107

107

−106

MGD701

CVBS

VBI

26 × 1/LLC

179 × 1/LLC

27 × 2/LLC

Y - output

HREF (50 Hz)

12 × 2/LLC

720 × 2/LLC

144 × 2/LLC

23 × 2/LLC

138 × 2/LLC

720 × 2/LLC

burst

RTS1 (PLIN)

(1)

processing delay CVBS->VPO

(2)

4/LLC

HREF (60 Hz)

HS (60 Hz)

sync clipped

16 × 2/LLC

HS (50 Hz)

programming range

(step size: 8/LLC)

HS (60 Hz)

programming range

(step size: 8/LLC)

43 × 2/LLC

Page 32

1998 May 15 32

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

Fig.24 Vertical timing diagram for 50 Hz [nominal input signal VNL in normal mode (VNOI = 00b)].

(1) ODD is switched to output RTS0 via I2C-bus bit RTSE0 = 0. (2) Additional VREF positions can be achieved via I2C-bits VCTR1 and VCTR0 (see Fig.9). The luminance peaking and the chrominance trap are bypassed during VREF = 0 if I2C-bus bit VBLB is set to logic 1. The chrominance delay line (chrominance-comb filter for NTSC, phase error correcting for PAL) is disabled during VREF = 0.

handbook, full pagewidth

313 314

315 316

317

318

319

335 336

1234567822625

HREF

input CVBS

(b) 2nd field

(a) 1st field

VREF VREF

VREF

VRLN = 1

(2)

VRLN = 0

(2)

624

623

622

HREF

input CVBS

312

311

310

VRLN = 0

(2)

337

MGG069

535 x 2/LLC

RTS0 (ODD)

(1)

RTS0 (ODD)

(1)

320

77 x 2/LLC

VRLN = 1

(2)

Page 33

1998 May 15 33

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

Fig.25 Vertical timing diagram for 60 Hz [nominal input signal VNL in normal mode (VNOI = 00b)].

(1) ODD is switched to output RTS0 via I2C-bus bit RTSE0 = 0. (2) Line numbers in parenthesis refer to CCIR line counting. (3) Additional VREF positions can be achieved via I2C-bus bits VCTR1 and VCTR0 (see Fig.9). The luminance peaking and the chrominance trap are bypassed during VREF = 0 if I2C-bus bit VBLB is set to logic 1. The chrominance delay line (chrominance-comb filter for NTSC, phase error correcting for PAL) is disabled during VREF = 0.

handbook, full pagewidth

(266) (267) (268) (269) (270) (271) (272) (273) (274)

(4) (5) (6) (7) (8) (9)

(10)

(11)

(20)

(3)

HREF

(b) 2nd field

(a) 1st field

input CVBS

(2)(1)

(525)

(21)

(22)

(283)

(284)

(265)

(264)

(263)

(262)

VRLN = 1

(3)

VRLN = 0

(3)

VRLN = 1

(3)

VRLN = 0

(3)

1234567

525

524

523

522

18 19

263 264 265 266 267 268 269 270 271

280

281

262

261

260

259

(285)

282

(2)

MGG070

520 x 2/LLC

RTS0 (ODD)

(1)

81 x 2/LLC

VREF

HREF

input CVBS

RTS0 (ODD)

(1)

Page 34

1998 May 15 34

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

Table 3 Digital output control

Note

1. Only active in 656-format (OFTS = 3).

OEYC FEI TCLO

(1)

VPO

15 to 8

VPO

7to0

000 Z 1 0 0 active 010 Z 110 Z 001ZZ 1 0 1 active Z 011ZZ 111ZZ

14 CLOCK SYSTEM

14.1 Clock generation circuit

The internal CGC generates the system clocks LLC, LLC2 and the clock reference signal CREF. The internally generated LFCO (triangular waveform) is multiplied by 4 via the analog PLL (including phase detector, loop filter, VCO and frequency divider). The rectangular output signals have a 50% duty factor.

Table 4 Clock frequencies

CLOCK FREQUENCY (MHz)

XTAL 24.576

LLC 27 LLC2 13.5 LLC4 6.75 LLC8 3.375

Fig.26 Block diagram of clock generation circuit.

handbook, full pagewidth

BAND PASS

FC = LLC/4

ZERO

CROSS

DETECTION

PHASE

DETECTION

LOOP

FILTER

DIVIDER

1/2

DIVIDER

1/2

OSCILLATOR

DELAY CREF

MGC632

LLC2

LLC

LFCO

Page 35

1998 May 15 35

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

14.2 Power-on control

Power-on reset is activated at power-on, chip enable, PLL clock generation failure and if the supply voltage falls below

2.7 V. The RES signal can be applied to reset other circuits of the digital picture processing system.

Fig.27 Power-on control circuit.

CE = chip enable input; XTAL = crystal oscillator output; LLCINT = internal system clock; RESINT = internal reset; LLC = line-locked clock output;

RES = reset output (active LOW).

handbook, full pagewidth

MGC633

128 LCC

896 LCC

digital delay

some ms

20 to 200 µs

PLL-delay

1 ms

RES

LLC

RESINT

LLCINT

XTAL

POC V

DDA

POC

LOGIC

ANALOG

POC V

DDD

DIGITAL

POC

DELAY

CLOCK

PLL

LLC

CLK0

RES

Page 36

1998 May 15 36

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

Table 5 Power-on control sequence

15 OUTPUT FORMATS Table 6 Output formats of the VPO bus (note 1)

INTERNAL POWER-ON CONTROL

SEQUENCE

PIN OUTPUT STATUS FUNCTION

Directly after power-on asynchronous reset

VPO15 to VPO0, RTCO, RTS0, RTS1, GPSW, HREF, VREF, HS, VS, LLC, LLC2 and CREF are in high-impedance state

direct switching to high impedance for 20 to 200 ms

Synchronous reset sequence LLC, LLC2, CREF, RTCO, RTS0,

RTS1, GPSW and SDA become active; VPO15 to VPO0, HREF , VREF, HS and VS are held in high-impedance state

internal reset sequence

Status after power-on control sequence

VPO15 to VPO0, HREF , VREF, HS and VS are held in high-impedance state

after power-on (reset sequence) a complete I

C-bus transmission is

required

BUS

SIGNAL

411 (12-BIT)

422

(16-BIT)

(2)

CCIR-656 (8-BIT)

(3)

RGB (16-BIT)

(4)

RGB (24-BIT)

(4)

VPO15 Y

07Y17Y27Y37

U07Y07V07Y

R4 R7 R7

VPO14 Y

06Y16Y26Y36

U06Y06V06Y

R3 R6 R6

VPO13 Y

05Y15Y25Y35

U05Y05V05Y

R2 R5 R5

VPO12 Y

04Y14Y24Y34

U04Y04V04Y

R1 R4 R4

VPO11 Y

03Y13Y23Y33

U03Y03V03Y

R0 R3 R3

VPO10 Y

02Y12Y22Y32

U02Y02V02Y

G5 G7 G7

VPO9 Y

01Y11Y21Y31

01Y01V01Y11

G4 G6 G6

VPO8 Y

00Y10Y20Y30

U00Y00V00Y

G3 G5 G5

VPO7 U

07U05U03U01

X X X X G2 G4 R2

VPO6 U

06U04U02U00

X X X X G1 G3 R1

VPO5 V

07V05V03V01

X X X X G0 G2 R0

VPO4 V

06V04V02V00

X X X X B4 B7 G1

VPO3 X X X X U

X X X X B3 B6 G0

VPO2 X X X X U

X X X X B2 B5 B2

VPO1 X X X X U

X X X X B1 B4 B1

VPO0 X X X X U

X X X X B0 B3 B0

Pixel order Y

0123 0 1 0 1 − note 5 note 6

Pixel order UV

000 −−

Data rates LLC2 LLC2 LLC LLC2 − I2C-bus

control signals

OFTS0 = 0 OFTS0 = 1 OFTS0 = 1 OFTS0 = 0 OFTS0 = 0 OFTS1 = 1 OFTS1 = 0 OFTS1 = 1 OFTS1 = 0 OFTS1 = 0

RGB888 = X RGB888 = X RGB888 = X RGB888 = 0 RGB888 = 1

Page 37

1998 May 15 37

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

Notes to Table 5

1. VPO bus allows connection to 5 V video data bus systems.

2. Values in accordance with CCIR 601.

3. Before and after the video data, video timing codes are inserted in accordance with CCIR 656. a) VPO15 to VPO8 = VPO7 to VPO0 = CCIR 656 data if I2C-bus bit TCLO = 0 b) VPO15 to VPO8 = CCIR 656 data, VPO7 to VPO0 = 3-state if I2C-bus bit TCLO = 1.

4. During HREF = LOW RGB levels are set to 16 (10 hex). RGB 16-bit is achieved by dropping the LSBs of the 8-bit signals (after dithering if desired).

5. CREF = 0 (see Fig.17).

6. CREF = 1 (see Fig.17).

Fig.28 VPO output signal range with default BCS settings.

Equations for modification to the YUV levels via BCS control I2C-bus bytes BRIG, CONT and SATN. Luminance:

Chrominance:

It should be noted that the resulting levels are limited to 1 to 254 in accordance with CCIR-601/656 standard.

OUT

Int

CONT

----------------- -

Y128–()× BRIG+=

OUT

Int

SATN

---------------- -

Cr Cb, 128–()× 128+=

CCIR Rec. 602 digital levels.

a. Y output range. b. U output range (Cb). c. V output range (Cr).

handbook, full pagewidth

LUMINANCE 100%

+255 +235

+128

+16

white

black

U-COMPONENT

+255 +240

+212 +212

+128

+16

+44

blue 100%

blue 75%

yellow 75%

yellow 100%

colourless

V-COMPONENT

+255 +240

+128

+16

+44

red 100%

red 75%

cyan 75% cyan 100%

colourless

MGC634

Page 38

1998 May 15 38

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

Fig.29 VBI data bypass output range.

VBI data levels are not dependent on BCS settings.

a. For sources containing 7.5 IRE black level offset (e.g. NTSC−M). b. For sources not containing black level offset.

handbook, full pagewidth

LUMINANCE

+255 +209

+71 +60

white

sync bottom

black shoulder

black

SYNC

LUMINANCE

+255

+199

+60

white

sync bottom

black shoulder = black

SYNC

MGD700

Fig.30 Oscillator application.

Order number: Philips 4322 143 05291.

a. With quartz crystal. b. With external clock.

handbook, full pagewidth

XTAL

XTALI

MGG072

XTAL

L = 10 µH ± 20%

C = 10 pF

C = 1 nF

quartz (3rd harmonic)

24.576 MHz

XTALI

SAA7111A SAA7111A

Page 39

1998 May 15 39

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

16 APPLICATION INFORMATION

Fig.31 Application diagram.

handbook, full pagewidth

Q1(24.576 MHz)

VPO(15 : 0)

SCL

DDD

AI22

FEI

SDA

RTCO

AOUT

GPSW

RTS0

RTS1

RES

CREF

LLC2

LLC

HREF

SSA

DDA

SSA

VREF

SAA7111A

47 Ω

22 nF

100 nF

C11

C12

C13

C14

C15

1 kΩ

n.c.

SSA2

SSS

SS1VSS2VSS3VSS4VSS5

IICSA

SSA1

SSA0

DDA0VDDA1VDDA2

DD1VDD2VDD3VDD4VDD5

TMS

TDI

TDO

TCK

TRST

C17

10 µH

C16 1 nF

10 pF

C18

1 kΩ

2533

34 35 36 37 38 39 42 43 44 45 46 47 48

27 30 60

28 29

20 21 22 23

XTAL

XTALI

MGG071

SSA

BST

n.c.

49 50 51

100 nF

47 Ω

22 nF

SSA

AI21

47 Ω

22 nF

SSA

AI12

47 Ω

22 nF

SSA

AI11

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R10

27 Ω

Page 40

1998 May 15 40

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

Fig.32 Application diagram for RGB 24-bit output format.

I2C-bus control bits: OFTS(1 : 0) = 00 (subaddress 10H, bits D7 and D6). RGB888 = 1 (subaddress 12H, bit D3).

handbook, full pagewidth

OEN D7

7 6 5 4 3 2 1 0

D6 D5 D4

e.g.

74HCT574

D3 D2 D1 D0

44 45 46 47 48 49 50 51

HREF 17 27 30 60 28 29 53 14 20 21 32 23

CLK

R (2 : 0)

R (7 : 0) O6 O5 O4 O3 O2 O1

DDVDD

G (1 : 0)

G (7 : 0)

B (2 : 0)

B (7 : 0)

LLC2N

MGG073

LLC2

e.g. 74HCT240

B (7 : 3)VPO (4 : 0)

VPO

(7 : 0)

SAA7111A

VPO (15 : 11) R (7 : 3)

G (7 : 5)

G (4 : 2)

VPO (10 : 8)

VPO (7 : 5)

VREF HS VS RTCO RTS1 RTS0 GPSW AOUT LLC

CREF RES

15 14 13 12 11 10 9 8

34 35 36 37 38 39 42 43

VPO

(15 : 8)

16.1 Layout hints

Use separate ground planes for analog and digital ground. Connect these planes at one point directly under the device, by using a zero Ω resistor. Use separate supply lines for analog and digital supply. Place the supply decoupling capacitors close to the supply pins.

Place the coupling (clamp) capacitors close to the analog input pins. Place the termination resistors close to the coupling capacitors. Care should be exercised concerning the hidden layout capacitors around the crystal application. To avoid reflection effects use serial resistors in the clock, sync and data lines.

Page 41

1998 May 15 41

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

17 I2C-BUS DESCRIPTION

17.1 I

C-bus format

Table 7 Write procedure

Table 8 Read procedure (combined format)

Table 9 Description of I

C-bus format

Notes

1. If more than one byte DATA is transmitted then the auto-increment of the subaddress is performed.

2. During slave transmitter mode the SCL-LOW period may be extended by pulling SCL to LOW (in accordance with the I

C-bus specification).

3. The I2C-bus subaddress 00 has to be initialized with 0 before being read.

S SLAVE ADDRESS W ACK-s SUBADDRESS ACK-s DATA (N BYTES) ACK-s P

S SLAVE ADDRESS W ACK-s SUBADDRESS ACK-s

Sr SLAVE ADDRESS R ACK-s DATA (N BYTES) ACK-m P

CODE DESCRIPTION

S START condition Sr repeated START condition Slave address W 0100 1000b (IICSA = LOW) or 0100 1010b (IICSA = HIGH) Slave address R 0100 1001b (IICSA = LOW) or 0100 1011b (IICSA = HIGH) ACK-s acknowledge generated by the slave ACK-m acknowledge generated by the master Subaddress subaddress byte; see Table 10 Data data byte; see Table 10; note 1 P STOP condition X = LSB slave

address

read/write control bit; X = 0, order to write (the circuit is slave receiver); X = 1, order to read (the circuit is slave transmitter)

Slave address read = 49H or 4BH; note 2

write = 48H or 4AH IICSA = 0 or 1

Subaddresses 00H chip version read and write; note 3

01H reserved − 02h to 05H front-end part read and write 06H to 13H decoder part read and write 14H reserved − 15H to 17H decoder part read and write 18H to 19H reserved − 1AH to 1CH Line-21 text slicer part read only 1DH to 1EH reserved − 1FH status byte read only

Page 42

1998 May 15 42

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

Table 10 I2C-bus receiver/transmitter overview

Note

1. All unused control bits must be programmed with logic 0.

SLAVE ADDRESS

READ WRITE IICSA

49H

4BH

48H 4AH

0 1

FUNCTION

SUB-

ADDR

D7 D6 D5 D4 D3 D2 D1 D0

Chip version 00 ID07 ID06 ID05 ID04 ID03 ID02 ID01 ID00 Reserved 01

(1) (1) (1) (1) (1) (1) (1) (1)

Analog input contr 1 02 FUSE1 FUSE0 GUDL2 GUDL1 GUDL0 MODE2 MODE1 MODE0 Analog input contr 2 03

(1)

HLNRS VBSL WPOFF HOLDG GAFIX GAI28 GAI18 Analog input contr 3 04 GAI17 GAI16 GAI15 GAI14 GAI13 GAI12 GAI11 GAI10 Analog input contr 4 05 GAI27 GAI26 GAI25 GAI24 GAI23 GAI22 GAI21 GAI20 Horizontal sync start 06 HSB7 HSB6 HSB5 HSB4 HSB3 HSB2 HSB1 HSB0 Horizontal sync stop 07 HSS7 HSS6 HSS5 HSS4 HSS3 HSS2 HSS1 HSS0 Sync control 08 AUFD FSEL EXFIL

(1)

VTRC HPLL VNOI1 VNOI0 Luminance control 09 BYPS PREF BPSS1 BPSS0 VBLB UPTCV APER1 APER0 Luminance

brightness

0A BRIG7 BRIG6 BRIG5 BRIG4 BRIG3 BRIG2 BRIG1 BRIG0

Luminance contrast 0B CONT7 CONT6 CONT5 CONT4 CONT3 CONT2 CONT1 CONT0 Chroma saturation 0C SATN7 SATN6 SATN5 SATN4 SATN3 SATN2 SATN1 SATN0 Chroma Hue control 0D HUEC7 HUEC6 HUEC5 HUEC4 HUEC3 HUEC2 HUEC1 HUEC0 Chroma control 0E CDTO CSTD2 CSTD1 CSTD0 DCCF FCTC CHBW1 CHBW0 Reserved 0F

(1) (1) (1) (1) (1) (1) (1) (1)

Format/delay control 10 OFTS1 OFTS0 HDEL1 HDEL0 VRLN YDEL2 YDEL1 YDEL0 Output control 1 11 GPSW CM99 FECO COMPO OEYC OEHV VIPB COLO Output control 2 12 RTSE1 RTSE0 TCLO CBR RGB888 DIT AOSL1 AOSL0 Output control 3 13 VCTR1 VCTR0 CCTR1 CCTR0 BCHI1 BCHI0 BCLO1 BCLO0 Reserved 14

(1) (1) (1) (1) (1) (1) (1) (1)

V_GATE1_START 15 VSTA7 VSTA6 VSTA5 VSTA4 VSTA3 VSTA2 VSTA1 VSTA0 V_GATE1_STOP 16 VSTO7 VSTO6 VSTO5 VSTO4 VSTO3 VSTO2 VSTO1 VSTO0 V_GATE1_MSB 17

(1) (1) (1) (1) (1) (1)

VSTO8 VSTA8

Reserved 18-19

(1) (1) (1) (1) (1) (1) (1) (1)

Text slicer status 1A

(1) (1) (1) (1)

F2VAL F2RDY F1VAL F1RDY

Decoded bytes of the text slicer

1B P1 BYTE16 BYTE15 BYTE14 BYTE13 BYTE12 BYTE11 BYTE10 1C P2 BYTE26 BYTE25 BYTE24 BYTE23 BYTE22 BYTE21 BYTE20

Reserved 1D-1E

(1) (1) (1) (1) (1) (1) (1) (1)

Status byte 1F STTC HLCK FIDT GLIMT GLIMB WIPA SLTCA CODE

Page 43

1998 May 15 43

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

17.2 I2C-bus detail

The I2C-bus receiver slave address is 48H/49H. Subaddresses 0F, 14, 18, 19, 1D and 1E are reserved; subaddress 01 is reserved for chip version.

17.2.1 S

UBADDRESS 00

Table 11 Chip version SA00; note 1

Note

1. X = reserved.

17.2.2 S

UBADDRESS 02

Table 12 Analog control 1 SA02; note 1

Notes

1. Mode select (see Figs 33 to 40).

2. For modes 0 to 3 use BYPS(SA09,D7) = 0 (chrominance trap active), for modes 4 to 7 use BYPS = 1 (chrominance trap bypassed).

Table 13 Analog control 1 SA 02, D5 to D3 (see Fig.14)

FUNCTION

LOGIC LEVELS

ID07 ID06 ID05 ID04 ID03 ID02 ID01 ID00

Chip version

V1 0001XXXX V2 0010XXXX

FUNCTION

(2)

CONTROL BITS D2 TO D0

MODE 2 MODE 1 MODE 0

Mode 0 : CVBS (automatic gain) 0 0 0 Mode 1 : CVBS (automatic gain) 0 0 1 Mode 2 : CVBS (automatic gain) 0 1 0 Mode 3 : CVBS (automatic gain) 0 1 1 Mode4:Y (automatic gain) + C (gain channel 2 ﬁxed to GAI2 level) 1 0 0 Mode5:Y (automatic gain) + C (gain channel 2 ﬁxed to GAI2 level) 1 0 1 Mode6:Y (automatic gain) + C (gain channel 2 adapted to Y gain) 1 1 0 Mode7:Y (automatic gain) + C (gain channel 2 adapted to Y gain) 1 1 1

DECIMAL VALUE UPDATE HYSTERESIS FOR 9-BIT GAIN

CONTROL BITS D5 TO D3

GUDL 2 GUDL 1 GUDL 0

0.... off 0 0 0

....7 ±7 LSB 1 1 1

Page 44

1998 May 15 44

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

Table 14 Analog control

ANALOG FUNCTION SELECT FUSE

CONTROL BITS D7 AND D6 FUSE 1 FUSE 0

Ampliﬁer plus anti-alias ﬁlter bypassed 0 0

01 Ampliﬁer active 1 0 Ampliﬁer plus anti-alias ﬁlter active 1 1

Fig.33 Mode 0; CVBS (automatic gain).

handbook, halfpage

AI22 AI21

AI12 AI11

CHROMA

LUMA

AD2

AD1

MGC637

Fig.34 Mode 1; CVBS (automatic gain).

handbook, halfpage

MGC638

AI22 AI21

AI12 AI11

CHROMA

LUMA

AD2

AD1

Fig.35 Mode 2; CVBS (automatic gain).

handbook, halfpage

MGC639

AI22 AI21

AI12 AI11

CHROMA

LUMA

AD2

AD1

Fig.36 Mode 3; CVBS (automatic gain).

handbook, halfpage

MGC640

AI22 AI21

AI12 AI11

CHROMA

LUMA

AD2

AD1

Fig.37 Mode 4 Y (automatic gain) + C

(gain channel 2 fixed to GAI2 level).

handbook, halfpage

MGC641

AI22 AI21

AI12 AI11

CHROMA

LUMA

AD2

AD1

Fig.38 Mode 5 Y (automatic gain) + C

(gain channel 2 fixed to GAI2 level).

handbook, halfpage

MGC642

AI22 AI21

AI12 AI11

CHROMA

LUMA

AD2

AD1

Page 45

1998 May 15 45

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

Fig.39 Mode 6 Y (automatic gain) + C

(gain channel 2 adapted to Y gain).

handbook, halfpage

MGC643

AI22 AI21

AI12 AI11

CHROMA

LUMA

AD2

AD1

Fig.40 Mode 7 Y (automatic gain) + C

(gain channel 2 adapted to Y gain).

handbook, halfpage

MGC644

AI22 AI21

AI12 AI11

CHROMA

LUMA

AD2

AD1

17.2.3 SUBADDRESS 03

Table 15 Analog control 2 (AICO2) SA03

FUNCTION BIT NAME LOGIC LEVEL CONTROL BIT

Static gain control channel 1 (GAI18) (see SA04)

Sign bit of gain control GAI18 see Table16 D0

Static gain control channel 2 (GAI28) (see SA05)

Sign bit of gain control GAI28 see Table17 D1

Gain control ﬁx (GAFIX)

Automatic gain controlled by MODE 1 and MODE 0 GAFIX 0 D2 Gain control is user programmable via GAI1 + GAI2 GAFIX 1 D2

Automatic gain control integration (HOLDG)

AGC active HOLDG 0 D3 AGC integration hold (freeze) HOLDG 1 D3

White peak off (WPOFF)

White peak control active WPOFF 0 D4 White peak off WPOFF 1 D4

Vertical blanking select (VBSL)

Long vertical blanking VBSL 0 D5 Short vertical blanking VBSL 1 D5

HL not reference select (HLNRS)

Normal clamping by HL not HLNRS 0 D6 Reference select by HL not HLNRS 1 D6

Page 46

1998 May 15 46

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

17.2.4 SUBADDRESS 04 Table 16 Gain control analog (AIC03); static gain control channel 1 GAI1 SA 04, D7 to D0

17.2.5 S

UBADDRESS 05

Table 17 Gain control analog (AIC04); static gain control channel 2 GAI2 SA 05, D7 to D0

17.2.6 S

UBADDRESS 06

Table 18 Horizontal sync begin SA 06, D7 to D0

DECIMAL

VALUE

GAIN

(dB)

SIGN

BIT

CONTROL BITS D7 TO D0

GAI18 GAI17 GAI16 GAI15 GAI14 GAI13 GAI12 GAI11 GAI10

0.... −5.98 0 0 0000000

....255 0 0 1 1111111

256.... 0 1 0 0000000

....511 5.98 1 1 1111111

DECIMAL

VALUE

GAIN

(dB)

SIGN BIT

(SA 03, D1)

CONTROL BITS D7 to D0

GAI28 GAI27 GAI26 GAI25 GAI24 GAI23 GAI22 GAI21 GAI20

0.... −5.98 0 00000000

....255 0 0 11111111

256.... 0 1 00000000

....511 5.98 1 11111111

DELAY TIME

(STEP SIZE = 8/LLC)

CONTROL BITS D7 to D0

HSB7 HSB6 HSB5 HSB4 HSB3 HSB2 HSB1 HSB0

−128...−108 forbidden (outside available central counter range)

−107... 1 0 0 1 0101

...108 (50Hz) 0 1 1 0 1100 ...107 (60Hz) 0 1 1 0 1011

109...127 (50Hz) forbidden (outside available central counter range)

108...127 (60Hz)

Page 47

1998 May 15 47

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

17.2.7 SUBADDRESS 07 Table 19 Horizontal sync stop SA 07, D7 to D0

17.2.8 S

UBADDRESS 08

Table 20 Sync control SA 08, D7 to D5, D3 to D0

DELAY TIME

(STEP SIZE = 8/LLC)

CONTROL BITS D7 to D0

HSS7 HSS6 HSS5 HSS4 HSS3 HSS2 HSS1 HSS0

−128...−108 forbidden (outside available central counter range)

−107... 1 0 0 1 0 1 0 1

...108 (50Hz) 0 1 1 0 1 1 0 0 ...107 (60Hz) 0 1 1 0 1 0 1 1

109...127 (50Hz) forbidden (outside available central counter range)

108...127 (60Hz)

FUNCTION BIT NAME LOGIC LEVEL CONTROL BIT

Vertical noise reduction (VNOI)

Normal mode VNOI1 0 D1

VNOI0 0 D0

Searching mode VNOI1 0 D1

VNOI0 1 D0

Free running mode VNOI1 1 D1

VNOI0 0 D0

Vertical noise reduction bypassed VNOI1 1 D1

VNOI0 1 D0

Horizontal PLL (HPLL)

PLL closed HPLL 0 D2 PLL open, horizontal frequency ﬁxed HPLL 1 D2

TV/VTR mode select (VTRC)

TV mode (recommended for poor quality TV signals only)

VTRC 0 D3

VTR mode (recommended as default setting) VTRC 1 D3

Extended loop ﬁlter (EXFIL)

Word width of the loop ﬁlter (LF2) ampliﬁcation = 16-bit EXFIL 0 D5 Word width of the loop ﬁlter (LF2) ampliﬁcation = 14-bit EXFIL 1 D5

Field selection (FSEL)

50 Hz, 625 lines FSEL 0 D6 60 Hz, 525 lines FSEL 1 D6

Automatic ﬁeld detection (AUFD)

Field state directly controlled via FSEL AUFD 0 D7 Automatic ﬁeld detection AUFD 1 D7

Page 48

1998 May 15 48

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

17.2.9 SUBADDRESS 09

Table 21 Luminance control SA 09, D7 to D0

Note

1. Not to be used with bypassed chrominance trap.

FUNCTION BIT NAME LOGIC LEVEL CONTROL BIT

Aperture factor (APER)

Aperture factor = 0 APER1 0 D1

APER0 0 D0

Aperture factor = 0.25 APER1 0 D1

APER0 1 D0

Aperture factor = 0.5 APER1 1 D1

APER0 0 D0

Aperture factor = 1.0 APER1 1 D1

APER0 1 D0

Update time interval for AGC value (UPTCV)

Horizontal update (once per line) UPTCV 0 D2 Vertical update (once per ﬁeld) UPTCV 1 D2

Vertical blanking luminance bypass (VBLB)

Active luminance processing VBLB 0 D3 Luminance bypass during vertical blanking VBLB 1 D3

Aperture band pass (centre frequency) (BPSS)

Centre frequency = 4.1 MHz BPSS1 0 D5

BPSS0 0 D4

Centre frequency = 3.8 MHz; note 1 BPSS1 0 D5

BPSS0 1 D4

Centre frequency = 2.6 MHz; note 1 BPSS1 1 D5

BPSS0 0 D4

Centre frequency = 2.9 MHz; note 1 BPSS1 1 D5

BPSS0 1 D4

Preﬁlter active (PREF)

Bypassed PREF 0 D6 Active PREF 1 D6

Chrominance trap bypass (BYPS)

Chrominance trap active; default for CVBS mode BYPS 0 D7 Chrominance trap bypassed; default for S-Video mode BYPS 1 D7

Page 49

1998 May 15 49

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

17.2.10 SUBADDRESS 0A Table 22 Luminance brightness control BRIG7 to BRIG0 SA 0A

17.2.11 S

UBADDRESS 0B

Table 23 Luminance contrast control CONT7 to CONT0 SA 0B

17.2.12 S

UBADDRESS 0C

Table 24 Chrominance saturation control SATN7 to SATN0 SA 0C

17.2.13 S

UBADDRESS 0D

Table 25 Chrominance hue control HUEC7 to HUEC0 SA 0D

OFFSET

CONTROL BITS D7 to D0

BRIG7 BRIG6 BRIG5 BRIG4 BRIG3 BRIG2 BRIG1 BRIG0

255 (bright) 1 1 1 1 1 1 1 1

128 (CCIR level) 1 0 0 0 0 0 0 0

0 (dark) 0 0 0 0 0 0 0 0

GAIN

CONTROL BITS D7 to D0

CONT7 CONT6 CONT5 CONT4 CONT3 CONT2 CONT1 CONT0

1.999 (maximum) 0 1 1 1 1 1 1 1

1.109 (CCIR level) 0 1 0 0 0 1 1 1

1.0 01000000

0 (luminance off) 0 0 0 0 0 0 0 0

−1 (inverse luminance) 1 1 0 0 0 0 0 0

−2 (inverse luminance) 1 0 0 0 0 0 0 0

GAIN

CONTROL BITS D7 to D0

SATN7 SATN6 SATN5 SATN4 SATN3 SATN2 SATN1 SATN0

1.999 (maximum) 0 1 1 1 1 1 1 1

1.0 (CCIR level) 0 1 0 0 0 0 0 0 0 (colour off) 0 0 0 0 0 0 0 0

−1 (inverse

chrominance)

11000000

−2 (inverse

chrominance)

10000000

HUE PHASE (DEG)

CONTROL BITS D7 to D0

HUEC7 HUEC6 HUEC5 HUEC4 HUEC3 HUEC2 HUEC1 HUEC0

+178.6.... 0 1 1 1 1 1 1 1

....0.... 0 0 0 0 0 0 0 0

....−180 10000000

Page 50

1998 May 15 50

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

17.2.14 SUBADDRESS 0E

Table 26 Chrominance control SA 0E

FUNCTION BIT NAME

LOGIC LEVEL

CONTROL

BIT

Chroma bandwidth (CHBW0 and CHBW1)

Small bandwidth (≈ 620 kHz) CHBW1 0 D1

CHBW0 0 D0

Nominal bandwidth (≈ 800 kHz) CHBW1 0 D1

CHBW0 1 D0

Medium bandwidth (≈ 920 kHz) CHBW1 1 D1

CHBW0 0 D0

Wide bandwidth (≈ 1000 kHz) CHBW1 1 D1

CHBW0 1 D0

Fast colour time constant (FCTC)

Nominal time constant FCTC 0 D2 Fast time constant FCTC 1 D2

Disable chrominance comb ﬁlter (DCCF)

Chrominance comb ﬁlter on (during VREF = 1) (see Figs 24 and 25) DCCF 0 D3 Chrominance comb ﬁlter off DCCF 1 D3

Colour standard (CSTD0 to CSTD2); logic levels 100, 110 and 111 are reserved, do not use

Colour standard control automatic switching between PAL BGHI and NTSC M (NTSC-Japan with special level adjustment; luminance brightness subaddress 0A = 95H, luminance contrast subaddress 0BH = 48H)

CSTD2 0 D6 CSTD1 0 D5 CSTD0 0 D4

Colour standard control automatic switching between NTSC 4.43 (50 Hz) and PAL 4.43 (60 Hz)

CSTD2 0 D6 CSTD1 0 D5 CSTD0 1 D4

Colour standard control automatic switching between PAL N and NTSC 4.43 (60 Hz)

CSTD2 0 D6 CSTD1 1 D5 CSTD0 0 D4

Colour standard control automatic switching between NTSC N and PAL M

CSTD2 0 D6 CSTD1 1 D5 CSTD0 1 D4

Colour standard control automatic switching between SECAM and PAL 4.43 (60 Hz)

CSTD2 1 D6 CSTD1 0 D5 CSTD0 1 D4

Clear DTO (CDTO)

Disabled CDTO 0 D7 Every time CDTO is set, the internal subcarrier DTO phase is reset to 0°

and the RTCO output generates a logic 0 at time slot 68 (see RTCO description Fig.20). So an identical subcarrier phase can be generated by an external device (e.g. an encoder).

CDTO 1 D7

Page 51

1998 May 15 51

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

17.2.15 SUBADDRESS 10

Table 27 Format/delay control SA 10

Table 28 VREF pulse position and length VRLN SA 10 (D3)

Notes

1. Additional VREF positions can be achieved via I

C-bus bits VCTR1 and VCTR0 (see Fig.9).

2. The numbers given in parenthesis refer to CCIR line counting.

Table 29 Fine position of HS HDEL0 and HDEL1 SA 10

Table 30 Output format selection OFTS0 and OFTS1 SA 10

LUMINANCE DELAY COMPENSATION

(STEPS IN 2/LLC)

CONTROL BITS D2 to D0

YDEL2 YDEL1 YDEL0

−4... 1 0 0

...0... 0 0 0

...3 0 1 1

VRLN

VREF at 60 Hz 525 LINES

(1)

VREF at 50 Hz 625 LINES

(1)

0101

Length 240 242 286 288 Line number ﬁrst last ﬁrst last ﬁrst last ﬁrst last Field 1

(2)

19 (22) 258 (261) 18 (21) 259 (262) 24 309 23 310

Field 2

(2)

282 (285) 521 (524) 281 (284) 522 (525) 337 622 336 623

FINE POSITION OF HS WITH A STEP SIZE

OF 2/LLC

CONTROL BITS D5 and D4

HDEL1 HDEL0

000 101 210 311

FORMATS

CONTROL BITS D7 and D6

OFTS1 OFTS0

RGB (5, 6 and 5), RGB (8, 8 and 8) (dependent on control bit RGB888); see Table 32

YUV 422 16 bits 0 1 YUV 411 12 bits 1 0 YUV CCIR-656 8 bits 1 1

Page 52

1998 May 15 52

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

17.2.16 SUBADDRESS 11

Table 31 Output control 1 SA 11

FUNCTION BIT NAME LOGIC LEVEL CONTROL BIT

Colour on (COLO)

Automatic colour killer COLO 0 D0 Colour forced on COLO 1 D0

Decoder VIP bypassed (VIPB)

DMSD data to YUV output VIPB 0 D1 ADC data to YUV output; dependent on mode settings VIPB 1 D1

Output enable horizontal/vertical sync (OEHV)

HS, HREF, VREF and VS high-impedance inputs OEHV 0 D2 Outputs HS, HREF, VREF and VS active OEHV 1 D2

Output enable YUV data (OEYC)

VPO-bus high-impedance inputs OEYC 0 D3 Output VPO-bus active OEYC 1 D3

Inverse composite blank (COMPO)

VREF is vertical reference COMPO 0 D4 VREF is inverse composite blank COMPO 1 D4

FEI control (FECO)

FEI sampling at CREF = LOW (SAA7110 compatible); (see Fig.19)

FECO 0 D5

FEI sampling at CREF = HIGH FECO 1 D5

Compatibility to SAA7199 (CM99)

Default value CM99 0 D6 To be set if SAA7199 (digital encoder) is used for

re-encoding in conjunction with RTCO

CM99 1 D6

General purpose switch (GPSW)

Switches directly pin 64 GPSW GPSW 0 D7

GPSW 1 D7

Page 53

1998 May 15 53

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

17.2.17 SUBADDRESS 12

Table 32 Output control 2 SA 12, D7 to D6, D4 to D0

FUNCTION BIT NAME LOGIC LEVEL CONTROL BIT

Analog test select (AOSL)

AOUT connected to internal test point 1 AOSL1 0 D1

AOSL0 0 D0

AOUT connected to input AD1 AOSL1 0 D1

AOSL0 1 D0

AOUT connected to input AD2 AOSL1 1 D1

AOSL0 0 D0

AOUT connected to internal test point 2 AOSL1 1 D1

AOSL0 1 D0

Dithering (noise shaping) control (DIT)

Dithering off DIT 0 D2 Dithering on DIT 1 D2

RGB output format selection (RGB888)

RGB (5, 6 and 5) RGB888 0 D3 RGB (8, 8 and 8) RGB888 1 D3

Chrominance interpolation ﬁlter function (CBR)

Cubic interpolation (default) CBR 0 D4 Linear interpolation (lower bandwidth) CBR 1 D4

3-state control VPO7 to VPO0 (TCLO)

VPO7 to VPO0 depends on OEYC,

FEI only (default)

(see Figs 18, 19 and 22)

TCLO 0 D5

VPO7 to VPO0 in 3-state [and OFTS (1 : 0) = 3] (see Tables 3 and 6)

TCLO 1 D5

Real time outputs mode select (RTSE0)

ODD switched to output pin 40 RTSE0 0 D6 VL switched to output pin 40 RTSE0 1 D6

Real time outputs mode select (RTSE1)

PLIN switched to output pin 39 RTSE1 0 D7 HL switched to output pin 39 RTSE1 1 D7

Page 54

1998 May 15 54

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

17.2.18 SUBADDRESS 13

Table 33 Output control 3 SA 13

FUNCTION BIT NAME LOGIC LEVEL CONTROL BIT

Bypass control LOW for VPO7 to VPO0

No bypass BCLO1 0 D1

BCLO0 0 D0

Permanent bypass BCLO1 0 D1

BCLO0 1 D0

Bypass controlled by V_GATE BCLO1 1 D1

BCLO0 0 D0

Bypass controlled by delayed V_GATE BCLO1 1 D1

BCLO0 1 D0

Bypass control HIGH for VPO15 to VPO8

No bypass BCHI1 0 D3

BCHI0 0 D2

Permanent bypass BCHI1 0 D3

BCHI0 1 D2

Bypass controlled by V_GATE BCHI1 1 D3

BCHI0 0 D2

Bypass controlled by delayed V_GATE BCHI1 1 D3

BCHI0 1 D2

Clock Reference Output Control

CREF is independent of VREF CCTR1 0 D5

CCTR0 0 D4

CREF is LOW if VREF = 0 CCTR1 0 D5

CCTR0 1 D4

CREF is HIGH if VREF = 0 CCTR1 1 D5

CCTR0 0 D4

CREF always = 1 CCTR1 1 D5

CCTR0 1 D4

Vertical Reference Output Control (VREF)

Internal VREF VCTR1 0 D7

VCTR0 0 D6

VREF_CCIR VCTR1 0 D7

VCTR0 1 D6

Programmable V_GATE VCTR1 1 D7

VCTR0 0 D6

Delayed programmable V_GATE VCTR1 1 D7

VCTR0 1 D6

Page 55

1998 May 15 55

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

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17.2.19 S

UBADDRESS 15

Table 34 Start of decoded data on VPO-port SA 15; note 1

Notes

1. Start of decoded data on VPO-port (end of bypassed region; start of VREF if selected by VCTR1 and VCTR0; see Figs 8 and 10).

2. Line numbers in brackets refer to CCIR line counting.

FIELD

FRAME

LINE

(2)

COUNTING

DECIMA

L VALUE

MSB

(SA 17,

D0)

CONTROL BITS D7 to D0

VSTA8 VSTA7 VSTA6 VSTA5 VSTA4 VSTA3 VSTA2 VSTA1 VSTA0

50Hz1st1 312100111000

2nd 314

1st 2 0.... 000000000

2nd 315

1st 312 ....310 100110111

2nd 625

60Hz1st1(4)262100000110

2nd 264 (267)

1st 2 (5) 0.... 000000000

2nd 265 (268)

1st 262 (265) ....260 100000101

2nd 525 (3)

Page 56

1998 May 15 56

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

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17.2.20 S

UBADDRESS 16

ABLE 35STOP OF DECODED DATA ON VPO-PORT SA16;NOTE 1

NOTES

1. STOP OF DECODED DATA ON VPO-PORT (BEGIN OF BYPASSED REGION; STOP OF VREF IF SELECTED BY VCTR1 AND VCTR0; SEE FIGS 8 AND 10).

2. LINE NUMBERS IN BRACKETS REFER TO CCIR LINE COUNTING.

17.2.21 S

UBADDRESS 17

Table 36 Sign bits of the VBI-data stream control

FIELD

FRAME

LINE

(2)

COUNTING

DECIMAL

VALUE

MSB

(SA 17, D0)

CONTROL BITS D7 to D0

VSTO8 VSTO7 VSTO6 VSTO5 VSTO4 VSTO3 VSTO2 VSTO1 VSTO0

50Hz1st1 3121 00111000

2nd 314

1st 2 0.... 0 00000000

2nd 315

1st 312 ....310 1 00110111

2nd 625

60Hz1st1(4)2621 00000110

2nd 264 (267)

1st 2 (5) 0.... 0 00000000

2nd 265 (268)

1st 262 (265) ....260 1 00000101

2nd 525 (3)

FUNCTION BIT NAME LOGIC LEVEL CONTROL BIT

VBI-data stream start (VSTA8); see SA 15

Sign bit VBI-data stream start VSTA8 see Table34 D0

VBI-data stream stop (VSTO8); see SA 16

Sign bit VBI-data stream stop VSTO8 seeTable 35 D1

Page 57

1998 May 15 57

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

17.2.22 SUBADDRESS 1A (READ-ONLY REGISTER) Table 37 Line-21 text slicer status SA 1A, D3 to D0

17.2.23 S

UBADDRESS 1B (READ-ONLY REGISTER)

Table 38 First decoded data byte of the text slicer SA 1B

17.2.24 SUBADDRESS 1C (READ-ONLY REGISTER) Table 39 Second decoded data byte of the text slicer SA 1C

17.2.25 S

UBADDRESS 1F (READ-ONLY REGISTER)

Table 40 Status byte SA 1F

C-BUS

STATUS BIT

NAME

FUNCTION STATUS BIT

F1RDY new data on ﬁeld 1 has been acquired (for asynchronous reading); active HIGH D0

F1VAL line-21 of ﬁeld 1 carries valid data; active HIGH D1

F2RDY new data on ﬁeld 2 has been acquired (for asynchronous reading); active HIGH D2

F2VAL line-21 of ﬁeld 2 carries valid data; active HIGH D3

C-BUS

TEXT DATA

BITS

FUNCTION DATA BITS

BYTE1 (6 to 0) data bit 6 to 0 of ﬁrst data byte D6 to D0

P1 parity error ﬂag bit; bit goes HIGH when a parity error has occurred D7

C-BUS

TEXT DATA

BITS

FUNCTION DATA BITS

BYTE2 (6 to 0) data bit 6 to 0 of second data byte D6 to D0

P2 parity error ﬂag bit; bit goes HIGH when a parity error has occurred D7

I2C-BUS

STATUS BIT

NAME

FUNCTION STATUS BIT

CODE colour signal in accordance with selected standard has been detected; active

HIGH

SLTCA slow time constant active in WIPA-mode; active HIGH D1

WIPA white peak loop is activated; active HIGH D2 GLIMB gain value for active luminance channel is limited [min (bottom)]; active HIGH D3 GLIMT gain value for active luminance channel is limited [max (top)]; active HIGH D4

FIDT identiﬁcation bit for detected ﬁeld frequency; LOW = 50 Hz, HIGH = 60 Hz D5

HLCK status bit for locked horizontal frequency; LOW = locked, HIGH = unlocked D6

STTC status bit for horizontal phase loop; LOW = TV time-constant,

HIGH = VTR time-constant

Page 58

1998 May 15 58

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

18 FILTER CURVES

18.1 Anti-alias ﬁlter curve

18.2 TUF-block ﬁlter curve

Fig.41 Anti-alias filter.

handbook, full pagewidth

(dB)

−42 024 68101214

f (MHz)

MGD138

−6

−12

−18

−24

−30

−36

Fig.42 Interpolation filter for the upsampled CVBS-signal.

handbook, full pagewidth

(dB)

−42

−48

−54

024 68101214

f (MHz)

MGG067

−6

−12

−18

−24

−30

−36

Page 59

1998 May 15 59

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

18.3 Luminance ﬁlter curves

handbook, full pagewidth

Y (MHz)

−30 024 86

MGD139

(dB)

−18

−6

(1) (2) (4) (3)

Fig.43 Luminance control SA 09H, 4.43 MHz Trap/CVBS mode, prefilter on, different aperture bandpass centre

frequencies.

(1) = 43H; (2) = 53H; (3) = 63H; (4) = 73H.

Fig.44 Luminance control SA 09H, 4.43 MHz Trap/CVBS mode, prefilter on, different aperture factors.

(1) = 40H; (2) = 41H; (3) = 42H; (4) = 43H.

handbook, full pagewidth

Y (MHz)

−30 024 86

MGD140

−18

−6

(1) (2) (3) (4)

(4) (3) (2) (1)

(dB)

Page 60

1998 May 15 60

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

Fig.45 Luminance control SA 09H, 4.43 MHz Trap/CVBS mode, prefilter off, different aperture band-pass centre

frequencies.

(1) = 03H; (2) = 13H; (3) = 23H; (4) = 33H.

handbook, full pagewidth

Y (MHz)

−30 024 86

MGD141

−18

−6

(1) (2) (4) (3)

(dB)

Fig.46 Luminance control SA 09H, Y/C mode, prefilter on, different aperture factors.

(1) = C0H; (2) = C1H; (3) = C2H; (4) = C3H.

handbook, full pagewidth

Y (MHz)

−30 024 86

MGD142

−18

−6

(1) (2) (3) (4)

(dB)

Page 61

1998 May 15 61

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

Fig.47 Luminance control SA 09H, Y/C mode, prefilter off, different aperture factors.

(1) = 80H; (2) = 81H; (3) = 82H; (4) = 83H.

handbook, full pagewidth

Y (MHz)

−30 024 86

MGD143

−18

−6

(1) (2) (3) (4)

(dB)

Fig.48 Luminance control SA 09H, 3.58 MHz Trap/CVBS mode, prefilter on, different aperture band-pass centre

frequencies.

(1) = 43H; (2) = 53H; (3) = 63H; (4) = 73H.

handbook, full pagewidth

Y (MHz)

−30 024 86

MGD144

−18

−6

(1) (2) (4) (3)

(dB)

Page 62

1998 May 15 62

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

Fig.49 Luminance control SA 09H, 3.58 MHz Trap/CVBS mode, prefilter on, different aperture factors.

(1) = 40H; (2) = 41H; (3) = 42H; (4) = 43H.

handbook, full pagewidth

Y (MHz)

−30 024 86

MGD145

−18

−6

(1) (2) (3) (4)

(4) (3) (2) (1)

(dB)

Fig.50 Luminance control SA 09H, 3.58 MHz Trap/CVBS mode, prefilter off, different aperture band-pass centre

frequencies.

(1) = 03H; (2) = 13H; (3) = 23H; (4) = 33H.

handbook, full pagewidth

Y (MHz)

−30 024 86

MGD146

−18

−6

(1) (2) (4) (3)

(dB)

Page 63

1998 May 15 63

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

18.4 Chrominance ﬁlter curves

19 I

C-BUS START SET-UP

• The given values force the following behaviour of the SAA7111A: – The analog input AI11 expects a signal in CVBS format; analog anti-alias filter active – Automatic field detection – YUV 4:2:2 16-bit output format enabled – Outputs HS, HREF, VREF and VS active – Contrast, brightness and saturation control in accordance with CCIR standards – Chrominance processing with nominal bandwidth (800 kHz).

Fig.51 Chrominance filter.

(1) Transfer characteristics of the chrominance low-pass dependent on CHBW[1 : 0] settings. CHBW [1 : 0] = 00; (2) CHBW [1 : 0] = 01; (3)

CHBW [1 : 0] = 10; (4) CHBW [1 : 0] = 11.

handbook, full pagewidth

2.7

−6

−12

−18

−24

−30

−36

−42

−48

−54

0 0.54 1.08 1.62 2,16

MGD147

(MHz)

(dB)

(1) (2) (3) (4)

(4) (1) (3) (2)

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Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

Table 41 I2C-bus start set-up values

Note

1. All X values must be set to LOW.

SUB

(HEX)

FUNCTION NAME

(1)

VALUES (BIN) (HEX)

76543210START

00 chip version ID07 to ID00; see Table 9 read only 01 reserved 0 0 0 0 0 0 0 0 00 02 analog input control 1 FUSE1 and FUSE0, GUDL2 to GUDL0,

MODE2 to MODE0

11000000 C0

03 analog input control 2 X, HLNRS, VBSL, WPOFF, HOLDG,

GAFIX, GAI28 and GAI18

00100011 33

04 analog input control 3 GAI17 to GAI10 0 0 0 0 0 0 0 0 00 05 analog input control 4 GAI27 to GAI20 0 0 0 0 0 0 0 0 00 06 horizontal sync start HSB7 to HSB0 1 1 1 0 1 0 1 1 EB 07 horizontal sync stop HSS7 to HSS0 1 1 1 0 0 0 0 0 E0 08 sync control AUFD, FSEL, EXFIL, X, VTRC, HPLL,

VNOI1 and VNOI0

10001000 88

09 luminance control BYPS, PREF , BPSS1 and BPSS0, VBLB,

UPTCV, APER1 and APER0

00000001 01

0A luminance brightness BRIG7 to BRIG0 1 0 0 0 0 0 0 0 80 0B luminance contrast CONT7 to CONT0 0 1 0 0 0 1 1 1 47 0C chrominance saturation SATN7 to SATN0 0 1 0 0 0 0 0 0 40 0D chroma hue control HUEC7 to HUEC0 0 0 0 0 0 0 0 0 00 0E chrominance control CDTO, CSTD2 to CSTD0, DCCF, FCTC,

CHBW1 and CHBW0

00000001 01

0F reserved 0 0 0 0 0 0 0 0 00

10 format/delay control OFTS1 and OFTS0, HDEL1 and HDEL0,

VRLN, YDEL2 to YDEL0

01000000 40

11 output control 1 GPSW, CM99, FECO, COMPO, OEYC,

OEHV, VIPB, and COLO

00011100 1C

12 output control 2 RTSE1 and RTSE0, TCLO, CBR,

RGB888 DIT, AOSL1 and AOSL0

00000001 00

13 output control 3 CCTR1 and CCTR0, BCHI1 and BCHI0,

BCLO1 and BCLO0, VCTR1 and VCTR0

00000000 00

14 reserved 0 0 0 0 0 0 0 0 00 15 VBI-data stream start VSTA7 to VSTA0 0 0 0 0 0 0 0 0 00 16 VBI-data stream stop VSTO7 to VSTO0 0 0 0 0 0 0 0 0 00 17 MSBs for VBI control X, X, X, X, X, X, VSTO8, and VSTA8 0 0 0 0 0 0 0 0 00

18-19 reserved 0 0 0 0 0 0 0 0 00

1A text slicer status 0, 0, 0, 0, F2VAL, F2RDY,

F1VAL, and F1RDY

read only register

1B decoded bytes of the

text slicer

P1, BYTE1 (6 to 0)

1C P2, BYTE2 (6 to 0)

1D-1E reserved 0 0 0 0 0 0 0 0 00

1F status byte STTC, HLCK, FIDT, GLIMT, GLIMB,

WIPA, SLTCA and CODE

read only register

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Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

20 PACKAGE OUTLINES

UNIT

max.

A1A2A3b

(1)

Zywv θ

REFERENCES

OUTLINE VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

1.60

0.20

0.05

1.45

1.35

0.25

0.27

0.17

0.18

0.12

10.1

9.9

0.5

12.15

11.85

1.45

1.05

7 0

o o

0.12 0.11.0 0.2

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.75

0.45

SOT314-2

95-12-19 97-08-01

(1) (1)(1)

10.1

9.9

12.15

11.85

1.45

1.05

detail X

(A )

v M

48 33

pin 1 index

w M

0 2.5 5 mm

scale

LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm

SOT314-2

Page 66

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Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

UNIT A1A2A3b

(1)

Zywv θ

REFERENCES

OUTLINE VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

0.25

0.10

2.75

2.55

0.25

0.45

0.30

0.23

0.13

14.1

13.9

0.8

17.45

16.95

1.2

0.8

7 0

0.16 0.100.161.60

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

1.03

0.73

SOT393-1 MS-022

96-05-21 97-08-04

(1) (1)(1)

14.1

13.9

17.45

16.95

1.2

0.8

detail X

(A )

v M

48 33

v M

w M

0 5 10 mm

scale

pin 1 index

QFP64: plastic quad flat package; 64 leads (lead length 1.6 mm); body 14 x 14 x 2.7 mm

SOT393-1

max.

3.00

Page 67

1998 May 15 67

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

21 SOLDERING

21.1 Introduction

There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used.

This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our

“IC Package Databook”

(order code 9398 652 90011).

21.2 Reﬂow soldering

Reflow soldering techniques are suitable for all LQFP and QFP packages.

The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our

“Quality

Reference Handbook”

(order code 9397 750 00192).

Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 50 and 300 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 °C.

21.3 Wave soldering

Wave soldering is not recommended for LQFP and QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices.

CAUTION

Wave soldering is NOT applicable for all LQFP and QFP packages with a pitch (e) equal or less than

0.5 mm.

If wave soldering cannot be avoided, for LQFP and QFP packages with a pitch (e) larger than 0.5 mm, the following conditions must be observed:

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave) soldering technique should be used.

• The footprint must be at an angle of 45° to the board

direction and must incorporate solder thieves downstream and at the side corners.

During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured.

Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.

21.4 Repairing soldered joints

Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C.

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Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

22 DEFINITIONS

23 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.

24 PURCHASE OF PHILIPS I

C COMPONENTS

Data sheet status

Objective speciﬁcation This data sheet contains target or goal speciﬁcations for product development. Preliminary speciﬁcation This data sheet contains preliminary data; supplementary data may be published later. Product speciﬁcation This data sheet contains ﬁnal product speciﬁcations.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the speciﬁcation is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the speciﬁcation.

Purchase of Philips I

C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.

Page 69

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Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

NOTES

Page 70

1998 May 15 70

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

NOTES

Page 71

1998 May 15 71

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

NOTES

Page 72

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Printed in The Netherlands 655102/1200/04/pp72 Date of release: 1998May 15 Document order number: 9397 750 03118

Datasheet SAA7111AHZ-01, SAA7111AHZ-02, SAA7111AHZ-03, SAA7111AH-01, SAA7111AH-03 Datasheet (Philips)

Specifications and Main Features

Frequently Asked Questions

User Manual