Datasheet SAA7111 Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

SAA7111

Video Input Processor (VIP)

Preliminary specification
Supersedes data of 1996 May 15
File under Integrated Circuits, IC22

1996 Oct 30

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

CONTENTS

1 FEATURES
2 APPLICATIONS
3 GENERAL DESCRIPTION
4 QUICK REFERENCE DATA
5 ORDERING INFORMATION
6 BLOCK DIAGRAM
7 PINNING
8 FUNCTIONAL DESCRIPTION

8.1 Analog input processing

8.2 Analog control circuits

8.2.1 Clamping

8.2.2 Gain control

8.3 Chrominance processing

8.4 Luminance processing

8.5 RGB matrix

8.6 VPO-bus (digital outputs)

8.7 Synchronization

8.8 Clock generation circuit

8.9 Power-on reset and CE input

8.10 RTCO output

8.11 The Line-21 text slicer

8.11.1 Suggestions for I2C-bus interface of the display
software reading line-21 data

9 GAIN CHARTS
10 LIMITING VALUES
11 CHARACTERISTICS
12 TIMING DIAGRAMS
13 CLOCK SYSTEM

13.1 Clock generation circuit

13.2 Power-on control

14 OUTPUT FORMATS
15 APPLICATION EXAMPLES
16 I2C-BUS DESCRIPTION

16.1 I2C-bus format

16.2 I2C-bus detail

16.2.1 Subaddress 00

16.2.2 Subaddress 02

16.2.3 Subaddress 03

16.2.4 Subaddress 04

16.2.5 Subaddress 05

16.2.6 Subaddress 06

16.2.7 Subaddress 07

16.2.8 Subaddress 08

16.2.9 Subaddress 09

16.2.10 Subaddress 0A

16.2.11 Subaddress 0B

16.2.12 Subaddress 0C

16.2.13 Subaddress 0D

16.2.14 Subaddress 0E

16.2.15 Subaddress 10

16.2.16 Subaddress 11

16.2.17 Subaddress 12

16.2.18 Subaddress 1A (read-only register)

16.2.19 Subaddress 1B (read-only register)

16.2.20 Subaddress 1C (read-only register)

16.2.21 Subaddress 1F (read-only register)
17 FILTER CURVES

17.1 Anti-alias filter curve

17.2 Luminance filter curves

17.3 Chrominance filter curves
18 I2C START SET-UP
19 PACKAGE OUTLINE
20 SOLDERING

20.1 Introduction

20.2 Reflow soldering

20.3 Wave soldering

20.3.1 PLCC

20.3.2 QFP

20.3.3 Method (PLCC and QFP)

20.4 Repairing soldered joints
21 DEFINITIONS
22 LIFE SUPPORT APPLICATIONS
23 PURCHASE OF PHILIPS I2C COMPONENTS

1996 Oct 30 2

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

1 FEATURES

• Four analog inputs, internal analog source selectors,

e.g. 4 × CVBS or 2 × Y/C or (1 × Y/C and 2 × CVBS)

• Two analog preprocessing channels

• Fully programmable static gain for the main channels or

automatic gain control for the selected CVBS or Y/C
channel

• Switchable white peak control

• Two built-in analog anti-aliasing filters

• Two 8-bit video CMOS analog-to-digital converters

(ADCs)

• On-chip clock generator

• Line-locked system clock frequencies

• Digital PLL for H-sync processing and clock generation

• Requires only one crystal (24.576 MHz) for all standards

• Horizontal and vertical sync detection

• Automatic detection of 50/60 Hz field frequency, and

automatic switching between standards PAL and NTSC

• Luminance and chrominance signal processing for

PAL BGHI, PAL N, PAL M, NTSC M, NTSC N and
NTSC 4.43

• User programmable luminance peaking or aperture

correction

• Cross-colour reduction for NTSC by chrominance comb

filtering

• PAL delay line for correcting PAL phase errors

• Real time status information output (RTCO)

• Brightness Contrast Saturation (BCS) control on-chip

• The YUV (CCIR-601) bus supports a data rate of:

– 864 × f

= 13.5 MHz for 625 line sources

H

– 858 × fH= 13.5 MHz for 525 line sources

• Data output streams for 16, 12 or 8-bit width with the

following formats:
– 411 YUV (12-bit)
– 422 YUV (16-bit)
– 422 YUV [CCIR-656] (8-bit)
– 565 RGB (16-bit) with dither
– 888 RGB (24-bit) with special application

• 720 active samples per line on the YUV bus

• One user programmable general purpose switch on an

output pin

• Built in line-21 text slicer

• Power-on control

• Two switchable outputs for the digitized CVBS or Y/C

input signals AD1 (7 to 0) and AD2 (7 to 0) via the

2

I

C-bus

• Chip enable function (reset for the clock generator)

• Compatible with memory-based features (line-locked

clock)

• Boundary scan test circuit complies with the

“IEEE Std. 1149.1−1990”

(ID-Code = 0 7111 02 B)

• I2C-bus controlled (full read-back ability by an external
controller).

2 APPLICATIONS

• Desktop video

• Multimedia

• Digital television

• Image processing

• Video phone.

3 GENERAL DESCRIPTION

The Video Input Processor (VIP) is a combination of a
two-channel analog preprocessing circuit including source
selection, anti-aliasing filter and ADC, an automatic clamp
and gain control, a Clock Generation Circuit (CGC), a
digital multi-standard decoder (PAL BGHI, PAL M, PAL N,
NTSC M and NTSC N), a brightness/contrast/saturation
control circuit and a colour space matrix (see Fig.1).

The CMOS circuit SAA7111, analog front-end and digital
video decoder, is a highly integrated circuit for desktop
video applications. The decoder is based on the principle
of line-locked clock decoding and is able to decode the
colour of PAL and NTSC signals into CCIR-601
compatible colour component values. The SAA7111
accepts as analog inputs CVBS or S-video (Y/C) from

2

TV or VTR sources. The circuit is I

C-bus controlled.

1996 Oct 30 3

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

4 QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V

DDD

V

DDA

T

amb

P

A+D

5 ORDERING INFORMATION

digital supply voltage 4.5 5.0 5.5 V
analog supply voltage 4.75 5.0 5.25 V
operating ambient temperature 0 25 70 °C
analog and digital power 0.77 1.0 1.26 W

TYPE NUMBER

PACKAGE

NAME DESCRIPTION VERSION

SAA7111 PLCC68 plastic leaded chip carrier; 68 leads SOT188-2
SAA7111 QFP64 plastic quad flat package; 64 leads (lead length 1.6 mm);

SOT393-1

body 14 × 14 × 2.7 mm

1996 Oct 30 4

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

6 BLOCK DIAGRAM

handbook, full pagewidth

BYPASS

AI11
AI12

AI21
AI22

n.c.

V

SS

n.c.

TDI

TCK

TMS

TDO

23 (14)

21 (12)
19 (10)

17 (8)
15 (6)

7,8,9 (64)
22 (13)

10,36,
37

18,14 (9,5)
20,16 (11,7)

12 (3)
2 (59)
13 (4)
1 (58)

11 (2)

ANALOG

PROCESSING

AND

ANALOG-TO-

DIGITAL

CONVERSION



AD2 AD1

ANALOG

PROCESSING

CONTROL

TEST

CONTROL

BLOCK

FOR
BOUNDARY
SCAN TEST

AND
SCAN TEST

CON

C/CVBS

Y/CVBS

Y

SYNCHRONIZATION

CHROMINANCE

CIRCUIT

AND

BRIGHTNESS

CONTRAST

SATURATION

CONTROL

LUMINANCE

CIRCUIT

SAA7111

CIRCUIT

Y

UV

LFCO

45 to 50

YUV-to-RGB

CONVERSION

AND

OUTPUT

FORMATTER

Y

2

I C-BUS

CONTROL

2

I C-BUS

INTERFACE

CLOCKS

CLOCK

GENERATION

CIRCUIT

POWER-ON

CONTROL

53 to 62

(34 to 39)
(42 to 51)

(52) 63
(31) 42

(53) 64

(61) 4
(62) 5
(63) 6

(54) 65
(55) 66

(21) 30
(22) 31
(20) 29

(23) 32

VPO
(0 : 15)

FEI
HREF

GPSW

IICSA
SDA
SCL

XTAL
XTALI

LLC2
CREF
LLC
RES

AOUT

V

SSA1-2

V

DDA1-2

TRST

(57,41,33,25,18)
68,52,44,34,27

V

DD1-5

The pin numbers given in parenthesis refer to the 64-pin package.

(56,40,32,26,19)
67,51,43,35,28

V

SS1-5

(30)41(27)38(17)26(29)40(28)39(60)

HSVS

VREF

Fig.1 Block diagram.

1996 Oct 30 5

RTS0

RTS1

RTCO

3

(15)24(16)25(24)

DDA0

V

SSA0

V

33

MGC653

CE

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

7 PINNING

SYMBOL

I/O DESCRIPTION

PLCC68 QFP64

TRST 1 58 I Test reset input not (active LOW), for boundary scan test;

notes 1, 2, 3 and 4.
TCK 2 59 I Test clock input for boundary scan test; note 3>
RTCO 3 60 O Real time control output: contains information about actual system

clock frequency, subcarrier frequency and phase and PAL sequence>

PINS

2

IICSA 4 61 I I

C-bus slave address select input; 0 = > 48h for write, 49h for read,

1 = > 4Ah for write, 4Bh for read.

2

SDA 5 62 I/O I
SCL 6 63 I/O I

C-bus serial data input/output.

2

C-bus serial clock input/output.
n.c. 7 64 − Not connected.
n.c. 8 −−Not connected.
n.c. 9 −−Not connected.
n.c. 10 1 − Not connected.
TDO 11 2 O Test data output for boundary scan test; note 3.
TDI 12 3 I Test data input for boundary scan test; note 3.
TMS 13 4 I Test mode select input for boundary scan test or scan test; note 3.
V

SSA2

14 5 GND Ground for analog supply voltage channel 2.
AI22 15 6 I Analog input 22.
V

DDA2

16 7 P Positive supply voltage (+5 V) for analog channel 2.
AI21 17 8 I Analog input 21.
V

SSA1

18 9 GND Ground for analog supply voltage channel 1.
AI12 19 10 I Analog input 12.
V

DDA1

20 11 P Positive supply voltage (+5 V) for analog channel 1.
AI11 21 12 I Analog input 11.
V

SSS

22 13 GND Substrate (connected to analog ground).
AOUT 23 14 O Analog test output; for testing the analog input channels.
V

DDA0

V

SSA0

VREF 26 17 O Vertical reference output signal (I

24 15 P Positive supply voltage (+5 V) for internal CGC.

25 16 GND Ground for internal CGC.

2

C-bit COMPO = 0) or inverse
composite blank signal (I2C-bit COMPO = 1) (enabled via I2C-bit
OEHV).

V
V

DD5
SS5

27 18 P Positive digital supply voltage 5 (+5 V).
28 19 GND Digital ground for positive supply voltage 5.

LLC 29 20 O Line-locked system clock output (27 MHz).

1

LLC2 30 21 O Line-locked clock

⁄2output (13.5 MHz).

CREF 31 22 O Clock reference output: this is a clock qualifier signal distributed by

the CGC for a data rate of LLC2. Using CREF all interfaces on the
VPO-bus are able to generate a bus timing with identical phase. If
CCIR-656 format is selected (OFTS0 = 1 and OFTS1 = 1) an inverse
composite blank signal (pixel qualifier) is provided on this pin.

1996 Oct 30 6

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

SYMBOL

I/O DESCRIPTION

PLCC68 QFP64

RES 32 23 O Reset output (active LOW); sets the device into a defined state. All

data outputs are in high impedance state. The I2C-bus is reset
(waiting for start condition) note 4.

CE 33 24 I Chip enable; connection to ground forces a reset.

PINS

V
V

DD4
SS4

34 25 P Positive digital supply voltage 4 (+5 V).

35 26 GND Digital ground for positive supply voltage 4.
n.c. 36 −−Not connected.
n.c. 37 −−Not connected.
HS 38 27 O Horizontal sync output signal (programmable); the positions of the

positive and negative slopes are programmable in 8 LLC increments

2

over a complete line (= 64 µs) via I

C-bus bytes HSB and HSS. Fine
position adjustment in 2 LLC increments can be performed via
I2C-bits HDEL1 and HDEL0.

2

RTS1 39 28 O Two functions output; controlled by I

C-bit RTSE1.
RTSE1 = 0: PAL line identifier (LOW = PAL line); indicates the
inverted and non-inverted R − Y component for PAL signals.
RTSE1 = 1: H-PLL locked indicator; a high state indicates that the
internal horizontal PLL has locked.

2

RTS0 40 29 O Two functions output; controlled by I

C-bit RTSE0.
RTSE0 = 0: odd/even field identification (HIGH = odd field).
RTSE0 = 1: vertical locked indicator; a HIGH state indicates that the
internal VNL has locked.

2

VS 41 30 O Vertical sync output signal (enabled via I

C-bit OEHV); this signal
indicates the vertical sync with respect to the YUV output. The HIGH
period of this signal is approximately six lines if the vertical noise
limiter (VNL) function is active. The positive slope contains the phase
information for a deflection controller.

2

HREF 42 31 O Horizontal reference output signal (enabled via I

C-bit OEHV); this
signal is used to indicate data on the digital YUV bus. The positive
slope marks the beginning of a new active line. The HIGH period of
HREF is 720 Y samples long. HREF can be used to synchronize data
multiplexer/demultiplexers. HREF is also present during the vertical
blanking interval.

V
V

SS3
DD3

43 32 GND Digital ground for positive supply voltage 3.
44 33 P Positive digital supply voltage 3 (+5 V).

VPO (15 to 10) 45 to 50 34 to 39 O Digital VPO-bus (Video Port Out) output signal; higher bits of the

16-bit YUV-bus or the 16-bit RGB-bus output signal. The output data
rate, the format and multiplexing scheme of the VPO-bus are

2

controlled via I

C-bits OFTS0 and OFTS1. With I2C-bit VIPB = 1 the
six MSBs of the digitized input signal (AD1 [7 to 2]) are connected to
these outputs.

V
V

SS2
DD2

51 40 GND Digital ground for positive supply voltage 2.
52 41 P Positive digital supply voltage 2 (+5 V).

1996 Oct 30 7

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

SYMBOL

I/O DESCRIPTION

PLCC68 QFP64

VPO (9 to 0) 53 to 62 42 to 51 O Digital VPO-bus output signal; lower bits of the 16-bit YUV-bus or the

16-bit RGB-bus output signal. The output data rate, the format and
multiplexing schema of the VPO-bus are controlled via I2C-bits
OFTS0 and OFTS1. With I2C-bit VIPB = 1 the digitized input signals
(AD1 [1 and 0] and AD2 [7 to 0]) are connected to these outputs.

FEI 63 52 I Fast enable input signal (active LOW); this signal is used to control

fast switching on the digital YUV-bus. A HIGH at this input forces the
IC to set its Y and UV outputs to the high impedance state; note 4.

GPSW 64 53 O General purpose switch output; the state of this signal is set via

PINS

2

C-bus control and the levels are TTL compatible.

I

XTAL 65 54 O Second output terminal of crystal oscillator; not connected if external

clock signal is used.

XTALI 66 55 I Input terminal for 24.576 MHz crystal oscillator or connection of

external oscillator with CMOS compatible square wave clock signal.

V
V

SS1
DD1

67 56 GND Digital ground for positive supply voltage 1.
68 57 P Positive digital supply voltage 1 (+5 V).

Notes

1. For board design without boundary scan implementation (pin compatibility with the SAA7110) connect theTRST pin
to ground.

2. This pin provides easy initialization of BST circuit. TRST can be used to force the TAP (Test Access Port) controller
to the Test-Logic-Reset state (normal operation) at once.

3. In accordance with the

“IEEE1149.1”

standard the pads TCK, TDI, TMS and TRST are input pads with an internal

pull-up transistor and TDO a 3-state output pad.

4. All pin names that carry an ‘overscore’ have been renamed due to Philips pin name conventions. In previous data
sheet versions these pins were marked by the suffix ‘N’, e.g. TRST = TRSTN.

1996 Oct 30 8

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

DD1VSS1

handbook, full pagewidth

n.c.
9

n.c.

8

n.c.
7

SCL
6

SDA
5

IICSA
4

RTCO
3

TCK
2

TRST
1

V



68

67

66 XTALI

XTAL
65

GPSW
64

FEI
63

VPO0
62

VPO1

61

V

SSA2

V

DDA2

V

SSA1

V

DDA1

AOUT

V

DDA0

V

SSA0

VREF

n.c.

TDO

TDI

TMS

AI22

AI21

AI12

AI11

V

SS

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

SAA7111

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44

VPO3
VPO3
VPO4
VPO5
VPO6
VPO7
VPO8
VPO9

V

DD2

V

SS2

VPO10
VPO11
VPO12
VPO13
VPO14
VPO15

V

DD3

27

28

29LLC

30

31

32

33

34

V

DD5

V

SS5

LLC2

CREF

RES

CE

V

DD4

Fig.2 Pin configuration (PLCC68).

1996 Oct 30 9

35

V

SS4

36
n.c.

37

n.c.

38
HS

39

RTS1

40

RTS0

41
VS

42

HREF

43

V

MGC636

SS3

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

handbook, full pagewidth

SS1

DD1

TRST

V

58

57

SAA7111

23

24
CE

RES

V

56

25

DD4

V

XTALI
55

26

SS4

V

XTAL
54

27
HS

GPSW
53

28

RTS1

FEI

52

29

RTS0

VPO0

51

30
VS

VPO1
50

31

HREF

VPO2
49

32

MBH226

SS3

V

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

VPO3
VPO4
VPO5

VPO6
VPO7
VPO8
VPO9
V

DD2

V

SS2

VPO10
VPO11
VPO12
VPO13
VPO14
VPO15

V

DD3

V

SSA2

V

DDA2

V

SSA1

V

DDA1

AOUT

V

DDA0

V

SSA0

n.c.

TDO

TDI

TMS

AI22

AI21

AI12

AI11

V

SS

RTCO
60

21

LLC2

TCK
59

22

CREF

IICSA

SDA

SCL

n.c.
64

63

62

61
1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16

17

18

19

20

LLC

SS5

DD5

V

V

VREF

Fig.3 Pin configuration (QFP64).

1996 Oct 30 10

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

8 FUNCTIONAL DESCRIPTION

8.1 Analog input processing

The SAA7111 offers four analog signal inputs, two analog
main channels with clamp circuit, analog amplifier,
anti-alias filter and video CMOS ADC (see Fig.6).

8.2 Analog control circuits

The anti-alias filters are adapted to the line-locked clock
frequency with help from a filter control. During the vertical
blanking, time gain and clamping control are frozen.

8.2.1 C

LAMPING

The clamp control circuit controls the correct clamping of
the analog input signals. The coupling capacitor is also
used to store and filter the clamping voltage. An internal
digital clamp comparator generates the information with
respect to clamp-up or clamp-down. The clamping levels
for the two ADC channels are fixed for luminance (60) and
chrominance (128). Clamping time in normal use is set
with the HCL pulse at the back porch of the video signal.

control (AGC) as part of the Analog Input Control (AICO).
The AGC (automatic gain control for luminance) is used to
amplify a CVBS or Y signal to the required signal
amplitude, matched to the ADCs input voltage range.
The AGC active time is the sync bottom of the video signal.

handbook, halfpage

(1 V(p-p) 75 Ω)

analog input level

maximum

+4 dB

−6 dB

minimum

range 10 dB0 dB

controlled

ADC input level

0 dB

MGC660

Fig.5 Automatic gain range.

HSY

TV line

HCL

MGC661

handbook, halfpage

225

60

1

analog line blanking

GAIN CLAMP

Fig.4 Analog line with clamp (HCL) and gain

range (HSY).

8.2.2 G

AIN CONTROL

Signal (white) peak control limits the gain at signal
overshoots. The flow charts (see Figs 10 and 11) show
more details of the AGC. The influence of supply voltage
variation within the specified range is automatically
eliminated by clamp and automatic gain control.

The gain control circuit receives (via the I2C-bus) the static
gain levels for the two analog amplifiers or controls one of
these amplifiers automatically via a built-in automatic gain

8.3 Chrominance processing

The 8-bit chrominance signal is fed to the multiplication
inputs of a quadrature demodulator, where two subcarrier
signals from the local oscillator DTO1 are applied
(0 and 90° phase relationship to the demodulator axis).
The frequency is dependent on the present colour
standard. The output signals of the multipliers are
low-pass filtered (four programmable characteristics) to
achieve the desired bandwidth for the colour difference
signals.

The colour difference signals are fed to the
Brightness/Contrast/Saturation block (BCS), which
includes the following five functions;

1. AGC (automatic gain control for chrominance).

2. Chroma amplitude matching [different gain factors for
(R−Y) and (B−Y) to achieve CCIR-601 levels Cr
and Cb].

3. Chroma saturation control.

4. Luminance contrast and brightness.

5. Limiting YUV to the values 1 (min.) and 254 (max.) to
fulfil CCIR-601 requirements.

1996 Oct 30 11

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

The burst processing block provides the feedback loop of
the chroma PLL and contains;

Burst gate accumulator
Colour identification and killer
Comparison nominal/actual burst amplitude
Loop filter chroma gain control
Loop filter chroma PLL
PAL sequence generation
Increment generation for DTO1 with divider to generate

stable subcarrier for non-standard signals.

The chroma comb filter block eliminates crosstalk between
the chrominance channels in accordance with the PAL
standard requirements. For NTSC colour standards the
chroma comb filter can be used to eliminate crosstalk from
luminance to chrominance (cross-colour) for vertical
structures. The comb filter can be switched off if desired.

The resulting signals are fed to the variable Y-delay
compensation, RGB matrix, dithering circuit and output
interface, which contains the VPO output formatter and the
output control logic (see Fig.7).

8.4 Luminance processing

The 8-bit luminance signal, a digital CVBS format or a
luminance format (S-VHS, HI8), is fed through a
switchable prefilter. High frequency components are
emphasized to compensate for loss. The following
chrominance trap filter (f
frequency selectable) eliminates most of the colour carrier
signal, therefore, it must be bypassed for S-video
(S-VHS, HI8) signals.

The high frequency components of the luminance signal
can be peaked (control for sharpness improvement via
I2C-bus) in two band-pass filters with selectable transfer
characteristic. This signal is then added to the original
(unpeaked) signal. A switchable amplifier achieves
common DC amplification, because the DC gains are
different in both chrominance trap modes. The improved
luminance signal is fed to the BCS control located in the
chrominance processing block (see Fig.8).

= 4.43 or 3.58 MHz centre

0

8.5 RGB matrix

Y data and Cr, Cb data are converted after interpolation
into RGB data in accordance with CCIR-601
recommendation. The realized matrix equations consider
the digital quantization:

R = Y + 1.371 Cr
G=Y−0.336 Cb − 0.698 Cr
B = Y + 1.732 Cb

After dithering (noise shaping) the RGB data is fed to the
output interface within the VPO-bus output formatter.

8.6 VPO-bus (digital outputs)

The 16-bit VPO-bus transfers digital data from the output
interfaces to a feature box or a field memory, a digital
colour space converter (SAA7192 DCSC), a video
enhancement and digital-to-analog processor
(SAA7165 VEDA2) or a colour graphics board
(Targa-format) as a graphical user interface.

The output data formats are controlled via the I
OFTS0, OFTS1 and RGB888. Timing for the data stream
formats, 411 YUV (12-bit), 422 YUV (16-bit),
565 RGB (16-bit) and 888 RGB (24-bit) with an LLC2 data
rate, is achieved by marking each second positive rising
edge of the clock LLC in conjunction with CREF (clock
reference) (except RGB 888, see special application in
Fig.27). The higher output signals VPO15 to VPO8 in the
YUV format perform the digital luminance signal. The
lower output signals VPO7 to VPO0 in the YUV format are
the bits of the multiplexed colour difference signals (B−Y)
and (R−Y). The arrangement of the RGB 565 and
RGB 888 data stream bits on the VPO-bus is given in
Table 5.

The data stream format 422 YUV (the 8 higher output
signals VPO15 to VPO8) in LLC data rate fulfils the
CCIR-656 standard with its own timing reference code at
the start and end of each video data block.

A pixel in the format tables is the time required to transfer
a full set of samples. In the event of a 4 :2:2format two
luminance samples are transmitted in comparison to one
(B−Y) and one (R−Y) sample within a pixel. The time
frames are controlled by the HREF signal.

2

C-bus bits

1996 Oct 30 12

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

Fast enable is achieved by setting input FEI to LOW.
The signal is used to control fast switching on the digital
VPO-bus. HIGH on this pin forces the YUV outputs to a
high-impedance state (see Figs 15 and 17).

The digitized analog PAL or NTSC signals AD1 (7 to 0)
and AD2 (7 to 0) are connected directly to the VPO-bus
via I2C-bit VIPB = 1.

AD1 (7 to 0) -> VPO (15 to 8) and
AD2 (7 to 0) ->VPO (7 to 0)

The selection of the analog input channels are controlled
via I2C-bus subaddress 02 MODE select.

8.7 Synchronization

The prefiltered luminance signal is fed to the
synchronization stage. Its bandwidth is reduced to 1 MHz
in a low-pass filter. The sync pulses are sliced and fed to
the phase detectors where they are compared with the
sub-divided clock frequency. The resulting output signal is
applied to the loop filter to accumulate all phase
deviations. Internal signals (e. g. HCL and HSY) are
generated in accordance with analog front-end
requirements. The output signals HS, VS, and PLIN are
locked to the timing reference, guaranteed between the
input signal and the HREF signal, as further improvements
to the circuit may change the total processing delay. It is
therefore not recommended to use them for applications
which require absolute timing accuracy on the input
signals. The loop filter signal drives an oscillator to
generate the line frequency control signal LFCO
(see Fig.8).

8.8 Clock generation circuit

The internal CGC generates all clock signals required for
the video input processor. The internal signal LFCO is a
digital-to-analog converted signal provided by the
horizontal PLL. It is the multiple of the line frequency
(6.75 MHz = 432 × f

). Internally the LFCO signal is

h

multiplied by a factor of 2 or 4 in the PLL circuit (including
phase detector, loop filtering, VCO and frequency divider)
to obtain the LLC and LLC2 output clock signals.
The rectangular output clocks have a 50% duty factor
(see Fig.22).

8.9 Power-on reset and CE input

A missing clock, insufficient digital or analog V

DDA0

supply
voltages (below 3.5 V) will initiate the reset sequence; all
outputs are forced to 3-state. The indicator output RES is
LOW for approximately 128 LLC after the internal reset
and can be applied to reset other circuits of the digital TV
system.

It is possible to force a reset by pulling the CE
(chip enable) to ground. After the rising edge of CE and
sufficient power supply voltage, the outputs LLC, LLC2,
CREF, RTCO, RTS0, RTS1, GPSW and SDA return from
3-state to active, while HREF, VREF, HS and VS remain in

2

3-state and have to be activated via I

C-bus programming

(see Table 4).

8.10 RTCO output

The real time control and status output signal contains
serial information about the actual system clock
(increment of the HPLL), subcarrier frequency [increment
and phase (via reset) of the FSC-PLL] and PAL sequence
bit. The signal can be used for various applications in
external circuits, e.g. in a digital encoder to achieve clean
encoding (see Fig.16).

8.11 The Line-21 text slicer

The text slicer block detects and acquires Line-21 Closed
Captioning data from a 525-line CVBS signal. Extended
data services on Line-21 Field 2 are also supported.
If valid data is detected the two data bytes are stored in two

2

C-bus registers. A parity check is also performed and the

I
result is stored in the MSB of the corresponding byte. A
third I2C-bus register is provided for data valid and data
ready flags. The two bits F1VAL and F2VAL indicate that
the input signal carries valid Closed Captioning data on the
corresponding fields. The data ready bits F1RDY and
F2RDY have to be evaluated if asynchronous I2C-bus
reading is used.

8.11.1 S

UGGESTIONS FOR I

DISPLAY SOFTWARE READING LINE

2

C-BUS INTERFACE OF THE

-21 DATA

There are two methods by which the software can acquire
the data;

1. Synchronous reading once per frame (or once per
field): It can use either the rising edge (Line-21 Field 1)
or both edges (Line-21 Field 1 or 2) of the ODD signal
(pin RTSO) to initiate an I2C-bus read transfer of the
three registers 1A, 1B and 1C.

2. Asynchronous reading: It can poll either the F1RDY bit
(Line-21 Field 1) or both F1RDY/F2RDY bits (Line-21
Field 1 or 2). After valid data has been read the
corresponding F*RDY bit is set to LOW until new data
has arrived. The polling frequency has to be slightly
higher than the frame or field frequency, respectively.

1996 Oct 30 13

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

AOUT

(14) 23

AND

TEST

BUFFER

SELECTOR

ADC2

AOSL (1 : 0)

SWITCH

BYPASS

FILTER

ANTI-ALIAS

ANALOG

AMPLIFIER

DAC9

FUSE (1 : 0)

ANALOG

ADC1

SWITCH

BYPASS

FILTER

ANTI-ALIAS

DAC9

AMPLIFIER

VERTICAL

FUSE (1 : 0)

CONTROL

BLANKING

CONTROL

ANTI-ALIAS

GAIN

CONTROL

VBLNK

SVREF

VBSL 8 8

HOLDG

GAFIX

HSY

GLIMB

GLIMT

WPOFF

GAI20-GAI28

GAI10-GAI18

GUDL0-GUDL2

HLNRS

WIPA

SLTCA

AD1BYPAD2BYP

handbook, full pagewidth

CROSS MULTIPLEXER

UPTCV

Fig.6 Analog input processing.

987 (64)

n.c.

n.c.

n.c.

18 (9)

SSA1

V

14 (5)

SSA2

V

CLAMP

CIRCUIT

SWITCH

SOURCE

15 (6)

17 (8)

AI22

AI21

20 (11)

DDA1

V

16 (7)

DDA2

V

CLAMP

SOURCE

19 (10)

21 (12)

AI12

CIRCUIT

SWITCH

AI11

1996 Oct 30 14

CLAMP

CONTROL

MODE

CONTROL

HCL

MODE 0

MODE 1

MODE 2

ANALOG

CONTROL

22 (13)

SSS

V

CHRLUM

MGC655

The pin numbers given in parenthesis refer to the 64-pin package.

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

AD1BYPAD2BYP

FEI

(52) 63

(42 to 51),

AND

CONTRAST,

BRIGHTNESS,

LOW-PASS

VPO

(9 : 0)VPO

45 to 50

53 to 62

(34 to 39),

AND 

OUTPUT

INTERFACE

FORMATTER

RGB

dithering

interpolation

RGB MATRIX

Y





CONTROL

SATURATION

PHASE

DEMOD.

AMPLITUDE

(15 : 10)



(31) 42

COMB

DIT CBR

UV

GAIN

CONTROL



AND Y-DELAY

DETECTOR

BURST GATE

ACCUMULATOR

HREF

GPSW

RTSE1

OFTS0

OFTS1

FILTERS

DCCF

COMPENSATION

BRIG

CODE

LOOP FILTER

FCTCCSTD 1

CONT

RTSE0

VIPB

RGB888

OEYC

SATN

VLOF

COLO

OEHV

FECO

RTCO

(60) 3

COMPO

VRLN



MGC645

Y

handbook, full pagewidth

CHBW0

CHBW1

INCREMENT

SUBCARRIER

CHRLUM

QUADRATURE

10 (1)

n.c.

DEMODULATOR

TEST

CONTROL

1 (58)

2 (59)

12 (3)

TDI

TCK

TRST

BLOCK

13 (4)

TMS

SUBCARRIER

11 (2)

TDO

GENERATION

(57,41,33,

25,18)

V

1996 Oct 30 15

AND

DIVIDER

GENERATION

HUEC

CONTROL

POWER-ON

32 (23)

68,52,44,

34,27



RES

DD1-5

INCS

CSTD 0

CLOCKS
CE

(56,40,32,26,19)

67,51,43,35,28



SS1-5

V

Fig.7 Chrominance circuit.

LUM

The pin numbers given in parenthesis refer to the 64-pin package.

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

DDA0VSSA0

CREF

LLC

LLC2

CE

V

XTALI

XTAL

(22) 31

CLOCKS

(21)30

(20) 29

CLOCK

GENERATOR

LINE-LOCKED

(24)33

(16) 25

(15) 24

CLOCK

CIRCUIT

GENERATION

(54) 65

(55) 66

CLOCK

CRYSTAL

GENERATOR

MGC654

CLOCK CIRCUIT

DAC6

INCS

APER0

APER1

Y

AND

ADDING

STAGE

WEIGHTING

VBLB

MATCHING

AMPLIFIER

VBLB

PHASE

FINE

PHASE

DETECTOR

COARSE

DETECTOR

AUFD

HSB

HPLL

HSS

VTRC

VTRC

EXFIL

STTC

HLCK

FSEL

VTRC

TIME

DISCRETE

OSCILLATOR 2

2

LOOP FILTER

(28)

(27)

COUNTER

39

RTS1

38

HS

handbook, full pagewidth

BPSS0

BPSS1

FILTER

VARIABLE

BAND-PASS

PREF

SYNC SLICER

LUMINANCE CIRCUIT

TRAP

CHROMINANCE

LUM

PREFILTER

BYPS

VBLB

PREF

SYNC

PREFILTER

TEXT

LINE 21

1996 Oct 30 16

FIDT

VNOI0

VNOI1

VTRC

SYNCHRONIZATION CIRCUIT

BYTE1

SLICER

BYTE2

STATUS

2

I C BUS CONTROL

VERTICAL

PROCESSOR

2

I C-BUS

INTERFACE

64 (53)

GPSW

(17)
(29)

(30)

(62)

(63)

(61)

26

VREF

40

RTS0

41

VS

5

SDASCLIICSA

6

4

Fig.8 Luminance and sync processing.

The pin numbers given in parenthesis refer to the 64-pin package.

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

9 GAIN CHARTS

handbook, full pagewidth

handbook, halfpage

7.5

factor

dB

5.5

3.5

bit [8] = 1

1.5

−0.5

−2.5

−4.5

0

= 20 x log10 gain =

dB

i > 256

bit [8] = 0

= 20 x log10 gain =

factor

dB

256 512

gain value (i)

Fig.9 Amplifier curve.

ANALOG INPUT

(

512

768 − i

(

i < 256

(

MGC648

257 + i

512

(

ADC

NO BLANKING ACTIVE

10 10

10

CLL

+ CLAMP − CLAMP

WIPE = white peak level (254); SBOT = sync bottom level (1); CLL = clamp level [60 Y (128 C)];
HSY = horizontal sync pulse; HCL = horizontal clamp pulse.

10

VBLK

GAIN -><- CLAMP

HCL HSY

01 10

SBOT

NO CLAMP

+ GAIN − GAIN

Fig.10 Clamp and gain flow.

fast − GAIN

WIPE

slow + GAIN

MGC647

1996 Oct 30 17

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

handbook, full pagewidth

NO ACTION

0

1

ANTI-ALIAS FILTER

0

1

<4

0

>248

ANALOG INPUT

AMPLIFIER

ADC

1

VBLK

1

HOLDG

1

>254

X = 0

gain

8

0

0

1

X

1

1

<1

0

DAC

LUMA/CHROMA DECODER

0

0

HSY

1

>254

X = 1

9

0

+1/F

STOP

X = system variable; Y = AGV − FGVI > GUDL; VBLK = vertical blanking pulse;
HSY = horizontal sync pulse; AGV = actual gain value; FGV = frozen gain value.

−

1/LLC2

+1/L

GAIN ACCUMULATOR (18 BITS)

ACTUAL GAIN VALUE 9-BIT (AGV) [−6/+6 dB]

1

AGV

Fig.11 Gain flow chart.

+1/LLC2 −1/LLC2

0

X

1

HSY

1

UPDATE

GAIN VALUE 9-BIT

+/− 0

0

0

Y

FGV

MGC652

1996 Oct 30 18

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

10 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DDD

V

DDA

V

diff

T

stg

T

amb

T

amb(bias)

V

esd

Note

1. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ resistor.

11 CHARACTERISTICS

= 4.5 to 5.5 V; V

V

DDD

digital supply voltage −0.5 +6.5 V
analog supply voltage −0.5 +6.5 V
voltage difference between V

SSAall

and V

SSall

− 100 mV
storage temperature −65 +150 °C
operating ambient temperature 0 +70 °C
operating ambient temperature under bias −10 +80 °C
electrostatic discharge all pins note 1 −2000 +2000 V

= 4.75 to 5.25 V; T

DDA

=25°C; unless otherwise specified.

amb

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V
I

DDD

P
V
I

DDA

P
P

DDD

D
DDA

A
A+D

digital supply voltage 4.5 5.0 5.5 V
digital supply current 100 130 160 mA
digital power 0.45 0.65 0.88 W
analog supply voltage 4.75 5.0 5.25 V
analog supply current 60 70 80 mA
analog power 0.32 0.35 0.38 W
analog and digital power 0.77 1.0 1.26 W

Analog part

I

clamp

V

i(p-p)

|Z

| input impedance clamping current off 200 −− kΩ

i

C

i

α

cs

clamping current VI= 1.25 V DC − 2 −µA
input voltage (peak-to-peak

value), AC coupling required

coupling
capacitor = 10 nF; note 1

0.55 1.0 1.5 V

input capacitance −− 10 pF
channel crosstalk fi= 5 MHz −−50 − dB

Analog-to-digital converters

B bandwidth at −3dB − 15 − MHz
φ

diff

differential phase (amplifier

− 2 − deg

plus anti-alias filter = bypass)

G

diff

differential gain (amplifier plus

− 2 − %

anti-alias filter = bypass)

f

ADC

ADC clock frequency 11 − 16 MHz

DLE DC differential linearity error − 0.5 − LSB
ILE DC integral linearity error − 1 − LSB

1996 Oct 30 19

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Digital inputs

V

IL

V

IH

V

IL(xtalI)

V

IH(xtalI)

V

ILn

V

IHn

I

LI

C

i(I/O)

C

i(n)

LOW level input voltage pins
SDA and SCL

HIGH level input voltage pins
SDA and SCL

LOW level CMOS input
voltage pin XTALI

HIGH level CMOS input
voltage pin XTALI

LOW level input voltage all
other inputs

HIGH level input voltage all
other inputs

input leakage current −− 1 µA
input capacitance inputs and outputs at

high-impedance

input capacitance all other
inputs

−0.5 − +1.5 V

0.7V

−− 0.3V

0.7V

− V

DDD

−− V

DDD

DDD

+ 0.5 V

DDD

V

−0.5 − +0.8 V

2.0 − V

DDD

+ 0.5 V

−− 8pF

−− 8pF

Digital outputs

V

OL

LOW level output voltage pins
SDA and SCL

V

OL

V

OH

V

OL(clk)

LOW level output voltage note 2 0 − 0.6 V
HIGH level output voltage note 2 2.4 − V
LOW level output voltage for

clocks

V

OH(clk)

HIGH level output voltage for
clocks

FEI input timing

t

SU;DAT

t

HD;DAT

input data set-up time 13 −− ns
input data hold time 3 −− ns

Data and control output timing

C

L

t

OHD;DAT

t

PD

t

PDZ

output load capacitance 15 − 50 pF
output hold time CL=15pF 5 −− ns
propagation delay CL=40pF −− 21 ns
propagation delay to 3-state −− 21 ns

SDA/SCL at 3 mA sink
current

−− 0.4 V

DDD

−0.5 − +0.6 V

2.6 − V

DDD

+ 0.5 V

V

1996 Oct 30 20

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Clock output timing (LLC and LLC2)

C

L(LLC)

T

cy

δLLC duty factors for t

t

r

t

f

t

dLLC2

Data qualifier output timing (CREF)

t

OHD;CREF

t

PD;CREF

output load capacitance 15 − 40 pF
cycle time LLC 35 − 39 ns

LLC2 70 − 78 ns

t

LLC2H/tLLC2

LLCH/tLLC

and

CL=40pF 40 − 60 %

rise time Vi= 0.6 to 2.6 V −− 5ns
fall time Vi= 2.6 to 0.6 V −− 5ns
delay time LLC output to LLC2

output

Vi= 1.5 V;
LLC/LLC2 = 40 pF

−1 − +1 ns

output hold time CL=15pF 4 −− ns
propagation delay from

CL=40pF −− 20 ns

positive edge of LLC

Clock input timing (XTALI)

δXTALI duty factor for t

Horizontal PLL

f

∆f

Hn

H/fHn

nominal line frequency 50 Hz field − 15625 − Hz

permissible static deviation −− 5.7 %

Subcarrier PLL

f

SCn

∆f

SCH/fSCHn

nominal subcarrier frequency PALBGHI, NTSC 443 − 4433619 − Hz

lock-in range ±400 −− Hz

XTALIH/tXTALI

nominal frequency 40 − 60 %

60 Hz field − 15734 − Hz

NTSC M − 3579545 − Hz
PAL M − 3575612 − Hz
PAL N − 3582056 − Hz

1996 Oct 30 21

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Crystal oscillator

f

n

∆f/f

n

∆Tf/f

n

CRYSTAL SPECIFICATION (X1)
T

ambX1

C

L

R

s

C

1

C

0

Notes

1. The levels must be measured with load circuits; 1.2 kΩ at 3 V (TTL load); CL= 50 pF.

2. The effects of rise and fall times are included in the calculation of t
drawings and conditions illustrated in Figs 12 and 13.

nominal frequency 3rd harmonic − 24.576 − MHz
permissible nominal

−− ±50 10

−6

frequency deviation
permissible nominal

−− ±20 10

−6

frequency deviation with
temperature

operating ambient

0 − 70 °C

temperature
load capacitance 8 −− pF
series resonance resistor − 40 80 Ω
motional capacitance − 1.5 ±20% − fF
parallel capacitance 3.5 ±20% pF

OHD;DAT

, tPD and t

. Timings and levels refer to

PDZ

Table 1 Processing delay

FUNCTION

TYPICAL ANALOG DELAY

AI22 −> ADCIN (AOUT) (ns)

Without amplifier or anti-alias filter 14

With amplifier plus anti-alias filter 72

DIGITAL DELAY

ADCIN -> VPO (LLC-CLOCKS)

[YDEL(2 to 0) = 000]

139With amplifier, without anti-alias filter 30

1996 Oct 30 22

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

12 TIMING DIAGRAMS

t

handbook, full pagewidth

CLOCK OUTPUT LLC

OUTPUTS VPO, HREF,
VREF, VS, HS

t

OHD;DAT

t

LLCH

LLC

t

LLCL

t

f

t

PD

t

r

2.6 V

1.5 V

0.6 V

MGC658

2.4 V

0.6 V

An explanation of the output formats is given in Table 5.

Fig.12 Clock/data timing (8-bit CCIR-656 format of the VPO-bus).

handbook, full pagewidth

CLOCK OUTPUT LLC

OUTPUT CREF

CLOCK OUTPUT LLC2

OUTPUTS VPO, HREF,
VREF, VS, HS



t

LLCH

t

OHD;CREF

t

dLLC2

t

LLC

t

PD

t

OHD;DAT

t

LLCL

t

f

t

r

t

OHD;CREF

t

LLC

2.6 V

1.5 V

0.6 V

t

PD

t

dLLC2

t

PD

MGC659

2.4 V

0.6 V

2.6 V

1.5 V

0.6 V

2.4 V

0.6 V

An explanation of the output formats is given in Table 5. The FEI timing of the VPO-bus is illustrated in Figs 15 and 17.

Fig.13 Clock/data timing (12/16-bit CCIR-601 format of the VPO-bus).

1996 Oct 30 23

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

handbook, full pagewidth

CLOCK OUTPUT LCC

t

LLCH

t

PD

OUTPUT CREF

t

OHD;CREF

RGB (8, 8, 8) data

VPO15 to VPO8

RGB (8, 8, 8) data

VPO7 to VPO0

An explanation of the output formats is given in Table 5.

t

LLC

t

LLCL

t

f

R(2 : 0)
G(1 : 0)
B(2 : 0)

t

r

R(7 : 3)
G(7 : 5)

t

LLC

t

OHD;CREF

t

PD

t

OHD;DAT

G(4 : 2)
B(7 : 3)

t

OHD;CREF

t

OHD;DAT

MBH227


2.4 V

1.5 V

0.6 V

2.4 V

1.5 V

0.6 V

2.4 V

1.5 V

0.6 V

2.4 V

1.5 V

0.6 V

handbook, full pagewidth

I2C-bit FECO = 1.

LLC

CREF

HREF

FEI

VPO

Fig.14 Clock/data timing for RGB888 output format.

t

PDZ

t

HD;DAT

from 3-state

t

PD

t

SU;DAT

t

OHD;DAT

to 3-state

Fig.15 FEI timing diagram (FEI sampling at CREF = HIGH).

MGC656

1996 Oct 30 24

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

handbook, full pagewidth

transmitted once per line

SEQUENCE

LOW

HIGH

128

BIT NO.:

TIME SLOT:

INCR

HPLL

INCR

FSCPLL

RESERVED

16

15

1

0 67

2

0

21

22

19

16

1617

1920

15

18

45

9

13

14

11 1012

6

8

7

3

452

3

0

1

63

RESERVED

1

68

(1) Set to zero for one transmission, if a phase reset of the fsc- DTO is applied via I2C-bit CDTO. RTCO sequence is generated in LLC/4.
The HPLL increment represents the actual LFCO frequency (f

INCR

=

f

-------------------------------------------------

LFCO

Where: f
The f

2

XTAL

increment represents the actual subcarrier frequency (related to the actual clock); 23 LSB from 24, MSB is 0b.

sc

INCR

f

-------------------------------------------------------

sc

×

HPLLfXTAL

word length DTO2

= 24.576 MHz, word length DTO2 = 20 bits.

FSCPLLfXTAL

word length DTO1

2

×

INCR

×=

---------------------------­2

HPLL

19

LFCO

× 4=f

); 16 LSB from 20, upper four bits are fixed to 0100b

LLC

Where: word length DTO1 = 24 bits.

Fig.16 Real time control output.

DTO RESET



RESERVED

50 Hz fields: 235



60 Hz fields: 232

MGC649

(1)

handbook, full pagewidth

LLC

CREF

HREF

t

SU;DAT

FEI

t

PDZ

VPO

to 3-state

Timing is compatible with SAA7110; I2C-bit FECO = 0.

Fig.17 FEI timing diagram (FEI sampling at CREF = LOW).

1996 Oct 30 25

t

OHD;DAT

t

HD;DAT

from 3-state

t

PD

MGC657

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

handbook, full pagewidth

LLC

CREF

LLC2

HREF

Yn

UVn

HREF

Yn

UVn

START OF ACTIVE LINE

0

U0 V0 U2 V2 U4

1234

END OF ACTIVE LINE

719718717716715

V716U716V714

U718 V718

MGC646

Fig.18 HREF timing diagram.

1996 Oct 30 26

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

handbook, full pagewidth

CVBS

Y - output

HREF (50 Hz)

RTS1 (PLIN)

HS

HS (50 Hz)

programming range

(step size: 8/LLC)

HREF (60 Hz)

HS (60 Hz)

(1)

108

50 x 2/LLC

139 x 1/LLC

720 x 2/LLC

7 x 2/LLC

3 x 2/LLC

720 x 2/LLC

0

0

burst

processing delay CVBS->VPO

sync clipped

12 x 2/LLC

144 x 2/LLC

113 x 2/LLC

4/LLC

16 x 2/LLC

138 x 2/LLC

(2)

−107

HS (60 Hz)

programming range

(step size: 8/LLC)

(1) PLIN is switched to output RTS1 via I2C-bit RTSE1 = 0.
(2) See Table 1.

107

0

Fig.19 Horizontal timing diagram.

1996 Oct 30 27

−106

MGC664

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

handbook, full pagewidth

23

input CVBS

HREF

VREF

VRLN = 1

VREF

VRLN = 0

VS

622

623

624

1234567822625

503 x 2/LLC

RTS0 (ODD)

input CVBS

HREF

VRLN = 1

VREF

VRLN = 0

VREF

VS

RTS0 (ODD)

(1)

310

(1)

311

312

313 314

a: 1st field

315 316

b: 2nd field

317

318

319

320

335 336

71 x 2/LLC

337

MGC662

(1) ODD is switched to output RTS0 via I2C-bit RTSE0 = 0.
The luminance peaking and the chrominance trap are bypassed during VREF = 0 if I2C-bit VBLB is set to logic 1.
The chrominance delay line (chroma-comb filter for NTSC, phase error correcting for PAL) is disabled during VREF = 0.

Fig.20 Vertical timing diagram for 50 Hz [nominal input signal VNL in normal mode (VNOI = 00b)].

1996 Oct 30 28

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

1234567

andbook, full pagewidth

input CVBS

HREF

VREF

VREF

VS

522

(525)

VRLN = 1

VRLN = 0

523

524

(2)(1)

525

(3)

(4) (5) (6) (7) (8) (9)

(10)

8

(11)

17

(20)

493 x 2/LLC

18 19

(21)

(22)

(2)

RTS0 (ODD)

input CVBS

HREF

VREF

VREF

RTS0 (ODD)

(1)

VS

(1)

259

(262)

VRLN = 1

VRLN = 0

260

(263)

261

(264)

a: 1st field

263 264 265 266 267 268 269 270 271

262

(266) (267) (268) (269) (270) (271) (272) (273) (274)

(265)

b: 2nd field

61 x 2/LLC

280

(283)

281

(284)

MGC663

282

(285)

(2)

(1) ODD is switched to output RTS0 via I2C-bit RTSE0 = 0.
(2) Line numbers in parenthesis refer to CCIR line counting.
The luminance peaking and the chrominance trap are bypassed during VREF = 0 if I2C-bit VBLB is set to logic 1.
The chrominance delay line (chroma-comb filter for NTSC, phase error correcting for PAL) is disabled during VREF = 0.

Fig.21 Vertical timing diagram for 60 Hz [nominal input signal VNL in normal mode (VNOI = 00b)].

1996 Oct 30 29

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

Table 2 Digital output control

VPO

OEYC FEI

15 to 0

(1)

15 to 8

(2)

7to0

00 Z Z Z
1 0 active active Z
01 Z Z Z
1 1 Z active Z

Notes

1. OFTS(1 : 0) = 10 or 01 or 00.

2. OFTS(1 : 0) = 11.

(2)

13 CLOCK SYSTEM

13.1 Clock generation circuit

The internal CGC generates the system clocks LLC, LLC2
and the clock reference signal CREF. The internal
generated LFCO (triangular waveform) is multiplied by
2 or 4 via the analog PLL (including phase detector, loop
filter, VCO and frequency divider). The rectangular output
signals have a 50% duty factor.

Table 3 Clock frequencies

CLOCK FREQUENCY (MHz)

XTAL 24.576

LLC 27
LLC2 13.5
LLC4 6.75
LLC8 3.375

handbook, full pagewidth

LFCO

BAND PASS

FC = LLC/4

ZERO

CROSS

DETECTION

PHASE

DETECTION

LOOP

FILTER

DIVIDER

1/2

Fig.22 Block diagram of clock generation circuit.

OSCILLATOR

DIVIDER

1/2

DELAY CREF

MGC632

LLC

LLC2

1996 Oct 30 30

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

13.2 Power-on control

Power-on reset is activated at power-on, chip enable, PLL clock generation failure and if the supply voltage falls below

3.5 V. The RES signal can be applied to reset other circuits of the digital picture processing system.

ndbook, full pagewidth

CE

XTAL

LLCINT

RESINT

CE

CLOCK

PLL

LLC

POC V

ANALOG

POC

LOGIC

DDA

POC V

DIGITAL

POC

DELAY

CLK0

DDD

RES

LLC

RES

some ms

CE = chip enable input; XTAL = crystal oscillator output; LLCINT = internal system clock;
RESINT = internal reset; LLC = line-locked system clock output; RES = reset output (active LOW).

20 to 200 µs

PLL-delay

<

digital delay

1 ms

Fig.23 Power-on control circuit.

1996 Oct 30 31

896 LCC

128 LCC

MGC633


Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

Table 4 Power-on control sequence

INTERNAL POWER-ON
CONTROL SEQUENCE

Directly after power-on
asynchronous reset

VPO15 to VPO0, RTCO, RTS0, RTS1,
GPSW, HREF, VREF, HS, VS, LLC, LLC2

PIN OUTPUT STATUS FUNCTION

direct switching to high impedance for
20 to 200 ms

and CREF are in high-impedance state

Synchronous reset
sequence

LLC, LLC2, CREF, RTCO, RTS0, RTS1,
GPSW and SDA become active;

internal reset sequence

VPO15 to VPO0, HREF, VREF, HS and VS
are held in high-impedance state

Status after power-on
control sequence

VPO15 to VPO0, HREF, VREF, HS and VS
are held in high-impedance state

after power-on (reset sequence) a complete

2

C-bus transmission is required

I

14 OUTPUT FORMATS
Table 5 Output formats

BUS SIGNAL 411 (12-BIT) 422 (16-BIT)

VPO15 Y07Y17Y27Y
VPO14 Y
VPO13 Y
VPO12 Y
VPO11 Y
VPO10 Y
VPO9 Y
VPO8 Y
VPO7 U
VPO6 U
VPO5 V
VPO4 V

06Y16Y26Y36
05Y15Y25Y35
04Y14Y24Y34
03Y13Y23Y33
02Y12Y22Y32
01Y11Y21Y31
00Y10Y20Y30

07U05U03U01

06U04U02U00
07V05V03V01
06V04V02V00

VPO3 X X X X U
VPO2 X X X X U
VPO1 X X X X U
VPO0 X X X X U

Y

37

07

Y

06

Y

05

Y

04

Y

03

Y

02

Y

01

Y

00

U

07

U

06

U

05

U

04
03
02
01
00

(1)

CCIR-656 (8-BIT)

Y
Y
Y
Y
Y
Y
Y
Y
V
V
V
V
V
V
V
V

U07Y07V07Y

17

U06Y06V06Y

16

U05Y05V05Y

15

U04Y04V04Y

14

U03Y03V03Y

13

U02Y02V02Y

12

U01Y01V01Y

11

U00Y00V00Y

10

XXXX G2 G4 R2

07

XXXX G1 G3 R1

06

XXXX G0 G2 R0

05

XXXX B4 B7 G1

04

XXXX B3 B6 G0

03

XXXX B2 B5 B2

02

XXXX B1 B4 B1

01

XXXX B0 B3 B0

00

(2)

RGB (16-BIT)

17
16
15
14
13
12
11
10

(3)

RGB (24-BIT)

R4 R7 R7
R3 R6 R6
R2 R5 R5
R1 R4 R4
R0 R3 R3
G5 G7 G7
G4 G6 G6
G3 G5 G5

(3)

Pixel order Y 0 1 2 3 0 1 0 1 − note 5 note 4
Pixel order UV 0 0 0 −−
Data rates LLC2 LLC2 LLC LLC2 LLC

2

C-bus

I
control signals

OFTS0 = 0 OFTS0 = 1 OFTS0 = 1 OFTS0 = 0 OFTS0 = 0
OFTS1 = 1 OFTS1 = 0 OFTS1 = 1 OFTS1 = 0 OFTS1 = 0

RGB888 = X RGB888 = X RGB888 = X RGB888 = 0 RGB888 = 1

Notes

1. Values in accordance with CCIR-601.

2. Before and after the video data, video timing codes are inserted in accordance with CCIR-656.

3. Values not defined during HREF = LOW.

4. CREF = 1 (see Fig.14).

5. CREF = 0 (see Fig.14).

1996 Oct 30 32

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

handbook, full pagewidth

CCIR Rec. 602 digital levels.

Equations for modification to the YUV levels via BCS control I2C bytes BRIG, CONT and SATN.
Luminance:

Y

OUT

Chrominance:

UV

OUT

It should be noted that the resulting levels are limited to 1 to 254 in accordance with CCIR-601/656 standard.

+255
+235

LUMINANCE 100%

+128

+16

0

(a) Y output range. (b) U output range (Cb). (c) V output range (Cr).

CONT

Int

----------------- -

Int

71

SATN

---------------- ­64

Y128–()× BRIG+=

Cr Cb, 128–()× 128+=

white

black

+255
+240

+212 +212

+128

U-COMPONENT

+44
+16

0

blue 100%
blue 75%

colourless

yellow 75%
yellow 100%

+255
+240

+128

+44
+16

V-COMPONENT

0

red 100%
red 75%

colourless

cyan 75%

cyan 100%

MGC634

Fig.24 VPO output signal range with default BCS settings.

handbook, full pagewidth

The pin numbers given in parenthesis refer to the 64-pin package.

quartz (3rd harmonic)

24.576 MHz

C =
10 pF

C =
10 pF

(a) With quartz crystal. (b) With external clock.

XTAL

65 (54)

XTALI

66 (55)

L = 10 µH ±20%

C =
1 nF

Fig.25 Oscillator application.

XTAL

65 (54)

SAA7111 SAA7111

XTALI

66 (55)

MGC635

1996 Oct 30 33

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

15 APPLICATION INFORMATION

handbook, full pagewidth

Q1(24.576 MHz)

AI22

V

AI21

V

AI12

V

AI11

V

L1

V

V

SSA

SSA

SSA

SSA

V

SDA

FEI

V
DDA

SSA

DDD

SCL

C16

1 nF

DD

10
µH

R4

75 Ω

R3

75 Ω

R2

75 Ω

R1

75 Ω

R6

100 nF

1 kΩ

C17
10 pF

C8

C4

10 nF

C3

10 nF

C2

10 nF

C1

10 nF

R5

1 kΩ

V

SS

100 nF

100 nF

XTAL

XTALI

C18

10 pF

V

SS

C9

C7

15 (6)

17 (8)

19 (10)

21 (12)

33 (24)

6 (63)
5 (62)

63 (52)

65 (54)

66 (55)

(16)

25

SSA0

V

DDA0VDDA1VDDA2

V

20

24

(11)

(15)

V

(9)
18

SSA1

V

SSA

(5)
14

SSA2

V

(7)

n.c.

n.c.

TMS

TDI

13

16

(4)

12
(3)

SAA7111

(40)

(13)

(56)

51

22

67

SS

SS1VSS2VSS3VSS4VSS5

V

V

V

SS

TDO

11

(2)

BST

n.c.

(32)

43

TCK
2

(59)

(26)

C15

C14

100 nF

C13

100 nF

V

SS

DD1VDD2VDD3VDD4VDD5

TRST

V

1

68

(61)

4

IICSA

SS

(57)

(64)

n.c.

52

(41)

(33)

8

7

n.c.

n.c.

(58)

(19)

35

28

V

27

34

44

(18)

(25)

(34) 45
(35) 46
(36) 47
(37) 48
(38) 49
(39) 50
(42) 53
(43) 54
(44) 55
(45) 56
(46) 57
(47) 58

(48) 59
(49) 60
(50) 61
(51) 62

(31) 42
(17) 26
(27) 38
(30) 41

(60) 3
(28) 39
(29) 40
(53) 64
(14) 23

(20) 29
(21) 30
(22) 31
(23) 32

37

36

9

10

n.c.

n.c.

n.c.

100 nF

C11

100 nF

15
14
13
12

11
10
9
8
7
6
5
4
3
2
1
0

C12

100 nF

MGC651

VPO(15 : 0)

HREF

VREF
HS
VS

RTCO
RTS1
RTS0
GPSW

AOUT

LLC

LLC2

CREF

RES

V

SS

The pin numbers given in parenthesis refer to the QFP64 package.

Fig.26 Application diagram.

1996 Oct 30 34

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

handbook, full pagewidth

VPO

(15 : 8)

VPO

(7 : 0)

(34) 45

(35) 46
(36) 47
(37) 48
(38) 49
(39) 50
(42) 53
(43) 54

(44) 55
(45) 56
(46) 57
(47) 58
(48) 59
(49) 60
(50) 61
(51) 62

SAA7111

(31) 42
(17) 26
(27) 38

(30) 41

(60) 3
(28) 39
(29) 40
(53) 64
(14) 23
(20) 29
(21) 30
(32) 31
(23) 32

15
14
13
12
11
10
9
8

7
6
5
4
3
2
1
0

VPO (15 : 11) R (7 : 3)

VPO (10 : 8)

VPO (7 : 5)

V

SS

OEN
D7
D6
D5
D4
D3
D2
D1
D0
V

SS

V

SS

HREF
VREF
HS
VS
RTCO
RTS1
RTS0
GPSW
AOUT
LLC

LLC2

CREF
RES

3

3

3

e.g.

74HCT574

5

V

DDVDD

O7
O6
O5
O4
O3
O2
O1

CLK

00

G (7 : 5)

G (4 : 2)

R (2 : 0)

G (1 : 0)

B (2 : 0)

B (7 : 3)VPO (4 : 0)

3

2

3

e.g. 74F240

8

8

8

R (7 : 0)

G (7 : 0)

B (7 : 0)

LLC2N

MGD137

The pin numbers given in parenthesis refer to the QFP64 package.
I2C-bus control bits:
OFTS(1 : 0) = 00 (subaddress 10h, bits D7 and D6).
RGB888 = 1 (subaddress 12h, bit D3).

Fig.27 Application diagram for RGB 24-bit output format.

1996 Oct 30 35

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

16 I2C-BUS DESCRIPTION

2

16.1 I
Table 6 Write procedure

Table 7 Read procedure (combined format)

Table 8 Description of I

S START condition
Sr repeated START condition
Slave address W 0100 1000b (IICSA = LOW) or 0100 1010b (IICSA = HIGH)
Slave address R 0100 1001b (IICSA = LOW) or 0100 1011b (IICSA = HIGH)
ACK s acknowledge generated by the slave
ACK m acknowledge generated by the master
Subaddress subaddress byte, see Table 9
Data data byte, see Table 9; note 1
P STOP condition
X = LSB slave

address
Slave address read = 49h or 4Bh; note 2

Subaddress 00h chip version read and write; note 3

C-bus format

S SLAVE ADDRESS W ACK s SUBADDRESS ACK s DATA (N BYTES) ACK s P

S SLAVE ADDRESS W ACK s SUBADDRESS ACK s

Sr SLAVE ADDRESS R ACK s DATA (N BYTES) ACK m P

2

C-bus format

CODE DESCRIPTION

read/write control bit; X = 0, order to write (the circuit is slave receiver); X = 1, order to read
(the circuit is slave transmitter)

write = 48h or 4Ah
IICSA = 0 or 1

01h reserved −
02h to 05h front-end part read and write
06h to 12h decoder part read and write
13h to 19h reserved −
1Ah to 1Ch Line-21 text slicer part read only
1Dh to 1Eh reserved −
1Fh status byte read only

Notes

1. If more than one byte DATA is transmitted then the auto-increment of the subaddress is performed.

2. During slave transmitter mode the SCL-LOW period may be extended by pulling SCL to LOW (in accordance with

2

the I

C-bus specification).

3. The I2C-bus subaddress 00 has to be initialized with 0 before being read.

1996 Oct 30 36

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

Table 9 I2C-bus receiver/transmitter overview

SLAVE ADDRESS

READ WRITE IICSA

49H and 4BH 48H and 4AH 0 and 1

REGISTER
FUNCTION

SUB-

ADDR.

D7 D6 D5 D4 D3 D2 D1 D0

Chip version 00 ID07 ID06 ID05 ID04 ID03 ID02 ID01 ID00
Reserved 01

(1) (1) (1) (1) (1) (1) (1) (1)

Analog input control 1 02 FUSE1 FUSE0 GUDL2 GUDL1 GUDL0 MODE2 MODE1 MODE0
Analog input control 2 03

(1)

HLNRS VBSL WPOFF HOLDG GAFIX GAI28 GAI18
Analog input control 3 04 GAI17 GAI16 GAI15 GAI14 GAI13 GAI12 GAI11 GAI10
Analog input control 4 05 GAI27 GAI26 GAI25 GAI24 GAI23 GAI22 GAI21 GAI20
Horizontal sync start 06 HSB7 HSB6 HSB5 HSB4 HSB3 HSB2 HSB1 HSB0
Horizontal sync stop 07 HSS7 HSS6 HSS5 HSS4 HSS3 HSS2 HSS1 HSS0
Sync control 08 AUFD FSEL EXFIL

(1)

VTRC HPLL VNOI1 VNOI0
Luminance control 09 BYPS PREF BPSS1 BPSS0 VBLB UPTCV APER1 APER0
Luminance brightness 0A BRIG7 BRIG6 BRIG5 BRIG4 BRIG3 BRIG2 BRIG1 BRIG0
Luminance contrast 0B CONT7 CONT6 CONT5 CONT4 CONT3 CONT2 CONT1 CONT0
Chroma saturation 0C SATN7 SATN6 SATN5 SATN4 SATN3 SATN2 SATN1 SATN0
Chroma Hue control 0D HUEC7 HUEC6 HUEC5 HUEC4 HUEC3 HUEC2 HUEC1 HUEC0
Chroma control 0E CDTO CM99 CSTD1 CSTD0 DCCF FCTC CHBW1 CHBW0
Reserved 0F

(1) (1) (1) (1) (1) (1) (1) (1)

Format/delay control 10 OFTS1 OFTS0 HDEL1 HDEL0 VRLN YDEL2 YDEL1 YDEL0
Output control 1 11 GPSW
Output control 2 12 RTSE1 RTSE0

(1)

FECO COMPO OEYC OEHV VIPB COLO

(1)

CBR RGB888 DIT AOSL1 AOSL0
Output control 3 13 VCTR1 VCTR0 CCTR1 CCTR0 BCHI1 BCHI0 BCLO1 BCLO0
Reserved 14

(1) (1) (1) (1) (1) (1) (1) (1)

V_GATE1_START 15 VSTA7 VSTA6 VSTA5 VSTA4 VSTA3 VSTA2 VSTA1 VSTA0
V_GATE1_STOP 16 VSTO7 VSTO6 VSTO5 VSTO4 VSTO3 VSTO2 VSTO1 VSTO0
V_GATE1_MSB 17
Reserved 18-19
Text slicer status 1A

Decoded bytes
of the text slicer

1B P1 BYTE16 BYTE15 BYTE14 BYTE13 BYTE12 BYTE11 BYTE10
1C P2 BYTE26 BYTE25 BYTE24 BYTE23 BYTE22 BYTE21 BYTE20

Reserved 1D-1E

(1) (1) (1) (1) (1) (1)
(1) (1) (1) (1) (1) (1) (1) (1)
(1) (1) (1) (1)

(1) (1) (1) (1) (1) (1) (1) (1)

F2VAL F2RDY F1VAL F1RDY

VSTO8 VSTA8

Status byte 1F STTC HLCK FIDT GLIMT GLIMB WIPA SLTCA CODE

Note

1. All unused control bits must be programmed with 0.

1996 Oct 30 37

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

16.2 I2C-bus detail

The I2C-bus receiver slave address is 48h/49h. Subaddresses 0F, 1D, 1E and 13 to 19 are reserved; subaddress 01 is
reserved for chip version.

16.2.1 S

UBADDRESS 00

Table 10 Chip version SA 00, D7 to D0

CONTROL BITS

FUNCTION

ID07 ID06 ID05 ID04 ID03 ID02 ID01 ID00

Chip version in read mode

(1)

0 0 00XXXX

chip version number reserved for chip name

Note

1. The I

16.2.2 S

2

C-bus subaddress 00 has to be initialized with 0 prior to reading it.

UBADDRESS 02

Table 11 Analog control 1 (Mode select; see Figs 28 to 35) SA 02, D2 to D0

CONTROL BITS D2 TO D0

FUNCTION

MODE 2 MODE 1 MODE 0

Mode 0: CVBS (automatic gain) 0 0 0
Mode 1: CVBS (automatic gain) 0 0 1
Mode 2: CVBS (automatic gain) 0 1 0
Mode 3: CVBS (automatic gain) 0 1 1
Mode 4: Y (automatic gain) + C (gain channel 2 fixed to GAI2 level) 1 0 0
Mode 5: Y (automatic gain) + C (gain channel 2 fixed to GAI2 level) 1 0 1
Mode 6: Y (automatic gain) + C (gain channel 2 adapted to Y gain) 1 1 0
Mode 7: Y (automatic gain) + C (gain channel 2 adapted to Y gain) 1 1 1

Table 12 Analog control 1 SA 02, D5 to D3 (see Fig.11)

CONTROL BITS D5 TO D3

DECIMAL VALUE UPDATE HYSTERESIS FOR 9-BIT GAIN

GUDL 2 GUDL 1 GUDL 0

0.... off 0 0 0

....7 ±7 LSB 1 1 1

Table 13 Analog control 1 SA 02, D7 and D6

CONTROL BITS D7 AND D6

ANALOG FUNCTION SELECT FUSE

FUSE 1 FUSE 0

Amplifier plus anti-alias filter bypassed 0 0

01
Amplifier active 1 0
Amplifier plus anti-alias filter active 1 1

1996 Oct 30 38

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

AI22

handbook, halfpage

AI21

AD2

CHROMA

AI22

handbook, halfpage

AI21

AD2

CHROMA

AI21
AI11

Fig.28 Mode 0; CVBS (automatic gain).

AI22

handbook, halfpage

AI21

AI12
AI11

Fig.30 Mode 2; CVBS (automatic gain).

AI22

handbook, halfpage

AI21

AD1

AD2

AD1

AD2

LUMA

MGC637

CHROMA

LUMA

MGC639

CHROMA

AI21
AI11

Fig.29 Mode 1; CVBS (automatic gain).

AI22

handbook, halfpage

AI21

AI12
AI11

Fig.31 Mode 3; CVBS (automatic gain).

AI22

handbook, halfpage

AI21

AD1

AD2

AD1

AD2

LUMA

MGC638

CHROMA

LUMA

MGC640

CHROMA

AI12
AI11

AD1

LUMA

MGC641

Fig.32 Mode 4 Y (automatic gain) + C

(gain channel 2 fixed to GAI1 level).

AI22

handbook, halfpage

AI21

AI12
AI11

AD2

AD1

CHROMA

LUMA

MGC643

Fig.34 Mode 6 Y (automatic gain) + C

(gain channel 2 adapted to Y gain).

1996 Oct 30 39

AI12
AI11

AD1

Fig.33 Mode 5 Y (automatic gain) + C

(gain channel 2 fixed to GAI1 level).

AI22

handbook, halfpage

AI21

AI12
AI11

AD2

AD1

Fig.35 Mode 7 Y (automatic gain) + C

(gain channel 2 adapted to Y gain).

LUMA

MGC642

CHROMA

LUMA

MGC644

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

16.2.3 SUBADDRESS 03

Table 14 Analog control 2 (AICO2)

FUNCTION LOGIC LEVEL DATA BIT

Static gain control channel 1 (GAI18)

Sign bit of gain control see Table 15 D0

Static gain control channel 2 (GAI28)

Sign bit of gain control see Table 16 D1

Gain control fix (GAFIX)

Automatic gain controlled by MODE 1 and MODE 0 0 D2
Gain control is user programmable via GAI1 + GAI2 1 D2

Automatic gain control integration (HOLDG)

AGC active 0 D3
AGC integration hold (freeze) 1 D3

White peak off (WPOFF)

White peak control active 0 D4
White peak off 1 D4

Vertical blanking select (VBSL)

Long vertical blanking 0 D5
Short vertical blanking 1 D5

HL not reference select (HLNRS)

Normal clamping by HL not 0 D6
Reference select by HL not 1 D6

16.2.4 S

Table 15 Gain control analog (AIC03); static gain control channel 1 GAI1 SA 04, D7 to D0

DECIMAL

UBADDRESS 04

GAIN

VALUE

0.... −5.98 0 0 0 000000

....255 0 0 1 1 111111

256.... 0 1 0 0 000000

....511 5.98 1 1 1 111111

(dB)

SIGN

BIT

GAI18 GAI17 GAI16 GAI15 GAI14 GAI13 GAI12 GAI11 GAI10

CONTROL BITS D7 TO D0

1996 Oct 30 40

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

16.2.5 SUBADDRESS 05

Table 16 Gain control analog (AIC04); static gain control channel 2 GAI2 SA 05

DECIMAL

VALUE

0.... −5.98 0 00000000

....255 0 0 11111111

256.... 0 1 00000000

....511 5.98 1 11111111

16.2.6 S

Table 17 Horizontal sync begin SA 06, D7 to D0

(STEP SIZE = 8/LLC)

16.2.7 S

Table 18 Horizontal sync stop SA 07

GAIN

(dB)

UBADDRESS 06

DELAY TIME

−128...−108 forbidden (outside available central counter range)

−107... 1 0 0 1 0 1 0 1

...108 0 1 1 0 1 1 0 0

109...127 forbidden (outside available central counter range)

UBADDRESS 07

SIGN BIT

(SA 03, D1)

GAI28 GAI27 GAI26 GAI25 GAI24 GAI23 GAI22 GAI21 GAI20

HSB7 HSB6 HSB5 HSB4 HSB3 HSB2 HSB1 HSB0

CONTROL BITS D7 to D0

CONTROL BITS D7 to D0

DELAY TIME

(STEP SIZE = 8/LLC)

−128...−108 forbidden (outside available central counter range)

−107... 1 0 0 1 0 1 0 1

...108 0 1 1 0 1 1 0 0

109...127 forbidden (outside available central counter range)

HSS7 HSS6 HSS5 HSS4 HSS3 HSS2 HSS1 HSS0

CONTROL BITS D7 to D0

1996 Oct 30 41

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

16.2.8 SUBADDRESS 08

Table 19 Sync control SA 08, D7 to D5, D3 to D0

FUNCTION VNOI BITS LOGIC LEVELS DATA BITS

Vertical noise reduction (VNOI)

Normal mode VNOI1 0 D1

VNOI0 0 D0

Searching mode VNOI1 0 D1

VNOI0 1 D0

Free running mode VNOI1 1 D1

VNOI0 0 D0

Vertical noise reduction bypassed VNOI1 1 D1

VNOI0 1 D0

Horizontal PLL (HPLL)

PLL closed − 0D2
PLL open, horizontal frequency fixed − 1D2

TV/VTR mode select (VTRC)

TV mode
(recommended for poor quality TV signals only)

VTR mode (recommended as default setting) − 1D3

Extended loop filter (EXFIL)

Word width of the loop filter (LF2) amplification = 16-bit − 0D5
Word width of the loop filter (LF2) amplification = 14-bit − 1D5

Field selection (FSEL)

50 Hz, 625 lines − 0D6
60 Hz, 525 lines − 1D6

Automatic field detection (AUFD)

Field state directly controlled via FSEL − 0D7
Automatic field detection − 1D7

− 0D3

1996 Oct 30 42

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

16.2.9 SUBADDRESS 09

Table 20 Luminance control

FUNCTION

Aperture factor (APER)

Aperture factor = 0 APER1 0 D1

Aperture factor = 0.25 APER1 0 D1

Aperture factor = 0.5 APER1 1 D1

Aperture factor = 1.0 APER1 1 D1

Update time interval for AGC value (UPTCV)

Horizontal update (once per line) − 0D2
Vertical update (once per field) − 1D2

Vertical blanking luminance bypass (VBLB

Active luminance processing − 0D3
Luminance bypass during vertical blanking − 1D3

Aperture band pass (centre frequency) (BPSS) D5 and D4

Centre frequency = 4.1 MHz BPSS1 0 D5

Centre frequency = 3.8 MHz; note 1 BPSS1 0 D5

Centre frequency = 2.6 MHz; note 1 BPSS1 1 D5

Centre frequency = 2.9 MHz; note 1 BPSS1 1 D5

APER/BPSS

BITS

APER0 0 D0

APER0 1 D0

APER0 0 D0

APER0 1 D0

BPSS0 0 D4

BPSS0 1 D4

BPSS0 0 D4

BPSS0 1 D4

LOGIC LEVELS DATA BITS

Prefilter active (PREF)

Bypassed − 0D6
Active − 1D6

Chrominance trap bypass (BYPS)

Chrominance trap active; default for CVBS mode − 0D7
Chrominance trap bypassed; default for S-Video mode − 1D7

Note

1. Not to be used with bypassed chrominance trap.

1996 Oct 30 43

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

16.2.10 SUBADDRESS 0A

Table 21 Luminance brightness control BRIG7 to BRIG0 SA 0A

OFFSET

255 (bright) 1 1 1 1 1 1 1 1

128 (CCIR level) 1 0 0 0 0 0 0 0

0 (dark) 0 0 0 0 0 0 0 0

16.2.11 S
Table 22 Luminance contrast control CONT7 to CONT0 SA 0B

1.109 (CCIR level) 0 1 0 0 0 1 1 1

−1 (inverse luminance) 1 1 0 0 0 0 0 0

−2 (inverse luminance) 1 0 0 0 0 0 0 0

16.2.12 SUBADDRESS 0C
Table 23 Chrominance saturation control SATN7 to SATN0 SA 0C

UBADDRESS 0B

GAIN

1.999 (maximum) 0 1 1 1 1 1 1 1

1.0 01000000

0 (luminance off) 0 0 0 0 0 0 0 0

BRIG7 BRIG6 BRIG5 BRIG4 BRIG3 BRIG2 BRIG1 BRIG0

CONT7 CONT6 CONT5 CONT4 CONT3 CONT2 CONT1 CONT0

CONTROL BITS D7 to D0

CONTROL BITS D7 to D0

GAIN

1.999 (maximum) 0 1 1 1 1 1 1 1

1.0 (CCIR level) 0 1 0 0 0 0 0 0
0 (colour off) 0 0 0 0 0 0 0 0

−1 (inverse chroma) 1 1 0 0 0 0 0 0

−2 (inverse chroma) 1 0 0 0 0 0 0 0

16.2.13 S

Table 24 Chrominance hue control HUEC7 to HUEC0 SA 0D

HUE PHASE (DEG)

UBADDRESS 0D

+178.6.... 0 1 1 1 1 1 1 1

....0.... 0 0 0 0 0 0 0 0

....−180 1 0 0 0 0 0 0 0

SATN7 SATN6 SATN5 SATN4 SATN3 SATN2 SATN1 SATN0

HUEC7 HUEC6 HUEC5 HUEC4 HUEC3 HUEC2 HUEC1 HUEC0

CONTROL BITS D7 to D0

CONTROL BITS D7 to D0

1996 Oct 30 44

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

16.2.14 SUBADDRESS 0E

Table 25 Chrominance control SA 0E

FUNCTION CHBW/CSTD LOGIC LEVELS DATA BITS

Chroma bandwidth (CHBW0 and CHBW1)

Small bandwidth (≈ 620 kHz) CHBW1 0 D1

CHBW0 0 D0

Nominal bandwidth (≈ 800 kHz) CHBW1 0 D1

CHBW0 1 D0

Medium bandwidth (≈ 920 kHz) CHBW1 1 D1

CHBW0 0 D0

Wide bandwidth (≈ 1000 kHz) CHBW1 1 D1

CHBW0 1 D0

Fast colour time constant (FCTC)

Nominal time constant − 0D2
Fast time constant − 1D2

Disable chroma comb filter (DCCF)

Chroma comb filter on (during VREF = 1)
(see Figures 20 and 21)

Chroma comb filter off − 1D3

Colour standard (CSTD0 and CSTD1)

Colour standard control automatic switching between
PAL BGHI and NTSC M

Colour standard control automatic switching between
NTSC 4.43 (50 Hz) and PAL 4.43 (60 Hz)

Colour standard control automatic switching between
PAL N and NTSC 4.43 (60 Hz)

Colour standard control automatic switching between
NTSC N and PAL M

CM99 compatibility to SAA7199

Default value − 0D6
To be set if SAA7199 (digital encoder) is used for

re-encoding in conjunction with RTCO

Clear DTO (CDTO)

Disabled − 0D7
Every time CDTO is set, the internal subcarrier DTO

phase is reset to 0° and the RTCO output generates a
logic 0 at time slot 68 (see RTCO description Fig.16).
So an identical subcarrier phase can be generated by
an external device (e.g. an encoder).

− 0D3

CSTD1 0 D5
CSTD0 0 D4
CSTD1 0 D5
CSTD0 1 D4
CSTD1 1 D5
CSTD0 0 D4
CSTD1 1 D5
CSTD0 1 D4

− 1D6

− 1D7

1996 Oct 30 45

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

16.2.15 SUBADDRESS 10

Table 26 Format/delay control SA 10

LUMINANCE DELAY COMPENSATION

(STEPS IN 2/LLC)

−4... 1 0 0

...0... 0 0 0

...3 0 1 1

Table 27 VREF pulse position and length VRLN SA 10 (D3)

VREF at 60 HZ 525 LINES

VRLN

0101

Length 240 242 286 288
Line number first last first last first last first last
Field 1 19 (22) 258 (261) 18 (21) 259 (262) 24 309 23 310
Field 2 282 (285) 521 (524) 281 (284) 522 (525) 337 622 336 623

Note

1. The numbers given in parenthesis refer to CCIR line counting.

Table 28 Fine position of HS HDEL0 and HDEL1 SA 10

FINE POSITION OF HS WITH A STEP SIZE

OF 2/LLC

000
101
210
311

YDEL2 YDEL1 YDEL0

(1)

HDEL1 HDEL0

CONTROL BITS D2 to D0

VREF at 50 HZ 625 LINES

CONTROL BITS D5 and D4

Table 29 Output format selection OFTS0 and OFTS1 SA 10

FORMATS

OFTS1 OFTS0

RGB 565, RGB 888 (dependent on control
bit RGB888) see Table 31

YUV 422 16 bits 0 1
YUV 411 12 bits 1 0
YUV CCIR-656 8 bits 1 1

1996 Oct 30 46

CONTROL BITS D7 and D6

00

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

16.2.16 SUBADDRESS 11

Table 30 Output control 1 SA 11

FUNCTION LOGIC LEVELS DATA BIT

Colour on (COLO)

Automatic colour killer 0 D0
Colour forced on 1 D0

Decoder VIP bypassed (VIPB)

DMSD data to YUV output 0 D1
ADC data to YUV output; dependent on mode

settings

Output enable horizontal/vertical sync (OEHV)

HS, HREF, VREF and VS high impedance inputs 0 D2
Outputs HS, HREF, VREF and VS active 1 D2

1D1

Output enable YUV data (OEYC)

VPO-bus high-impedance inputs 0 D3
Output VPO-bus active 1 D3

Inverse composite blank (COMPO)

VREF is vertical reference 0 D4
VREF is inverse composite blank 1 D4

FEI control (FECO)

FEI sampling at CREF = LOW
(SAA7110 compatible; see Fig.17

FEI sampling at CREF = HIGH 1 D5

General purpose switch (GPSW)

Switches directly pin 64 (53) GPSW; note 1 0 D7

Note

1. The pin number given in parenthesis refers to the 64-pin package.

0D5

1D7

1996 Oct 30 47

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

16.2.17 SUBADDRESS 12

Table 31 Output control 2 SA 12

FUNCTION AOSL BITS LOGIC LEVELS DATA BITS

Analog test select (AOSL)

AOUT connected to internal test point 1 AOSL1 0 D1

AOSL0 0 D0

AOUT connected to input AD1 AOSL1 0 D1

AOSL0 1 D0

AOUT connected to input AD2 AOSL1 1 D1

AOSL0 0 D0

AOUT connected to internal test point 2 AOSL1 1 D1

AOSL0 1 D0

Dithering (noise shaping) control (DIT)

Dithering off − 0D2
Dithering on − 1D2

RGB output format selection (RGB888)

RGB565 − 0D3
RGB888 − 1D3

Chroma interpolation filter function (CBR)

Cubic interpolation (default) − 0D4
Linear interpolation (lower bandwidth) − 1D4

Real time outputs mode select (RTSE0)

ODD switched to output pin 40 (29); note 1 − 0D6
VL switched to output pin 40 (29); note 1 − 1D6

Real time outputs mode select (RTSE1)

PLIN switched to output pin 39 (28); note 1 − 0D7
HL switched to output pin 39 (28); note 1 − 1D7

Note

1. The pin number given in parenthesis refers to the 64-pin package.

1996 Oct 30 48

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

16.2.18 SUBADDRESS 1A (READ-ONLY REGISTER)

Table 32 Line-21 text slicer status SA 1A

2

I

C-BUS

CONTROL BITS

F1RDY new data on field 1 has been acquired (for asynchronous reading); active HIGH D0

F1VAL Line-21 of field 1 carries valid data; active HIGH D1

F2RDY new data on field 2 has been acquired (for asynchronous reading); active HIGH D2

F2VAL Line-21 of field 2 carries valid data; active HIGH D3

FUNCTION DATA BIT

16.2.19 S

UBADDRESS 1B (READ-ONLY REGISTER)

Table 33 First decoded data byte of the text slicer SA 1B,

2

C-BUS

I

CONTROL BITS

FUNCTION DATA BIT

BYTE1 (6 to 0) data bit 6 to 0 of first data byte D6 to D0

P1 parity error flag bit; bit goes HIGH when a parity error has occurred D7

16.2.20 S

UBADDRESS 1C (READ-ONLY REGISTER)

Table 34 Second decoded data byte of the text slicer SA 1C

I2C-BUS

CONTROL BITS

FUNCTION DATA BIT

BYTE2 (6:0) data bit 6 to 0 of second data byte D6 to D0

P2 parity error flag bit; bit goes HIGH when a parity error has occurred D7

16.2.21 SUBADDRESS 1F (READ-ONLY REGISTER)

Table 35 Status byte SA 1F

2

C-BUS

I

CONTROL BITS

FUNCTION DATA BIT

CODE colour signal according to selected standard has been detected; active HIGH D0

SLTCA slow time constant active in WIPA-mode; active HIGH D1

WIPA white peak loop is activated; active HIGH D2
GLIMB gain value for active luminance channel is limited [min (bottom)]; active HIGH D3
GLIMT gain value for active luminance channel is limited [max (top)]; active HIGH D4

FIDT identification bit for detected field frequency; LOW = 50 Hz, HIGH = 60 Hz D5
HLCK status bit for locked horizontal frequency; LOW = locked, HIGH = unlocked D6
STTC status bit for horizontal phase loop; LOW = TV time-constant,

D7

HIGH = VTR time-constant

1996 Oct 30 49

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

17 FILTER CURVES

17.1 Anti-alias filter curve

handbook, full pagewidth

6

V

(dB)

0

−6

−12

−18

−24

−30

−36

−42

024 68101214

17.2 Luminance filter curves

MGD138

f (MHz)

Fig.36 Anti-alias filter.

18

handbook, full pagewidth

V

Y

(dB)

6

−6

−18

−30

024 86

(1) = 43h; (2) = 53h; (3) = 63h; (4) = 73h.

(1)
(2)
(4)
(3)

(1)
(2)
(4)
(3)

f

Y (MHz)

MGD139

Fig.37 Luminance control SA 09h, 4.43 MHz Trap/CVBS mode, prefilter on, different aperture band-pass centre

frequencies.

1996 Oct 30 50

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

18

handbook, full pagewidth

V

Y

(dB)

6

−6

−18

−30

024 86

(1) = 40h; (2) = 41h; (3) = 42h; (4) = 43h.

Fig.38 Luminance control SA 09h, 4.43 MHz Trap/CVBS mode, prefilter on, different aperture factors.

(1)
(2)
(3)
(4)

(4)
(3)
(2)
(1)

f

Y (MHz)

MGD140

18

handbook, full pagewidth

V

Y

(dB)

6

−6

−18

−30

024 86

(1) = 03h; (2) = 13h; (3) = 23h; (4) = 33h.

(1)
(2)
(4)
(3)

(1)
(2)
(4)
(3)

f

Y (MHz)

MGD141

Fig.39 Luminance control SA 09h, 4.43 MHz Trap/CVBS mode, prefilter off, different aperture band-pass centre

frequencies.

1996 Oct 30 51

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

18

handbook, full pagewidth

V

Y

(dB)

6

−6

−18

−30

024 86

(1) = C0h; (2) = C1h; (3) = C2h; (4) = C3h.

Fig.40 Luminance control SA 09h, Y/C mode, prefilter on, different aperture factors.

(1)
(2)
(3)
(4)

f

Y (MHz)

MGD142

18

handbook, full pagewidth

V

Y

(dB)

6

−6

−18

−30

024 86

(1) = 80h; (2) = 81h; (3) = 82h; (4) = 83h.

Fig.41 Luminance control SA 09h, Y/C mode, prefilter off, different aperture factors.

(1)
(2)
(3)
(4)

f

Y (MHz)

MGD143

1996 Oct 30 52

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

18

handbook, full pagewidth

V

Y

(dB)

6

−6

−18

−30

024 86

(1) = 43h; (2) = 53h; (3) = 63h; (4) = 73h.

(1)
(2)
(4)
(3)

(1)
(2)
(4)
(3)

f

Y (MHz)

MGD144

Fig.42 Luminance control SA 09h, 3.58 MHz Trap/CVBS mode, prefilter on, different aperture band-pass centre

frequencies.

18

handbook, full pagewidth

V

Y

(dB)

6

−6

−18

−30

024 86

(1) = 40h; (2) = 41h; (3) = 42h; (4) = 43h.

(1)
(2)
(3)
(4)

(4)
(3)
(2)
(1)

Fig.43 Luminance control SA 09h, 3.58 MHz Trap/CVBS mode, prefilter on, different aperture factors.

f

Y (MHz)

MGD145

1996 Oct 30 53

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

18

handbook, full pagewidth

V

Y

(dB)

6

(1)
(2)
(4)

−6

−18

−30

024 86

(1) = 03h; (2) = 13h; (3) = 23h; (4) = 33h.

(3)

(1)
(2)
(4)
(3)

f

Y (MHz)

MGD146

Fig.44 Luminance control SA 09h, 3.58 MHz Trap/CVBS mode, prefilter off, different aperture band-pass centre

frequencies.

1996 Oct 30 54

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

17.3 Chrominance filter curves

handbook, full pagewidth

6

V

(dB)

0

−6
(1)

−12

−18

−24

−30

−36

−42

−48

−54

0 0.54 1.08 1.62 2,16

Transfer characteristics of the chroma low-pass dependent on CHBW[1:0] settings.
(1) CHBW [1 : 0] = 00; (2) CHBW [1 : 0] = 01; (3) CHBW [1 : 0] = 10; (4) CHBW [1 : 0] = 11.

(2)
(3)
(4)

Fig.45 Chrominance filter.

(4)
(1)
(3)
(2)

f

(MHz)

MGD147

2.7

2

C-BUS START SET-UP

18 I

• The given values force the following behaviour of the SAA7111:
– the analog input AI11 expects a signal in CVBS format; analog anti-alias filter active
– automatic field detection
– YUV 422/16-bit output format enabled
– outputs HS, HREF, VREF and VS active
– contrast, brightness and saturation control in accordance with CCIR standards
– chrominance processing with nominal bandwidth (800 kHz).

1996 Oct 30 55

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

Table 36 I2C-bus start set-up values

SUB

(HEX)

FUNCTION NAME

(1)

VALUES (BIN) (HEX)

76543210START

00 chip version ID0(7 : 0); note 2 0 0 00000000
01 reserved 0 0 00000000
02 analog input control 1 FUSE(1 : 0), GUDL(2 : 0), MODE(2 : 0) 1 1 000000C0
03 analog input control 2 X, HLNRS, VBSL, WPOFF, HOLDG,

0010001123

GAFIX, GAI28, GAI18
04 analog input control 3 GAI(17 : 10) 0 0 00000000
05 analog input control 4 GAI(27 : 20) 0 0 00000000
06 horizontal sync start HSB(7 : 0) 1 1 101011EB
07 horizontal sync stop HSS(7 : 0) 1 1 100000E0
08 sync control AUFD, FSEL, EXFIL, X, VTRC, HPLL,

1000100088

VNOI(1 : 0)
09 luminance control BYPS, PREF, BPSS(1 : 0), VBLB,

0000000101

UPTCV, APER(1 : 0)
0A luminance brightness BRIG(7 : 0) 1 0 00000080
0B luminance contrast CONT(7 : 0) 0 1 00011147
0C chrominance saturation SATN(7 : 0) 0 1 00000040
0D chroma hue control HUEC(7 : 0) 0 0 00000000
0E chrominance control CDTO, CM99, CSTD(1 : 0), DCCF,

0000000101

FCTC, CHBW(1 : 0)
0F reserved 0 0 00000000
10 format/delay control OFTS(1 : 0), HDEL(1 : 0), VRLN,

0100000040

YDEL(2 : 0)
11 output control 1 GPSW, X, FECO, COMPO, OEYC,

000111001C

OEHV, VIPB, COLO
12 output control 2 RTSE(1: 0), X, CBR, RGB888, DIT,

0000000101

AOSL(1 : 0)
13-19 reserved 0 0 00000000
1A text slicer status 0, 0, 0, 0, F2VAL, F2RDY, F1VAL, F1RDY read only register
1B decoded bytes of the
1C P2, BYTE2(6 : 0)
1D-

text slicer
reserved 0 0 00000000

P1, BYTE1(6 : 0)

1E
1F status byte STTC, HLCK, FIDT, GLIMT, GLIMB,

read only register

WIPA, SLTCA, CODE

Notes

1. All X values must be set to LOW.

2. The I

2

C-bus subaddress 00 has to be initialized with 0 prior to reading.

1996 Oct 30 56

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

19 PACKAGE OUTLINES

PLCC68: plastic leaded chip carrier; 68 leads

e

y

61

68

1

pin 1 index

D

X

SOT188-2

e

E

4460

43

A

Z

E

b

p

b

1

w M

H

E

E

e

A

A

1

A

4

(A )

3

k

9

β

1

27

k

10 26

e

Z

D

H

D

v M

A

D

B

v M

B

0 5 10 mm

scale

DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)

UNIT A

mm

0.180

inches

0.165

A

1

min. max. max. max. max.

4.57

0.51

4.19

0.020

A

0.25

0.01

A

4

3

3.30

0.13

b

0.53

0.33

0.021

0.013

b

p

1

0.81

0.66

0.032

0.026

D

24.33

24.13

0.958

0.950

(1)

(1)

E

eH

e

D

1.27

0.05

23.62

22.61

0.930

0.890

24.33

24.13

0.958

0.950

e

E

23.62

22.61

0.930

0.890

H

25.27

25.02

0.995

0.985

D

25.27

25.02

0.995

0.985

Note

1. Plastic or metal protrusions of 0.01 inches maximum per side are not included.

OUTLINE

VERSION

SOT188-2

IEC JEDEC EIAJ

112E10 MO-047AC

REFERENCES

k

1

k

E

1.22

1.07

0.048

0.042

0.51

0.020

L

1.44

1.02

0.057

0.040

detail X

p

EUROPEAN

PROJECTION

L

p

(1) (1)

Z

Z

E

D

ywv β

0.18 0.100.18

0.007 0.0040.007

2.16

0.085

2.16

0.085

o

45

ISSUE DATE

92-11-17
95-03-11

1996 Oct 30 57

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

QFP64: plastic quad flat package; 64 leads (lead length 1.6 mm); body 14 x 14 x 2.7 mm

c

y

X

A

48 33

49

pin 1 index

64

1

32

Z

E

e

A

H

E

E

2

A

A

1

w M

b

p

17

16

detail X

SOT393-1

Q

(A )

3

θ

L

p

L

w M

b

e

p

D

H

D

Z

D

B

v M

0 5 10 mm

scale

DIMENSIONS (mm are the original dimensions)

mm

A

max.

3.00

0.25

0.10

2.75

2.55

0.25

UNIT A1A2A3b

cE

p

0.45

0.23

0.30

0.13

(1)

(1) (1)(1)

D

14.1

13.9

eH

H

14.1

13.9

0.8

17.45

16.95

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

OUTLINE

VERSION

IEC JEDEC EIAJ

REFERENCES

SOT393-1 MS-022

1996 Oct 30 58

v M

D

A

B

E

17.45

16.95

LLpQZywv θ

1.4

1.03

0.73

1.1

0.16 0.100.161.60

EUROPEAN

PROJECTION

Z

D

1.2

1.2

0.8

0.8

ISSUE DATE

E

o

7

o

0

94-06-22
96-05-21

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

20 SOLDERING

20.1 Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“IC Package Databook”

20.2 Reflow soldering

Reflow soldering techniques are suitable for all PLCC and
QFP packages.

The choice of heating method may be influenced by larger
PLCC or QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our

Reference Handbook”

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.

(order code 9398 652 90011).

“Quality

(order code 9397 750 00192).

• The package footprint must incorporate solder thieves at
the downstream corners.

20.3.2 QFP

Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

If wave soldering cannot be avoided, the following
conditions must be observed:

• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.

• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.

Even with these conditions, do not consider wave
soldering the following packages: QFP52 (SOT379-1),
QFP100 (SOT317-1), QFP100 (SOT317-2),
QFP100 (SOT382-1) or QFP160 (SOT322-1).

20.3.3 M

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

ETHOD (PLCC AND QFP)

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.

20.3 Wave soldering

20.3.1 PLCC
Wave soldering techniques can be used for all PLCC

packages if the following conditions are observed:

• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.

• The longitudinal axis of the package footprint must be
parallel to the solder flow.

1996 Oct 30 59

20.4 Repairing soldered joints

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

21 DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

22 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

23 PURCHASE OF PHILIPS I

Purchase of Philips I
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.

2

C COMPONENTS

2

C components conveys a license under the Philips’ I2C patent to use the

1996 Oct 30 60

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

NOTES

1996 Oct 30 61

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

NOTES

1996 Oct 30 62

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

NOTES

1996 Oct 30 63

Philips Semiconductors – a worldwide company

Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

Tel. [phone], Fax. [phone]
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. [phone], Fax. [phone]

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Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,
Tel. [phone], Fax. [phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
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Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,

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Worli, MUMBAI 400 018, Tel. [phone], Fax. [phone]

Indonesia: see Singapore
Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. [phone], Fax. [phone]
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180,

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Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,

20124 MILANO, Tel. [phone], Fax. [phone]
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Tel. [phone], Fax. [phone]
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,

Tel. [phone], Fax. [phone]
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,

Tel. [phone], Fax. [phone]
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,

Tel. [phone]

Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
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Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
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Spain: Balmes 22, 08007 BARCELONA,
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Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
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Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66,
Chung Hsiao West Road, Sec. 1, P.O. Box 22978,
TAIPEI 100, Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. 1996 SCA52
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

Printed in The Netherlands 657021/1200/02/pp64 Date of release: 1996 Oct 30 Document order number: 9397 750 01185