Datasheet SAA5249GP-E, SAA5249P-E Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

SAA5249

Integrated VIP and Teletext with
Background Memory Controller
(IVT1.1BMCX)

Preliminary specification
Supersedes data of December 1993
File under Integrated Circuits, IC02

1996 Nov 07

Philips Semiconductors Preliminary specification

Integrated VIP and Teletext with
Background Memory Controller

FEATURES

• Complete teletext decoder featuring a background
memory controller in a single 48-pin DIP package.
Capable of storing of up to 512 teletext pages in an
external DRAM, giving instant access to the teletext
data

• Automatic processing of extension packet 26 for widest
possible language decoding. All our standard language
options can be available, and the language option is
readable via I2C-bus.

• 100% hardware compatible with the SAA5247 plug-in
replacement and with the possibility of extra market in
those countries with packet 26 transmissions.
Still pin-aligned to SAA5254 and SAA5244A.

• 100% software compatible with the SAA5247, and
SAA5244A, except if the special OSD symbols were
used. Also 100% software compatible to SAA5254. In all
events there is a change to the ROM ID number.

• The device is pin-aligned with the other members of the
new Philips teletext decoder family, i.e. SAA5281 and
the SAA5254, making one hardware solution for the
whole range

• Low software overhead for the microprocessor

• RGB interface to standard colour decoder ICs, push-pull

output drive.

GENERAL DESCRIPTION

The Integrated VIP and Teletext (IVT1.1BMCX) is a
teletext decoder (contained within a single chip package)
for decoding 625-line based World System Teletext
transmissions. With its built-in background memory
controller the device can store incoming teletext packets in
the external 1M4 DRAM. With this large packet store
which can be rapidly scanned, we can achieve near
instantaneous access to all the pages transmitted by the
broadcaster.

This version of the decoder also contains some extra
hardware to process extension packet 26 automatically,
extending the markets to which the TV chassis can be
shipped and offering many more language options for the
set maker.

SAA5249

QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V

DD

I

DD

V

syn

V

vid

f

XTAL

T

amb

supply voltage 4.5 5.0 5.5 V
supply current − 90 120 mA
sync amplitude 0.1 0.3 0.6 V
video amplitude 0.7 1.0 1.4 V
crystal frequency − 27 − MHz
operating ambient temperature −20 − +70 °C

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

PACKAGE

SAA5249P/E DIP48 plastic dual in-line package; 48 leads (600 mil) SOT240-1
SAA5249GP/E QFP64 plastic quad flat package; 64 leads (lead length 1.95 mm);

SOT319-1

body 14 × 20 × 2.7 mm; high stand-off height

1996 Nov 07 2

Philips Semiconductors Preliminary specification

Integrated VIP and Teletext with
Background Memory Controller

BLOCK DIAGRAM

SAA5249

handbook, full pagewidth

DD1

DD2

SSn

SS1

46
45

3

12

16, 22
38

7

8

SEL1
SEL2

V

V

V

V

REF+

A0 to A9 D0 to D3

10

4

SAA5249

DATA SLICER

AND

CLOCK

REGENERATOR

DCVBS

ANALOG

TO

DIGITAL

CONVERTER

42

23

DRAM INTERFACE

RASR/W CAS1 ODD/EVEN

24 41

BACKGROUND

MUX

MEMORY

CONTROL

TIMING

CHAIN

29

TELETEXT

ACQUISITION

AND

DECODING

COR

21 27

DISPLAY

R/G/BY BLANK RGBREFCAS0

3

20 17 to 19 28

HAMMING
CHECKER

AND

PACKET 26

PROCESSING

ENGINE

MEMORY

2

I C - BUS

INTERFACE

PAGE

31

SDA

30

SCL

OSCOUT

OSCIN

4

CRYSTAL

5

OSCILLATOR

6

GNDO

INPUT CLAMP

SYNC

SEPARATOR

911

BLACK IREF STTV/LFBPOL

Fig.1 Block diagram for SOT240-1 (DIP48) package.

1996 Nov 07 3

AND

DISPLAY 

CLOCK
PHASE

LOCKED

LOOP

10 13 15 14

CVBS

VCR/FFB

MLB304

Philips Semiconductors Preliminary specification

Integrated VIP and Teletext with
Background Memory Controller

PINNING

SAA5249

SYMBOL

SOT240-1 SOT319-1

(1)

DESCRIPTION

n.c. 1 1 not connected
n.c. 2 2 not connected

PIN

V

DD1

3 25 +5 V supply
OSCOUT 4 27 27 MHz crystal oscillator output
OSCIN 5 28 27 MHz crystal oscillator input
GNDO 6 29 0 V crystal oscillator ground
V

SS1

7 12 0 V ground
REF+ 8 32 positive reference voltage; this pin should be connected to ground via a

100 nF capacitor

BLACK 9 35 video black level storage pin; this pin should be connected to ground via a

100 nF capacitor

CVBS 10 36 composite video input pin; a positive-going 1 V (p-p) input is required,

connected via a 100 nF capacitor
IREF 11 37 reference current input pin; connected to ground via a 27 kΩ resistor
V

DD2

12 38 +5 V supply
POL 13 39 STTV/LFB/FFB polarity selection pin
STTV/LFB 14 40 sync to TV output pin/line flyback input pin; function controlled by an

internal register bit (scan sync mode)

VCR/FFB 15 42 PLL time constant switch/field input pin; function controlled by an internal

register bit (scan sync mode)

V

SS2

16 30 0 V ground
REF−−31 negative reference voltage; this pin should be connected to REF+ via a

100 nF capacitor
R 17 49 dot rate character output of the RED colour information
G 18 50 dot rate character output of the GREEN colour information
B 19 51 dot rate character output of the BLUE colour information
RGBREF 20 52 input DC voltage to define the output high level on the RGB pins
BLANK 21 53 dot rate fast blanking output
V

SS3

22 54, 55 0 V ground; internally connected for SOT319
CAS0 23 56 column address select to external DRAM for BMCX function
CAS1 24 57 column address select to external DRAM for BMCX function for second

DRAM where two 256 k × 4 devices are used
A4 25 58 address output to external DRAM for BMCX function
A3 26 59 address output to external DRAM for BMCX function
COR 27 60 programmable output to provide contrast reduction of the TV picture for

mixed text and picture displays or when viewing newsflash/subtitle pages;

open drain output

EVEN 28 61 25 Hz output synchronized with the CVBS input field sync pulses to

ODD/

produce a non-interlaced display by adjustment of the vertical deflection

currents

1996 Nov 07 4

Philips Semiconductors Preliminary specification

Integrated VIP and Teletext with
Background Memory Controller

SAA5249

SYMBOL

Y 29 62 dot rate character output of teletext foreground colour information; open

SCL 30 63 serial clock input for I2C-bus; it can still be driven HIGH during power-down

SDA 31 64 serial data port for the I

A5 32 4 address output to external DRAM for BMCX function
A2 33 5 address output to external DRAM for BMCX function
A6 34 6 address output to external DRAM for BMCX function
A1 35 8 address output to external DRAM for BMCX function
A7 36 9 address output to external DRAM for BMCX function
A0 37 11 address output to external DRAM for BMCX function
V

SS4

A8 39 13 address output to external DRAM for BMCX function
A9 40 14 address output to external DRAM for BMCX function
RAS 41 15 row address select to external DRAM

W 42 18 read/write for external DRAM

R/
D2 43 19 data input/output for external DRAM
D0 44 20 data input/output for external DRAM
SEL2 45 21 RAM select input to choose external DRAM size
SEL1 46 22 RAM select input to choose external DRAM size
D3 47 23 data input/output for external DRAM
D1 48 24 data input/output for external DRAM

SOT240-1 SOT319-1

38 43 0 V ground

PIN

(1)

drain output

of the device

2

C-bus; open drain output. It can still be driven

HIGH during power-down of the device

DESCRIPTION

Note

1. The remaining pins for SOT319 are not connected.

1996 Nov 07 5

Philips Semiconductors Preliminary specification

Integrated VIP and Teletext with
Background Memory Controller

V

DD1

OSCOUT

OSCIN

n.c.
n.c.

48

1
2
3
4
5

D1

47

D3
SEL1

46
45

SEL2
D0

44

SAA5249

GNDO

V

SS1

REF

BLACK

CVBS

IREF

V

DD2
POL

STTV/LFB

VCR/FFB

V

SS2

RGBREF

BLANK

V

SS3
CAS0
CAS1

43
42
41

40
39
38

37
36
35
34
33
32
31

30
29
28

27
26
25

D2
R/W

RAS
A9
A8

V

SS4
A0
A7

A1
A6
A2
A5

SDA

SCL
Y
ODD/EVEN

COR
A3
A4

6
7
8

9
10
11
12

SAA5249P

13
14
15
16
17

R

18

G
B

19
20

21
22

23
24

MLB305

Fig.2 Pin configuration; SOT240-1 (DIP48).

1996 Nov 07 6

Philips Semiconductors Preliminary specification

Integrated VIP and Teletext with
Background Memory Controller

index
corner

n.c.
n.c.
n.c.

A5

A2
A6
n.c.
A1
A7

n.c.

A0

V

SS1

A8
A9

RAS

n.c.
n.c.

R/W

D2

SDA

64
1
2
3
4
5
6
7
8
9

10
11
12

13
14
15
16
17
18
19

SCL
63

Y
62

ODD/EVEN
61

COR

A3

60

59

SAA5249GP

A4
58

CAS1
57

CAS0
56

SS3

V
55

SS3

V

54

BLAN
53

RGBREF

52

51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

B
G

R

n.c.

V

SS4
VCR/FFB
n.c.

STTV/LFB
POL

V

DD2

IREF
CVBS
BLACK
n.c.
n.c.

SAA5249

20

21

D0

SEL2

22

SEL1

23
D3

24
D1

25

V

DD1

26

n.c.

Fig.3 Pin configuration; SOT319-1 (QFP64).

1996 Nov 07 7

27

28

OSCIN

OSCOUT

29

GNDO

30

SS2

V

31

REF

32

REF

MLB306

Philips Semiconductors Preliminary specification

Integrated VIP and Teletext with
Background Memory Controller

LIMITING VALUES

In accordance with Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER MIN. MAX. UNIT

V

DD

V

I

V

O

I

O

I

IOK

T

amb

QUALITY AND RELIABILITY

supply voltage (all supplies) −0.3 +6.5 V
input voltage (any input) −0.3 VDD+ 0.5 V
output voltage (any output) −0.3 VDD+ 0.5 V
output current (each output) −±10 mA
DC input or output diode current −±20 mA
operating ambient temperature −20 +70 °C

SAA5249

This device will meet Philips Semiconductors General Quality Specification for Business group

Circuits SNW-FQ-611-Part E”

. The principal requirements are shown in Tables 1 to 4.

“Consumer Integrated

1996 Nov 07 8

Philips Semiconductors Preliminary specification

Integrated VIP and Teletext with
Background Memory Controller

Group A
Table 1 Acceptance tests per lot

TEST REQUIREMENTS

Mechanical cumulative target: <100 ppm
Electrical cumulative target: <100 ppm

Group B
Table 2 Processability tests (by package family)

TEST REQUIREMENTS

Solderability <7% LTPD
Mechanical <15% LTPD
Solder heat resistance <15% LTPD

Group C

SAA5249

(1)

(1)

Table 3 Reliability tests (by process family)

TEST CONDITIONS REQUIREMENTS

(1)

Operational life 168 hours at Tj= 150 °C <1500 FPM; equivalent to <100 FITS

at Tj=70°C

Humidity life temperature, humidity, bias

<2000 FPM
(1000 hours, 85 °C, 85% RH or
equivalent test)

Temperature cycling performance T

stg(min)

to T

stg(max)

<2000 FPM

Table 4 Reliability tests (by device type)

TEST CONDITIONS REQUIREMENTS

ESD and latch-up ESD Human body model

<15% LTPD

(1)

2000 V, 100 pF, 1.5 kΩ
ESD Machine model

<15% LTPD
200 V, 100 pF, 1.5 kΩ

latch-up 100 mA, 1.5 × V

DD

<15% LTPD
(absolute maximum)

Note to Tables 1 to 4

1. ppm = fraction of defective devices, in parts per million.
LTPD = Lot Tolerance Percent Defective.
FPM = fraction of devices failing at test condition, in Failures Per Million.
FITS = Failures In Time Standard.

1996 Nov 07 9

Philips Semiconductors Preliminary specification

Integrated VIP and Teletext with
Background Memory Controller

CHARACTERISTICS

V

=5V±10%; T

DD

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

DD

I

DD(tot)

supply voltage 4.5 5.0 5.5 V
total supply current − 90 120 mA

Inputs

CVBS
V

sync

t

d(sync)

sync amplitude 0.1 0.3 0.6 V
delay from CVBS to TCS output

from STTV buffer (nominal video,
average of leading/trailing edge)

∆t

d(sync)

change in sync delay between all
black and all white video input at
nominal levels

V

vid(p-p)

video input amplitude
(peak-to-peak value)

display PLL catching range ±7 −−%

Z

source

C

i

source impedance −−250 Ω

input capacitance −−10 pF
IREF
R

gnd

resistor to ground − 27 − kΩ
POL
V

IL

V

IH

I

LI

C

i

LOW level input voltage −0.3 − +0.8 V

HIGH level input voltage 2.0 − VDD+ 0.5 V

input leakage current Vi= 0 to V

input capacitance −−10 pF
LFB
V

IL

V

IH

I

LI

I

i

t

d(LFB)

LOW level input voltage −0.3 − +0.8 V

HIGH level input voltage 2.0 − VDD+ 0.5 V

input leakage current Vi= 0 to V

input current note 1 −1 − +1 mA

delay between LFB front edge

and input video line sync
VCR/FFB
V

IL

V

IH

I

LI

I

i

LOW level input voltage −0.3 − +0.8 V

HIGH level input voltage 2.0 − VDD+ 0.5 V

input leakage current Vi= 0 to V

input current note 1 −1 − +1 mA

= −20 to +70 °C; unless otherwise specified.

amb

DD

DD

DD

−150 0 +150 ns

0 − 25 ns

0.7 1.0 1.4 V

−10 − +10 µA

−10 − +10 µA

− 250 − ns

−10 − +10 µA

SAA5249

1996 Nov 07 10

Philips Semiconductors Preliminary specification

Integrated VIP and Teletext with
Background Memory Controller

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

RGBREF note 2
V

IL

I

LI

I

DC

SEL1 AND SEL2
V

IL

V

IH

I

LI

SCL
V

IL

V

IH

I

LI

f

SCL

t

r

t

f

C

i

Inputs/outputs

LOW level input voltage −0.3 − VDD+ 0.5 V

input leakage current Vi= 0 to V

DD

−10 − +10 µA

DC current −−10 mA

LOW level input voltage −0.3 − +0.8 V

HIGH level input voltage 2.0 − VDD+ 0.5 V

input leakage current Vi= 0 to V

DD

−10 − +10 µA

LOW level input voltage −0.3 − +1.5 V

HIGH level input voltage 3.0 − VDD+ 0.5 V

input leakage current Vi= 0 to V

DD

−10 − +10 µA
clock frequency 0 − 100 kHz
input rise time 10% to 90% −−2µs
input fall time 90% to 10% −−2µs
input capacitance −−10 pF

SAA5249

C

RYSTAL OSCILLATOR (OSCIN; OSCOUT)

f

XTAL

G

v

G

m

C

i

C

FB

crystal frequency − 27 − MHz
small signal voltage gain 3.5 −−
mutual conductance fi= 100 kHz 1.5 −−mA/V
input capacitance −−10 pF
feedback capacitance −−5pF

BLACK
C

blk

I

LI

storage capacitor to ground − 100 − nF
input leakage current Vi= 0 to V

SDA
V

IL

V

IH

I

LI

C

i

t

r

t

f

V

OL

t

f

C

L

LOW level input voltage −0.3 − +1.5 V
HIGH level input voltage 3.0 − VDD+ 0.5 V
input leakage current Vi= 0 to V
input capacitance −−10 pF
input rise time 10% to 90% −−2µs
input fall time 90% to 10% −−2µs
LOW level output voltage IOL= 3 mA 0 − 0.5 V
output fall time 3 V to 1 V −−200 ns
load capacitance −−400 pF

DD

DD

−10 − +10 µA

−10 − +10 µA

1996 Nov 07 11

Philips Semiconductors Preliminary specification

Integrated VIP and Teletext with
Background Memory Controller

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

D0 TO D3
V

IL

V

IH

I

LI

C

i

V

OL

V

OH

t

r

t

f

C

L

Outputs

STTV
G

stt

V

TCS

V

DCs

I

O

C

L

A0 TO A9 ADDRESS OUTPUT TO MEMORY A0 TO A9
V

OL

V

OH

C

L

t

r

t

f

R/W, CASO AND CAS1
V

OL

V

OH

C

L

t

r

t

f

LOW level input voltage −0.3 − +0.8 V
HIGH level input voltage 2.0 − VDD+ 0.5 V
input leakage current −10 − +10 µA
input capacitance −−10 pF
LOW level output voltage IOL= +1.6 mA 0 − 0.4 V
HIGH level output voltage IOH= −0.2 mA 2.4 − V
output rise time 0.6 to 2.2 V −−20 ns
output fall time 2.2 to 0.6 V −−20 ns
load capacitance −−50 pF

gain of STTV relative to video

0.9 1.0 1.1
input

TCS amplitude 0.2 0.3 0.45 V
DC shift between TCS output and

−−0.15 V
nominal video output

output drive current −−3.0 mA
load capacitance −−100 pF

LOW level output voltage IOL= +1.6 mA 0 − 0.4 V
HIGH level output voltage IOH= −0.2 mA 2.4 − V
load capacitance −−50 pF
output rise time 0.6 to 2.2 V −−20 ns
output fall time 2.2 to 0.6 V −−20 ns

LOW level output voltage IOL= +1.6 mA 0 − 0.4 V
HIGH level output voltage IOH= −0.2 mA 2.4 − V
load capacitance −−50 pF
output rise time 0.6 to 2.2 V −−20 ns
output fall time 2.2 to 0.6 V −−20 ns

SAA5249

DD

DD

DD

V

V

V

1996 Nov 07 12

Philips Semiconductors Preliminary specification

Integrated VIP and Teletext with
Background Memory Controller

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

R, G AND B
V

OL

V

OH

| output impedance −−200 Ω

|Z

o

C

L

I

DC

t

r

t

f

BLANK
V

OL

V

OH

V

OH

V

OH

C

L

t

r

t

f

ODD/EVEN
V

OL

V

OH

C

L

t

r

t

f

COR AND Y(OPEN-DRAIN)
V

OH

V

OL

C

L

t

f

I

LO

t

skew

LOW level output voltage IOL= 2 mA 0 − 0.2 V
HIGH level output voltage IOH= −1.6 mA;

RGBREF ≤ VDD− 2V

RGBREF

−0.25

RGBREF RGBREF

load capacitance −−50 pF
DC current −−−3.3 mA
output rise time 10% to 90% −−20 ns
output fall time 90% to 10% −−20 ns

LOW level output voltage IOL= 1.6 mA 0 − 0.4 V
HIGH level output voltage IOH= −0.2 mA;

1.1 −−V

VDD= 4.5 V

HIGH level output voltage IOH= 0 mA;

−−2.8 V

VDD= 5.5 V
allowed voltage at pin with external pull-up −−VDDV
load capacitance −−50 pF
output rise time 10% to 90% −−20 ns
output fall time 90% to 10% −−20 ns

LOW level output voltage IOL= +1.6 mA 0 − 0.4 V
HIGH level output voltage IOH= −0.2 mA 2.4 − V
load capacitance −−120 pF
output rise time 0.6 to 2.2 V −−50 ns
output fall time 2.2 to 0.6 V −−50 ns

pull-up voltage at pin −−VDDV
output voltage LOW IOL= 5 mA 0 − 1.0 V
load capacitance −−25 pF
output fall time load resistor of 1.2 kΩ

−−50 ns
to VDD; measured
between VDD− 0.5 V
and 1.5 V

output leakage current Vi= 0 to V
skew delay between display

DD

−10 − +10 µA

−−20 ns

outputs R, G, B, COR, Y and
BLANK

SAA5249

+0.25

DD

V

V

1996 Nov 07 13

Philips Semiconductors Preliminary specification

Integrated VIP and Teletext with
Background Memory Controller

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Timing

DRAM INTERFACE
t

RC

t

RP

t

RAS

t

CAS

t

ASR

t

RAH

t

ASC

t

CAH

t

RCD

t

RAD

t

RSH

t

CSH

t

CRP

t

DZO

, t

t

r

f

t

WCS

t

WCH

t

DS

t

DH

t

RAC

t

CAC

t

AA

t

RCS

t

RCH

t

RRH

t

RAL

t

OFF1

t

CDD

read or write cycle time 344 380 415 ns
RAS precharge time 125 140 155 ns
RAS pulse width 194 210 230 ns
CAS pulse width 113 133 153 ns
row address set-up time 30 60 80 ns
row address hold time 50 60 92 ns
column address set-up time 50 60 75 ns
column address hold time 50 60 70 ns
RAS to CAS delay time 130 148 160 ns
RAS to column address delay

60 74 105 ns

time
RAS hold time 15 60 70 ns
CAS hold time 260 286 300 ns
CAS to RAS precharge time 60 70 80 ns
CAS set-up time from data input 200 225 280 ns
rise and fall times 10 15 20 ns
write set-up time 193 212 235 ns
write command hold time 116 137 150 ns
data input set-up time 193 212 235 ns
data input hold time 42 62 80 ns
access time from RAS 165 183 220 ns
access time from CAS 0 3540ns
access time from address 95 108 120 ns
read command set-up time 193 212 235 ns
read command hold time to CAS 0 1020ns
read command hold time to RAS 55 65 100 ns
column address to RAS lead time 90 133 150 ns
output buffer turn-off time 20 30 40 ns
CAS to data input delay time 25 35 45 ns

SAA5249

1996 Nov 07 14

Philips Semiconductors Preliminary specification

Integrated VIP and Teletext with
Background Memory Controller

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

I2C-BUS
t

LOW

t

HIGH

t

SU;DAT

t

HD;DAT

t

SU;STO

t

BUF

t

HD;STA

t

SU;STA

Notes

1. This current is the maximum allowed into the inputs when line and field flyback signals are connected to these inputs.
Series current limiting resistors must be used to limit the input currents to ±1 mA.

2. RGBREF is the positive supply pin for the RGB output pins and it must be able to source the IOH current from the
R, G and B pins. The leakage specification on RGBREF only applies when there is no current load on the RGB pins.

clock LOW period 4 −−µs
clock HIGH period 4 −−µs
data set-up time 250 −−ns
data hold time 170 −−ns
set-up time from clock HIGH to

4 −−µs

STOP
START set-up time following a

4 −−µs

STOP
START hold time 4 −−µs
START set-up time following

4 −−µs

clock LOW-to-HIGH transition

SAA5249

1996 Nov 07 15

Philips Semiconductors Preliminary specification

Integrated VIP and Teletext with
Background Memory Controller

SAA5249

64 µs

64 µs

32 34.33

64 µs

59.33

27.33 32

MLA037 - 2

handbook, full pagewidth

1 2 3456 7

0 4.66

LSP

0 2.33

EP

(Line Sync Pulse)

0

BP

(Equalizing Pulse)

(Broad Pulse)

625

624

623

622

621

(312)

(311)

(310)

(309)

(308)

309 310 311 312 313 314 (1) 315 (2) 316 (3) 317 (4) 318 (5) 319 (6) 320 (7)

TCS interlaced

308 309 310 311 312 1 2 3 4 5 6 7

TCS interlaced

Fig.4 Composite sync waveforms.

TCS non-interlaced

1996 Nov 07 16

Philips Semiconductors Preliminary specification

Integrated VIP and Teletext with
Background Memory Controller

SAA5249

handbook, full pagewidth

(1) Also BLANK in character and box blanking.

LSP

(TCS)

0 4.66

R, G, B, Y

(1)

0

R, G, B, Y

(1)

0

Fig.5 Display output timing (a) line rate (b) field rate.

40 µs

display period

16.67

lines 42 to 291 inclusive (and 355 to 604 inclusive interlaced)

display period

41

56.67 µs

64 µs

291

line numbers

MLA662 - 1

312

handbook, full pagewidth

SDA

t

LOW

t

SCL

SDA

MBC764

t

BUF

t

HD;STA

Fig.6 I2C-bus timing.

1996 Nov 07 17

t

r

SU;STA

t

HD;DAT

t

HIGH

t

f

t

SU;DAT

t

SU;STO

Philips Semiconductors Preliminary specification

Integrated VIP and Teletext with
Background Memory Controller

RAS

t

RAS

t

RC

SAA5249

CAS

ADDRESS

WE

DATA OUTPUT

DATA INPUT

t

f

t

ASR

t

RAH

ROW COLUMN

t

RCD

t

RAD

t

RCS

high impedance

t

RAC

tt

DZO

t

ASC

t

RSH

t
t

t

RAL

t

CAH

t

CAC

t

AA

high impedance

CAS
CSH

t

DATA VALID

t

RP

t

RRH

OFF1

t

CRP

t

RCH

CDD

MBA732

Fig.7 DRAM interface timing; read cycle.

1996 Nov 07 18

Philips Semiconductors Preliminary specification

Integrated VIP and Teletext with
Background Memory Controller

RAS

t

RAS

t

RC

SAA5249

CAS

ADDRESS

WE

DATA INPUT

DATA OUTPUT

t

t

ASR

t

RSH

t

WCH

t

DH

t

CAS

t

CSH

f

t

RAH

ROW

t

RCD

t

WCS

t

t

DS

ASC

COLUMN

t

CAH

DATA VALID

high impedance

t

RP

t

CRP

MBA731

Fig.8 DRAM interface timing; write cycle.

1996 Nov 07 19

Philips Semiconductors Preliminary specification

Integrated VIP and Teletext with
Background Memory Controller

SAA5249

MBA073 - 4

1 2 3456 7

FIRST FIELD START (EVEN)

625

(312)

624

(311)

623

(310)

622

(309)

621

(308)

48 µs

31 µs

16 µs

SECOND FIELD START (ODD)

313 314 (1) 315 (2) 316 (3) 317 (4) 318 (5) 319 (6) 320 (7)

31 µs

Fig.9 ODD/EVEN timing.

2 µs

2 µs

309 310 311 312

TCS interlaced

ODD/EVEN output

(normal sync mode)

ODD/EVEN output

(normal sync mode

when VCS to SCS

mode active)

ODD/EVEN output

(slave sync mode)

1996 Nov 07 20

TCS interlaced

ODD/EVEN output

(normal sync mode)

ODD/EVEN output

(normal sync mode

when VCS to SCS

mode active)

ODD/EVEN output

(slave sync mode)

Philips Semiconductors Preliminary specification

Integrated VIP and Teletext with
Background Memory Controller

APPLICATION INFORMATION

SAA5249

+5 V

C2

33 µF

C1

100 nF

12

IC1

SAA5249

15

IC2

D34D17D06A8

4748443943

3

D3

DD1

DD2

V

V

COR

ODD/EVENBGRBLANKYVCR

2819181721

27

C13

100 nF

5

1

CC

SS

V

V

D23A719A6

20

18

36

34373235332625

D1D0A8D2A7

29

1513101620

OE

A517A112A213A314A4

15

A6A0A5A1A2A3A4

CVBSVRGBREF

BLACK

STTV

9

14

C11

100 nF

C12

10 µF

A0

A910WE8RAS9CAS

2

11

40424123244645

A9

R/W

RAS

CAS0

POL

OSCOUT

OSCIN

45876

V

REF +

SS1

SS2

C14

100

nF

5

1

SS

CC

V
D2D1D0A8A7A6A3A1A0WERAS

SEL2

SDA

OE

V

102019181716141312

SS3 SS4

C10 100 nF

V , V

22, 38

A4A2A5

+5 V

IC3

CAS1

IREF

GNDO

4

303111

15

D3

376

SEL1

SCL

C13 and C14

are optional

surface mounted

capacitors mounted

close to IC

892

R10

4.7 kΩ

R9

4.7 kΩ

LK4

LK3

CAS

LINK

LINK

IC2 and IC3 pin-outs are for 

Dual In-Line Package (DIP)

-

-
256K x 4

-

IC2 IC3

DRAM (120 nS)

LINK

34

1M x 4 -

256K x 4

256K x 4

MLB307

6

R G B BLANKING ODD/EVEN

KEY

1 2345

GND

X3

+5 V

R1

10 kΩ

1

X1

KEY

2

VCR

+5 V

C3

100 

nF

3

CVBS

C8 100 nF

R2

1 kΩ

LK1

LINK

4

STTV

C9 

100 nF
L1

C5 8.2 pF

C4

100 nF

LK2

LINK

3.3 µH

C7 1 nF

R11

C7

R3

NOTE :

FOR +VE GOING

1

X2

1996 Nov 07 21

R9

27 kΩ

G1

27 MHz

3.3 kΩ

15 pF

1 kΩ

FOR - VE 

GOING

SYNC FIT LK2

SYNC FIT LK1

2

KEY

+5 V

+5 V

3

R6

R5

R7 220 Ω

4.7 kΩ

4.7 kΩ

R8 220 Ω

4

KEY

123

GND

X4

n.c.

5

SCL SDA

Fig.10 Application diagram; 1 or 4 Mbit DRAM.

D

Philips Semiconductors Preliminary specification

Integrated VIP and Teletext with
Background Memory Controller

IVT1.1BMCX page memory organization

The organization of the page memory is illustrated by Fig.11. The IVT1.1BMCX provides an additional row as compared
with first generation decoders; this brings the display format up to 40 characters by 25 rows. Rows 0 to 23 form the
teletext page; Row 24 is the extra row available for software generated status messages and FLOF/FASTEXT prompt
information.

fixed character

written by IVT hardware

7 characters

for status

71

alphanumerics white for normal
alphanumerics green when looking
for display page

24 characters from page header
rolling when display page looked for

8 characters

always rolling

(time)

824

ROW

0
1
2
3
4

SAA5249

page information

PACKET X / 24 if R0D7 = 0

PACKET X / 27 / 0

PACKETS 8 / 30 / 0 to 15

MBA275 - 2

MAIN PAGE DISPLAY AREA

PACKET X / 22
PACKET X / 23

PACKET X / 24 STORED HERE IF R0D7 = 1

10 14

10 bytes for

received

14 bytes

free for use

by microcontroller

Fig.11 Basic page memory organization.

REMARK TO Fig.11

Row 0

Row 0 is for the page header. The first seven columns

ROW

0
1
2

(0 to 6) are free for status messages. The eighth is an
alphanumeric white or green control character, written
automatically by IVT1.1BMCX to give a green rolling
header when a page is being looked for. The last eight
characters are for rolling time.

Row 25

MBA274

5

to

20

21
22
23
24
25

Fig.12 Organization of the extension memory.

1996 Nov 07 22

The first 10 bytes of row 25 contain control data relating to
the received page as shown in Table 5. The remaining
14-bytes are free for use by the microcomputer.

Philips Semiconductors Preliminary specification

Integrated VIP and Teletext with
Background Memory Controller

Table 5 Row 25 received control data format

D0 PU0 PT0 MU0 MT0 HU0 HT0 C7 C11 MAG0 0
D1 PU1 PT1 MU1 MT1 HU1 HT1 C8 C12 MAG1 0
D2 PU2 PT2 MU2 MT2 HU2 C5 C9 C13 MAG2 0
D3 PU3 PT3 MU3 C4 HU3 C6 C10 C14 0 0
D4 HAM.ER HAM.ER HAM.ER HAM.ER HAM.ER HAM.ER HAM.ER HAM.ER
D5 0 0 0 0 0 0 0 0 0 PBLF
D60000000000
D70000000000

Column 0 1 2 3 4 5 6 7 8 9

Table 6 Page number and sub-code for Table 5

Page number

MAG magazine
PU page units
PT page tens
PBLF page being looked for
FOUND LOW for page has been found
HAM.ER hamming error in corresponding byte

SAA5249

FOUND 0

Page sub-code

MU minutes units
MT minutes tens
HU hours units
HT hours tens
C4 to C14 transmitted control bits

1996 Nov 07 23

Philips Semiconductors Preliminary specification

Integrated VIP and Teletext with
Background Memory Controller

Register maps

IVT1.1BMCX mode registers R0 to R11 are shown in Table 7. R0 to R10 are write only; R11 is read/write.
Register map (R3), for page requests, is shown in detail in Table 9.

Table 7 Register map (notes 1 to 5)

REGISTER D7 D6 D5 D4 D3 D2 D1 D0

Adv. control 0 X24 POS FREE

RUN PLL

Mode 1 VCS TO

SCS

Page
request
address

Page
request
data

Display
control
(normal)

Display
control
(newsflash
/subtitle)

Display
mode

Cursor row 9 − CLEAR

Cursor
column

Cursor data 11 D7 D6 D5 D4 D3 D2 D1 D0
Device

status

2 −− − − TB START

3 −− CLEAR

−−−−−−−−

5 BKGND

OUT

6 BKGND

OUT

7 STATUS

BTM
TOP

−−−−−−−−

10 −− C5 C4 C3 C2 C1 C0

625/525

11B

SYNC

7 + P/
8-BIT

BKGND IN COR OUT COR IN TEXT OUT TEXT IN PON OUT PON IN

BKGND IN COR OUT COR IN TEXT OUT TEXT IN PON OUT PON IN

CURSORONCONCEA

MEM.

ROM VERR4ROM

AUTO
ODD/
EVEN

ACQ
ON/OFF

B.M.

L REVEAL
ON

A0 R4 R3 R2 R1 R0

VER R3

DISABLE
HDR
ROLL

DISABLE
PKT 26

PRD4 PRD3 PRD2 PRD1 PRD0

TOP/BTM
HALF

ROM VERR2ROM VERR1ROM

DISPLAY
SRATUS
ROW
ONLY

DEW/
FULL
FIELD

SINGLE
DOUBLE
HEIGHT

DISABLE
ODD/
EVEN

TCS
ON

COLUMN
SC2

BOX ON24BOX ON

VER R0

SAA5249

− R11/R11B

SELECT

T1 T0

START
COLUMN
SC1

1-23

TEXT
SIGNAL
QUALITY

START
COLUMN
SC0

BOX ON 0

VCS
SIGNAL
QUALITY

1996 Nov 07 24

Philips Semiconductors Preliminary specification

Integrated VIP and Teletext with
Background Memory Controller

Notes

1. The dash (−) indicates these bits are inactive and must be written to logic 0 for future compatibility.

2. All bits in registers R0 to R10 are cleared to logic 0 on power-up except bits D0 and D1 of Registers R1, R5 and R6
which are set to logic 1.

3. All memory is cleared to space (00100000) on power-up, except Row 0 Column 7 Chapter 0, which is alpha white
(00000111) as the acquisition circuit is enabled but the page is on hold.

4. TB must be set to logic 0 for normal operation.

5. The I2C-bus slave address is 0010001.

Table 8 Register description

R0 ADVANCED CONTROL - auto increments to register 1

R11/R11B SELECT selects reading of R11 or R11B
DISABLE ODD/
DISPLAY STATUS ROW when SET = 1 and R1D6 = 1 open (8-bit mode) then all the text display is blanked

DISABLE HDR ROLL disables green rolling header and time
AUTO ODD/

FREE RUN PLL will force the PLL to free run in all conditions
X24 POS automatic display of FASTEXT prompt row when logic 1

EVEN forces ODD/EVEN output LOW when logic 1

out apart from the status row, this allows the page memory to be used for
non-textural data, such as in the German TOP system

EVEN when set forces ODD/EVEN LOW if any TV picture displayed, if DISABLE

ODD/EVEN = 0

SAA5249

R1 MODE - auto increments to register 2

T0, T1 interlace/non-interlace 312/313 line control (see Table 10)
TCS ON text composite sync or direct sync select (see Table 10 for FFB mode selection)
DEW/FULL FIELD field-flyback or full-channel mode
DISABLE PKT 26 disable automatic processing of packet 26

ON/OFF acquisition circuits turned off when logic 1

ACQ
7 + P/8-BIT 7-bits with parity checking or 8-bit mode
VCS TO SCS when logic 1 enables display of messages with 60Hz input signal

R2 PAGE REQUEST ADDRESS - auto increments to register 3

COL SCO - SC2 point to start column for page request data (see Table 9)
TB must be logic 0 for normal operation

R3 PAGE REQUEST DATA - does not auto increment (see Table 9)
CLEAR B.M. when set to logic 1. Useful when transmission channel changes

R5 NORMAL DISPLAY CONTROL - auto increments to register 6
R6 NEWSFLASH/SUBTITLE DISPLAY CONTROL - auto increments to register 7; (note 1)

PON picture on
TEXT text on
COR contrast reduction on
BKGND background colour on

1996 Nov 07 25

Philips Semiconductors Preliminary specification

Integrated VIP and Teletext with

C-bus

2

C-bus

SAA5249

Background Memory Controller

R7 DISPLAY MODE - does not auto increment

BOX ON 0 boxing function allowed on Row 0
BOX ON 1-23 boxing function allowed on Rows 1 to 23
BOX ON 24 boxing function allowed on Row 24
DOUBLE HEIGHT to display double height text
BOTTOM HALF to select bottom half of page when DOUBLE HEIGHT = 1
REVEAL ON to reveal concealed text
CURSOR ON to display cursor
STATUS TOP row 25 displayed above or below the main text

R9 CURSOR ROW - auto increments to register 10

R0 to R4 active row for data written to or read from memory via the I
A0 selects display memory page (when = 0) or extension packet memory (when = 1)
CLEAR MEM. when set to 1, clears the display memory; this bit is automatically reset

R10 CURSOR COLUMN - auto increments to register 11 or 11B

C0 to C5 active column for data written to or read from memory via the I

2

R11 CURSOR DATA - does not auto increment

D0 to D7 data read from/written to memory via I2C-bus, at location pointed to by R9 and

R10. This location automatically increments each time R11 is accessed

R11B DEVICE STATUS - does not auto increment

VCS SIGNAL QUALITY indicates that the video signal quality is good and PLL is phase locked to input

video when = 1
TEXT SIGNAL QUALITY if a good teletext signal is being received when logic 1
ROM VER R0 to R4 indicated language/ROM variant. For Western European = 11000
625/525 SYNC if the input video is a 525 line signal when logic 1

Note

1. These functions have IN and OUT referring to inside and outside the boxing function respectively.

1996 Nov 07 26

Philips Semiconductors Preliminary specification

Integrated VIP and Teletext with
Background Memory Controller

Table 9 Register map for page requests (R3); notes 1 to 5

START COLUMN PRD4 PRD3 PRD2 PRD1 PRD0

0 DO CARE

magazine

1 DO CARE

page tens PT3 PT2 PT1 PT0

2 DO CARE

page units PU3 PU2 PU1 PU0

3 DO CARE

hours tens X X HT1 HT0

4 DO CARE

hours units HU3 HU2 HU1 HU0

5 DO CARE

minutes tens X MT2 MT1 MT0

6 DO CARE

minutes units MU3 MU2 MU1 MU0

HOLD MAG2 MAG1 MAG0

SAA5249

Notes

1. Abbreviations are as for Table 5 except for DO CARE bits.

2. When the DO CARE bit is set to logic 1 this means the corresponding digit is to be taken into account for page
requests. If the DO CARE bit is set to logic 0 the digit is ignored. This allows, for example, normal or timed page
selection.

HOLD is set LOW, the page is held and not updated.

3. If

4. Columns auto-increment on successive I2C-bus transmission bytes.

5. X = don't care.

Table 10 Interlace/non-interlace 312/313 line control and ODD/EVEN field detection option; notes 1 and 2

TCS ON

FFB MODE

X 0 0 interlaced 312.5/312.5 lines
X 0 1 non-interlaced 312/313 lines (note 1)
X 1 0 non-interlaced 312/313 lines (note 1)

011

111

Notes

1. Reverts to interlaced mode if a newsflash or subtitle is being displayed.

2. X = Don't care.

T1 T0 RESULT

SCS (scan composite sync) mode: FFB leading edge in first broad
pulse of field

SCS (scan composite sync) mode: FFB leading edge in second
broad pulse of field

1996 Nov 07 27

Philips Semiconductors Preliminary specification

Integrated VIP and Teletext with
Background Memory Controller

CLOCK SYSTEMS
Crystal oscillator

The crystal is a conventional 2-pin design operating at 27 MHz. It is capable of oscillating with both fundamental and third
overtone mode crystals. External components should be used to suppress the fundamental output of the third overtone
as illustrated in Fig.13.

SAA5249



8.2 pF

1 nF

3.3 µH

3.3 kΩ

27 MHz 

3rd

overtone

V

DD1

OSCOUT

100 nF15 pF

OSCIN

GNDO

3 (25)

4 (27)

5 (28)

6 (29)

SAA5249

CRYSTAL

OSCILLATOR

MLB308

Fig.13 Crystal oscillator application diagram for SOT240-1; pins in parenthesis are for SOT319-1.

Table 11 Crystal characteristics (see Fig.13)

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

Crystal (27 MHz, 3rd overtone)

C1 series capacitance − 1.7 − pF
C0 parallel capacitance − 5.2 − pF
C

L

R

r

load capacitance − 20 − pF

resonance resistance −−50 Ω
R1 series resistance − 20 −Ω
X

a

X

j

X

d

ageing −−±510

adjustment tolerance −−±25 10

drift −−±25 10

−6

/year

−6

−6

1996 Nov 07 28

Philips Semiconductors Preliminary specification

Integrated VIP and Teletext with
Background Memory Controller

CHARACTER SETS

The WST specification allows the selection of national character sets via the page header transmission bits, C12 to C14.
The basic 96 character sets differ only in 13 national option characters as indicated in the Tables 16, 17 and 18 with
reference to their table position in the basic character matrix illustrated in Table 15. The IVT1.1BMCX automatically
decodes transmission bits C12 to C14. Tables 12, 13 and 14 illustrate the character matrixes.

Character bytes are listed as transmitted from b1 to b7.

MLA663

handbook, full pagewidth

SAA5249

alphanumerics and

graphics 'space'

character

0000010

contiguous

graphics character

0110111

alphanumerics

character

1011010

separated

graphics character

0110111

= =

Fig.14 Character format.

alphanumerics or

blast-through

alphanumerics

character

0001001

separated

graphics character

1111111

background

colour

alphanumerics

character

1111111

contiguous

graphics character

1111111

display

colour

1996 Nov 07 29

Philips Semiconductors Preliminary specification

Integrated VIP and Teletext with

1

1

1

0

0

SAA5249

1

1

1

1

0

1

MBA429

1

1

0

1

Background Memory Controller

Table 12 SAA5249P/E character data input decoding, West European languages; notes 1 to 9
For character version number (11000) see Register 11B.

b

handbook, full pagewidth

B

8

I

b

T
S

b4b3b2b

0 0 0 0

0 0 1 0

0 1 0 1

1 0 0 0

7

b

6

b

5

1

column

r
o

w

0

10 0 0 1

2

30 0 1 1

40 1 0 0

5

60 1 1 0

70 1 1 1

8

91 0 0 1 steady

101 0 1 0 end box

111 0 1 1 start box ESC

121 1 0 0

131 1 0 1

141 1 1 0 SO

151 1 1 1 SI

0

0

0 or 1

0

0 or 1

0

0

0

0

0

0

0

0

0

0

0

1

1

0

1

0

0 1 22a3 3a4 5 66a77a 8 912131415

alpha -

numerics

numerics

alpha -

numerics

numerics

numerics

numerics

magenta

numerics

numerics

normal

double

black

alpha -

red

green

alpha -

yellow

alpha -

blue

alpha -

alpha -

cyan

alpha -

white

flash

height

height

graphics

black

graphics

red

graphics

green

graphics

yellow

graphics

blue

graphics
magenta

graphics

cyan

(2)

graphics

white

conceal

display

(2) (2)

contiguous

graphics

(2)

separated

graphics

(2) (2)

black

back -

ground

new

back -

ground

(1)

hold

graphics

(1) (2)

release

graphics

(1)

1

1

1

1

1

0

1

0

0

1

1

0

1

0

1

0

1

1

0

1

1

1

0

0

0

0

1

1

1996 Nov 07 30

Philips Semiconductors Preliminary specification

Integrated VIP and Teletext with
Background Memory Controller

Table 13 SAA5249P/H character data input decoding, West European languages; notes 1 to 9
For character version number (11001) see Register 11B.

SAA5249

handbook, full pagewidth

b

B

8

I

b

T

7

S

b4b3b2b

0 0 0 0

0 0 1 0

0 1 0 1

1 0 0 0

b

0

0

6

b

5

1

column

r
o

w

alpha -

numerics

0

black

alpha -

numerics

10 0 0 1

red

alpha -

numerics

2

green
alpha -

numerics

30 0 1 1

yellow

alpha -

numerics

40 1 0 0

blue

alpha -

numerics

5

magenta

alpha -

numerics

60 1 1 0

cyan

alpha -

70 1 1 1

numerics

white

8

flash

91 0 0 1 steady

101 0 1 0 end box

111 0 1 1 start box ESC

normal

121 1 0 0

height

double

131 1 0 1

height

141 1 1 0 SO

151 1 1 1 SI

0

0 or 1

0

0 or 1

0

0

0

0

0

0

0

0

0

0

1

1

0

1

0

0 1 22a3 3a4 5 66a 77a8 912131415

graphics

black

graphics

red

graphics

green

graphics

yellow

graphics

blue

graphics

magenta

graphics

cyan

(2)

graphics

white

conceal

display

(2) (2)

contiguous

graphics

(2)

separated

graphics

(1)

(2) (2)

black

back -

ground

new

back -

ground

(1)

hold

graphics

(1) (2)

release

graphics

1

0

1

1

1

0

1

0

0

1

1

0

1

0

1

0

1

1

1

1

1

0

0

1

1

0

1

1

0

0

1

1

0

0

0

1

1

1

1

0

1

1

MLA961

1

1996 Nov 07 31

Philips Semiconductors Preliminary specification

Integrated VIP and Teletext with
Background Memory Controller

Table 14 SAA5249P/T character data input decoding, West European and Turkish languages; notes 1 to 9
For character version number (11010) see Register 11B.

SAA5249

handbook, full pagewidth

b

B

8

I

b

T

7

S

b4b3b2b

0 0 0 0

0 0 1 0

0 1 0 1

1 0 0 0

b

6

0

0

b

5

1

0

column

0 1 22a3 3a4 5 66a77a 8 912131415

r
o
w

alpha -

numerics

0

black

alpha -

numerics

10 0 0 1

red

alpha -

numerics

2

green
alpha -

numerics

30 0 1 1

yellow
alpha -

numerics

40 1 0 0

blue

alpha -

numerics

5

magenta

alpha -

numerics

60 1 1 0

cyan

alpha -

70 1 1 1

numerics

white

8

flash

91 0 0 1 steady

101 0 1 0 end box

111 0 1 1 start box ESC

normal

121 1 0 0

height

double

131 1 0 1

height

141 1 1 0 SO

151 1 1 1 SI

0

0

0

0

graphics

black

graphics

red

graphics

green

graphics

yellow

graphics

blue

graphics
magenta

graphics

cyan

(2)

graphics

white

conceal

display

(2) (2)

contiguous

graphics

(2)

separated

graphics

(2) (2)

black

back -

ground

new

back -

ground

(1)

hold

graphics

(1) (2)

release

graphics

0 or 1

0

0 or 1

0

0

0

0

0

0

0

0

1

1

1

0

(1)

1

1

1

1

1

0

1

0

1

1

0

1

0

1

0

1

1

1

1

1

0

0

1

1

0

1

1

0

0

1

0

1

0

0

1

1

1

1

0

MBA431

1

1

1

1996 Nov 07 32

Philips Semiconductors Preliminary specification

Integrated VIP and Teletext with

1

1

1

0

0

SAA5249

1

1

1

0

1

1

1

1

0

1

Background Memory Controller

Table 15 SAA5249P/R character data input decoding, Baltic and Cyrillic languages; notes 1 to 9
For character version number (11101) see Register 11B.

B

b

8

I

b

T
S

b4b3b2b

0 0 0 1

0 1 0 0

0 1 0 1

andbook, full pagewidth

0 1 1 1

7

b

6

b

5

1

0

column

r
o
w

alpha -

numerics

00 0 0 0

black

alpha -

numerics

1

alpha -

numerics

20 0 1 0

green
alpha -

numerics

30 0 1 1

yellow

alpha -

numerics

4

blue

alpha -

numerics

5

magenta

alpha -

numerics

60 1 1 0

cyan

alpha -

7

numerics

white

81 0 0 0 flash

steady

91 0 0 1

101 0 1 0 end box

0

0 or 1

0

0 or 1

0

0

0

0

0

0

0

0

0

0

0

1

1

0

1

0

0

1 22a3 3a4 5 66a 77a8 912131415

graphics

black

graphics

(2)

(2)

(2)

red

graphics

green

graphics

yellow

graphics

blue

graphics

magenta

graphics

cyan

graphics

white

conceal

display

contiguous

graphics

separated

graphics

(2)

red

1

1

1

1

1

0

1

0

0

1

1

0

1

0

1

0

1

1

1

0

1

0

1

1

0

0

0

1

111 0 1 1 start box TWIST

(2) (2)

height

height

(1)

(1)

black

back -

ground

new

back -

ground

hold

graphics

release

graphics

(2)

normal

121 1 0 0

double

131 1 0 1

141 1 1 0 SO

151 1 1 1 SI

1996 Nov 07 33

MBA648 - 1

Philips Semiconductors Preliminary specification

Integrated VIP and Teletext with
Background Memory Controller

Notes to Tables 12, 13, 14 and 15

1. These control characters are reserved for compatibility with other data codes.

2. These control characters are presumed before each row begins.

3. Control characters shown in Columns 0 and 1 are normally displayed as spaces.

4. Characters may be referred to by column and row (for example 2/5 refers to %).

5. Black represents displayed colour. White represents background.

6. The SAA5249 national option characters are illustrated in Tables 16, 17,18 and 19.

7. Characters 8/6, 8/7, 9/5, 9/6 and 9/7 are special characters for combining with character 8/5
(E, H and T codes only).

8. National option characters will be displayed according to the setting of control bits C12 to C14. These will be mapped
into the basic code table into positions shown in Tables 16, 17, 18 and 19.

9. Columns 2a, 3a, 6a and 7a are displayed in graphics mode.

SAA5249

1996 Nov 07 34

Philips Semiconductors Preliminary specification

f

Integrated VIP and Teletext with
Background Memory Controller

SAA5249

6/0

NC

7/11

5/11

NC

NC

7/12

5/12

NC

NC

7/13

5/13

NC

NC

7/14

5/14

NC

NC

MLA630

NC

5/15

ull pagewidth

NC

2/0 2/8 3/0 3/8 4/0 4/8 5/0 5/8 7/86/8 7/0

2/9 3/1 3/9 4/1 4/9 5/1 5/9 6/1 6/9 7/1 7/9

2/1

2/2 2/10 3/2 3/10 4/2 4/10 5/2 5/10 6/2 6/10 7/2 7/10

2/11 3/3 3/11 4/3 4/11 5/3 6/3 6/11 7/3

2/3

2/12 3/4 3/12 4/4 4/12 5/4 6/4 6/12 7/4

NC

2/4

Table 16 SAA5249 basic character matrix; note 1

1996 Nov 07 35

NC

2/5 2/13 3/5 3/13 4/5 4/13 5/5 6/5 6/13 7/5

2/6 2/14 3/6 3/14 4/6 4/14 5/6 6/6 7/6

2/7 2/15 3/7 3/15 4/7 4/15 5/7 6/7 6/15 7/7 7/15

Note

1. Where: NC = national option character position.

Philips Semiconductors Preliminary specification

Integrated VIP and Teletext with
Background Memory Controller

Table 17 SAA5249P/E national option character set; note 1

SAA5249

andbook, full pagewidth

LANGUAGE

C12 C13 C14

ENGLISH

GERMAN

SWEDISH

ITALIAN

FRENCH

SPANISH

(1)

PHCB

000

001

010

011

100

101

2 / 3

2 / 4 4 / 0

CHARACTER POSITION (COLUMN / ROW)

5 / 11 5 / 12 5 / 13 5 / 14 5 / 15 6 / 0 7 / 11 7 / 12 7 / 13 7 / 14

Note

1. PHCB are the Page Header Control Bits. Other combinations default to English.

MLB458

1996 Nov 07 36

Philips Semiconductors Preliminary specification

Integrated VIP and Teletext with
Background Memory Controller

Table 18 SAA5249P/H national option character set; note 1

SAA5249

handbook, full pagewidth

LANGUAGE

C12 C13 C14

POLISH

GERMAN

SWEDISH

SERBO-CROAT

CZECHOSLOVAKIA

RUMANIAN

(1)

PHCB

000

001

010

101

110

111

2 / 3

2 / 4 4 / 0

CHARACTER POSITION (COLUMN / ROW)

5 / 11 5 / 12 5 / 13 5 / 14 5 / 15 6 / 0 7 / 11 7 / 12 7 / 13 7 / 14

MLA966

Note

1. PHCB are the Page Header Control Bits. Other combinations default to German. Only the above characters change
with the PHCB. All other characters in the basic set are shown in Table 15.

1996 Nov 07 37

Philips Semiconductors Preliminary specification

Integrated VIP and Teletext with
Background Memory Controller

Table 19 SAA5249P/R national option character set; note 1

SAA5249

andbook, full pagewidth

LANGUAGE

ESTONIAN

LETTISH /
LITHUANIAN

RUSSIAN

(1)

PHCB

C12 C13 C14

010

011

100

CHARACTER POSITION (COLUMN / ROW)

2 / 3

2 / 4 4 / 0

234567

0

1

2

3

4

5

6

5 / 11 5 / 12 5 / 13 5 / 14 5 / 15 6 / 0 7 / 11 7 / 12 7 / 13 7 / 14

7

8

9

10

11

12

13

14

15

MEA597

Note

1. PHCB are the Page Header Control Bits. Other combinations default to Estonian.

1996 Nov 07 38

Philips Semiconductors Preliminary specification

Integrated VIP and Teletext with
Background Memory Controller

PACKAGE OUTLINES

SAA5249

DIP48: plastic dual in-line package; 48 leads (600 mil)

D

seating plane

L

Z

48

pin 1 index

e

b

SOT240-1

M

E

A

2

A

A

1

w M

b

1

25

E

c

(e )

1

M

H

1

0 5 10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

A

A

UNIT

inches

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

max.

mm

OUTLINE
VERSION

SOT240-1

1 2

min.

max.

1.4

1.14

0.055

0.045

IEC JEDEC EIAJ

b

b

1

0.53

0.38

0.021

0.015

0.014

0.009

REFERENCES

cD E e M

0.36

62.60

0.23

61.60

2.46

2.42

1996 Nov 07 39

14.22

13.56

0.56

0.53

24

(1)(1)

e

L

1

3.90

3.05

0.15

0.12

M

E

15.88

15.24

0.63

0.60

EUROPEAN

PROJECTION

18.46

15.24

0.73

0.60

H

w

0.2542.54 15.24

0.010.10 0.60

ISSUE DATE

92-11-17
95-01-25

max.

0.083 0.19 0.014 0.16

(1)

Z

2.14.9 0.36 4.06

Philips Semiconductors Preliminary specification

Integrated VIP and Teletext with
Background Memory Controller

QFP64: plastic quad flat package;
64 leads (lead length 1.95 mm); body 14 x 20 x 2.7 mm; high stand-off height

c

y

X

SAA5249

SOT319-1

51 33

52

pin 1 index

64

1

w M

b

0.25

p

D

H

D

cE

p

0.50

0.25

0.35

0.13

e

DIMENSIONS (mm are the original dimensions)

mm

A

max.

3.3

0.36

0.10

2.87

2.57

UNIT A1A2A3b

A

32

Z

E

e

H

E

E

w M

b

p

20

19

Z

D

B

0 5 10 mm

scale

(1)

(1) (1)(1)

D

20.1

19.9

eH

H

14.1

13.9

24.2

1

23.6

D

v M

A

v M

B

LLpQZywv θ

E

18.2

17.6

1.0

0.6

1.43

1.23

A

2

A

A

1

detail X

0.2 0.10.21.95

Q

(A )

3

θ

L

p

L

Z

E

D

1.2

0.8

o

7

o

0

1.2

0.8

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

OUTLINE
VERSION

SOT319-1

IEC JEDEC EIAJ

REFERENCES

1996 Nov 07 40

EUROPEAN

PROJECTION

ISSUE DATE

92-11-17
95-02-04

Philips Semiconductors Preliminary specification

Integrated VIP and Teletext with
Background Memory Controller

SAA5249

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“IC Package Databook”

DIP

OLDERING BY DIPPING OR BY WA VE

S
The maximum permissible temperature of the solder is

260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.

EPAIRING SOLDERED JOINTS

R
Apply a low voltage soldering iron (less than 24 V) to the

lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.

QFP

REFLOW SOLDERING
Reflow soldering techniques are suitable for all QFP

packages.
The choice of heating method may be influenced by larger

plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our

Reference Handbook”

(order code 9398 652 90011).

). If the

stg max

“Quality

(order code 9397 750 00192).

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary from
50 to 300 seconds depending on heating method. Typical
reflow temperatures range from 215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheat for 45 minutes at 45 °C.

WAVE SOLDERING
Wave soldering is not recommended for QFP packages.

This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

If wave soldering cannot be avoided, the following
conditions must be observed:

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)
soldering technique should be used.

• The footprint must be at an angle of 45° to the board

direction and must incorporate solder thieves
downstream and at the side corners.

Even with these conditions, do not consider wave
soldering the following packages: QFP52 (SOT379-1),
QFP100 (SOT317-1), QFP100 (SOT317-2),
QFP100 (SOT382-1) or QFP160 (SOT322-1).

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured. Maximum permissible solder
temperature is 260 °C, and maximum duration of package
immersion in solder is 10 seconds, if cooled to less than
150 °C within 6 seconds. Typical dwell time is 4 seconds
at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

R

EPAIRING SOLDERED JOINTS

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

1996 Nov 07 41

Philips Semiconductors Preliminary specification

Integrated VIP and Teletext with
Background Memory Controller

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

SAA5249

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

PURCHASE OF PHILIPS I

2

C COMPONENTS

2

Purchase of Philips I
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.

C components conveys a license under the Philips’ I2C patent to use the

1996 Nov 07 42

Philips Semiconductors Preliminary specification

Integrated VIP and Teletext with
Background Memory Controller

NOTES

SAA5249

1996 Nov 07 43

Philips Semiconductors – a worldwide company

Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

Tel. [phone], Fax. [phone]
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. [phone], Fax. [phone]

Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,
Tel. [phone], Fax. [phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. [phone]

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. [phone], Fax. [phone]

Colombia: see South America
Czech Republic: see Austria
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,

Tel. [phone], Fax. [phone]
Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. [phone], Fax. [phone]/xxx
France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex,

Tel. [phone], Fax. [phone]
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,

Tel. [phone], Fax. [phone]
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,

Tel. [phone], Fax. [phone]

Hungary: see Austria
India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd.

Worli, MUMBAI 400 018, Tel. [phone], Fax. [phone]

Indonesia: see Singapore
Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. [phone], Fax. [phone]
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180,

Tel. [phone], Fax. [phone]
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,

20124 MILANO, Tel. [phone], Fax. [phone]
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,

Tel. [phone], Fax. [phone]
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,

Tel. [phone], Fax. [phone]
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,

Tel. [phone], Fax. [phone]
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,

Tel. [phone]

Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. [phone], Fax. [phone]

South America: Rua do Rocio 220, 5th floor, Suite 51,
04552-903 São Paulo, SÃO PAULO - SP, Brazil,
Tel. [phone], Fax. [phone]

Spain: Balmes 22, 08007 BARCELONA,
Tel. [phone], Fax. [phone]

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone], Fax. [phone]

Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66,
Chung Hsiao West Road, Sec. 1, P.O. Box 22978,
TAIPEI 100, Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. 1996 SCA52
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

Printed in The Netherlands 537021/50/02/pp44 Date of release: 1996 Nov07 Document order number: 9397 750 01014