Page 1
INTEGRATED CIRCUITS
DATA SH EET
SAA4995WP
PANorama-IC (PAN-IC)
Preliminary specification
File under Integrated Circuits, IC02
1997 Jun 10
Page 2
Philips Semiconductors Preliminary specification
PANorama-IC (PAN-IC) SAA4995WP
FEATURES
• Horizontal sample rate conversion in both zoom and
compress direction, with a sample rate conversion factor
between 0.5 and 2 (in 384 steps)
• Dynamic sample rate conversion for panorama mode
display e.g. 4 : 3 material on a 16 : 9 display
• Dynamic sample rate conversion for amaronap mode
display of e.g. 16 : 9 material on a 4 : 3 display
• Operates with 1fh and 2f
h
• Programmable via microcontroller SNERT
(Synchronous No parity Eight bit Receive Transmit) bus.
GENERAL DESCRIPTION
The PAN-IC is an add-on IC to be used, for example,
between analog-to-digital conversion and a serial (field)
memory. The device performs the following tasks:
• Linear horizontal sample rate conversion in both zoom
and compress direction, with a sample rate conversion
factor between 0.5 and 2
• Dynamic sample rate conversion for panorama mode
display of e.g. 4 : 3 material on a 16 : 9 display
• Dynamic sample rate conversion for amaronap mode
display of e.g. 16 : 9 material on a 4 : 3 display.
The PAN-IC has the ability to increase the data rate from
the ADC to a maximum of twice the data rate at the output.
To achieve this a clock rate at twice the normal output
clock rate is needed to write data to the memory.
All actions to generate a lower data rate, produces disable
cycles in Write Enable (WE).
QUICK REFERENCE DATA
SYMBOL PARAMETER MIN. TYP. MAX. UNIT
V
I
DD
f
CLK
T
DD
amb
supply voltage 4.5 5 5.5 V
supply current − 110 − mA
operating clock frequency −−33 MHz
operating ambient temperature 0 − 70 °C
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME DESCRIPTION VERSION
SAA4995WP PLCC44 plastic leaded chip carrier; 44 leads SOT187-2
1997 Jun 10 2
Page 3
Philips Semiconductors Preliminary specification
PANorama-IC (PAN-IC) SAA4995WP
BLOCK DIAGRAM
handbook, full pagewidth
Y
I7
to
Y
I0
UI1/U
and
VI1/V
WE
I
SNDA
SNCL
VRST
I0
I0
CL16
37 to 44
1 to 4
7
CL16 CLK
34
35
36
CLK
5 31
CL16
CL16
C
C
'0'
1
2
SECAM
NOTCH
CLK
V
DD1
10 12
MUX
notch
GND1
V
CLK
SAA4995WP
INTEGRATORMUX
X0rX0IX1rX1IX2rX
SNERT BUS INTERFACE
GND2
DD2
15 16
FRONT-END
FRONT-END
INTEGRATOR
LINE CONTROL
2I
in-phase
V
VPD
VPD
out-phase
DD3
33 30
SPL
init
GND3
BACK-END
BACK-END
+
C
0
notch
V
DD4
VPD
VPD
8 9
GND4
6 32
∆Y∆UV
DTO
C0
C1
C2
29 to 22
21 to 18
Y
O7
to
Y
O0
VO0/V
O1
and
UO0/U
O1
17
WE
O
14
WE
od
13
T1
11
T0
Fig.1 Block diagram.
1997 Jun 10 3
TEST
SCANIN
MGK176
Page 4
Philips Semiconductors Preliminary specification
PANorama-IC (PAN-IC) SAA4995WP
PINNING
SYMBOL PIN DESCRIPTION
U
I1
U
I0
V
I1
V
I0
1 U input bit 1
2 U input bit 0
3 V input bit 1
4 V input bit 0
CL16 5 half system clock
V
DD4
WE
I
6 supply voltage 4
7 write enable input
TEST 8 test mode switch
SCANIN 9 input for scan chain
V
DD1
10 supply voltage 1
T0 11 test mode switch 0
GND1 12 ground 1
T1 13 test mode switch 1
WE
V
DD2
od
14 write enable odd samples
15 supply voltage 2
GND2 16 ground 2
WE
V
O0
V
O1
U
O0
U
O1
Y
O0
Y
O1
O
17 write enable output
18 V output bit 0
19 V output bit 1
20 U output bit 0
21 U output bit 1
22 luminance output bit 0
23 luminance output bit 1
SYMBOL PIN DESCRIPTION
Y
O2
Y
O3
Y
O4
Y
O5
Y
O6
Y
O7
24 luminance output bit 2
25 luminance output bit 3
26 luminance output bit 4
27 luminance output bit 5
28 luminance output bit 6
29 luminance output bit 7
GND3 30 ground 3
CLK 31 system clock
GND4 32 ground 4
V
DD3
33 supply voltage 3
SNDA 34 data input from interface
SNERT bus
SNCL 35 clock input from interface
SNERT bus
VRST 36 reset input in the vertical
blanking interval
Y
I7
Y
I6
Y
I5
Y
I4
Y
I3
Y
I2
Y
I1
Y
I0
37 luminance input bit 7
38 luminance input bit 6
39 luminance input bit 5
40 luminance input bit 4
41 luminance input bit 3
42 luminance input bit 2
43 luminance input bit 1
44 luminance input bit 0
1997 Jun 10 4
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Philips Semiconductors Preliminary specification
PANorama-IC (PAN-IC) SAA4995WP
handbook, full pagewidth
WE
TEST
SCANIN
V
DD1
T0
GND1
T1
WE
od
V
DD2
GND2
WE
DD4
CL16
VI0VI1UI0UI1Y
V
6
5
4
3
2
7
I
8
9
10
11
12
13
14
15
16
17
O
18
19
O1UO0UO1YO0YO1YO2
O0
V
V
SAA4995WP
21
20
22
I0
I1
YI2YI3Y
Y
1
44
43
42
23
24
25
26
O3
YO4YO5Y
Y
I4
41
40
39
Y
I5
Y
38
I6
37
Y
I7
36
VRST
SNCL
35
34
SDNA
V
33
DD3
GND4
32
CLK
31
30
GND3
Y
29
O7
27
28
MGK175
O6
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION
The PAN-IC is an add-on IC to be used, for example,
between analog-to-digital conversion and a serial (field)
memory. The device performs the following tasks:
• Linear horizontal sample rate conversion in both zoom
and compress direction, with a sample rate conversion
factor between 0.5 and 2
• Dynamic sample rate conversion for panorama mode
display of e.g. 4 : 3 material on a 16 : 9 display
• Dynamic sample rate conversion for amaronap mode
display of e.g. 16 : 9 material on a 4 : 3 display.
The PAN-IC has the ability to increase the data rate from
the ADC (maximum 16 MHz in a 16/32 MHz concept) to a
maximum of twice the data rate. For this, a 32 MHz clock
rate is needed to write to the memory. All actions to
generate a lower data rate produces disable cycles in write
enable.
In panorama and amaronap modes, the sample rate
conversion factor is modulated along the video line.
In the centre of the line a high quality compression (e.g.
4
with a factor
⁄3) has to be made. Towards the sides of the
line, more and more expansion and compression
respectively is made. The sample rate conversion factor
over a line will have a bathtub shape, with parameters
illustrated in Fig.3:
• X0l and X0r, where in-between a constant data rate is
maintained (area I) and starting points from where a
curve can be programmed for its 2nd derivative (in
areas II and V)
• X1l and X1r, points from where a new curve can be
programmed for its 2nd derivative (for areas III and IV)
• X2l corresponds to the first sample in the output data
stream, defined by start of WE
I
• X2r corresponds to the last sample in the output data
stream, defined by the programmed number of samples
• C1, which controls the second derivatives of the data
rate in areas II and V
• C2, which controls the second derivatives of the data
rate in areas III and IV.
1997 Jun 10 5
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Philips Semiconductors Preliminary specification
PANorama-IC (PAN-IC) SAA4995WP
Interpolation function
The interpolation for phase positions between the original
samples, is achieved with a variable phase delay filter with
10 taps for luminance signals and 4 taps for chrominance
signals. For luminance the PAN-IC supplies samples up to
32 MHz. For chrominance the PAN-IC supplies each
U and V samples with a data rate of 8 MHz (max).
Processing control in the PAN-IC
The compress factor (see Fig.4) at any position in the lines
is a function of the dynamically changing DTO-increment.
When DTO
DTO
incr
unchanged; when DTO
= 255, the sample rate is divided by 2; when
incr
= 0, the sample rate in the PAN-IC remains
= −128, the sample rate is
incr
doubled.
Control of number of samples per line
Three possibilities exist for the relationship between the
end of WE
and the required number of samples per line for
I
storage in the field memory:
• WEI negative edge coincides with the required last
sample in the line; standard operation.
• WEI negative edge is reached before the present last
sample in the line was required; extra dummy WE cycles
will be generated at the maximum rate (zoom factor 2)
to arrive at the required number of samples per line.
• The required number of samples per line is reached
before WEI negative edge; the DTO calculations will
continue until the required number of samples is
reached, but without generation of WE cycles.
The programmed number of samples per line is thus
always realized, independent of all other controls (unless
the line period becomes insufficient to store up to the last
sample in a line). When using odd/even sample
distribution, the programmed number of samples refers to
the number of samples in each data stream.
Consequently, the total number of samples is twice as
many.
There is an offset in the programmed number of samples
compared to the effective number of samples per line.
• Effective number of Y samples = 4 × (programmed
number of samples + 1)
• Effective number of UV samples = 1 × (programmed
number of samples + 1)
SECAM Y notch
A notch filter at the Y input of the PAN-IC can be switched
on. The purpose of this filter is to prevent artefacts from
scan velocity modulation with SECAM inputs. The notch
filter is an FIR filter with coefficients (−103030−1).
When fs= 16 MHz, the notch frequency is 4 MHz; the
maximum gain of the filter is +3 dB at 2 and 6 MHz.
Timing
The inputs are related to CL16 (half system clock). This
clock is used for reference in the PAN-IC from the CL16
pin. The system clock must have a fixed phase relationship
to the CL16 enable signal (one clock system).
Relationship of WE to video data
WE inputs and outputs may be used with either coincident
or advanced WE to video timing (see Fig.5). The advanced
WE to video timing is applicable to field memories, such as
the SAA4955TJ. The input and output WEs of the PAN-IC
can be programmed separately to either timing by the
in-phase and out-phase bits.
Odd/even sample distribution
The PAN-IC usually delivers a complete YUV data stream
to one receiving device, e.g. a field memory. Optionally, a
data stream can be split into odd and even samples, to be
received by two receiving devices.
The relationship between Y and UV samples is then
non-trivial (see Tables 1 to 4).
1997 Jun 10 6
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Philips Semiconductors Preliminary specification
PANorama-IC (PAN-IC) SAA4995WP
NO SPLITTING INTO ODD AND EVEN SAMPLE STREAM
Table 1 Normal output YUV data stream
EOEOEOEOEOEOE
0
Y
0
UV
76
S
PLITTING INTO ODD AND EVEN SAMPLE STREAM
Keeps corresponding parts of the UV samples in one stream (UV0, UV8, etc. in even stream and UV4, UV12, etc. in odd
stream): The odd data stream misses two samples at the start of a line and has two dummy samples at the end of the
line, to keep the UV format correct and maintain the same line length as for the even stream (In the odd stream, the last
two Y samples and the last U and V samples of a line are not valid).
Table 2 Even YUV data stream
E − E − E − E − E − E − E
0
Y
0
UV
76
1
Y
0
UV
54
− Y
− UV
2
Y
0
UV
32
2
0
54
3
Y
0
UV
10
− Y
− UV
4
Y
4
UV
76
4
0
32
5
Y
4
UV
54
− Y
− UV
6
Y
4
UV
32
6
0
10
7
Y
4
UV
10
− Y
− UV
8
Y
8
UV
76
8
8
76
9
Y
8
UV
54
− Y
− UV
Y10Y
8
UV
32
10
8
54
11
8
UV
10
− Y
− UV
UV
12
Y
12
76
12
12
32
Table 3 Odd YUV data stream
−−−−−O−O−O−O−
−−−−−Y
−−−−−UV
5
4
76
−Y
− UV
7
4
54
−Y
− UV
9
4
32
−Y11−
− UV
4
10
−
The even and odd data streams given in Tables 2 and 3 can be distributed to two receiving devices with input enable
facilities. A separate input signal for each of the receiving devices must then be applied while the even YUV data stream
and odd YUV data stream are again combined.
OMBINED ODD/EVEN OUTPUT YUV DATA STREAM
C
Table 4 Distribution with odd/even input enable signals
E − E − E − EOEOEOE
0
Y
0
UV
76
−Y
− UV
2
0
54
−Y
− UV
4
0
32
5
Y
4
UV
76
6
Y
0
UV
10
7
Y
4
UV
54
8
Y
8
UV
75
9
Y
4
UV
32
Y10Y
8
UV
54
UV
11
10
12
Y
4
UV
8
32
1997 Jun 10 7
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Philips Semiconductors Preliminary specification
PANorama-IC (PAN-IC) SAA4995WP
handbook, full pagewidth
area:
sample
rate
positions:
active period
IV
C
2
X
2I
X
V
C
1
1I
X
0I
I
C
0
II
C
1
X
0r
III
C
2
X
1r
X
MGK177
2r
Fig.3 Panorama mode.
handbook, full pagewidth
2
compress
factor
1
0.5
−256 −128 0
Fig.4 Compress factor.
1997 Jun 10 8
DTO
incr
MGK178
256
Page 9
Philips Semiconductors Preliminary specification
PANorama-IC (PAN-IC) SAA4995WP
handbook, full pagewidth
CL16
WE
I
WE
I
YUV
I
CLK
WEO/WE
WEO/WE
YUV
od
od
O
Fig.5 WE timing.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
with in-phase = 0
with in-phase = 1
with out-phase = 0
with out-phase = 1
MGK179
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
V
I
o/out
DD
, V
i
o
supply voltage −0.5 +6.5 V
input and output voltages −0.5 VDD+ 0.5 V
output current per output pin − 20 mA
P/out power dissipation per output pin − 100 mW
T
T
V
stg
amb
ESD
storage temperature −55 +140 °C
operating ambient temperature −40 +85 °C
electrostatic handling for all pins note 1 −±2000 V
note 2 −±300 V
Notes
1. Human body model: C = 100 pF, R = 1.5 kΩ, V = 2 kV.
2. Machine model: C = 200 pF, R = 0 Ω, V = 300 V.
THERMAL CHARACTERISTICS
SYMBOL PARAMETER VALUE UNIT
R
th j-a
thermal resistance from junction to ambient in free air 50 K/W
1997 Jun 10 9
Page 10
Philips Semiconductors Preliminary specification
PANorama-IC (PAN-IC) SAA4995WP
CHARACTERISTICS
V
= 5.0 V; T
DD
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
DD
I
DD
f
CLK
f
CL16
V
IL
V
IH
C
i
V
OL
V
OH
t
su(i)(D)
t
h(i)(CL16)
t
su(i)(CL16)
t
h(i)(CL16)
t
h(o)
t
d
T
amb
T
j
=25°C; unless otherwise specified.
amb
supply voltage 4.5 5 5.5 V
supply current − 110 − mA
operating frequency (CLK) −−33 MHz
operating frequency (CL16) −
1
⁄2f
CLK
− MHz
LOW level input voltage −−0.8 V
HIGH level input voltage 2.0 − V
DD
V
input capacitance − 10 15 pF
LOW level output voltage Io=4mA −−0.4 V
HIGH level output voltage Io= −4 mA 2.6 3.4 − V
input set-up time with respect to CL16
rising edge
input hold time with respect to CL16
rising edge
input set-up time with respect to CLK
except pins SNDA, SNCL,
8 −−ns
VRST and CLK; see Fig.6
except pins SNDA, SNCL,
0 −−ns
VRST and CLK; see Fig.6
see Fig.6 7 −−ns
rising edge
input hold time with respect to CLK
see Fig.6 3 −−ns
rising edge
output hold time with respect to CLK CL= 7 pF 5 −−ns
output delay time with respect to CLK CL=15pF −−19 ns
operating ambient temperature 0 − 70 °C
junction temperature −−125 °C
handbook, full pagewidth
CLK
t
t
su(i)(D)
h(i)(CL16)
t
h(i)(D)
t
CL16
data
input
data
output
t
su(i)(CL16)
Fig.6 Clock timing.
1997 Jun 10 10
h(o)
t
su(i)(CL16)
t
d
t
h(i)(CL16)
data validdata valid
MGK180
Page 11
Philips Semiconductors Preliminary specification
PANorama-IC (PAN-IC) SAA4995WP
MICROCONTROLLER BUS TIMING (SNERT BUS)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
T
cy(SNCL)
t
su(i)
t
h(i)
t
h(o)(D)
t
d
SNCL cycle time see Fig.7 1 −µs
input data set-up time see Fig.7 90 − ns
input data hold time see Fig.7 50 − ns
output data hold time see Fig.7 0 − ns
output data delay time see Fig.7 − 700 ns
data
valid
T
cy(SNCL)
data
valid
data
valid
MGK181
handbook, full pagewidth
SNCL
SNDA
(receiver
mode)
SNDA
(transmitter
mode)
LSB
data
valid
t
su(i)
data
valid
t
h(i)
t
d
t
h(o)(D)
Fig.7 SNERT bus interface timing.
MICROCONTROLLER BUS CONTROL (SNERT BUS)
The following control table applies (Table 5), for control via the microcontroller bus (SNERT bus, consisting of SNCL,
SNDA and VRST signals). Data communication is by writing to the PAN-IC (address 40H to 48H) and reading from it
(address 49H)
Table 5 SNERT-bus control
ADDRESS
(HEX)
40 X
FUNCTION # OF BITS
1l
8 7 : 0 definition of X1l with a resolution of 4 samples; see Fig.3 and
BIT
POSITION
REMARKS
note 1
41 X
0l
8 7 : 0 definition of X0l with a resolution of 4 samples; see Fig.3 and
note 1
42 X
0r
8 7 : 0 definition of X0r with a resolution of 4 samples; see Fig.3 and
note 1
43 X
1r
8 7 : 0 definition of X1r with a resolution of 4 samples; see Fig.3 and
note 1
44 output samples
per line
8 7 : 0 resolution of 4 luminance samples; actual #
samples = (programmed # samples + 1) × 4; note 2
1997 Jun 10 11
Page 12
Philips Semiconductors Preliminary specification
PANorama-IC (PAN-IC) SAA4995WP
ADDRESS
(HEX)
45 C
FUNCTION # OF BITS
0
8 7 : 0 constant DTO
BIT
POSITION
REMARKS
value for area I, MSB extended by zoom bit
incr
at address 48 (twos complement value); see Figs 3 and 4
46 C
1
6 5 : 0 2nd derivatives for DTO
for areas II and V
incr
(twos complement value); see Figs 3 and 4
distribution 1 6 enables odd/even sample distribution; see Tables 1 to 4
47 C
2
6 5 : 0 2nd derivatives for DTO
for areas III and IV
incr
(twos complement value)
test 1 1 6 test bit, must be logic 0 in normal operation
notch 1 7 SECAM Y notch on/off (logic 1 = on, logic 0 = off)
48 zoom bit 1 0 logic 1 = zoom, logic 0 = compress in area I
in-phase 1 1 logic 1 = shifted relation WE_IN to input data; see Fig.5
out-phase 1 2 logic 1 = shifted relation WE
/WEod to output data; see Fig.5
O
init 1 3 circuitry is initialized at VRST pulse
vrst_xfer 1 4 new settings are activated at VRST pulse
keep 1 5 compression curve is kept from last active line in field
test 2 1 6 test bit, must be logic 0 in normal operation
adapt 1 7 adapt bit, must be logic 0 in normal operation
49 identify read 8 read bits 7 : 0 PAN-IC identifies by pulling all bits LOW (hardware cluck)
Notes
1. For a symmetrical bathtub curve Xnl+Xnr= output samples per line + 1.
2. WEI falling edge delay to the WEO latest sample should not be equal to the pipeline delay. This can be controlled
with the WEI length via the microcontroller.
TEST
The test mode can be chosen via pins TEST, T0 and T1.
Table 6 Test modes
PIN NAME
MODE
TEST T1 T0
Functional test 0 X
Test mode on 1 X
Note
1. X = don’t care.
1997 Jun 10 12
(1)
(1)
(1)
X
(1)
X
Page 13
Philips Semiconductors Preliminary specification
PANorama-IC (PAN-IC) SAA4995WP
PACKAGE OUTLINE
PLCC44: plastic leaded chip carrier; 44 leads
e
D
y
40
44
1
pin 1 index
6
β
k
717
e
D
H
D
X
2939
SOT187-2
e
E
A
Z
E
28
H
E
E
A
A
1
A
e
18
k
1
v M
Z
D
A
4
B
v M
B
w M
detail X
b
p
b
1
(A )
3
L
p
0 5 10 mm
scale
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)
UNIT A
mm
0.180
inches
0.165
A
1
min. max. max. max. max.
4.57
0.51
4.19
0.020
A
0.25
0.01
A
4
3
3.05
0.12
b
0.53
0.33
0.021
0.013
b
p
1
0.81
0.66
0.032
0.026
(1)
D
16.66
16.51
0.656
0.650
(1)
E
eH
16.66
1.27
16.51
0.656
0.05
0.650
e
D
16.00
14.99
0.630
0.590
e
E
16.00
14.99
0.630
0.590
17.65
17.40
0.695
0.685
Note
1. Plastic or metal protrusions of 0.01 inches maximum per side are not included.
OUTLINE
VERSION
SOT187-2
IEC JEDEC EIAJ
112E10 MO-047AC
REFERENCES
1997 Jun 10 13
H
E
D
17.65
17.40
0.695
0.685
k
1.22
1.07
0.048
0.042
k
0.51
0.020
1
0.057
0.040
L
p
1.44
1.02
EUROPEAN
PROJECTION
(1) (1)
Z
Z
E
D
ywv β
0.18 0.100.18
0.007 0.0040.007
2.16
0.085
2.16
0.085
o
45
ISSUE DATE
92-11-17
95-02-25
Page 14
Philips Semiconductors Preliminary specification
PANorama-IC (PAN-IC) SAA4995WP
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our
“IC Package Databook”
Reflow soldering
Reflow soldering techniques are suitable for all PLCC
packages.
The choice of heating method may be influenced by larger
PLCC packages (44 leads, or more). If infrared or vapour
phase heating is used and the large packages are not
absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our
Reference Handbook”
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
(order code 9398 652 90011).
“Quality
(order code 9398 510 63011).
Wave soldering
Wave soldering techniques can be used for all PLCC
packages if the following conditions are observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
• The package footprint must incorporate solder thieves at
the downstream corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Repairing soldered joints
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
1997 Jun 10 14
Page 15
Philips Semiconductors Preliminary specification
PANorama-IC (PAN-IC) SAA4995WP
DEFINITIONS
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of this specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1997 Jun 10 15
Page 16
Philips Semiconductors – a worldwide company
Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,
Tel. +61 2 9805 4455, Fax. +61 2 9805 4466
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,
Tel. +43 1 60 101, Fax. +43 1 60 101 1210
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773
Belgium: see The Netherlands
Brazil: seeSouth America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15thfloor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 689 211, Fax. +359 2 689 102
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700
Colombia: see South America
Czech Republic: see Austria
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,
Tel. +45 32 88 2636, Fax. +45 31 57 0044
Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615800, Fax. +358 9 61580920
France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex,
Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 23 53 60, Fax. +49 40 23 536 300
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,
Tel. +30 1 4894 339/239, Fax. +30 1 4814 240
Hungary: seeAustria
India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd.
Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722
Indonesia: see Singapore
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,
Tel. +81 3 3740 5130, Fax. +81 3 3740 5077
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381
Middle East: see Italy
Netherlands: Postbus 90050, 5600PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811
Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341
Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. +48 22 612 2831, Fax. +48 22 612 2327
Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,
Tel. +65 350 2538, Fax. +65 251 6500
Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. +27 11 470 5911, Fax. +27 11 470 5494
South America: Rua do Rocio 220, 5th floor, Suite 51,
04552-903 São Paulo, SÃO PAULO - SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 829 1849
Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 3 301 6312, Fax. +34 3 301 4107
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 632 2000, Fax. +46 8 632 2745
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2686, Fax. +41 1 481 7730
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793
Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. +90 212 279 2770, Fax. +90 212 282 6707
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381
Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1997 SCA54
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Internet: http://www.semiconductors.philips.com
Printed in The Netherlands 547047/20/01/pp16 Date of release: 1997 Jun 10 Document order number: 9397 750 01609
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