Datasheet SA5225D Datasheet (Philips)

INTEGRATED CIRCUITS

SA5225

Fiber optic postamplifier

Product specification
Replaces datasheet NE/SA5225 of 1997 Jun 05
IC19 Data Handbook

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1998 Oct 07

Philips Semiconductors Product specification

SA5225Fiber optic postamplifier

DESCRIPTION

The SA5225 is a high-gain limiting amplifier that is designed to
process signals from fiber optic preamplifiers. Capable of operating
at 125Mb/s, the chip has input signal level-detection with a
user-adjustable threshold. The DATA and LEVEL-DETECT outputs
are differential for optimum noise margin and ease of use. Also
available is the SA5224 which is optimized for FDDI applications.

FEA TURES

•Wideband operation: 1.0kHz to 120MHz typical

•Applicable in 155Mb/s OC3/SONET receivers

•Operation with single +5V or –5.2V supply

•Differential 10k ECL outputs

•Programmable input signal level-detection

•Fully differential for excellent PSRR to 1GHz

APPLICATIONS

•Data communication in noisy industrial environments

•LANs

ORDERING INFORMATION

DESCRIPTION TEMPERATURE RANGE ORDER CODE DWG #

16-Pin Plastic Small Outline (SO) Package

PIN DESCRIPTION

CAZN
CAZP

GND

D

IN

D

IN

V

CCA

CF

JAM

Figure 1. Pin Configuration

–40 to +85°C

A

D Package

1
2
3
4
5
6
7
8

16

V

SET

V

15

REF

14

V

CCE

13

D

OUT

12

D

OUT

11

GND

E

ST

10

9

ST

SD00374

SA5225D SOT109-1

BLOCK DIAGRAM

V

V

D

D

REF

SET

C

V

(4)

IN

(5)

IN

(15)

(16)

GND

C

AZN

A

AZP

LIMITING

AMPLIFIER

LEVEL

DETECTOR

C

F

ECL

BUFFER

CCA

(6) (2) (1) (16)

REFERENCE

JAM

BUFFER

SD

BUFFER

V

CCE

(11)(7)(3)

GND

(13)

D

OUT

(12)

D

OUT

JAM

(8)

ST

(9)

(10)

ST

SD00375

E

Figure 2. Block Diagram

1998 Oct 07 853-1595 20141

2

Philips Semiconductors Product specification

SA5225Fiber optic postamplifier

PIN DESCRIPTIONS

PIN NO. NAME FUNCTION

1 C

2 C

AZN

AZP

3 GNDAAnalog GND pin. Connect to ground for +5V upshifted ECL operation. Connect to –5.2V for standard ECL

4 D
5 D
6 V

CCA

7 C
8 JAM This ECL-compatible input controls the output buffers D

9 ST Input signal level-detect STATUS. This ECL output is high when the input signal is below the user programmable

10 ST ECL compliment of ST (Pin 9).
11 GND

12 D

13 D

14 V

15 V
16 V

OUT

OUT

CCE

REF
SET

Auto-zero capacitor pin. Connecting a capacitor between this pin and C
limiting amplifier.

Auto-zero capacitor pin. Connecting a capacitor between this pin and C
limiting amplifier.

will cancel the offset voltage of the

AZP

will cancel the offset voltage of the

AZN

operation. Must be at same potential as GNDE (Pin 11).
Differential input. DC bias level is set internally at approximately 2.9V. Complimentary to DIN (Pin 5).

IN

Differential input. DC bias level is set internally at approximately 2.9V. Complimentary to DIN (Pin 4).

IN

Analog power supply pin. Connect to a +5V supply for upshifted ECL operation. Connect to ground for standard
ECL operation. Must be at same potential as V

Filter capacitor for level detector. Capacitor should be connected between this pin and V

F

is applied, the outputs will follow the input signal. When an ECL HIGH signal is applied, the D
will latch into LOW and HIGH states, respectively. When left unconnected, this pin is actively pulled-low (JAM OFF).

CCE

(Pin 14).

OUT

and D

.

CCA

(Pins 12 and 13). When an ECL LOW signal

OUT

OUT

and D

threshold level.

Digital GND pin. Connect to ground for +5V upshifted ECL operation. Connect to a negative supply for normal ECL

E

operation. Must be at the same potential as GNDA (Pin 3).
ECL-compatible output. Nominal level is V

condition. Complimentary to D

OUT

(Pin 13).

ECL-compatible output. Nominal level is V
condition. Complimentary to D

OUT

(Pin 12).

–1.3V. When JAM is HIGH, this pin will be forced into an ECL HIGH

CCE

–1.3V. When JAM is HIGH, this pin will be forced into an ECL LOW

CCE

Digital power supply pin. Connect to a +5V supply for upshifted ECL operation. Connect to ground during normal
ECL operation. Must be at the same potential as V

CCA

(Pin 6).
Reference voltage for threshold level voltage divider. Nominal value is approximately 2.64V.
Input threshold level setting circuit. This input can come from a voltage divider between V

and GNDA.

REF

OUT

pins

ABSOLUTE MAXIMUM RATINGS

SYMBOL PARAMETER RATING UNITS

T

V

P

CC

T

A

T

J

STG

D

Power supply (VCC - GND) 6 V
Operating ambient –40 to +85 °C
Operating junction –55 to +150 °C
Storage –65 to +150 °C
Power dissipation, TA = 25°C (still air)

16-pin Plastic SO

1

1100 mW

NOTE:

1. Maximum dissipation is determined by the ambient temperature and the thermal resistance,
: 16-pin SO: θJA = 110°C/W

θ

JA

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER RATING UNITS

V

CC

T

A

T

J

Supply voltage 4.5 to 5.5 V
Ambient temperature ranges –40 to +85 °C
Junction temperature ranges –40 to +110 °C

1998 Oct 07

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Philips Semiconductors Product specification

SYMBOL

PARAMETER

TEST CONDITIONS

UNIT

SYMBOL

PARAMETER

TEST CONDITIONS

UNIT

SA5225Fiber optic postamplifier

DC ELECTRICAL CHARACTERISTICS

Min and Max limits apply over operating temperature at VCC = 5V ±10%, unless otherwise specified.
Typical data apply at T

Input signal voltage

V

IN

V

V
V

V

V

I
I
V
V

OS

V

TH

HYS
CC

INL

OH
OL

Input offset voltage
Input RMS noise

N

Input level-detect programmability single-en­ded

Level-detect hysteresis
V
JAM input current Pin 8 = 0V –10 10

Minimum input for JAM = high

IH

Maximum input for JAM = low

IL

4

Status pins –1.0 –0.81 V

4

Status pins –1.95 –1.63 V

NOTES:

1. These ECL specifications are referenced to the V

2. Guaranteed by design.

3. Also see the SA5224 which has 5dB ±1dB hysteresis for FDDI compatibility.

4. Valid for Status pins only (#9, 10).

= 25°C and VCC = +5V.

A

single-ended
differential

+ V

CCA

supply current No ECL loading 27 35

CCE

SA5225

Min Typ Max

0.002

0.004

2

2

VIN = 200kHz square wave 2 12 mV

3

2 3 4 dB

1.5

V

3.0
50 µV
60 µV

P-P

P-P

mA

µA

1

1

rail and apply for TA = 0°C to 85°C.

CCE

–1.165

–1.490 V

V

DC
DC
DC
DC

Table 1. 10K ECL Voltage Levels (referenced to V

) (Pins 12 & 13 only)

CCE

PARAMETER –30°C 0°C 25°C 75°C 85°C UNIT

V

OHMAX

V

OHMIN

V

OLMAX

V

OLMIN

–0.890 –0.840 –0.810 –0.735 –0.700 V
–1.060 –1.020 –0.980 –0.920 –0.890 V
–1.650 –1.630 –1.630 –1.600 –1.615 V
–1.890 –1.950 –1.950 –1.950 –1.920 V

AC ELECTRICAL CHARACTERISTICS

Min and Max limits apply for 4.5 ≤ VCC ≤ 5.5V.
Typical data apply at T

BW
BW

R
C

tr, t

t

PWD

R

R

t

LD

Lower –3dB bandwidth CAZ = 0.1µF 0.5 1.0 1.5 kHz

1

Upper –3dB bandwidth 90 120 150 MHz

2

Input resistance Pin 4 or 5 2.9 4.5 7.6 kΩ

IN

Input capacitance Pin 4 or 5 2.5 pF

IN

ECL output

f

Pulsewidth distortion 0.3
Auto zero output resistance Pin 1 or 2 155 250 423

AZ

Level-detect filter resistance Pin 7 14 24 41 kΩ

F

Level-detect time constant CF = 0 0.5 1.0 2.0 µs

NOTE:

1. Both outputs should be terminated identically to minimize differential feedback to the device inputs on a PC board or substrate.

= 25°C and VCC = +5V.

A

1

risetime,
falltime

RL = 50Ω

To V

CCE

20–80%

– 2V

SA5225

Min Typ Max

1.2 2.2 ns

DC
DC
DC
DC

ns

P-P

kΩ

1998 Oct 07

4

Philips Semiconductors Product specification

V

V

SA5225Fiber optic postamplifier

INPUT SIGNAL LEVEL-DETECTION

The SA5225 allows for user programmable input signal

CLOCK

NE5212 NE5224

RECOVERY

&

RETIMING

SD00376

Figure 3. Typical Fiber Optic Receiving System

INPUT BIASING

The DATA INPUT pins (4 and 5) are DC biased at approximately

2.9V by an internal reference generator. The SA5225 can be DC
coupled, but the driving source must operate within the allowable

1.4V to 4.4V input signal range (for V

= 5V). If AC coupling is

CC

used to remove any DC compatibility requirement, the coupling
capacitors C1 and C2 must be large enough to pass the lowest input
frequency of interest. For example, .001µF coupling capacitors
react with the internal 4.5k input bias resistors to yield a lower –3dB
frequency of 35kHz. This then sets a limit on the maximum number
of consecutive “1”s or “0”s that can be sensed accurately at the
system data rate. Capacitor tolerance and resistor variation (2.9k to

7.6k) must be included for an accurate calculation.

AUTO-ZERO CIRCUIT

Figure 5 also shows the essential details of the auto-zero circuit. A
feedback amplifier (A4) is used to cancel the offset voltage of the
forward signal path, so the input to the internal ECL comparator (A6)
is at its toggle point in the absence of any input signal. The time
constant of the cancelling circuitry is set by an external capacitor
(C

) connected between Pins 1 and 2. The formula for the lower

AZ

–3dB frequency is:

f



3dB

where RAZ is the internal driving impedance which can vary from
155k to 423k over temperature and device fabrication limits. The
input coupling time constant must also be considered in determining
the lower frequency response of the SA5225.

2  R

150

AZ

 C

AZ

level-detection and can automatically disable the switching of its
ECL data outputs if the input is below a set threshold. This prevents
the outputs from reacting to noise in the absence of a valid input
signal, and insures that data will only be transmitted when the input
signal-to-noise ratio is sufficient for low bit-error-rate system
operation. Complimentary ECL flags (ST and STB) indicate whether
the input signal is above or below the desired threshold level.

Figure 6 shows a simplified block diagram of the SA5225
level-detect system. The input signal is amplified and rectified
before being compared to a programmable reference. A filter is
included to prevent noise spikes from triggering the level-detector.
This filter has a nominal 1µs time constant, and additional filtering
can be achieved by using an external capacitor (CF) from Pin 7 to
V

(the internal driving impedance is nominally 24k). The

CCA

resultant signal is then compared to a programmable level, V

SET

,
which is set by an internal voltage reference (2.64V) and an external
resistor divider (R1 and R2). The value of R1 + R2 should be
maintained at approximately 5k.

HYST

V

V

TL

(OFF) (ON)

TH

SD00377

Figure 4.

The circuit is designed to operate accurately over a differential
2-12mV
V

SET

square-wave input level detect range. This level,

P-P

/100, is the average of VTH and VTL.

Nominal hysteresis of 3dB is provided by the complimentary ECL

SET



85

. For

P-P

output comparator yielding
example, with V

= 1.2V, a 14.05mV

SET

V

SET



TL

121

P-P

V

TH

and

square-wave differential
input will drive the ST pin high, and an input level below 9.95mV
will drive the ST pin low.

Since a “JAM” function is provided (Pin 8) and can force the data
outputs to a predetermined state (D

and JAM pins can be connected together to automatically

ST

= LOW, D

OUT

= HIGH), the

OUT

disable signal transmission when the chip senses that the input
signal is below the desired threshold. JAM (Pin 8) low enables the
Data Outputs. ST

will be in a high ECL state for input signals below

threshold.

1998 Oct 07

DATA IN

C

AZ

R

V

BIAS

R

C1

C2

4.5kΩ

D

IN

D

INB

R

IN

IN

4.5kΩ

A1 +

–

AZ

250kΩ

A3 A6

R

AZ

250kΩ

A4

D

OUT

D

OUTB

Figure 5. SA5225 Sample Application: Forward Gain Path Including Auto-Zero

5

ECL 10K

DATA OUT

SD00668

Philips Semiconductors Product specification

SA5225Fiber optic postamplifier

V

CCA

C

F

DATA IN

50X

2.64V

V

REF

R

1

.25X

R

2

LOW-PASS

FILTER

+
–

ST
ST

LEVEL­DETECT
FLAGS

Figure 6. SA5225 Sample Application: Input Signal Level-Detect System

D

D

V

V

V

SET

REF

CCE

OUT

OUT

16

R

15

14

13

12

1

0.1µF

1

C

C

AZ

0.1µF

C

IN1

DATA IN DATA OUT

0.1µF

0.1µF

C

IN2

AZN

2

C

AZP

3

GND

A

D

4

IN

5

D

IN

ECL 10K

SD00669

50Ω

R

5V

R

4

50Ω

R

2

3

3V

5V

0.1µF 0.1µF

V

6

CCA

C

7

F

JAM

8

GND

11

E

R

ST

10

ST

9

5

50Ω

Figure 7. SA5225 Sample Application with VCC = 5.0V

NOTE: A 50Ω resistor is required from Pin 9 to 3V only if the ST pin is required to meet 10k ECL specifications.

Die Sales Disclaimer

Due to the limitations in testing high frequency and other parameters
at the die level, and the fact that die electrical characteristics may
shift after packaging, die electrical parameters are not specified and
die are not guaranteed to meet electrical characteristics (including
temperature range) as noted in this data sheet which is intended
only to specify electrical characteristics for a packaged device.

All die are 100% functional with various parametrics tested at the
wafer level, at room temperature only (25°C), and are guaranteed to
be 100% functional as a result of electrical testing to the point of
wafer sawing only. Although the most modern processes are
utilized for wafer sawing and die pick and place into waffle pack
carriers, it is impossible to guarantee 100% functionality through this
process. There is no post waffle pack testing performed on
individual die.

1998 Oct 07

6

LEVEL-DETECT
STATUS

SD00380

Philips Semiconductors Product specification

SA5225Fiber optic postamplifier

Since Philips Semiconductors has no control of third party
procedures in the handling or packaging of die, Philips
Semiconductors assumes no liability for device functionality or
performance of the die or systems on any die sales.

CAZN

CAZP

2

GNDA

DIN

3

4

Although Philips Semiconductors typically realizes a yield of 85%
after assembling die into their respective packages, with care
customers should achieve a similar yield. However, for the reasons
stated above, Philips Semiconductors cannot guarantee this or any
other yield on any die sales.

V

SET

V

1

16

15

14

13

REF

V

CCE

DOUT

ECN No.: 01671
1991 Jul 8

DIN

V

CF

JAM

CCA

5

6

78 910

Figure 8. SA5225 Bonding Diagram

12

11

DOUT

GND

ST

ST

SD00493

E

1998 Oct 07

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Philips Semiconductors Product specification

SA5225Fiber optic postamplifier

SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

1998 Oct 07

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Philips Semiconductors Product specification

SA5225Fiber optic postamplifier

NOTES

1998 Oct 07

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Philips Semiconductors Product specification

SA5225Fiber optic postamplifier

Data sheet status

Data sheet
status

Objective
specification

Preliminary
specification

Product
specification

Product
status

Development

Qualification

Production

Definition

This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.

[1]

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.

Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone [phone]

 Copyright Philips Electronics North America Corporation 1998

All rights reserved. Printed in U.S.A.

Date of release: 10-98

Document order number: 9397 750 04629

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1998 Oct 07

10