Datasheet S93VP462P-2.7, S93VP462P-A, S93VP462P-B, S93VP462S-2.7, S93VP462S-A Datasheet (SUMMIT)
...Page 1
SUMMIT MICROELECTRONICS, Inc. • 300 Orchard City Drive, Suite 131 • Campbell, CA 95008 • Telephone 408-378-6461 • Fax 408-378-6586 • www.summitmicro.com
1
S93VP462/S93VP463
© SUMMIT MICROELECTRONICS, Inc. 1998
2040-01 10/23/98
Characteristics subject to change without notice
VOLTAGE-SENSE™ Write Protected Memory
FEATURES
• Voltage-Sense Write Protection
— Low V
CC
Write Lockout
— All Writes Inhibited when V
CC
< V
TRIP
— Protects Against Inadvertent Writes During
- Power-up
- Power-down
- Brown-out Conditions
— All Devices ‘Readable’ from 1.8V to 5.5V
- User Selectable V
TRIP
Levels
• Memory
— 1K-bit Microwire Memory
— S93VP462
– Internally Ties ORG Low
– 100% Compatible with All 8-bit
Implementations
–
Sixteen Byte Page Write Capability
— S93VP463
– Internally Ties ORG High
– 100% Compatible With all 16-bit
Implementations
–
Eight Word Page Write Capability
APPLICATIONS
New designs for applications where data corruption
cannot be permitted.
Replacement of existing industry standard 1K
memories.
OVERVIEW
The S93VP462 and S93VP463 are voltage monitoring
memory devices that write protect the array from inadvertent writes whenever V
CC
is below V
TRIP
.
Both devices have 1k-bits of E
2
PROM memory that is
accessible via the industry standard microwire bus. The
S93VP462 is configured with an internal ORG pin tied
low providing a 8-bit byte organization and the
S93VP463 is configured with an internal ORG pin tied
high providing a 16-bit word organization. Both the
S93VP462 and S93VP463 have page write capability.
The devices are designed for a minimum 1,000,000
program/erase cycles and have data retention in excess of 100 years.
BLOCK DIAGRAM
GND
+
-
V
CC
8
V
TRIP
CS
DI
DO
DATA I/O
MODE
DECODE
WRITE
CONTROL
CIRCUITRY
SK
1
2
3
4
5
I
RESET
PULSE
GENERATOR
NONVOLATILE
MEMORY
ARRAY
6 7
NC NC
2040 ILL2.0
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S93VP462/S93VP463
2040-01 10/23/98
PIN FUNCTIONS
Pin Name Function
CS Chip Select
SK Clock Input
DI Serial Data Input
DO Serial Data Output
V
CC
+2.7 to 6.0V Power Supply
GND Ground
NC No Connect
PIN CONFIGURATION
DIP Package (P)
SOIC Package (S)
DEVICE OPERATION
WRITE LOCKOUT DESCRIPTION
The S93VP462/VP463 provides a precision internal
reset controller that ensures correct system operation
during brown-out and power-up/-down conditions.
During power-up, the write lockout remains active until
V
CC
reaches the V
TRIP
threshold. Write lockout will
continue to be driven for approximately 150 ms after V
CC
reaches V
TRIP
. During power-down, write lockout will be
driven active when even V
CC
falls below V
TRIP
.
GENERAL OPERATION
The S93VP462/VP463 is a 1024-bit nonvolatile memory
intended for use with industry standard microprocessors. The S93VP463 is organized as X16, seven 9-bit
instructions control the reading, writing and erase
operations of the device. The S93VP462 is organized as
X8, seven 10-bit instructions control the reading, writing
and erase operations of the device. The device operates
on a single 3V or 5V supply and will generate on chip, the
high voltage required during any write operation.
Instructions, addresses, and write data are clocked into
the DI pin on the rising edge of the clock (SK). The DO
pin is normally in a high impedance state except when
reading data from the device, or when checking the
ready/busy status after a write operation.
The ready/busy status can be determined after the start
of a write operation by selecting the device (CS high) and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that
the device is ready for the next instruction. See the
Applications Aid section for detailed use of the ready
busy status.
The format for all instructions is: one start bit; two op
code bits and either six (x16) or seven (x8) address or
instruction bits.
2040 ILL1.0
CS
SK
DI
DO
V
CC
NC
NC
GND
1
2
3
4
8
7
6
5
CS
SK
DI
DO
V
CC
NC
NC
GND
1
2
3
4
8
7
6
5
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S93VP462/S93VP463
2040-01 10/23/98
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the S93VP462/
VP463 will come out of the high impedance state and,
will first output an initial dummy zero bit, then begin
shifting out the data addressed (MSB first). The output
data bits
will toggle on the rising edge of the SK clock and
are stable after the specified time delay
(t
PD0
or t
PD1
).
Write
After receiving a WRITE command, address and the
data, the CS (Chip Select) pin must be deselected for a
minimum of 250ns (t
CSMIN
). The falling edge of CS will
start automatic erase and write cycle to the memory
location specified in the instruction. The ready/busy
status of the S93VP462/VP463 can be determined by
selecting the device and polling the DO pin.
Erase
Upon receiving an ERASE command and address, the
CS (Chip Select) pin must be deselected for a minimum
of 250ns (t
CSMIN
). The falling edge of CS will start the
auto erase cycle of the selected memory location. The
ready/busy status of the S93VP462/VP463 can be
determined by selecting the device and polling the DO
pin. Once cleared, the content of a cleared location
returns to a logical “1” state.
Figure 1. Sychronous Data Timing
Figure 2. Read Instruction Timing
SK
2040 ILL 3.0
DI
CS
DO
t
DIS
t
PD0,tPD1
t
CSMIN
t
CSS
t
DIS
t
DIH
t
SKHI
t
CSH
VALID VALID
DATA VALID
t
SKLOW
SK
2040 ILL4.0
CS
DI
DO
t
CS
STANDBY
t
HZ
HIGH-ZHIGH-Z
11 0
ANA
N–1
A
0
0
DND
N–1
D1D
0
t
PD0
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S93VP462/S93VP463
2040-01 10/23/98
Erase/Write Enable and Disable
The S93VP462/VP463 powers up in the write disable
state. Any writing after power-up or after an EWDS
(write disable) instruction must first be preceded by the
EWEN (write enable) instruction.
Once the write instruction is enabled, it will remain enabled until power to
the device is removed, or the EWDS instruction is sent.
The EWDS instruction can be used to disable all
S93VP462/VP463 write and clear instructions, and will
prevent any accidental writing or clearing of the device.
Data can be read normally from the device regardless
of the write enable/disable status.
Erase All
Upon receiving an ERAL command, the CS (Chip
Select) pin must be deselected for a minimum of 250ns
(t
CSMIN
). The falling edge of CS will start the self clocking
clear cycle of all memory locations in the device. The
clocking of the SK pin is not necessary after the device
has entered the self clocking mode. The ready/busy
status of the S93VP462/VP463 can be determined by
selecting the device and polling the DO pin. Once
cleared, the contents of all memory bits will be in a
logical “1” state.
Write All
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
250ns (t
CSMIN
). The falling edge of CS will start the self
clocking data write to all memory locations in the device.
The clocking of the SK pin is not necessary after the
device has entered the self clocking mode. The ready/
busy status of the S93VP462/VP463 can be determined
by selecting the device and polling the DO pin. It is not
necessary for all memory locations to be cleared before
the WRAL command is executed.
Page Write
93462 - Assume WEN has been issued. The host will
then take CS high, and begin clocking in the start bit,
write command and 7-bit address immediately followed by the first byte of data to be written. The host
can then continue clocking in 8-bit bytes of data with
each byte to be written to the next higher address.
Internally the address pointer is incremented after
receiving each group of eight clocks; however, once
the address counter reaches xxx 1111 it will roll over
to xxx 0000 with the next clock. After the last bit is
clocked in no internal write operation will occur until CS
is brought low.
93463 - Assume WEN has been issued. The host will
then take CS high, and begin clocking in the start bit,
write command and 6-bit address immediately
followed by the first 16-bit word of data to be written.
The host can then continue clocking in 16-bit words of
data with each word to be written to the next higher
address. Internally the address pointer is incremented
after receiving each group of sixteen clocks; however,
once the address counter reaches xxx x111 it will roll
over to xx x000 with the next clock. After the last bit is
clocked in no internal write operation will occur until CS
is brought low.
Continuous Read
This begins just like a standard read with the host
issuing a read instruction and clocking out the data
byte [word]. If the host then keeps CS high and
continues generating clocks on SK, the S93VP462/
VP463 will output data from the next higher address
location. The S93VP462/VP463 will continue
incrementing the address and outputting data so long
as CS stays high. If the highest address is reached, the
address counter will roll over to address 0000. CS
going low will reset the instruction register and any
subsequent read must be initiated in the normal manner of issuing the command and address.
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S93VP462/S93VP463
2040-01 10/23/98
Figure 3. Write Instruction Timing
Figure 4. Erase Instruction Timing
Figure 5. EWEN/EWDS Instruction Timing
SK
2040 ILL 5.0
CS
DI
DO
t
CS
STANDBY
HIGH-Z
HIGH-Z
101
ANA
N-1
A
0
D
N
D
0
BUSY
READY
STATUS
VERIFY
t
SV
t
HZ
t
EW
SK
2040 ILL6.0
CS
DI
DO
STANDBY
HIGH-Z
HIGH-Z
1
A
N
A
N-1
BUSY READY
STATUS VERIFY
t
SV
t
HZ
t
EW
t
CS
11
A
0
SK
2040 ILL 7.0
CS
DI
STANDBY
10
0
*
* ENABLE=1 1
DISABLE=00
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S93VP462/S93VP463
2040-01 10/23/98
Figure 7. WRAL Instruction Timing
INSTRUCTION SET
Instruction Start Opcode Address Data Comments
Bit x8 x16 x8 x16
READ 1 10 A6–A0 x(A5–A0) Read Address AN–A0
ERASE 1 11 A6–A0 x(A5–A0) Clear Address AN–A0
WRITE 1 01 A6–A0 x(A5–A0) D7–D0 D15–D0 Write Address AN–A0
EWEN 1 00 11xxxxx 11xxxx Write Enable
EWDS 1 00 00xxxxx 00xxxx Write Disable
ERAL 1 00 10xxxxx 10xxxx Clear All Addresses
WRAL 1 00 01xxxxx 01xxxx D7–D0 D15–D0 Write All Addresses
2040 PGM T5.0
Figure 6. ERAL Instruction Timing
SK
2040 ILL 8.0
CS
DI
DO
t
CS
HIGH-Z
HIGH-Z
10 1
BUSY READY
STATUS VERIFY
t
SV
t
HZ
t
EW
00
STANDBY
SK
2040 ILL 10.0
CS
DI
DO
t
CS
HIGH-Z
10 1
BUSY READY
STATUS VERIFY
t
SV
t
HZ
t
EW
00
STANDBY
D
O
D
N
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S93VP462/S93VP463
2040-01 10/23/98
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ....................................................................................................................................–55°C to +125°C
Storage Temperature .........................................................................................................................................–65°C to +150°C
Voltage on any Pin with Respect to Ground
(1)
.............................................................................................–2.0V to +VCC +2.0V
V
CC
with Respect to Ground.................................................................................................................................. –2.0V to +7.0V
Package Power Dissipation Capability (Ta = 25°C) .............................................................................................................1.0W
Lead Soldering Temperature (10 secs) .............................................................................................................................. 300°C
Output Short Circuit Current
(2)
...........................................................................................................................................100 mA
*COMMENT
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to
any absolute maximum rating for extended periods may affect device performance and reliability.
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V
CC
+1V.
D.C. OPERATING CHARACTERISTICS (over recommended operating conditions unless otherwise specified)
Limits
Symbol Parameter Min. Typ. Max. Units Test Conditions
I
CC
Power Supply Current 3 mA DI = 0.0V, fSK = 1MHz
(Operating) V
CC
= 5.0V, CS = 5.0V,
Output Open
I
SB
Power Supply Current 50 µA CS = 0V
(Standby) Reset Outputs Open
I
LI
Input Leakage Current 2 µAVIN = 0V to V
CC
I
LO
Output Leakage Current 10 µAV
OUT
= 0V to VCC,
(Including ORG pin) CS = 0V
V
IL1
Input Low Voltage -0.1 0.8 V 4.5V≤VCC<5.5V
V
IH1
Input High Voltage 2 VCC+1 V
V
IL2
Input Low Voltage 0 VCCX0.2 V 1.8V≤VCC<2.7V
V
IH2
Input High Voltage VCCX0.7 VCC+1 V
V
OL1
Output Low Voltage 0.4 V 4.5V≤VCC<5.5V
V
OH1
Output High Voltage 2.4 V IOL = 2.1mA
IOH = -400µA
V
OL2
Output Low Voltage 0.2 V 1.8V≤VCC<2.7V
V
OH2
Output High Voltage VCC-0.2 V IOL = 1mA
IOH = -100µA
2040 PGM T3.0
RELIABILITY CHARACTERISTICS
Symbol Parameter Min. Max. Units Reference Test Method
N
END
(3)
Endurance 1,000,000 Cycles/Byte MIL-STD-883, Test Method 1033
T
DR
(3)
Data Retention 100 Years MIL-STD-883, Test Method 1008
V
ZAP
(3)
ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015
I
LTH
(3)(4)
Latch-Up 100 mA JEDEC Standard 17
2040 PGM T2.0
Temperature Min Max
Commercial 0°C +70°C
Industrial -40°C +85°C
RECOMMENDED OPERATING CONDITIONS
2040 PGM T7.0
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S93VP462/S93VP463
2040-01 10/23/98
Limits
V
CC
=2.7V-4.5V VCC=4.5V-5.5V Test
SYMBOL PARAMETER Min. Max. Min. Max. UNITS Conditions
t
CSS
CS Setup Time 100 50 ns
t
CSH
CS Hold Time 0 0 ns VIL = 0.45V
t
DIS
DI Setup Time 200 100 ns VIH = 2.4V
t
DIH
DI Hold Time 200 100 ns CL = 100pF
t
PD1
Output Delay to 1 0.5 0.25 µsVOL = 0.8V
t
PD0
Output Delay to 0 0.5 0.25 µsVOH = 2.0v
t
HZ
(1)
Output Delay to High-Z 200 100 ns
t
EW
Program/Erase Pulse Width 10 10 ms
t
CSMIN
Minimum CS Low Time 0.5 0.25 µs
t
SKHI
Minimum SK High Time 0.5 0.25 µs
t
SKLOW
Minimum SK Low Time 0.5 0.25 µs
t
SV
Output Delay to Status Valid 0.5 0.25 µsCL = 100pF
SK
MAX
Maximum Clock Frequency DC 500 DC 1000 KHZ
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
A.C. CHARACTERISTICS (over recommended operating conditions unless otherwise specified)
CL = 100pF
2040 PGM T6.0
PIN CAPACITANCE
Symbol Test Max. Units Conditions
C
OUT
(1)
OUTPUT CAPACITANCE (DO) 5 pF V
OUT
=OV
C
IN
(1)
INPUT CAPACITANCE (CS, SK, DI, ORG) 5 pF VIN=OV
2040 PGM T4.0
Page 9
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S93VP462/S93VP463
2040-01 10/23/98
t
PUW
t
GLITCH
t
LDLY
V
LOCK
V
CC
t
PUW
t
LDLY
V
LOCKOUT
V
LOCKOUT
V
LOCKOUT
Internal Action
2040 ILL9.0
Figure 8. V
LOCK
Timing Diagram
2019 PGM T1 1.3
Page 10
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S93VP462/S93VP463
2040-01 10/23/98
.228 (5.80)
.244 (6.20)
.016 (.40)
.035 (.90)
.020 (.50)
.010 (.25)
x45°
.0192 (.49)
.0138 (.35)
.061 (1.75)
.053 (1.35)
.0098 (.25)
.004 (.127)
.05 (1.27) TYP.
.275 (6.99) TYP.
.030 (.762) TYP.
8 Places
.050 (1.27) TYP.
.050 (1.270) TYP.
8 Places
.157 (4.00)
.150 (3.80)
.196 (5.00)
1
.189 (4.80)
FOOTPRINT
8pn JEDEC SOIC ILL.2
.375
(9.525)
PIN 1 INDICATOR
.015 (.381) Min.
.130 (3.302)
.100 (2.54)
TYP.
.018 (.457)
TYP.
.060 ± .005
(1.524) ± .127
TYP.
.130 (3.302)
SEATING PLANE
.070 (1.778)
.0375 (0.952)
.300 (7.620)
5°-7°TYP.
(4 PLCS)
.350 (8.89)
.009 ± .002
(.229 ± .051)
0°-15°
.250
(6.350)
8pn PDIP/P ILL.3
8 Pin SOIC (Type S) Package JEDEC (150 mil body width)
8 Pin PDIP (Type P) Package
Page 11
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S93VP462/S93VP463
2040-01 10/23/98
Ready/Busy Status
During the internal write operation the S93VP462/VP463 memory array is inaccessible. After starting the write
operation (taking CS low) the host can implement a 10ms timeout routine or alternatively it can employ a polling routine
that tests the state of the DO pin.
After starting the write, testing for the status is easily accomplished by taking CS high and testing the state of DO. If
it is low the device is still busy with the internal write. If it is high the write operation has completed.
For the polling routine the host has the option of toggling CS for each test of DO, or it can place CS high and then
intermittently test DO. SK is
not required for any of these operations. Once the device is ready, it will continue to drive
DO high whenever the S93VP462/VP463 is selected. The ready state of DO can be cleared by clocking in a start bit;
this start bit can either be the beginning of a new command sequence or it can be a dummy start bit with CS returning
low before the host issues a new command.
SK
2040 ILL13.0
CS
DI
DO
t
CS
HIGH-Z
HIGH-Z
STATUS CLEARED
BUSY READY
STATUS VERIFY
t
SV
t
HZ
t
EW
Page 12
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S93VP462/S93VP463
2040-01 10/23/98
NOTICE
SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve
design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described
herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent
infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon
a user’s specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc.
shall not be liable for any damages arising as a result of any error or omission.
SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety
or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written
assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and
(c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances.
Voltage-Sense™ and VOLTAGE-SENSE™ are trademarks of Summit Microelectronics, Inc.
© Copyright 1998 SUMMIT Microelectronics, Inc.
ORDERING INFORMATION
S93VP463
Base Part Number
S93VP463 = 16-bit configuration
S93VP462 = 8-bit configuration
Tape and Reel Option
Blank = Tube
T = Tape and Reel
Package
P = 8 Lead PDIP
S = 8 Lead 150mil SOIC
Operating Voltage Range
A = 4.5V to 5.5V V
TRIP
Min. @ 4.25V
B = 4.5V to 5.5V V
TRIP
Min. @ 4.50V
2.7 = 2.7V to 5.5V V
TRIP
Min. @ 2.55V
P -2.7 T
2040 ILL11.0
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