Datasheet S9318S Datasheet (SUMMIT)

SUMMIT

MICROELECTRONICS, Inc.

Nonvolatile DACPOT™ Electronic Potentiometer
With Up/Down Counter Interface

FEATURES

• Digitally Controlled Electronic Potentiometer

• 8-Bit Digital-to-Analog Converter (DAC)
– Independent Reference Inputs

– Differential Non-Linearity - ±0.5LSB max
– Integral Non-Linearity - ±1LSB max

•V

Value in E2PROM for Power-On Recall

OUT

– Equivalent to 256-Step Potentiometer

• Unity Gain Op Amp Drives up to 1mA

• Simple Trimming Adjustment
– Up/Down Counter Style Operation

• Low Noise Operation

• “Clickless” Transitions between DAC Steps

• No Mechanical Wearout Problem
– 1,000,000 Stores (typical)

– 100 Year Data Retention

• Operation from +2.7V to +5.5V Supply

OVERVIEW

The S9318 DACPOT™ trimmer is an 8-bit nonvolatile
DAC designed to replace mechanical potentiometers.
The S9318 includes a unity-gain amplifier to buffer the
DAC output and enables V
The DACPOT trimmer operates over a supply voltage
range of 2.7V to 5.5V.

The S9318’s simple up/down counter input provides an
ideal interface for automatic test equipment to dither and
monitor the V
and consistent calibration of even the most sophisticated
systems.

The S9318 is a pin-compatible performance upgrade for
other industry nonvolatile potentiometers. The S9318
offers double the resolution of these devices and provides
‘clickless’ transitions of V

S9318

to swing from rail to rail.

OUT

voltage. This interface allows for quick

OUT

.

OUT

• Low Power, 1mW max at +5V

FUNCTIONAL BLOCK DIAGRAM

UP/DN

INC

CS

Counter

&

Write

Control

8-bit E2 PROM

8-bit
Data

Register

V

DD

8-bit DAC

-

+

AMP

V

V

OUT

V

H

L

GND

2016 ILL2.1

SUMMIT MICROELECTRONICS, Inc. • 300 Orchard City Drive, Suite 131 • Campbell, CA 95008 • Telephone [phone] • Fax [phone] • www.summitmicro.com

© SUMMIT MICROELECTRONICS, Inc. 1999
2016-04 4/24/99

1

Characteristics subject to change without notice

S9318

PIN NAMES

Symbol Description

INC Increment Input, High to Low

Edge Trigger

UP/DN Up/Down Input controlling relative

V

movement

OUT

V

H

V+ reference input
GND Analog and Digital Ground
V

OUT

V

L

Trimmed Voltage Output

V- reference input

CS Active low chip select input

V

DD

Supply Voltage (2.7V to 5.5V)

Analog Section

The S9318 is an 8-bit, voltage output digital-to-analog
converter (DAC). The DAC consists of a resistor network
that converts an 8-bit value into equivalent analog output
voltages in proportion to the applied reference voltage.

Reference Inputs

The voltage differential between the VL and VH inputs
sets the full-scale output voltage range. VL must be equal
to or greater than ground (i.e. a positive voltage). VH must
be greater than VL and less than or equal to VDD. See
table on page 3 for guaranteed operating limits.

Output Buffer Amplifier

The voltage output is a precision unity-gain follower that
can slew up to 1V/µs.

Digital Interface

The interface is designed to emulate a simple up/down
counter, but instead of a parallel count output, a
ratiometric voltage output is provided.

PINOUT

INC

UP/DN

V

GND

Chip Select (

1

2

3

H

4

CSCS

CS) is an active low input. Whenever CS is

CSCS

8

7

6

5

2016 ILL1.1

V

CS

V

V

DD

L

OUT

high the S9318 is in standby mode and consumes the
least power. This mode is equivalent to a potentiometer
that is adjusted to the required setting. When CS is low the
S9318 will recognize transitions on the INC input and will
move the V

either toward the VH reference or toward

OUT

the VL reference depending upon the state of the UP/DN
input.

The host may exit an adjustment routine in two ways:
deselecting the S9318 while INC is low will not perform a
store operation (a subsequent power cycle will recall the
original data); deselecting the S9318 while INC is high will
store the current V

Increment (

INCINC

INC) is an edge triggered input. Whenever

INCINC

setting into nonvolatile memory.

OUT

CS is low and a high to low transition occurs on the INC
input, the V

voltage will either move toward VH or V

OUT

depending upon the state of the UP/DN input.

UP/Down (UP/

DNDN

DN) is an input that will determine the V

DNDN

OUT

movement relative to VH and VL. When CS is low, UP/DN
is high and there is a high to low transition on INC, the
V

voltage will move (1/256th x VH-VL) toward VH.

OUT

When CS and UP/DN are low, and there is a high to low
transition on INC, the V

will move (1/256th x VH-VL)

OUT

toward VL.

L

2016-04 4/24/99

2

S9318

ABSOLUTE MAXIMUM RATINGS*

Temperature Under Bias -55°C to +125°C
Storage Temperature -65°C to +150°C
Voltage on pins with reference to GND:

Analog Inputs -0.5V to VDD+.5V

Digital Inputs -0.5V to VDD+.5V

Analog Outputs -0.5V to VDD+.5V

Digital Outputs -0.5V to VDD+.5V

Lead Solder Temperature (10 secs) 300°C

RECOMMENDED OPERATING CONDITIONS

Condition Min Max

Temperature -40°C +85°C

V

DD

+2.7V +5.5V

DAC DC ELECTRICAL CHARACTERISTICS
VDD = +2.7V to +5.5V, V

Symbol Parameter Conditions Min. Typ. Max. Units

Accuracy

INL Integral Non-Linearity I
DNL Differential Non-Linearity I

= VDD, V

refH

= 0V, TA = -40°C to +85°C, unless specified otherwise

refL

= 100µA, - 0.5 ±1 LSB

LOAD

= 100µA, - 0.1 ±0.5 LSB

LOAD

Guaranteed but not tested

*COMMENT

Stresses above those listed under Absolute Maxi­mum Ratings may cause permanent damage to
the device. These are stress ratings only, and
functional operation of the device at these or any
other conditions outside those listed in the opera­tion sections of this specification is not implied.
Exposure to any absolute maximum rating for
extended periods may affect device performance
and reliability.

2016 PGM T1.1

References

Analog
Output

V

H

V

L

R

IN

TCR

G

EFS

V

OUT

TCV

V

Input Voltage V

refH

V

Input Voltage Gnd - V

refL

V

to V

refH

Temperature Coefficient V

IN

of R

IN

Resistance - 38K - Ω

refL

refH

to V

refL

refL

- 600 - ppm/°C

-VDDV

refH

Full-Scale Gain Error DATA = FF - - ±1 LSB

ZS Zero-Scale Output Voltage DATA = 00 0 20 mV

OUTVOUT

Temperature VDD = +5, I

Coefficient V

= +5V, V

refH

= 50µA,

LOAD

= 0V - - 50 µV/°C

refL

Guaranteed but not tested
I
R

L

OUT

Amplifier Output Load Current
Amplifier Output Resistance

-200 +1000 µA

IL = 100µA VDD = +5V - 10 Ω

VDD = +3V - 20 Ω
PSRR Power Supply Rejection I
e

N

Amplifier Output Noise f = 1KHz, VDD = +5V - 90 - nV/ H

= 10µA - - 1 LSB/V

LOAD

THD Total Harmonic Distortion VIN = 1V rms, f = 1KHz - 0.08 - %
BW Bandwidth - 3dB V

= 100mV rms - 300 - kHz

IN

2016 PGM T3.4

V

Z

3

2016-04 4/24/99

RELIABILITY CHARACTERISTICS

Symbol Parameter Min Max Unit Test Method

S9318

V

ZAP

I

LTH

T

DR

N

END

ESD Susceptibility 2000 V MS-883, TM 3015
Latch-Up 100 mA JEDEC Standard 17
Data Retention 100 Years MS-883, TM 1008
Endurance 1,000,000 Stores MS-883, TM 1033

2016 PGM T2.0

DC ELECTRICAL CHARACTERISTICS VDD = +2.7V to +5.5V, VH = VDD, VL = 0V, Unless otherwise specified

Symbol Parameter Conditions Min Max Units

I

DD

Supply Current CS = V

IL

1.2 mA

during store, note 1

I

SB

I

IH

I

IL

V

IH

V

IL

Notes:

1. IDD is the supply current drawn while the EEPROM is being updated. IDD does not include the current that flows through the Reference
resistor chain.

2. CS, UP/DN and INC have internal pull-up resistors of approximately 200kΩ. When the input is pulled to ground the resulting output
current will be VDD/200kΩ.

Supply Standby Current CS = V
Input Leakage Current VIN = V

IH

DD

200 µA

10 µA
Input Leakage Current, note 2 VIN = 0V -25 µA
High Level Input Voltage 2 V

DD

V

Low Level Input Voltage 0 0.8 V

2016 PGM T4.3

2016-04 4/24/99

4

OPERATIONAL TRUTH TABLE

S9318

INCINC

INC

INCINC

HITOLO L H V
HITOLO L L V

HLO

LLO

V

DD

CSCS

CS UP/

CSCS

HI X Store Setting

TO

HI X Maintain Setting, NO Store

TO

V

DD

DNDN

DN Operation

DNDN

toward V

OUT

toward V

OUT

V

DD

Standby

H

L

AC TIMING CHARACTERISTICS VDD = +4.5V to +5.5V

Symbol Parameter Min Max Units

t

CLIL

t

IHDC

t

DCIL

t

IL

t

IH

t

IHCH

t

WP

t

ILVOUT

CS to INC Setup 100 ns
INC High to UP/DN Change 100 ns
UP/DN to INC Setup 100 ns
INC Low Period 200 ns
INC High Period 200 ns
INC Inactive to CS Inactive 100 ns
Write Cycle Time 5 ms
INC to V

Delay 5 µs

OUT

2016 PGM T5.1

2016 PGM T6.1

CS

INC

UP/DN

V

OUT

t

CLIL

t

IL

t

IHDC

t

ILVOUT

t

IH

t

IHDHLD

AC TIMING DIAGRAM

5

t

IHCH

t

WP

2016 ILL3.1

2016-04 4/24/99

8 Pin SOIC (Type S) Package JEDEC (150 mil body width)

.050 (1.27) TYP.

.157 (4.00)
.150 (3.80)

.275 (6.99) TYP.

.050 (1.270) TYP.
8 Places

S9318

1

.196 (5.00)
.189 (4.80)

.061 (1.75)
.053 (1.35)

.0192 (.49)
.0138 (.35)

ORDERING INFORMATION

Base Part Number

.0098 (.25)
.004 (.127)

.05 (1.27) TYP.

S9318 S

FOOTPRINT

.035 (.90)
.016 (.40)

Package

S = 8 Pin SOIC

.020 (.50)
.010 (.25)

.244 (6.20)
.228 (5.80)

2016 ILL4.1

.030 (.762) TYP.
8 Places

x45°

8pn JEDEC SOIC ILL.2

NOTICE

SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve
design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described
herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent
infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon
a user’s specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc.
shall not be liable for any damages arising as a result of any error or omission.

SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety
or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written
assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and
(c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances.

© Copyright 1999 SUMMIT Microelectronics, Inc.

2016-04 4/24/99

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