Page 1
INTEGRATED CIRCUITS
83C751/87C751
80C51 8-bit microcontroller family
2K/64 OTP/ROM, I2C, low pin count
Product specification
Supersedes data of 1998 Jan 19
IC20 Data Handbook
1998 May 01
Page 2
Philips Semiconductors Product specification
80C51 8-bit microcontroller family
2
2K/64 OTP/ROM, I
DESCRIPTION
The Philips 83C751/87C751 offers the advantages of the 80C51
architecture in a small package and at low cost.
The 8XC751 Microcontroller is fabricated with Philips high-density
CMOS technology. Philips epitaxial substrate minimizes CMOS
latch-up sensitivity.
The 8XC751 contains a 2k × 8 ROM (83C751) EPROM (87C751), a
64 × 8 RAM, 19 I/O lines, a 16-bit auto-reload counter/timer, a
five-source, fixed-priority level interrupt structure, a bidirectional
inter-integrated circuit (I
oscillator.
The on-board inter-integrated circuit (I
8XC751 to operate as a master or slave device on the I
area network. This capability facilitates I/O and RAM expansion,
access to EEPROM, processor-to-processor communication, and
efficient interface to a wide variety of dedicated I
FEA TURES
•80C51 based architecture
•Inter-Integrated Circuit (I
•Small package sizes
– 24-pin DIP (300 mil “skinny DIP”)
– 24-pin Shrink Small Outline Package
– 28-pin PLCC
•87C751 available in one-time programmable plastic packages
•Wide oscillator frequency range
•Low power consumption:
– Normal operation: less than 11mA @ 5V, 12MHz
– Idle mode
– Power-down mode
•2k × 8 ROM (83C751)
2k × 8 EPROM (87C751)
•64 × 8 RAM
•16-bit auto reloadable counter/timer
•Fixed-rate timer
•Boolean processor
•CMOS and TTL compatible
•Well suited for logic replacement, consumer and industrial
applications
•LED drive outputs
2
C) serial bus interface, and an on-chip
2
C) serial bus interface
C, low pin count
2
C) bus interface allows the
2
C small
2
C peripherals.
PIN CONFIGURATIONS
P3.4/A4
1
P3.3/A3
2
RST
V
X2
X1
SS
PP
10
11
12
5
11
3
4
5
6
7
8
9
12 18
PinFunction
P3.2/A2/A10
P3.1/A1/A9
P3.0/A0/A8
P0.2/V
P0.1/SDA/OE–PGM
P0.0/SCL/ASEL
Pin Function
1 P3.4/A4
2 P3.3/A3
3 P3.2/A2/A10
4 P3.1/A1/A9
5 NC*
6 P3.0/A0/A8
7 P0.2/V
8 P0.1/SDA/OE-PGM
9 P0.0//SCLASEL
* DO NOT CONNECT
PP
83C751/87C751
24
V
CC
P3.5/A5
23
22
P3.6/A6
21
PLASTIC
DUAL
IN-LINE
PACKAGE
AND
SHRINK
SMALL
OUTLINE
PACKAGE
4126
PLASTIC
LEADED
CHIP
CARRIER
10 NC*
11 RST
12 X2
13 X1
14 V
SS
15 P1.0/D0
16 P1.1/D1
17 P1.2/D2
18 P1.3/D3
P3.7/A7
20
P1.7/T0/D7
P1.6/INT1
19
18
P1.5/INT0/D5
17
P1.4/D4
16
P1.3/D3
15
P1.2/D2
14
P1.1/D1
13
P1.0/D0
25
19
Pin Function
/D6
19 P1.4/D4
20 P1.5/INT0
21 NC*
22 NC*
23 P1.6/INT1
24 P1.7/T0/D7
25 P3.7/A7
26 P3.6/A6
27 P3.5/A5
28 V
CC
/D5
/D6
SU00315
1998 May 01 853-0599 19326
2
Page 3
Philips Semiconductors Product specification
80C51 8-bit microcontroller family
2
2K/64 OTP/ROM, I
C, low pin count
83C751/87C751
ORDERING INFORMATION
ROM EPROM
S83C751–1N24 S87C751–1N24 OTP 0 to +70, Plastic Dual In-line Package 3.5 to 12MHz SOT222-1
S83C751–2N24 S87C751–2N24 OTP –40 to +85, Plastic Dual In-line Package 3.5 to 12MHz SOT222-1
S83C751–4N24 S87C751–4N24 OTP 0 to +70, Plastic Dual In-line Package 3.5 to 16MHz SOT222-1
S83C751–5N24 S87C751–5N24 OTP –40 to +85, Plastic Dual In-line Package 3.5 to 16MHz SOT222-1
S83C751–1A28 S87C751–1A28 OTP 0 to +70, Plastic Leaded Chip Carrier 3.5 to 12MHz SOT261-3
S83C751–2A28 S87C751–2A28 OTP –40 to +85, Plastic Leaded Chip Carrier 3.5 to 12MHz SOT261-3
S83C751–4A28 S87C751–4A28 OTP 0 to +70, Plastic Leaded Chip Carrier 3.5 to 16MHz SOT261-3
S83C751–5A28 S87C751–5A28 OTP –40 to +85, Plastic Leaded Chip Carrier 3.5 to 16MHz SOT261-3
S83C751–1DB S87C751–1DB OTP 0 to +70, Shrink Small Outline Package 3.5 to 12MHz SOT340-1
S83C751–4DB S87C751–4DB OTP 0 to +70, Shrink Small Outline Package 3.5 to 16MHz SOT340-1
NOTE:
1. OTP = One Time Programmable EPROM.
1
TEMPERATURE RANGE °C
AND PACKAGE
FREQUENCY
DRAWING
NUMBER
1998 May 01
3
Page 4
Philips Semiconductors Product specification
80C51 8-bit microcontroller family
2
2K/64 OTP/ROM, I
BLOCK DIAGRAM
V
CC
V
SS
RAM ADDR
REGISTER
B
REGISTER
C, low pin count
RAM
ACC
TMP2
PSW
I2C
CONTROL
ALU
P0.0–P0.2
PORT 0
DRIVERS
PORT 0
LATCH
TMP1
PCON I2CFG I2STA TCON
I2DAT I2CON IE
TH0 TL0
RTH RTL
INTERRUPT, SERIAL
PORT AND TIMER BLOCKS
STACK
POINTER
ROM/
EPROM
83C751/87C751
PROGRAM
ADDRESS
REGISTER
BUFFER
PC
INCRE-
MENTER
RST
TIMING
AND
CONTROL
OSCILLATOR
X1
INSTRUCTION
PD
REGISTER
X2
PORT 1
LATCH
PORT 1
DRIVERS
P1.0–P1.7
PORT 3
LATCH
PORT 3
DRIVERS
P3.0–P3.7
PROGRAM
COUNTER
DPTR
SU00316
1998 May 01
4
Page 5
Philips Semiconductors Product specification
80C51 8-bit microcontroller family
2
2K/64 OTP/ROM, I
C, low pin count
83C751/87C751
PIN DESCRIPTIONS
PIN NO.
MNEMONIC
V
SS
V
CC
P0.0–P0.2 8–6 9–7 I/O Port 0: Port 0 is a 3-bit open-drain, bidirectional port. Port 0 pins that have 1s written to them float,
P1.0–P1.7 13–20 15–20,
P3.0–P3.7 5–1,
RST 9 11 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device.
X1 11 13 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits.
X2 10 12 O Crystal 2: Output from the inverting oscillator amplifier.
NOTE:
1. When P0.2 is at or close to 0V it may affect the internal ROM operation. We recommend that P0.2 be tied to V
(e.g., 2kΩ).
DIP/
SSOP
23–21
LCC TYPE NAME AND FUNCTION
12 14 I Circuit Ground Potential
24 28 I Supply voltage during normal, idle, and power-down operation.
and in that state can be used as high-impedance inputs. Port 0 also serves as the serial I2C
interface. When this feature is activated by software, SCL and SDA are driven low in accordance
with the I
subsystem presents a 0. The state of the pin can always be read from the port register by the
program.
To comply with the I2C specification, P0.0 and P0.1 are open drain bidirectional I/O pins with the
electrical characteristics listed in the tables that follow. While these differ from “standard TTL”
characteristics, they are close enough for the pins to still be used as general-purpose I/O in
non-I
memory as follows:
6 7 N/A VPP (P0.2) – Programming voltage input. (See Note 1.)
7 8 I OE/PGM (P0.1) – Input which specifies verify mode (output enable) or the program mode.
8 9 I ASEL (P0.0) – Input which indicates which bits of the EPROM address are applied to port 3.
7 8 I/O SDA (P0.1) – I2C data.
8 9 I/O SCL (P0.0) – I2C clock.
23, 24
18 20 I INT0 (P1.5): External interrupt.
19 23 I INT1 (P1.6): External interrupt.
20 24 I T0 (P1.7): Timer 0 external input.
6, 4–1,
27–25
OE/PGM = 1 output enabled (verify mode).
OE/PGM = 0 program mode.
ASEL = 0 low address byte available on port 3.
ASEL = 1 high address byte available on port 3 (only the three least significant bits are used).
I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written
to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins
that are externally pulled low will source current because of the internal pull-ups. (See DC
Electrical Characteristics: I
mode and accepts as inputs the value to program into the selected address during the program
mode. Port 1 also serves the special function features of the 80C51 family as listed below:
I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written
to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins
that are externally being pulled low will source current because of the pull-ups. (See DC Electrical
Characteristics: I
be programmed (or verified). The 11-bit address is multiplexed into this port as specified by
P0.0/ASEL.
An internal diffused resistor to VSS permits a power-on RESET using only an external capacitor to
V
the device in the programming state allowing programming address, data and V
programming or verification purposes. The RESET serial sequence must be synchronized with the
X1 input.
X1 also serves as the clock to strobe in a serial bit stream into RESET to place the device in the
programming state.
2
C protocol. These pins are driven low if the port register bit is written with a 0 or if the I2C
2
C applications. Port 0 also provides alternate functions for programming the EPROM
). Port 1 serves to output the addressed EPROM contents in the verify
IL
). Port 3 also functions as the address input for the EPROM memory location to
IL
. After the device is reset, a 10-bit serial sequence, sent LSB first, applied to RESET, places
CC
via a small pullup
CC
to be applied for
PP
1998 May 01
5
Page 6
Philips Semiconductors Product specification
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
80C51 8-bit microcontroller family
2
2K/64 OTP/ROM, I
ABSOLUTE MAXIMUM RATINGS
C, low pin count
1, 2
PARAMETER
83C751/87C751
RATING UNIT
Storage temperature range –65 to +150 °C
Voltage from V
Voltage from any pin to V
CC
to V
SS
(except VPP) –0.5 to VCC + 0.5 V
SS
–0.5 to +6.5 V
Power dissipation 1.0 W
Voltage on VPP pin to V
SS
0 to +13.0 V
Maximum IOL per I/O pin 10 mA
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.
2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.
DC ELECTRICAL CHARACTERISTICS
T
= 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10% for 87C751, VCC = 5V ±10% for 83C751, VSS = 0V
amb
V
IL
V
IH
V
IH1
Input low voltage, except SDA, SCL –0.5 0.2VDD–0.1 V
Input high voltage, except X1, RST 0.2VCC+0.9 VCC+0.5 V
Input high voltage, X1, RST 0.7V
SDA, SCL, P0.2
V
IL1
V
IH2
V
OL
V
OL1
V
OH
Input low voltage –0.5 0.3V
Input high voltage 0.7V
Output low voltage, ports 1 and 3 IOL = 1.6mA
Output low voltage, port 0.2 IOL = 3.2mA
2
2
Output high voltage, ports 1 and 3 IOH = –60µA 2.4 V
IOH = –25µA 0.75V
IOH = –10µA 0.9V
Port 0.0 and 0.1 (I2C) – Drivers
V
OL2
Output low voltage IOL = 3mA 0.4 V
Driver, receiver combined: (over VCC range)
C Capacitance 10 pF
I
IL
I
TL
I
LI
R
RST
C
IO
I
PD
Logical 0 input current, ports 1 and 3 VIN = 0.45V –50 µA
Logical 1 to 0 transition current, ports 1 and 3
3
VIN = 2V (0 to 70°C)
VIN = 2V (–40 to +85°C)
Input leakage current, port 0 0.45 < VIN < V
CC
Internal pull-down resistor 25 175 kΩ
Pin capacitance
Power-down current
4
Test freq = 1MHz,
T
= 25°C
amb
VCC = 2 to VCC max 50 µA
VSS = 0V
V
PP
I
PP
I
CC
VPP program voltage (for 87C751 only)
Program current (for 87C751 only) VPP = 13.0V 50 mA
Supply current (see Figure 2)
VCC = 5V±10%
T
= 21°C to 27°C
amb
NOTES TO DC ELECTRICAL CHARACTERISTICS ON NEXT PAGE.
1
LIMITS
MIN MAX
CC
CC
VCC+0.5 V
CC
VCC+0.5 V
0.45 V
0.45 V
CC
CC
–650
–750
±10 µA
10 pF
12.5 13.0 V
V
V
V
µA
µA
1998 May 01
6
Page 7
Philips Semiconductors Product specification
80C51 8-bit microcontroller family
2
2K/64 OTP/ROM, I
C, low pin count
83C751/87C751
NOTES TO DC ELECTRICAL CHARACTERISTICS:
1. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V
noted.
2. Under steady state (non-transient) conditions, I
Maximum I
Maximum I
Maximum total I
If I
exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
OL
test conditions.
per port pin: 10mA (NOTE: This is 85°C spec.)
OL
per 8-bit port: 26mA
OL
for all outputs: 67mA
OL
must be externally limited as follows:
OL
unless otherwise
SS
3. Pins of ports 1 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when V
4. Power-down I
5. Active I
RST = port 0 = V
6. Idle I
CC
port 0 = V
CC
is measured with all output pins disconnected; X1 driven with t
CC
is measured with all output pins disconnected; X1 driven with t
; RST = VSS.
CC
is measured with all output pins disconnected; port 0 = VCC; X2, X1 n.c.; RST = VSS.
CC
is approximately 2V .
IN
. ICC will be slightly higher if a crystal oscillator is used.
CLCH
CLCH
, t
, t
= 5ns, VIL = VSS + 0.5V, VIH = VCC – 0.5V; X2 n.c.;
CHCL
= 5ns, VIL = VSS + 0.5V, VIH = VCC – 0.5V; X2 n.c.;
CHCL
AC ELECTRICAL CHARACTERISTICS
T
= 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10% for 87C751, VCC = 5V ±10% for 83C751, VSS = 0V
amb
12MHz CLOCK VARIABLE CLOCK
SYMBOL PARAMETER MIN MAX MIN MAX UNIT
1/t
CLCL
Oscillator frequency: 3.5 12 MHz
External Clock (Figure 1)
t
CHCX
t
CLCX
t
CLCH
t
CHCL
High time 20 20 ns
Low time 20 20 ns
Rise time 20 20 ns
Fall time 20 20 ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V
noted.
2. Load capacitance for ports = 80pF.
1, 2
3.5 16 MHz
unless otherwise
SS
1998 May 01
7
Page 8
Philips Semiconductors Product specification
80C51 8-bit microcontroller family
2
2K/64 OTP/ROM, I
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has five characters. The first character is always
‘t’ (= time). The other characters, depending on their positions,
indicate the name of a signal or the logical status of that signal. The
designations are:
C – Clock
D – Input data
H – Logic level high
L – Logic level low
Q – Output data
T – Time
V – V alid
X – No longer a valid logic level
Z – Float
VCC –0.5
0.45V
C, low pin count
+ 0.9
0.2 V
CC
– 0.1
0.2 V
CC
Figure 1. External Clock Drive
t
CHCL
t
CLCX
t
CLCL
t
CLCH
t
CHCX
83C751/87C751
SU00297
22
20
18
16
14
I
(mA)
CC
12
10
8
6
4
2
4MHz 8MHz 12MHz 16MHz
FREQ
Figure 2. ICC vs. FREQ
Maximum I
values taken at VCC max and worst case temperature.
CC
Typical I
values taken at VCC = 5.0V and 25°C.
CC
Notes 5 and 6 refer to DC Electrical Characteristics.
MAX ACTIVE I
TYP ACTIVE I
MAX IDLE I
TYP IDLE I
CC
CC
SU00298
CC
6
CC
6
5
5
1998 May 01
8
Page 9
Philips Semiconductors Product specification
80C51 8-bit microcontroller family
2
2K/64 OTP/ROM, I
OSCILLA T OR CHARACTERISTICS
X1 and X2 are the input and output, respectively, of an inverting
amplifier which can be configured for use as an on-chip oscillator.
To drive the device from an external clock source, X1 should be
driven while X2 is left unconnected. There are no requirements on
the duty cycle of the external clock signal, because the input to the
internal clock circuitry is through a divide-by-two flip-flop. However,
minimum and maximum high and low times specified in the data
sheet must be observed.
RESET
A reset is accomplished by holding the RST pin high for at least two
machine cycles (24 oscillator periods), while the oscillator is running.
To insure a good power-up reset, the RST pin must be high long
enough to allow the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At power-up, the voltage on
V
and RST must come up at the same time for a proper start-up.
CC
IDLE MODE
In idle mode, the CPU puts itself to sleep while all of the on-chip
peripherals stay active. The instruction to invoke the idle mode is the
last instruction executed in the normal operating mode before the
idle mode is activated. The CPU contents, the on-chip RAM, and all
of the special function registers remain intact during this mode. The
idle mode can be terminated either by any enabled interrupt (at
which time the process is picked up at the interrupt service routine
and continued), or by a hardware reset which starts the processor in
the same manner as a power-on reset.
POWER-DOWN MODE
In the power-down mode, the oscillator is stopped and the
instruction to invoke power-down is the last instruction executed.
Only the contents of the on-chip RAM are preserved. A hardware
reset is the only way to terminate the power-down mode. the control
bits for the reduced power modes are in the special function register
PCON.
Table 1. External Pin Status During Idle and
Power-Down Modes
MODE Port 0 Port 1 Port 2
Idle Data Data Data
Power-down Data Data Data
C, low pin count
83C751/87C751
should be noted that stack depth is limited to 64 bytes, the amount
of available RAM. A reset loads the stack pointer with 07 (which is
pre-incremented on a PUSH instruction).
(FFH) 255
Special
Function
Registers
(80H) 128
(3FH) 63
Internal Data
RAM
(00H) 0
SU00299
Figure 3. Memory Map
Program Memory
On the 8XC751, program memory is 2048 bytes long and is not
externally expandable, so the 80C51 instructions MOVX, LJMP, and
LCALL are not implemented. The only fixed locations in program
memory are the addresses at which execution is taken up in
response to reset and interrupts, which are as follows:
Event Address
Reset 000
External INT0
Counter/timer 0 00B
External INT1
Timer I 01B
2
I
C serial 023
Counter/Timer Subsystem
The 8XC751 has one counter/timer called timer/counter 0. Its
operation is similar to mode 2 operation on the 80C51, but is
extended to 16 bits with 16 bits of autoload. The controls for this
counter are centralized in a single register called TCON.
A watchdog timer, called Timer I, is for use with the I
2
In I
C applications, this timer is dedicated to time-generation and
bus monitoring of the I
use as a fixed time-base.
Program Memory
003
013
2
C subsystem.
2
C. In non-I2C applications, it is available for
DIFFERENCES BETWEEN THE 8XC751 AND THE
80C51
Memory Organization
The central processing unit (CPU) manipulates operands in two
address spaces as shown in Figure 3. The part’s internal memory
space consists of 2k bytes of program memory, and 64 bytes of data
RAM overlapped with the 128-byte special function register area.
The differences from the 80C51 are in RAM size (64 bytes vs. 128
bytes), in external RAM access (not available on the 83C751), in
internal ROM size (2k bytes vs. 4k bytes), and in external program
memory expansion (not available on the 83C751). The 128-byte
special function register (SFR) space is accessed as on the 80C51
with some of the registers having been changed to reflect changes
in the 83C751 peripheral functions. The stack may be located
anywhere in internal RAM by loading the 8-bit stack pointer (SP). It
1998 May 01
Counter Timer – Special Function Register
The counter/timer has only one mode of operation, so the TMOD
SFR is not used. There is also only one counter/timer, so there is no
need for the TL1 and TH1 SFRs found on the 80C51. These have
been replaced on the 83C751 by RTL and RTH, the counter/timer
reload registers. Table 3 shows the special function registers, their
locations, and reset values.
Interrupt Subsystem – Fixed Priority
The IP register and the 2-level interrupt system of the 80C51 are
eliminated. Simultaneous interrupt conditions are resolved by a
single-level, fixed priority as follows:
Highest priority: Pin INT0
Lowest priority: Serial I
9
Counter/timer flag 0
Pin INT1
Timer I
2
C
Page 10
Philips Semiconductors Product specification
80C51 8-bit microcontroller family
2
2K/64 OTP/ROM, I
Special Function Register – Interrupt Subsystem
Because the interrupt structure is single level on the 83C751, there
is no need for the IP SFR, so it is not used.
Serial Communications
The 8XC751 contains an I2C serial communications port instead of
the 80C51 UART. The I
interface with all of the hardware necessary to support multimaster
and slave operations. Also included are receiver digital filters and
timer (timer I) for communication watch-dog purposes. The I
serial port is controlled through four special function registers; I
control, I
2
C data, I2C status, and I2C configuration.
Special Function Register –
Serial Communications
The 83C751 contains many of the special function registers (SFR)
that are found on the 80C51. Due to the different peripheral features
on the 83C751, there are several additional SFRs and several that
have been changed.
Since the standard UART found on the 80C51 has been replaced by
2
the I
C serial interface, the UART SFRs, SCON, and SBUF have
2
C serial port is a single bit hardware
C, low pin count
2
C
2
C
been replaced by I2CON and I2DAT, and two additional I
have been added (I2STA and I2CFG).
I/O Port Latches (P0, P1, P3)
The port latches function the same as those on the 80C51. Since
there is no port 2 on the 83C751, the P2 latch is not used. Port 0 on
the 83C751 has only 3 bits, so only 3 bits of the P0 SFR have a
useful function.
Special Function Register – I/O Port Latches
There is no Port2 on the 8XC751, so P2 is not used. Also, only 3
bits of P0 SFR have a useful function.
Data Pointer (DPTR)
The data pointer (DPTR) consists of a high byte (DPH) and a low
byte (DPL). In the 80C51 this register allows the access of external
data memory using the MOVX instruction. Since the 83C751 does
not support MOVX or external memory accesses, this register is
generally used as a 16-bit offset pointer of the accumulator in a
MOVC instruction. DPTR may also be manipulated as two
independent 8-bit registers.
83C751/87C751
2
C registers
Table 2. I2C Special Function Register Addresses
REGISTER ADDRESS BIT ADDRESS
NAME SYMBOL ADDRESS MSB LSB
I2C control I2CON 98 9F 9E 9D 9C 9B 9A 99 98
I2C data I2DAT 99 – – – – – – – –
I2C configuration I2CFG D8 DF DE DD DC DB DA D9 D8
I2C status I2STA F8 FF FE FD FC FB FA F9 F8
ROM CODE SUBMISSION
When submitting ROM code for the 80C751, the following must be specified:
1. 2k byte user ROM data
ADDRESS
0000H to 07FFH DATA 7:0 User ROM Data
CONTENT BIT(S) COMMENT
1998 May 01
10
Page 11
Philips Semiconductors Product specification
80C51 8-bit microcontroller family
2
2K/64 OTP/ROM, I
C, low pin count
83C751/87C751
Table 3. 8XC751 Special Function Registers
SYMBOL DESCRIPTION
ACC* Accumulator E0H E7 E6 E5 E4 E3 E2 E1 E0 00H
B* B register F0H F7 F6 F5 F4 F3 F2 F1 F0 00H
DPTR:
DPH
DPL
I2CFG*# I2C configuration D8H/RD
I2CON*# I2C control 98H/RD RDAT ATN DRDY ARL STR STP
I2DAT# I2C data 99H/RD RDAT 0 0 0 0 0 0 0 80H
Data pointer
(2 bytes)
High byte
Low byte
DIRECT
ADDRESS
83H
82H
WR
WR CXA IDLE CDR CARL CSTR CSTP XSTR XSTP
WR XDAT X X X X X X X
BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION
MSB LSB
DF DE DD DC DB DA D9 D8
SLAVEN MASTRQ
SLAVEN MASTRQ
9F 9E 9D 9C 9B 9A 99 98
0 TIRUN – – CT1 CT0 0000xx00B
CLRTI TIRUN – – CT1 CT0
MASTER
– 81H
RESET
VALUE
00H
00H
FF FE FD FC FB FA F9 F8
I2STA*# I2C status F8H – IDLE XDATA XACTV
AF AE AD AC AB AA A9 A8
IE*# Interrupt enable ABH EA – – EI2 ET1 EX1 ET0 EX0 00H
P0*# Port 0 80H – – – – – – SDA SCL xxxxx111B
97 96 95 94 93 92 91 90
P1* Port 1 90H T0 INT1 INT0 – – – – – FFH
P3* Port 3 B0H B7 B6 B5 B4 B3 B2 B1 B0 FFH
PCON# Power control 87H – – – – – – PD IDL xxxxxx00B
D7 D6 D5 D4 D3 D2 D1 D0
PSW* Program status word D0H CY AC F0 RS1 RS0 OV – P 00H
SP Stack pointer 81H 07H
8F 8E 8D 8C 8B 8A 89 88
TCON*# Timer/counter control 88H GA TE C/T TF TR IE0 IT0 IE1 IT1 00H
MAKSTR MAKSTP
82 81 80
XSTR XSTP x0100000B
TL# Timer low byte 8AH 00H
TH# Timer high byte 8CH 00H
RTL# Timer low reload 8BH 00H
RTH# Timer high reload 8DH 00H
* SFRs are bit addressable.
# SFRs are modified from or added to the 80C51 SFRs.
1998 May 01
11
Page 12
Philips Semiconductors Product specification
80C51 8-bit microcontroller family
2
2K/64 OTP/ROM, I
I/O Port Structure
The 8XC751 has two 8-bit ports (ports 1 and 3) and one 3-bit port
(port 0). All three ports on the 8XC751 are bidirectional. Each
consists of a latch (special function register P0, P1, P3), an output
driver, and an input buffer. Three port 1 pins and two port 0 pins are
multifunctional. In addition to being port pins, these pins serve the
function of special features as follows:
Port PinAlternate Function
P0.0 I
P0.1 I
P1.5 INT0 (external interrupt 0 input)
P1.6 INT1 (external interrupt 1 input)
P1.7 T0 (timer 0 external input)
Ports 1 and 3 are identical in structure to the same ports on the
80C51. The structure of port 0 on the 8XC751 is similar to that of the
80C51 but does not include address/data input and output circuitry.
As on the 80C51, ports 1 and 3 are quasi-bidirectional while port 0 is
bidirectional with no internal pullups.
Timer/Counter
The 8XC751 has two timers: a 16-bit timer/counter and a 10-bit
fixed-rate timer. The 16-bit timer/counter’s operation is similar to
mode 2 operation on the 80C51, but is extended to 16 bits. The
timer/counter is clocked by either 1/12 the oscillator frequency or by
transitions on the T0 pin. The C/T pin in special function register
TCON selects between these two modes. When the TCON TR bit is
set, the timer/counter is enabled. Register pair TH and TL are
incremented by the clock source. When the register pair overflows,
the register pair is reloaded with the values in registers RTH and
RTL. The value in the reload registers is left unchanged. See the
83C751 counter/timer block diagram in Figure 4. The TF bit in
special function register TCON is set on counter overflow and, if the
interrupt is enabled, will generate an interrupt.
2
C clock (SCL)
2
C data (SDA)
C, low pin count
83C751/87C751
TCON Register
MSB LSB
GATE C/T TF TR IE0 IT0 IE1 IT1
GATE 1 – Timer/counter is enabled only when INT0 pin is
high, and TR is 1.
0 – Timer/counter is enabled when TR is 1.
C/T 1 – Counter/timer operation from T0 pin.
0 – Timer operation from internal clock.
TF 1 – Set on overflow of TH.
0 – Cleared when processor vectors to interrupt routine
and by reset.
TR 1 – Timer/counter enabled.
0 – Timer/counter disabled.
IE0 1 – Edge detected in INT0
IT0 1 – INT0
0 – INT0
is edge triggered.
is level sensitive.
IE1 1 – Edge detected on INT1
IT1 1 – INT1
0 – INT1
is edge triggered.
is level sensitive.
These flags are functionally identical to the corresponding 80C51
flags, except that there is only one timer on the 83C751 and the
flags are therefore combined into one register.
Note that the positions of the IE0/IT0 and IE1/IT1 bits are
transposed from the positions used in the standard 80C51 TCON
register.
Timer I is used to control the timing of the I
a “bus locked” condition, by causing an interrupt when nothing
happens on the I
2
C bus for an inordinately long period of time while
a transmission is in progress. If the interrupt does not occur, the
program can attempt to correct the fault and allow the last I2C
transmission to be repeated.
2
The I
C watchdog timer, timer I, is also available as a
general-purpose fixed-rate timer when the I
used. A clock rate of 1/12 the oscillator frequency forms the input to
the timer. Timer I has a timeout interval of 1024 machine cycles
when used as a fixed-rate timer.
.
.
2
C bus and also to detect
2
C interface is not being
1998 May 01
INT0
OSC
T0 Pin
Gate
Pin
÷ 12
C/T = 0
C/T = 1
TR
TL TH TF
Reload
RTL RTH
Int.
SU00300
Figure 4. 83C751 Counter/Timer Block Diagram
12
Page 13
Philips Semiconductors Product specification
80C51 8-bit microcontroller family
2
2K/64 OTP/ROM, I
2
C Serial Interface
I
2
C bus uses two wires (SDA and SCL) to transfer information
The I
between devices connected to the bus. The main features of the bus
are:
•Bidirectional data transfer between masters and slaves
•Serial addressing of slaves (no added wiring)
•Acknowledgment after each transferred byte
•Multimaster bus
•Arbitration between simultaneously transmitting masters without
corruption of serial data on bus
•The 82B715 extends communication distance to 100 feet (30M).
2
A large family of I
of this manual for more details on the bus and available ICs.
The 83C751 I
software required to drive the I
interface which in addition to including the necessary arbitration and
framing error checks, includes clock stretching and a bus timeout
timer. The interface is synchronized to software either through polled
loops or interrupts. Refer to the application note AN422, in
Section 4, entitled “Using the 8XC751 Microcontroller as an I
Master” for additional discussion of the 83C751 I
sample driver routines.
Six time spans are important in I
timer I:
•The MINIMUM HIGH time for SCL when this device is the master.
•The MINIMUM LOW time for SCL when this device is a master.
This is not very important for a single-bit hardware interface like
this one, because the SCL low time is stretched until the software
responds to the I
meets or exceeds the MIN LO time. In cases where the software
responds within MIN HI + MIN LO) time, timer I will ensure that
the minimum time is met.
•The MINIMUM SCL HIGH TO SDA HIGH time in a stop condition.
•The MINIMUM SDA HIGH TO SDA LOW time between I
and start conditions (4.7µs, see spec.).
•The MINIMUM SDA LOW TO SCL LOW time in a start condition.
•The MAXIMUM SCL CHANGE time while an I
progress. A frame is in progress between a start condition and the
following stop condition. This time span serves to detect a lack of
software response on this 8XC751 as well as external I
problems. SCL “stuck low” indicates a faulty master or slave. SCL
“stuck high” may mean a faulty device, or that noise induced onto
2
the I
C bus caused all masters to withdraw from I2C arbitration.
The first five of these times are 4.7µs (see I
covered by the low order three bits of timer I. Timer I is clocked by
the 8XC751 oscillator, which can vary in frequency from 0.5 to
16MHz. Timer I can be preloaded with one of four values to optimize
timing for different oscillator frequencies. At lower frequencies,
software response time is increased and will degrade maximum
C compatible ICs is available. See the I2C section
2
C subsystem includes hardware to simplify the
2
C flags. The software response time normally
C, low pin count
2
C bus. The hardware is a single bit
2
2
2
C
C Bus
C stop
2
C interface and
2
C operation and are insured by
2
C frame is in
2
C specification) and are
83C751/87C751
performance of the I
description for prescale values (CT0, CT1).
The MAXIMUM SCL CHANGE time is important, but its exact span
is not critical. The complete 10 bits of timer I are used to count out
the maximum time. When I
cleared by transitions on the SCL pin. The timer does not run
between I
recently than the last start). When this counter is running, it will carry
out after 1020 to 1023 machine cycles have elapsed since a change
on SCL. A carry out causes a hardware reset of the 83C751 I
interface and generates an interrupt if the timer I interrupt is
enabled. In cases where the bus hangup is due to a lack of software
response by this 83C751, the reset releases SCL and allows I
operation among other devices to continue.
2
I
If I
interrupt will occur whenever the ATN flag is set by a start, stop,
arbitration loss, or data ready condition (refer to the description of
ATN following). In practice, it is not ef ficient to operate the I
interface in this fashion because the I
would somehow have to distinguish between hundreds of possible
conditions. Also, since I
software may execute faster if the code simply waits for the I
interface.
Typically, the I
condition at an idle slave device, or a stop condition at an idle master
device (if it is waiting to use the I
enabling the I
2
I
Reading I2CON
RDAT The data from SDA is captured into “Receive DATa”
ATN “ATteNtion” is 1 when one or more of DRDY, ARL, STR, or
DRDY “Data ReaDY” (and thus ATN) is set when a rising edge
2
C frames (i.e., whenever reset or stop occurred more
C Interrupts
2
C interrupts are enabled (EA and EI2 are both set to 1), an I2C
C Register I2CON
Read
Write CXA IDLE CDR CARL CSTR CSTP XSTR XSTP
765432 1 0
RDAT ATN DRDY ARL STR STP MASTER –
whenever a rising edge occurs on SCL. RDAT is also
available (with seven low-order zeros) in the I2DAT
register. The dif ference between reading it here and there
is that reading I2DAT clears DRDY, allowing the I
proceed on to another bit. T ypically, the first seven bits of a
received byte are read from I2DAT, while the 8th is read
here. Then I2DA T can be written to send the Ack bit and
clear DRDY.
STP is 1. Thus, ATN comprises a single bit that can be
tested to release the I
occurs on SCL, except at idle slave. DRDY is cleared by
writing CDR = 1, or by writing or reading the I2DAT
register. The following low period on SCL is stretched until
the program responds by clearing DRDY.
2
C bus. See special function register I2CFG
2
C operation is enabled, this counter is
2
C
2
2
2
C interrupt service routine
2
C can operate at a fairly high rate, the
2
C interrupt should only be used to indicate a start
2
2
C interrupt only during the aforementioned conditions.
C bus). This is accomplished by
2
C service routine from a “wait loop.”
C
2
C to
2
C
C
1998 May 01
13
Page 14
Philips Semiconductors Product specification
80C51 8-bit microcontroller family
2
2K/64 OTP/ROM, I
Checking ATN and DRDY
When a program detects ATN = 1, it should next check DRDY. If
DRDY = 1, then if it receives the last bit, it should capture the data
from RDAT (in I2DAT or I2CON). Next, if the next bit is to be sent, it
should be written to I2DAT. One way or another, it should clear
DRDY and then return to monitoring ATN. Note that if any of ARL,
STR, or STP is set, clearing DRDY will not release SCL to high, so
that the I
ATN = 1, and DRDY = 0, it should go on to examine ARL, STR, and
STP.
ARL “Arbitration Loss” is 1 when transmit Active was set, but
STR “STaRt” is set to a 1 when an I
STP “SToP” is set to 1 when an I
MASTER“MASTER” is 1 if this 83C751 is currently a master on the
Writing I2CON
Typically, for each bit in an I
ATN = 1. Based on DRDY, ARL, STR, and STP, and on the current
bit position in the message, it may then write I2CON with one or
more of the following bits, or it may read or write the I2DAT register.
CXA Writing a 1 to “Clear Xmit Active” clears the Transmit
2
C will not go on to the next bit. If a program detects
this 83C751 lost arbitration to another transmitter.
Transmit Active is cleared when ARL is 1. There are four
separate cases in which ARL is set.
1. If the program sent a 1 or repeated start, but another
device sent a 0, or a stop, so that SDA is 0 at the
rising edge of SCL. (If the other device sent a stop, the
setting of ARL will be followed shortly by STP being
set.)
2. If the program sent a 1, but another device sent a
repeated start, and it drove SDA low before the
83C751 could drive SCL low. (This type of ARL is
always accompanied by STR = 1.)
3. In master mode, if the program sent a repeated start,
but another device sent a 1, and it drove SCL low
before this 83C751 could drive SDA low.
4. In master mode, if the program sent stop, but it could
not be sent because another device sent a 0.
detected at a non-idle slave or at a master. (STR is not set
when an idle slave becomes active due to a start bit; the
slave has nothing useful to do until the rising edge of SCL
sets DRDY.)
at a non-idle slave or at a master. (STP is not set for a
stop condition at an idle slave.)
2
I
C. MASTER is set when MASTRQ is 1 and the bus is
not busy (i.e., if a start bit hasn’t been received since reset
or a “Timer I” time-out, or if a stop has been received since
the last start). MASTER is cleared when ARL is set, or
after the software writes MASTRQ = 0 and then XSTP = 1.
2
C message, a service routine waits for
Active state. (Reading the I2DAT register also does this.)
C, low pin count
2
C start condition is
2
C stop condition is detected
83C751/87C751
Regarding Transmit Active
Transmit Active is set by writing the I2DAT register, or by writing
I2CON with XSTR = 1 or XSTP = 1. The I
the SDA line low when Transmit Active is set, and the ARL bit will
only be set to 1 when Transmit Active is set. Transmit Active is
cleared by reading the I2DAT register, or by writing I2CON with
CXA = 1. Transmit Active is automatically cleared when ARL is 1.
IDLE Writing 1 to “IDLE” causes a slave’s I
ignore the I
is 1, then a stop condition will make the 83C751 into a
master).
CDR Writing a 1 to “Clear Data Ready” clears DRDY. (Reading
or writing the I2DAT register also does this.)
CARL Writing a 1 to “Clear Arbitration Loss” clears the ARL bit.
CSTR Writing a 1 to “Clear STaRt” clears the STR bit.
CSTP Writing a 1 to “Clear SToP” clears the STP bit. Note that if
one or more of DRDY, ARL, STR, or STP is 1, the low time
of SCL is stretched until the service routine responds by
clearing them.
XSTR Writing 1s to “Xmit repeated STaRt” and CDR tells the I
hardware to send a repeated start condition. This should
only be at a master. Note that XSTR need not and should
not be used to send an “initial” (nonrepeated) start; it is
sent automatically by the I
includes the effect of writing I2DAT with XDAT = 1; it sets
Transmit Active and releases SDA to high during the SCL
low time. After SCL goes high, the I
the suitable minimum time and then drives SDA low to
make the start condition.
XSTP Writing 1s to “Xmit SToP” and CDR tells the I
to send a stop condition. This should only be done at a
master. If there are no more messages to initiate, the
service routine should clear the MASTRQ bit in I2CFG to 0
before writing XSTP with 1. Writing XSTP = 1 includes the
effect of writing I2DAT with XDAT = 0; it sets Transmit
Active and drives SDA low during the SCL low time. After
SCL goes high, the I
minimum time and then releases SDA to high to make the
stop condition.
NOTE: Because of the manner in which register bit addressing is
implemented in the 80C51 family, the I2CON register should never be
altered by use of the SETB, CLR, CPL, MOV (bit), or JBC
instructions. This is due to the fact that read and write functions of this
register are different. Testing of I2CON bits via the JB and JNB
instructions is supported.
2
C until the next start condition (but if MASTRQ
2
C hardware waits for the suitable
2
C interface will only drive
2
C hardware to
2
C hardware. Writing XSTR = 1
2
C hardware waits for
2
C hardware
2
C
1998 May 01
14
Page 15
Philips Semiconductors Product specification
80C51 8-bit microcontroller family
2
2K/64 OTP/ROM, I
2
C Register I2DAT
I
Read
Write XDAT X X X X X X X
RDAT “Receive DATa” is captured from SDA every rising edge of
XDAT “Xmit Data” sets the data for the next bit. Writing I2DAT
Regarding Software Response Time
Because the 83C751 can run at 16MHz, and because the I
interface is optimized for high-speed operation, it is quite likely that
an I
at a rising edge of SCL) and write I2DAT before SCL has gone low
again. If XDAT were applied directly to SDA, this situation would
produce an I
about this possibility because XDAT is applied to SDA only when
SCL is low.
Conversely, a program that includes an I
a long time to respond to DRDY. Typically, an I
on a flag-polling basis during a message, with interrupts from other
peripheral functions enabled. If an interrupt occurs, it will delay the
response of the I
about this very much either, because the I
SCL low time until the service routine responds. The only constraint
on the response is that it must not exceed the Timer I time-out,
which is at least 765 microseconds.
76543210
RDAT 0 0 0 0 0 0 0
SCL. Reading I2DA T also clears DRDY and the Transmit
Active state.
also clears DRDY and sets the Transmit Active state.
2
C service routine will sometimes respond to DRDY (which is set
2
C protocol violation. The programmer need not worry
2
C service routine. The programmer need not worry
C, low pin count
2
C
2
C service routine may take
2
C routine operates
2
C hardware stretches the
83C751/87C751
2
I
C Register I2CFG
Read
Write SLAVEN MASTRQ CLRTI TIRUN – – CT1 CT0
SLAVEN Writing a 1 to “SLAVe ENable” enables the slave functions
MASTRQ Writing a 1 to “MASTRQ” requests mastership of the I
CLRTI Writing a 1 to this bit clears the Timer I interrupt flag. This
TIRUN Writing a 1 to this bit lets Timer I run; a zero stops and
CT1,0 These two bits are programmed as a function of the OSC
Values to be used in the CT1 and CT0 bits are shown in Table 5. To
allow the I
oscillator frequency , compare the actual oscillator rate to the f
max column in the table. The value for CT1 and CT0 is found in the
first line of the table where f
actual frequency.
The table also shows the osc/12 count for various settings of
CT1/CT0. This allows calculation of the actual minimum high and
low times for SCL as follows:
SCL min high/low time (in microseconds) = 12 * count / osc (in MHz)
For instance, at a 16MHz frequency, with CT1/CT0 set to 10, the
minimum SCL high and low times will be 5.25µs.
The table also shows the Timer I timeout period (given in machine
cycles) for each CT1/CT0 combination. The timeout period varies
because of the way in which minimum SCL high and low times are
measured. When the I
at every SCL transition with a value dependent upon CT1/CT0. The
preload value is chosen such that a minimum SCL high or low time
has elapsed when Timer I reaches a count of 008 (the actual value
preloaded into Timer I is 8 minus the osc/12 count).
7 6 5 4 3210
SLAVEN MASTRQ 0 TIRUN – – CT1 CT0
2
of the I
C subsystem. If SLAVEN and MASTRQ are 0, the
2
I
C hardware is disabled. This bit is cleared to 0 by reset
and by an I
2
C time-out.
If a frame from another master is in progress when this
bit is changed from 0 to 1, action is delayed until a stop
condition is detected. Then, or immediately if a frame is
not in progress, a start condition is sent and DRDY is set
(thus making ATN 1 and generating an I
When a master wishes to release mastership status of
2
the I
C, it writes a 1 to XSTP in I2CON. MASTRQ is
cleared by reset and by an I
2
C time-out.
2
C interrupt).
bit position always reads as a 0.
clears it. Together with SLAVEN, MASTRQ, and
MASTER, this bit determines operational modes as
shown in Table 4.
rate, to optimize the MIN HI and LO time of SCL when
this 83C751 is a master on the I
2
C. The time value
determined by these bits controls both of these
parameters, and also the timing for stop and start
conditions. These bits are cleared to 00 by reset.
2
C bus to run at the maximum rate for a particular
OSC
max is greater than or equal to the
OSC
2
C interface is operating, Timer I is preloaded
2
C.
1998 May 01
15
Page 16
Philips Semiconductors Product specification
80C51 8-bit microcontroller family
2
2K/64 OTP/ROM, I
C, low pin count
83C751/87C751
Table 4. Interaction of TIRUN with SLAVEN, MASTRQ, and MASTER
SLAVEN,
MASTRQ,
MASTER
All 0 0 The I2C interface is disabled. Timer I is cleared and does not run. This is the state assumed after a reset. If an I2C
All 0 1 The I2C interface is disabled. Timer I operates as a free-running time base. Use this mode only in non-I2C
Any or all 1 0 The I2C interface is enabled. The 3 low-order bits of Timer I run for min-time generation, but the hi-order bits do
Any or all 1 1 The I2C interface is enabled. Timer I runs during frames on the I2C, and is cleared by transitions on SCL, and by
TIRUN OPERATING MODE
application wants to ignore the I2C at certain times, it should write SLAVEN, MASTRQ, and TIRUN all to zero.
applications.
not, so that there is no checking for I2C being “hung.” This configuration can be used for very slow I2C operation.
Start and Stop conditions. This is the normal state for I
2
C operation.
Table 5. CT1, CT0 Values
CT1, CT0 OSC/12 COUNT f
10 7 16.8MHz 1023 cycles
01 6 14.4MHz 1022 cycles
00 5 12.0MHz 1021 cycles
11 4 9.6MHz 1020 cycles
MAX TIMEOUT PERIOD
OSC
I2C Register I2STA
READ ONLY
7654 3 2 10
–
IDLE XDATA XACTV MAKSTR MAKSTP XSTR XSTP
MSB LSB
This register is read only and reflects the internal status of the I2C
hardware. IDLE, XSTR, and XSTP reflect the status of the like
named bits in the I2CON register.
XDATA The content of the transmitter buffer.
XACTV Transmitter active.
MAKSTR This bit is high while the hardware is effecting a start
condition.
MAKSTP This bit is high while the hardware is effecting a stop
condition.
XSTR This bit is active while the hardware is effecting a
repeated start condition.
XSTP This bit is active while the hardware is effecting a
repeated stop condition.
Interrupts
The interrupt structure is a five-source, one-level interrupt system.
Interrupt sources common to the 80C51 are the external interrupts
(INT0
, INT1) and the timer/counter interrupt (ET0). The I2C interrupt
(EI2) and Timer I interrupt (ETI) are the other two interrupt sources.
The interrupt sources are listed below in their order of polling
sequence priority.
Upon interrupt or reset the program counter is loaded with specific
values for the appropriate interrupt service routine in program
memory. These values are:
Event Address Priority
Reset 000 Highest
INT0 003
Counter/Timer 0 00B
INT1 013
Timer I 01B
2
I
C 023 Lowest
Program Memory
The interrupt enable register (IE) is used to individually enable or
disable the five sources. Bit EA
be used to globally enable or disable all interrupt sources. The
interrupt enable register is described below. All other interrupt details
are based on the 80C51 interrupt architecture.
Interrupt Enable Register
76543210
EA
Symbol Position Function
EA
– IE.6 Reserved
– IE.5 Reserved
EI2 IE.4 Enables or disables the I
ETI IE.3 Enables or disables the Timer I overflow
EX1 IE.2 Enables or disables external interrupt 1.
ET0 IE.1 Enables or disables the Timer 0 overflow
EX0 IE.0 Enables or disables external interrupt 0.
X X EI2 ETI EX1 ET0 EX0
IE.7 Disables all interrupts. If EA = 0, no interrupt
will be acknowledged. If EA = 1, each interrupt
source is individually enabled or disabled by
setting or clearing its enable bit
If EI2 = 0, the I
interrupt. If ETI = 0, the Timer I interrupt is
disabled.
If EX1 = 0, external interrupt 1 is disabled.
interrupt. If ET0 = 0, theTimer 0 interrupt is
disabled.
If EX0 = 0, external interrupt 0 is disabled.
in the interrupt enable register can
2
2
C interrupt is disabled
C interrupt.
1998 May 01
16
Page 17
Philips Semiconductors Product specification
80C51 8-bit microcontroller family
2
2K/64 OTP/ROM, I
87C751 PROGRAMMING CONSIDERA TIONS
EPROM Characteristics
The 87C751 is programmed by using a modified Quick-Pulse
Programming algorithm similar to that used for devices such as the
87C451 and 87C51. It differs from these devices in that a serial data
stream is used to place the 87C751 in the programming mode.
Figure 5 shows a block diagram of the programming configuration
for the 87C751. Port pin P0.2 is used as the programming voltage
supply input (V
(PGM/) signal. This pin is used for the 25 programming pulses.
Port 3 is used as the address input for the byte to be programmed
and accepts both the high and low components of the eleven bit
address. Multiplexing of these address components is performed
using the ASEL input. The user should drive the ASEL input high
and then drive port 3 with the high order bits of the address. ASEL
should remain high for at least 13 clock cycles. ASEL may then be
driven low which latches the high order bits of the address internally.
the high address should remain on port 3 for at least two clock
cycles after ASEL is driven low. Port 3 may then be driven with the
low byte of the address. The low address will be internally stable 13
clock cycles later. The address will remain stable provided that the
low byte placed on port 3 is held stable and ASEL is kept low. Note:
ASEL needs to be pulsed high only to change the high byte of the
address.
Port 1 is used as a bidirectional data bus during programming and
verify operations. During programming mode, it accepts the byte to
be programmed. During verify mode, it provides the contents of the
EPROM location specified by the address which has been supplied
to Port 3.
The XTAL1 pin is the oscillator input and receives the master system
clock. This clock should be between 1.2 and 6MHz.
The RESET pin is used to accept the serial data stream that places
the 87C751 into various programming modes. This pattern consists
of a 10-bit code with the LSB sent first. Each bit is synchronized to
the clock input, X1.
Programming Operation
Figures 6 and 7 show the timing diagrams for the program/verify
cycle. RESET should initially be held high for at least two machine
cycles. P0.1 (PGM/) and P0.2 (V
RESET operation. At this point, these pins function as normal
quasi-bidirectional I/O ports and the programming equipment may
pull these lines low. However, prior to sending the 10-bit code on the
RESET pin, the programming equipment should drive these pins
high (V
IH
for the data stream which places the 87C751 in the programming
mode. Data bits are sampled during the clock high time and thus
should only change during the time that the clock is low. Following
transmission of the last data bit, the RESET pin should be held low.
Next the address information for the location to be programmed is
placed on port 3 and ASEL is used to perform the address
multiplexing, as previously described. At this time, port 1 functions
as an output.
A high voltage V
(This sets Port 1 as an input port). The data to be programmed into
the EPROM array is then placed on Port 1. This is followed by a
series of programming pulses applied to the PGM/ pin (P0.1). These
pulses are created by driving P0.1 low and then high. This pulse is
signal). Port pin P0.1 is used as the program
PP
). The RESET pin may now be used as the serial data input
level is then applied to the VPP input (P0.2).
PP
C, low pin count
) will be at VOH as a result of the
PP
83C751/87C751
repeated until a total of 25 programming pulses have occurred. At
the conclusion of the last pulse, the PGM/ signal should remain high.
The V
signal may now be driven to the VOH level, placing the
PP
87C751 in the verify mode. (Port 1 is now used as an output port).
After four machine cycles (48 clock periods), the contents of the
addressed location in the EPROM array will appear on Port 1.
The next programming cycle may now be initiated by placing the
address information at the inputs of the multiplexed buffers, driving
the V
pin to the VPP voltage level, providing the byte to be
PP
programmed to Port1 and issuing the 26 programming pulses on the
PGM/ pin, bringing V
byte.
Programming Modes
The 87C751 has four programming features incorporated within its
EPROM array. These include the USER EPROM for storage of the
application’s code, a 16-byte encryption key array and two security
bits. Programming and verification of these four elements are
selected by a combination of the serial data stream applied to the
RESET pin and the voltage levels applied to port pins P0.1 and
P0.2. The various combinations are shown in Table 6.
Encryption Key Table
The 87C751 includes a 16-byte EPROM array that is programmable
by the end user. The contents of this array can then be used to
encrypt the program memory contents during a program memory
verify operation. When a program memory verify operation is
performed, the contents of the program memory location is
XNOR’ed with one of the bytes in the 16-byte encryption table. The
resulting data pattern is then provided to port 1 as the verify data.
The encryption mechanism can be disable, in essence, by leaving
the bytes in the encryption table in their erased state (FFH) since
the XNOR product of a bit with a logical one will result in the original
bit. The encryption bytes are mapped with the code memory in
16-byte groups. the first byte in code memory will be encrypted with
the first byte in the encryption table; the second byte in code
memory will be encrypted with the second byte in the encryption
table and so forth up to and including the 16the byte. The encryption
repeats in 16-byte groups; the 17th byte in the code memory will be
encrypted with the first byte in the encryption table, and so forth.
Security Bits
Two security bits, security bit 1 and security bit 2, are provided to
limit access to the USER EPROM and encryption key arrays.
Security bit 1 is the program inhibit bit, and once programmed
performs the following functions:
1. Additional programming of the USER EPROM is inhibited.
2. Additional programming of the encryption key is inhibited.
3. Verification of the encryption key is inhibited.
4. Verification of the USER EPROM and the security bit levels may
still be performed.
(If the encryption key array is being used, this security bit should be
programmed by the user to prevent unauthorized parties from
reprogramming the encryption key to all logical zero bits. Such
programming would provide data during a verify cycle that is the
logical complement of the USER EPROM contents).
Security bit 2, the verify inhibit bit, prevents verification of both the
USER EPROM array and the encryption key arrays. The security bit
levels may still be verified.
back down to the VC level and verifying the
PP
1998 May 01
17
Page 18
Philips Semiconductors Product specification
80C51 8-bit microcontroller family
2
2K/64 OTP/ROM, I
Programming and Verifying Security Bits
Security bits are programmed employing the same techniques used
to program the USER EPROM and KEY arrays using serial data
streams and logic levels on port pins indicated in Table 6. When
programming either security bit, it is not necessary to provide
address or data information to the 87C751 on ports 1 and 3.
Verification occurs in a similar manner using the RESET serial
stream shown in Table 6. Port 3 is not required to be driven and the
results of the verify operation will appear on ports 1.6 and 1.7.
Ports 1.7 contains the security bit 1 data and is a logical one if
programmed and a logical zero if not programmed. Likewise, P1.6
contains the security bit 2 data and is a logical one if programmed
and a logical zero if not programmed.
C, low pin count
Erasure Characteristics
Erasure of the EPROM begins to occur when the chip is exposed to
light with wavelengths shorter than approximately 4,000 angstroms.
Since sunlight and fluorescent lighting have wavelengths in this
range, exposure to these light sources over an extended time (about
1 week in sunlight, or 3 years in room level fluorescent lighting)
could cause inadvertent erasure. For this and secondary effects,
it is recommended that an opaque label be placed over the
window. For elevated temperature or environments where solvents
are being used, apply Kapton tape Flourless part number 2345–5 or
equivalent.
The recommended erasure procedure is exposure to ultraviolet light
(at 2537 angstroms) to an integrated dose of at least 15W-s/cm
Exposing the EPROM to an ultraviolet lamp of 12,000µW/cm
83C751/87C751
for 20 to 39 minutes, at a distance of about 1 inch, should be
sufficient.
Erasure leaves the array in an all 1s state.
Table 6. Implementing Program/Verify Modes
OPERATION SERIAL CODE P0.1 (PGM/) P0.2 (VPP)
Program user EPROM 296H –* V
Verify user EPROM 296H V
Program key EPROM 292H –* V
Verify key EPROM 292H V
Program security bit 1 29AH –* V
Program security bit 2 298H –* V
Verify security bits 29AH V
NOTE:
* Pulsed from V
to VIL and returned to VIH.
IH
IH
IH
IH
2
.
2
rating
PP
V
IH
PP
V
IH
PP
PP
V
IH
PROGRAMMING
V
VOLTAGE
PP/VIH
CLK SOURCE
XTAL1
RESET
P0.2
P0.1
PULSES
SOURCE
ADDRESS STROBE
MIN 2 MACHINE
CYCLES
UNDEFINED
UNDEFINED
87C751
A0–A10
RESET
CONTROL
LOGIC
P3.0–P3.7
P0.0/ASEL
P0.1
P0.2
XTAL1
RESET
V
CC
V
SS
P1.0–P1.7
Figure 5. Programming Configuration
TEN BIT SERIAL CODE
BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 9
Figure 6. Entry into Program/Verify Modes
+5V
DATA BUS
SU00317
SU00302
1998 May 01
18
Page 19
Philips Semiconductors Product specification
80C51 8-bit microcontroller family
2
2K/64 OTP/ROM, I
C, low pin count
83C751/87C751
EPROM PROGRAMMING AND VERIFICATION
T
= 21°C to +27°C, VCC = 5V ±10%, VSS = 0V
amb
SYMBOL PARAMETER MIN MAX UNIT
1/t
CLCL
1
t
AVGL
t
GHAX
t
DVGL
t
GHDX
t
SHGL
t
GHSL
t
GLGH
2
t
AVQV
t
GHGL
t
MASEL
t
HAHLD
t
HASET
t
ADSTA
NOTES:
1. Address should be valid at least 24t
2. For a pure verify mode, i.e., no program mode in between, t
Oscillator/clock frequency 1.2 6 MHz
Address setup to P0.1 (PROG–) low 10µs + 24t
Address hold after P0.1 (PROG–) high 48t
Data setup to P0.1 (PROG–) low 38t
Data hold after P0.1 (PROG–) high 36t
CLCL
CLCL
CLCL
CLCL
VPP setup to P0.1 (PROG–) low 10 µs
VPP hold after P0.1 (PROG–) 10 µs
P0.1 (PROG–) width 90 110 µs
VPP low (VCC) to data valid 48t
CLCL
P0.1 (PROG–) high to P0.1 (PROG–) low 10 µs
ASEL high time 13t
Address hold time 2t
Address setup to ASEL 13t
Low address to valid data 48t
before the rising edge of P0.2 (VPP).
CLCL
AVQV
is 14t
CLCL
maximum.
CLCL
CLCL
CLCL
CLCL
12.75V
P0.2 (V
)
5V
PP
t
SHGL
25 PULSES
)
P0.1 (PGM
t
t
AVGL
t
ADSTA
GLGH
98µs MIN
10µs MIN
t
DVGLtGHDX
t
MASEL
P0.0 (ASEL)
t
HASET
PORT 3
PORT 1 INVALID DATA VALID DATA DATA TO BE PROGRAMMED INVALID DATA VALID DATA
HIGH ADDRESS LOW ADDRESS
VERIFY MODE PROGRAM MODE VERIFY MODE
t
HAHLD
t
GHGL
5V
t
GHSL
t
AVQV
Figure 7. Program/Verify Cycle
SU00303
1998 May 01
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent
to use the components in the I2C system provided the system conforms to the
2
I
C specifications defined by Philips. This specification can be ordered using the
code 9398 393 40011.
19
Page 20
Philips Semiconductors Product specification
80C51 8-bit microcontroller family
2
2K/64 OTP/ROM, I
DIP24: plastic dual in-line package; 24 leads (300 mil) SOT222-1
C, low pin count
83C751/87C751
1998 May 01
20
Page 21
Philips Semiconductors Product specification
80C51 8-bit microcontroller family
2
2K/64 OTP/ROM, I
PLCC28: plastic leaded chip carrer; 28 leads; pedestal SOT261-3
C, low pin count
83C751/87C751
1998 May 01
21
Page 22
Philips Semiconductors Product specification
80C51 8-bit microcontroller family
2
2K/64 OTP/ROM, I
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1
C, low pin count
83C751/87C751
1998 May 01
22
Page 23
Philips Semiconductors Product specification
80C51 8-bit microcontroller family
2
2K/64 OTP/ROM, I
C, low pin count
83C751/87C751
NOTES
1998 May 01
23
Page 24
Philips Semiconductors Product specification
80C51 8-bit microcontroller family
2
2K/64 OTP/ROM, I
Data sheet status
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
C, low pin count
Definition
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1]
83C751/87C751
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Date of release: 05-98
Document order number: 9397 750 03845
1998 May 01
24
Loading...