Datasheet S80C196MC, S83C196MC Datasheet (Intel Corporation)

*Other brands and names are the property of their respective owners.

Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.

April 1994COPYRIGHT©INTEL CORPORATION, 1995 Order Number: 270946-005

8XC196MC

INDUSTRIAL MOTOR CONTROL

MICROCONTROLLER

87C196MC 16 Kbytes of On-Chip OTPROM*

87C196MC, ROM 16 Kbytes of On-Chip Factory-Programmed OTPROM

80C196MC ROMless

Y

High-Performance CHMOS 16-Bit CPU

Y

16 Kbytes of On-Chip OTPROM/
Factory-Programmed OTPROM

Y

488 bytes of On-Chip Register RAM

Y

Register to Register Architecture

Y

Up to 53 I/O Lines

Y

Peripheral Transaction Server (PTS)
with 11 Prioritized Sources

Y

Event Processor Array (EPA)
Ð 4 High Speed Capture/Compare

Modules

Ð 4 High Speed Compare Modules

Y

Extended Temperature Standard

Y

Two 16-Bit Timers with Quadrature
Decoder Input

Y

3-Phase Complementary Waveform
Generator

Y

13 Channel 8/10-Bit A/D with Sample/
Hold with Zero Offset Adjustment H/W

Y

14 Prioritized Interrupt Sources

Y

Flexible 8-/16-Bit External Bus

Y

1.75 ms 16 x 16 Multiply

Y

3 ms 32/16 Divide

Y

Idle and Power Down Modes

The 8XC196MC is a 16-bit microcontroller designed primarily to control 3 phase AC induction and DC brush­less motors. The 8XC196MC is based on Intel’s MCS

É

96 16-bit microcontroller architecture and is manufac-

tured with Intel’s CHMOS process.

The 8XC196MC has a three phase waveform generator specifically designed for use in ‘‘Inverter’’ motor
control applications. This peripheral allows for pulse width modulation, three phase sine wave generation with
minimal CPU intervention. It generates 3 complementary non-overlapping PWM pulses with resolutions of

0.125 ms (edge trigger) or 0.250 m s (centered).

The 8XC196MC has 16 Kbytes on-chip OTPROM/ROM and 488 bytes of on-chip RAM. It is available in three
packages; PLCC (84-L), SDIP (64-L) and EIAJ/QFP (80-L).

Note that the 64-L SDIP package does not include P1.4, P2.7, P5.1 and the CLKOUT pins.

Operational characteristics are guaranteed over the temperature range of

b

40§Ctoa85§C.

The 87C196MC contains 16 Kbytes on-chip OTPROM. The 83C196MC contains 16 Kbytes on-chip ROM. All
references to the 80C196MC also refers to the 83C196MC and 87C196MC unless noted.

*OTPROM (One Time Programmable Read Only Memory) is the same as EPROM but it comes in an unwindowed package

and cannot be erased. It is user programmable.

8XC196MC

270946– 1

NOTE:

Connections between the standard I/O ports and the bus are not shown.

Figure 1. 87C196MC Block Diagram

2

8XC196MC

PROCESS INFORMATION

This device is manufactured on PX29.5, a CHMOS
III-E process. Additional process and reliability infor­mation is available in Intel’s

Components Quality

and Reliability Handbook,

Order Number 210997.

270946– 16

EXAMPLE: N87C196MC is 84-Lead PLCC OTPROM,
16 MHz.
For complete package dimensional data, refer to the
Intel Packaging Handbook (Order Number 240800).

NOTE:

1. EPROMs are available as One Time Programmable
(OTPROM) only.

Figure 3. The 8XC196MC Family Nomenclature

Thermal Characteristics

Package

i

ja

i

jc

Type

PLCC 35§C/W 13§C/W

QFP 56§C/W 12§C/W

SDIP TBD TBD

All thermal impedance data is approximate for static air
conditions at 1W of power dissipation. Values will change
depending on operation conditions and application. See
the Intel

Packaging Handbook

(order number 240800) for a

description of Intel’s thermal impedance test methodology.

8XC196MC Memory Map

Description Address

External Memory or I/O 0FFFFH

06000H

Internal ROM/EPROM or External 5FFFH
Memory (Determined by EA

)

2080H

Reserved. Must contain FFH. 207FH
(Note 5)

205EH

PTS Vectors 205DH

2040H

Upper Interrupt Vectors 203FH

2030H

ROM/EPROM Security Key 202FH

2020H

Reserved. Must contain FFH. 201FH
(Note 5)

201CH

Reserved. Must Contain 20H 201BH
(Note 5)

CCB1 201AH

Reserved. Must Contain 20H 2019H
(Note 5)

CCB0 2018H

Reserved. Must contain FFH. 2017H
(Note 5)

2014H

Lower Interrupt Vectors 2013H

2000H

SFR’s 1FFFH

1F00H

External Memory 1EFFH

0200H

488 Bytes Register RAM (Note 1) 01FFH

0018H

CPU SFR’s (Notes 1, 3) 0017H

0000H

NOTES:

1. Code executed in locations 0000H to 03FFH will be
forced external.

2. Reserved memory locations must contain 0FFH unless
noted.

3. Reserved SFR bit locations must contain 0.

4. Refer to 8XC196KC for SFR descriptions.

5. WARNING: Reserved memory locations must not be
written or read. The contents and/or function of these lo­cations may change with future revisions of the device.
Therefore, a program that relies on one or more of these
locations may not function properly.

3

8XC196MC

270946– 2

NOTE:

*The pin sequence is correct.

The 64-Lead SDIP package does not include the following pins: P1.4/ACH12, P2.7/COMPARE3, P5.1/INST,
CLKOUT.

Figure 2. 64-Lead Shrink DIP (SDIP) Package

4

8XC196MC

270946– 3

NOTE:

NC means No Connect. Do not connect these pins.

Figure 3. 84-Lead PLCC Package

5

8XC196MC

270946– 4

NOTE:

NC means No Connect. Do not connect these pins.

Figure 4. 80-Lead Shrink EIAJQFP (Quad Flat Pack)

6

8XC196MC

PIN DESCRIPTIONS (Alphabetically Ordered)

Symbol Function

ACH0–ACH12 Analog inputs to the on-chip A/D converter. ACH0–7 share the input pins
(P0.0–P0.7, P1.0 – P1.4)

with P0.0 – 7 and ACH8 –12 share pins with P1.0 – 4. If the A/D is not used,
the port pins can be used as standard input ports.

ANGND Reference ground for the A/D converter. Must be held at nominally the

same potential as V

SS

.

ALE/ADV(P5.0) Address Latch Enable or Address Valid output, as selected by CCR. Both

options allow a latch to demultiplex the address/data bus on the signal’s
falling edge. When the pin is ADV

, it goes inactive (high) at the end of the

bus cycle. ALE/ADV

is active only during external memory accesses. Can be

used as standard I/O when not used as ALE/ADV.

BHE/WRH (P5.5) Byte High Enable or Write High output, as selected by the CCR. BHE will go

low for external writes to the high byte of the data bus. WRH

will go low for

external writes where an odd byte is being written. BHE

/WRH is activated

only during external memory writes.

BUSWIDTH (P5.7) Input for bus width selection. If CCR bits 1 and 2e1, this pin dynamically

controls the bus width of the bus cycle in progress. If BUSWIDTH is low, an
8-bit cycle occurs. If it is high, a 16-bit cycle occurs. This pin can be used as
standard I/O when not used as BUSWIDTH.

CAPCOMP0–CAPCOMP3 The EPA Capture/Compare pins. These pins share P2.0 – P2.3. If not used
(P2.0–P2.3)

for the EPA, they can be configured as standard I/O pins.

CLKOUT Output of the internal clock generator. The frequency is (/2 of the oscillator

frequency. It has a 50% duty cycle.

COMPARE0–COMPARE3 The EPA Compare pins. These pins share P2.4 – P2.7. If not used for the
(P2.4–P2.7)

EPA, they can be configured as standard I/O pins.

EA External Access enable pin. EAe0 causes all memory accesses to be

external to the chip. EA

e

1 causes memory accesses from location 2000H

to 5FFFH to be from the on-chip OTPROM/QROM. EA

e

12.5V causes

execution to begin in the programming mode. EA

is latched at reset.

EXTINT A programmable input on this pin causes a maskable interrupt vector

through memory location 203CH. The input may be selected to be a
positive/negative edge or a high/low level using WGÐPROTECT (1FCEH).

INST (P5.1) INST is high during the instruction fetch from the external memory and

throughout the bus cycle. It is low otherwise. This pin can be configured as
standard I/O if not used as INST.

NMI A positive transition on this pin causes a non-maskable interrupt which

vectors to memory location 203EH. If not used, it should be tied to VSS. May
be used by Intel Evaluation boards.

PORT0 8-bit high impedance input-only port. Also used as A/D converter inputs.

Port0 pins should not be left floating. These pins also used to select
programming modes in the OTPROM devices.

PORT1 5-bit high impedance input-only port. P1.0–P1.4 are also used as A/D

converter inputs. In addition, P1.2 and P1.3 can be used as Timer 1 clock
input and direction select respectively.

PORT2 8-bit bidirectional I/O port. All of the Port2 pins are shared with the EPA I/O

pins (CAPCOMP0 – 3 and COMPARE0 –3).

PORT3 8-bit bidirectional I/O ports with open drain outputs. These pins are shared
PORT4

with the multiplexed address/data bus which uses strong internal pullups.

PORT5 8-bit bidirectional I/O port. 7 of the pins are shared with bus control signals

(ALE

, INST, WR,RD, BHE, READY, BUSWIDTH). Can be used as standard

I/O.

7

8XC196MC

PIN DESCRIPTIONS (Alphabetically Ordered) (Continued)

Symbol Function

PORT6 8-bit output port. P6.6 and P6.7 output PWM, the others are used as the Wave

Form Generator outputs. Can be used as standard output ports.

PWM0, PWM1 Programmable duty cycle, Programmable frequency Pulse Width Modulator
(P6.6, P6.7)

pins. The duty cycle has a resolution of 256 steps, and the frequency can vary
from 122 Hz to 31 KHz (16 MHz input clock). Pins may be configured as
standard output if PWM is not used.

RD (P5.3) Read signal output to external memory. RD is low only during external memory

reads. Can be used as standard I/O when not used as RD

.

READY (P5.6) Ready input to lengthen external memory cycles. If READYe0, the memory

controller inserts wait states until the next positive transition of CLKOUT
occurs with READY

e

1. Can be used as standard I/O when not used as

READY.

RESET Reset input to and open-drain output from the chip. Held low for at least 16

state times to reset the chip. Input high for normal operation. RESET has an
Ohmic internal pullup resistor.

T1CLK Timer 0 Clock input. This pin has two other alternate functions: ACH10 and
(P1.2)

P1.2.

T1DIR Timer 0 Direction input. This pin has two other alternate functions: ACH11 and
(P1.3)

P1.3.

V

PP

The programming voltage is applied to this pin. It is also the timing pin for the
return from Power Down circuit. Connect this pin with a 1 mF capacitor to V

SS

anda1MXresistor to VCC. If the Power Down feature is not used, connect
the pin to V

CC

.

WG1–WG3/WG1–WG3 3 phase output signals and their complements used in motor control
(P6.0–P6.5)

applications. The pins can also be configured as standard output pins.

WR/WRL (P5.2) Write and Write Low output to external memory. WR will go low every external

write. WRL

will go low only for external writes to an even byte. Can be used as

standard I/O when not used as WR

/WRL.

XTAL1 Input of the oscillator inverter and the internal clock generator. This pin should

be used when using an external clock source.
XTAL2 Output of the oscillator inverter.
PMODE Determines the EPROM programming mode.

(P0.4–7)
PACT A low signal in Auto Programming mode indicates that programming is in

(P2.5)

process. A high signal indicates programming is complete.
PALE A falling edge in Slave Programming Mode and Auto Configuration Byte

(P2.1)

Programming Mode indicates that ports 3 and 4 contain valid programming

address/command information (input to slave).
PROG A falling edge in Slave Programming Mode begins programming. A rising edge

(P2.2)

ends programming.
PVER A high signal in Slave Programming Mode and Auto Configuration Byte

(P2.0)

Programming Mode indicates the byte programmed correctly.
CPVER Cumulative Program Verification. Pin is high if all locations since entering a

(P2.6)

programming mode have programmed correctly.
AINC Auto Increment. Active low input enables the auto increment mode. Auto

(P2.4)

increment will allow reading or writing of sequential EPROM locations without

address transactions across the PBUS for each read or write.

8

8XC196MC

ABSOLUTE MAXIMUM RATINGS

Ambient Temperature

Under Bias АААААААААААААААААА

b

40§Ctoa85§C

Storage Temperature ААААААААААb65§Ctoa150§C

Voltage from EA or V

PP

to VSSor ANGNDААААААААААААААААААААa13.00V

Voltage on V

PP

or EQ

to VSSor ANGND ААААААААААААААb0.5V to 13.0V

Voltage on Any Other Pin

to V

SS

or ANGND АААААААААААb0.5V toa7.0V

(1)

Power Dissipation ААААААААААААААААААААААА1.5W

(2)

NOTES:

1. This includes V

PP

and EA on ROM or CPU only devices.

2. Power dissipation is based on package heat transfer lim­itations, not device power consumption.

NOTICE: This data sheet contains preliminary infor­mation on new products in production. The specifica­tions are subject to change without notice. Verify with
your local Intel Sales office that you have the latest
data sheet before finalizing a design.

*

WARNING: Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
‘‘Operating Conditions’’ is not recommended and ex­tended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability.

OPERATING CONDITIONS

Symbol Description Min Max Units

T

A

Ambient Temperature Under Bias

b

40

a

85

§

C

V

CC

Digital Supply Voltage 4.50 5.50 V

V

REF

Analog Supply Voltage 4.00 5.50 V

F

OSC

Oscillator Frequency 8 16 MHz

NOTE:

ANGND and V

SS

should be nominally at the same potential. Also VSSand V

SS1

must be at the same potential.

DC ELECTRICAL CHARACTERISTICS (Over Specified Operating Conditions)

Symbol Parameter Min Max Units Test Conditions

V

IL

Input Low Voltage

b

0.5 0.3 V

CC

V

V

IH

Input High Voltage 0.7 V

CC

V

CC

a

0.5 V

V

OL

Output Low Voltage 0.3 V I

OL

e

200 mA

Port 2 and 5, P6.6, P6.7, 0.45 V I

OL

e

3.2 mA

CLKOUT

1.5 V I

OL

e

7mA

V

OL1

Output Low Voltage on Port 3/4 1.0 V I

OL

e

15 mA

V

OL2

Output Low Voltage on 0.45 V I

OL

e

10 mA

Port 6.0 – 6.5

V

OH

Output High Voltage V

CC

b

0.3 V I

OH

eb

200 mA

V

CC

b

0.7 V I

OH

eb

3.2 mA

V

CC

b

1.5 V I

OH

eb

7mA

V

th

a

–V

th

b

Hysteresis Voltage Width on 0.2 V Typical
RESET

9

8XC196MC

DC ELECTRICAL CHARACTERISTICS (Over Specified Operating Conditions) (Continued)

Symbol Parameter Min Typ Max Units Test Conditions

I

LI

Input Leakage Current on All Input

g

10 mA0VkV

IN

k

VCC–0.3V (in RESET)

Only Pins

I

LI1

Input Leakage Current on Port0

g

3 mA0VkV

IN

k

V

REF

and Port1

I

IL

Input Low Current on BD Ports

b

70 mAV

IN

e

0.3 V

CC

(Note 1)

I

IL1

Input Low Current on P5.4 and

b

7 mA 0.2 V

CC

P2.6 during Reset

I

OH

Output High Current on P5.4 and

b

2 mA 0.7 V

CC

P2.6 during Reset

I

CC

Active Mode Current in Reset 50 70 mA XTAL1e16 MHz,

I

REF

A/D Conversion Reference Current 2 5 mA

V

CC

e

V

PP

e

V

REF

e

5.5V

I

IDL

Idle Mode Current 15 30 mA

I

PD

Power-Down Mode Current 5 50 mAV

CC

e

V

PP

e

V

REF

e

5.5V

R

RST

RESET Pin Pullup Resistor 6k 65k X

C

S

Pin Capacitance (Any Pin to VSS)10pFF

TEST

e

1.0 MHz

NOTES:

1. BD (Bidirectional ports) include:
P2.0–P2.7, except P2.6
P3.0–P3.7
P4.0–P4.7
P5.0–P5.3
P5.5–P5.7

2. During normal (non-transient) conditions, the following total current limits apply:
P6.0–P6.5 I

OL

:40mA IOH:28mA

P3 I

OL

:90mA IOH:42mA

P4 I

OL

:90mA IOH:42mA

P5, CLKOUT I

OL

:35mA IOH:35mA

P2, P6.6, P6.7 I

OL

:63mA IOH:63mA

10

8XC196MC

EXPLANATION OF AC SYMBOLS

Each symbol is two pairs of letters prefixed by ‘‘T’’ for time. The characters in a pair indicate a signal and its
condition, respectively. Symbols represent the time between the two signal/condition points.

Conditions: Signals:

H Ð High

L Ð Low

V Ð Valid

X Ð No Longer Valid

Z Ð Floating

A Ð Address

B Ð BHE

C Ð CLKOUT

D Ð DATA

G Ð Buswidth

H Ð HOLD

HA Ð HLDA

L Ð ALE/ADV

BR Ð BREQ

RÐRD

WÐWR/WRH/WRL

X Ð XTAL1

Y Ð READY

Q Ð Data Out

AC ELECTRICAL CHARACTERISTICS (Over Specified Operating Conditions)

Test Conditions: Capacitive load on all pins

e

100 pF, Rise and fall timese10 ns, F

OSC

e

16 MHz.

The system must meet the following specifications to work with the 87C196MC:

Symbol Parameter Min Max Units Notes

F

XTAL

Frequency on XTAL1 8 16 MHz 3

T

OSC

1/F

XTAL

62.5 125 ns

T

AVYV

Address Valid to READY Setup 2 T

OSC

b

75 ns

T

LLYV

ALE Low to READY Setup T

OSC

b

70 ns 4

T

YLYH

Not READY Time No Upper Limit ns

T

CLYX

READY Hold after CLKOUT Low 0 T

OSC

b

30 ns 1

T

LLYX

READY Hold after ALE Low T

OSC

b

15 2 T

OSC

b

40 ns 1

T

AVGV

Address Valid to BUSWIDTH Setup 2 T

OSC

b

75 ns

T

LLGV

ALE Low to BUSWIDTH Setup T

OSC

b

60 ns 4

T

CLGX

Buswidth Hold after CLKOUT Low 0 ns

T

AVDV

Address Valid to Input Data Valid 3 T

OSC

b

55 ns 2

T

RLDV

RD Active to Input Data Valid T

OSC

b

22 ns 2

T

CLDV

CLKOUT Low to Input Data Valid T

OSC

b

50 ns

T

RHDZ

End of RD to Input Data Float T

OSC

ns

T

RXDX

Data Hold after RD Inactive 0 ns

NOTES:

1. If Max is exceeded, additional wait states will occur.

2. If wait states are used, add 2 T

OSC

* N, where Nenumber of wait states.

3. Testing performed at 8 MHz. However, the device is static by design and will typically operate below 1 Hz.

4. These timings are included for compatibility with older

b

90 and BH products. They should not be used for newer high-

speed designs.

11

8XC196MC

AC ELECTRICAL CHARACTERISTICS (Continued)

Test Conditions: Capacitive load on all pins

e

100 pF, Rise and fall timese10 ns, F

OSC

e

16 MHz.

The 87C196MC will meet the following timing specifications:

Symbol Parameter Min Max Units Notes

T

XHCH

XTAL1 to CLKOUT High or Low 30 110 ns

T

CLCL

CLKOUT Cycle Time 2 T

OSC

ns

T

CHCL

CLKOUT High Period T

OSC

b

10 T

OSC

a

15 ns

T

CLLH

CLKOUT Falling Edge to ALE Rising

b

515ns

T

LLCH

ALE Falling Edge to CLKOUT Rising

b

20 15 ns

T

LHLH

ALE Cycle Time 4 T

OSC

ns 3

T

LHLL

ALE High Period T

OSC

b

10 T

OSC

a

10 ns

T

AVLL

Address Setup to ALE Falling Edge T

OSC

b

15 ns

T

LLAX

Address Hold after ALE Falling T

OSC

b

40 ns

T

LLRL

ALE Falling Edge to RD Falling T

OSC

b

30 ns

T

RLCL

RD Low to CLKOUT Falling Edge 4 30 ns

T

RLRH

RD Low Period T

OSC

b

5T

OSC

a

25 ns 3

T

RHLH

RD Rising Edge to ALE Rising Edge T

OSC

T

OSC

a

25 ns 1

T

RLAZ

RD Low to Address Float 5 ns

T

LLWL

ALE Falling Edge to WR Falling T

OSC

b

10 ns

T

CLWL

CLKOUT Low to WR Falling Edge 0 25 ns

T

QVWH

Data Stable to WR Rising Edge T

OSC

b

23 ns

T

CHWH

CLKOUT High to WR Rising Edge

b

10 15 ns

T

WLWH

WR Low Period T

OSC

b

30 ns 3

T

WHQX

Data Hold after WR Rising Edge T

OSC

b

25 ns

T

WHLH

WR Rising Edge to ALE Rising Edge T

OSC

b

10 T

OSC

a

15 ns 1

T

WHBX

BHE, INST Hold after WR Rising T

OSC

b

10 ns

T

WHAX

AD8–15 Hold after WR Rising T

OSC

b

30 ns 2

T

RHBX

BHE, INST Hold after RD Rising T

OSC

b

10 ns

T

RHAX

AD8–15 Hold after RD Rising T

OSC

b

30 ns 2

NOTES:

1. Assuming back to back cycles.

2. 8-bit bus only.

3. If wait states are used, add 2 T

OSC

*N, where Nenumber of wait states.

12

8XC196MC

SYSTEM BUS TIMINGS

270946– 5

13

8XC196MC

READY TIMINGS (One Wait State)

270946– 6

BUSWIDTH TIMINGS

270946– 7

14

8XC196MC

EXTERNAL CLOCK DRIVE

Symbol Parameter Min Max Units

1/T

XLXL

Oscillator Frequency 8 16.0 MHz

T

XLXL

Oscillator Period 62.5 125 ns

T

XHXX

High Time 22 ns

T

XLXX

Low Time 22 ns

T

XLXH

Rise Time 10 ns

T

XHXL

Fall Time 10 ns

EXTERNAL CRYSTAL CONNECTIONS

270946– 14

NOTE:

Keep oscillator components close to chip and use
short, direct traces to XTAL1, XTAL2 and V

SS

. When

using crystals, C1

e

20 pF, C2e20 pF. When using
ceramic resonators, consult manufacturer for recom­mended circuitry.

EXTERNAL CLOCK CONNECTIONS

270946– 15

* Required if TTL driver used.

Not needed if CMOS driver is used.

EXTERNAL CLOCK DRIVE WAVEFORMS

270946– 8

An external oscillator may encounter as much as a 100 pF load at XTAL1 when it starts-up. This is due to
interaction between the amplifier and its feedback capacitance. Once the external signal meets the V

IL

and

V

IH

specifications the capacitance will not exceed 20 pF.

AC TESTING INPUT, OUTPUT WAVEFORMS

270946– 9
AC Testing inputs are driven at 3.5V for a Logic ‘‘1’’ and 0.45V for
a Logic ‘‘0’’. Timing measurements are made at 2.0V for a Logic
‘‘1’’ and 0.8V for a Logic ‘‘0’’.

FLOAT WAVEFORMS

270946– 10
For Timing Purposes a Port Pin is no Longer Floating when a
100 mV change from Load Voltage Occurs and Begins to Float
when a 100 mV change from the Loaded V

OH/VOL

Level occurs

I

OL/IOH

e

s

g

15 mA.

15

8XC196MC

A TO D CHARACTERISTICS

The sample and conversion time of the A/D convert­er in the 8-bit or 10-bit modes is programmed by
loading a byte into the ADÐTIME Special Function
Register. This allows optimizing the A/D operation
for specific applications. The ADÐTIME register is
functional for all possible values, but the accuracy of
the A/D converter is only guaranteed for the times
specificed in the operating conditions table.

The value loaded into ADÐTIME bits 5, 6, 7 deter­mines the sample time, T

SAM

, and is calculated us-

ing the following formula:

SAM

e

(T

SAM

c

F

OSC

)b2

8

T

SAM

e

Sample time, ms

F

OSC

e

Processor frequency, MHz

SAM

e

Value loaded into ADÐTIME

bits 5, 6, 7

SAM must be in the range 1 through 7.

The value loaded into ADÐTIME bits 0 –5 deter­mines the conversion time, T

CONV

, and is calculated

using the following formula:

CONV

e

(T

CONV

c

F

OSC

)b3

2B

b

1

T

CONV

e

Conversion time, ms

F

OSC

e

Processor frequency, MHz

B

e

8 for 8-bit conversion

B

e

10 for 10-bit conversion

CONV

e

Value loaded into ADÐTIME

bits 0–5

CONV must be in the range 2 through 31.

The converter is ratiometric, so absolute accuracy is
dependent on the accuracy and stability of V

REF

.

V

REF

must be close to VCCsince it supplies both the
resistor ladder and the analog portion of the convert­er and input port pins. There is also an ADÐTEST
SFR that allows for conversion on ANGND and
V

REF

as well as adjusting the zero offset. The abso­lute error listed is WITHOUT doing any adjustments.

A/D CONVERTER SPECIFICATION

The specifications given assume adherence to the
operating conditions section of this data sheet. Test­ing is performed with V

REF

e

5.12V and 16.0 MHz
operating frequency. After a conversion is started,
the device is placed in the IDLE mode until the con­version is complete.

16

8XC196MC

10-BIT MODE A/D OPERATING CONDITIONS

Symbol Description Min Max Units

T

A

Ambient Temperature

b

40

a

85

§

C

V

CC

Digital Supply Voltage 4.50 5.50 V

V

REF

Analog Supply Voltage 4.00 5.50 V

(1)

T

SAM

Sample Time 1.0 ms

(2)

T

CONV

Conversion Time 10.0 20.0 ms

(2)

F

OSC

Oscillator Frequency 8.0 16.0 MHz

NOTES:

ANGND and V

SS

should nominally be at the same potential.

1. V

REF

must be within 0.5V of VCC.

2. The value of ADÐTIME is selected to meet these specifications.

10-BIT MODE A/D CHARACTERISTICS (Over Specified Operating Conditions)

Parameter Typical

(1)

Min Max Units*

Resolution 1024 1024 Levels

10 10 Bits

Absolute Error 0

g

4 LSBs

Full Scale Error 0.25g0.5 LSBs

Zero Offset Error 0.25g0.5 LSBs

Non-Linearity 1.0g2.0

g

4 LSBs

Differential Non-Linearity

l

b

1

a

2 LSBs

Channel-to-Channel Matching

g

0.1 0

g

1.0 LSBs

Repeatability

g

0.25 0 LSBs

Temperature Coefficients:

Offset 0.009 LSB/C
Full Scale 0.009 LSB/C
Differential Non-Linearity 0.009 LSB/C

Off Isolation

b

60 dB

(2, 3)

Feedthrough

b

60 dB

(2)

VCCPower Supply Rejection

b

60 dB

(2)

Input Series Resistance 750 2K X

(4)

Voltage on Analog Input Pin ANGNDb0.5 V

REF

a

0.5 V

(5, 6)

Sampling Capacitor 3 pF

DC Input Leakage

g

10

g

3.0 mA

NOTES:

*An ‘‘LSB’’, as used here has a value of approximately 5 mV. (See Embedded Microcontrollers and Processors Handbook
for A/D glossary of terms).

1. These values are expected for most parts at 25

§

C but are not tested or guaranteed.

2. DC to 100 KHz.

3. Multiplexer Break-Before-Make is guaranteed.

4. Resistance from device pin, through internal MUX, to sample capacitor.

5. These values may be exceeded if the pin current is limited to

g

2 mA.

6. Applying voltages beyond these specifications will degrade the accuracy of other channels being converted.

7. All conversions performed with processor in IDLE mode.

17

8XC196MC

8-BIT MODE A/D OPERATING CONDITIONS

Symbol Description Min Max Units

T

A

Ambient Temperature

b

40

a

85

§

C

V

CC

Digital Supply Voltage 4.50 5.50 V

V

REF

Analog Supply Voltage 4.00 5.50 V

(1)

T

SAM

Sample Time 1.0 ms

(2)

T

CONV

Conversion Time 7.0 20.0 ms

(2)

F

OSC

Oscillator Frequency 8.0 16.0 MHz

NOTES:

ANGND and V

SS

should nominally be at the same potential.

1. V

REF

must be within 0.5V of VCC.

2. The value of ADÐTIME is selected to meet these specifications.

8-BIT MODE A/D CHARACTERISTICS (Over the Above Operating Conditions)

Parameter Typical

(1)

Min Max Units*

Resolution 256 256 Level

8 8 Bits

Absolute Error 0

g

1 LSBs

Full Scale Error

g

0.5 LSBs

Zero Offset Error

g

0.5 LSBs

Non-Linearity 0

g

1 LSBs

Differential Non-Linearity

l

b

1

a

1 LSBs

Channel-to-Channel Matching 0

g

1.0 LSBs

Repeatability

g

0.25 LSBs

Temperature Coefficients:

Offset 0.003 LSB/C
Full Scale 0.003 LSB/C
Differential Non-Linearity 0.003 LSB/C

Off Isolation

b

60 dB

(2, 3)

Feedthrough

b

60 dB

(2)

VCCPower Supply Rejection

b

60 dB

(2)

Input Series Resistance 750 2K X

(4)

Voltage on Analog Input Pin V

SS

b

0.5 V

REF

a

0.5 V

(5, 6)

Sampling Capacitor 3 pF

DC Input Leakage

g

10

g

3.0 mA

NOTES:

*An ‘‘LSB’’ as used here, has a value of approximately 20 mV. (See Embedded Microcontrollers and Processors Handbook
for A/D glossary of terms).

1. These values are expected for most parts at 25

§

C but are not tested or guaranteed.

2. DC to 100 KHz.

3. Multiplexer Break-Before-Make is guaranteed.

4. Resistance from device pin, through internal MUX, to sample capacitor.

5. These values may be exceeded if the pin current is limited to

g

2 mA.

6. Applying voltages beyond these specifications will degrade the accuracy of other channels being converted.

7. All conversions performed with processor in IDLE mode.

18

8XC196MC

EPROM SPECIFICATIONS

OPERATING CONDITIONS

Symbol Description Min Max Units

T

A

Ambient Temperature during Programming 20 30

§

C

V

CC

Supply Voltage during Programming 4.5 5.5 V

(1)

V

REF

Reference Supply Voltage during Programming 4.5 5.5 V

(1)

V

PP

Programming Voltage 12.25 12.75 V

(2)

V

EA

EA Pin Voltage 12.25 12.75 V

(2)

F

OSC

Oscillator Frequency during Auto 6.0 8.0 MHz
and Slave Mode Programming

T

OSC

Oscillator Frequency during 6.0 12.0 MHz
Run-Time Programming

NOTES:

1. V

CC

and V

REF

should nominally be at the same voltage during programming.

2. V

PP

and VEAmust never exceed the maximum specification, or the device may be damaged.

3. V

SS

and ANGND should nominally be at the same potential (0V).

4. Load capacitance during Auto and Slave Mode programming

e

150 pF.

AC EPROM PROGRAMMING CHARACTERISTICS

Symbol Parameter Min Max Units

T

SHLL

Reset High to First PALE

Low 1100 T

OSC

T

LLLH

PALE Pulse Width 50 T

OSC

T

AVLL

Address Setup Time 0 T

OSC

T

LLAX

Address Hold Time 100 T

OSC

T

PLDV

PROG Low to Word Dump Valid 50 T

OSC

T

PHDX

Word Dump Data Hold 50 T

OSC

T

DVPL

Data Setup Time 0 T

OSC

T

PLDX

Data Hold Time 400 T

OSC

T

PLPH

(1)

PROG Pulse Width 50 T

OSC

T

PHLL

PROG High to Next PALE Low 220 T

OSC

T

LHPL

PALE High to PROG Low 220 T

OSC

T

PHPL

PROG High to Next PROG Low 220 T

OSC

T

PHIL

PROG High to AINC Low 0 T

OSC

T

ILIH

AINC Pulse Width 240 T

OSC

T

ILVH

PVER Hold after AINC Low 50 T

OSC

T

ILPL

AINC Low to PROG Low 170 T

OSC

T

PHVL

PROG High to PVER Valid 220 T

OSC

NOTE:

1. This specification is for the Word Dump Mode. For programming pulses, use the Modified Quick Pulse Algorithm.

19

8XC196MC

DC EPROM PROGRAMMING CHARACTERISTICS

Symbol Parameter Min Max Units

I

PP

VPPSupply Current (When Programming) 100 mA

NOTE:

Do not apply V

PP

until VCCis stable and within specifications and the oscillator/clock has stabilized or the device may be

damaged.

SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE

2709461– 11

NOTE:

P3.0 must be high (‘‘1’’)

20

8XC196MC

SLAVE PROGRAMMING MODE IN WORD DUMP WITH AUTO INCREMENT

270946– 12

NOTE:

P3.0 must be low (‘‘0’’)

SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM
WITH REPEATED PROG PULSE AND AUTO INCREMENT

270946– 13

21

8XC196MC

87C196MC DESIGN
CONSIDERATIONS

When an indirect shift during divide occurs the upper
3 bits of the shift count are not masked completely.
If the shift count register has the value 32*n where n

e

1, 3, 5 or 7, the operand will be shifted 32 times.

This should have resulted in no shift taking place.

DATA SHEET REVISION HISTORY

This data sheet (270946-004) is valid for devices
with a ‘‘B’’ at the end of the topside tracking number.
Data sheets are changed as new device information
becomes available. Verify with your local Intel sales
office that you have the latest version before finaliz­ing a design or ordering devices.

The following important differences exist between
this data sheet (270946-002) and the previous ver­sion (270946-003):

1. The data sheet was reorganized to standard for­mat.

2. Added 83C196MC device.

3. Added package thermal characteristics.

4. Added note on missing pins on SDIP package.

5. Removed SFR maps (now in user’s manual).

6. Added note on T

LLYV

and T

LLGV

specifications.

7. Changed 10-bit mode T

CONV

(MIN) to 10.0 ms

from 15.0 ms.

8. Changed 10-bit mode T

CONV

(MAX) to 20.0 ms

from 18.0 ms.

9. Changed VREF (MIN) in 8- and 10-bit mode to

4.0V from 4.5V.

The following important differences exist between
data sheet 270946-003 and the previous version
(270946-002):

1. The data sheet title was changed to better reflect
the purpose of the 87C196MC as an AC Inverter/
DC Brushless Motor Control Microcontroller.

2. The standard temperature range for this part now
covers

b

40§Ctoa85§C.

3. EXTINT function description now includes
WGÐPROTECT (1FCEH) as the name and ad­dress of the register used to select positive/neg­ative or high/low detection for EXTINT.

4. The memory range 01F00H–01FBFH was added
to the SFR map as RESERVED.

5. I

IL

changed fromb60 mAtob70 mA.

6. I

REF

changed from 5 mA to 2 mA maximum and

the typical specification was removed.

7. The READY description of the READY TIMINGS
(One Wait State) graphic was modified to denote
the shifting of the leading edge of READY versus
frequency. At 16 MHz the falling edge of READY
occurs before the falling edge of ALE.

8. AC Testing Input, Output Waveform was
changed to reflect inputs driven at 3.5V for a
Logic ‘‘1’’ and .45V for a Logic ‘‘0’’ and timing
measurements made at 2.0V for a Logic ‘‘1’’
and 0.8V for a Logic ‘‘0’’.

9. Float Waveform was changed from I

OL/IOH

e

g

15 mA to IOL/I

OH

s

g

15 mA

10. ADÐTIME register for 10-bit conversions was
changed from 0C7H to 0D8H. The number of
sample time states was changed from 24 to 25
states, the conversion time states was changed
from 80 to 240 states, and the total conversion
time for ADÐTIME

e

D8H replaced the total

conversion time for ADÐTIME

e

C7H.

11. The number of sample time states for an 8-bit
conversion was changed from 20 states to 21
states.

12. There is a single entry in the ERRATA section of
this version of the data sheet concerning the
results of an indirect shift during divide.

The following important differences exist between
this data sheet (270946-002) and the previous ver­sion (270946-001):

1. T

A

Ambient Temperature Under Bias Min

changed from

b

20§Ctob40§C.

2. I

REF

A/D Conversion Reference Current Max

changed from 5 mA to 2 mA.

3. Testing levels changed from TTL values to

CMOS values.

4. A/D Input Series Resistance Max changed from

1.2 KX to 2 KX.

22