Datasheet S-7600A Datasheet (Epson)

Download

Page 1

S-7600A TCP/IP NETWORK STACK LSI - Revision 1.3

Hardware Specification

S-7600A

TCP/IP Network Stack LSI

Components Marketing Dept. Marketing Section 2

Phone +81-43-211-1028 Fax +81-43-211-8035

8, Nakase 1-chome, Mihama-ku Chiba-shi, Chiba 261-8507, Japan

Seiko Instruments Inc.

Page 2

Page 3

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

TABLE OF CONTE NTS

1. INTRODUCTION........................................................................................................................... 1-1

1.1. P

1.2. F

1.3. B

1.4. T

1.5. D

1.6. A

1.7. C

RODUCT OVERVIEW EATURES ENEFITS RADEMARKS EFINITIONS PPLICABLE DOCUMENTS AUTIONS

............................................................................................................................... 1-1

................................................................................................................................. 1-1

........................................................................................................................... 1-2

............................................................................................................................ 1-2

................................................................................................................................1-2

............................................................................................................... 1-1

......................................................................................................... 1-2

2. FUNCTIONAL BLOCK DIAGRAM ............................................................................................... 2-1

3. TERMINALS.................................................................................................................................. 3-1

3.1. P

3.2. P

3.3. P

3.4. P

IN ASSIGNMENT ACKAGE DIMENSIONS IN DESCRIPTION IN CONFIGURATION

...................................................................................................................... 3-1

............................................................................................................. 3-2

..................................................................................................................... 3-3

................................................................................................................ 3-4

4. ELECTRICAL CHARACTERISTICS............................................................................................. 4-1

4.1. A

4.2. R

BSOLUTE MAXIMUM RATINGS ECOMMENDED OPERATING CONDITIONS

4.3. DC C

4.4. P

OWER CURRENT CONSUMPTION

HARACTERISTICS

............................................................................................................. 4-2

.................................................................................................. 4-1

................................................................................. 4-1

............................................................................................. 4-2

5. MPU INTERFACE......................................................................................................................... 5-1

5.1. O

5.2. P

VERVIEW

ARALLEL INTERFACE

............................................................................................................................... 5-1

............................................................................................................... 5-1

5.2.1. 68k Family MPU Mode.................................................................................................... 5-2

5.2.1.1. Write Cycle Timing ................................................................................................................5-2

5.2.1.2. Read Cycle Timing................................................................................................................5-3

5.2.2. x80 Family MPU Mode.................................................................................................... 5-4

5.2.2.1. Write Cycle Timing ................................................................................................................5-4

5.2.2.2. Read Cycle Timing................................................................................................................5-5

5.3. S

ERIAL INTERFACE

................................................................................................................... 5-6

5.3.1. Write Cycle Timing.......................................................................................................... 5-6

5.3.2. Read Cycle Timing.......................................................................................................... 5-7

5.4. I

NTERRUPT

............................................................................................................................... 5-8

6. MEMORY REQUIREMENTS........................................................................................................ 6-1

6.1. O

6.2. M

6.3. M

VERVIEW EMORY INTERFACE ARCHITECTURE EMORY MAP

............................................................................................................................... 6-1

........................................................................................ 6-1

.......................................................................................................................... 6-2

7. S-7600A REGISTER DEFINITIONS............................................................................................. 7-1

7.1. O

7.2.

7.3. R

VERVIEW

API R

EGISTER DEFINITIONS

............................................................................................................................... 7-1

EGISTER MAP

................................................................................................................. 7-1

............................................................................................................ 7-4

7.3.1. Revision Register (0x00)................................................................................................ 7-4

7.3.2. General Control Register (0x01).................................................................................... 7-4

7.3.3. Generic Socket Location Register (0x02)...................................................................... 7-5

7.3.4. Master Interrupt (0x04) ..................................................................................................7-5

7.3.5. Serial Port Configuration / Status Register (0x08)......................................................... 7-6

7.3.6. Serial Port Interrupt Register (0x09).............................................................................. 7-8

7.3.7. Serial Port Interrupt Mask Register (0x0A) .................................................................... 7-8

7.3.8. Serial Port Data Register (0x0B).................................................................................... 7-9

7.3.9. BAUD Rate Divider Registers (0x0C-0x0D)................................................................... 7-9

Seiko Instruments Inc.

Page 4

TCP/IP Network Stack LSI

S-7600A

7.3.10. Our IP Address Registers (0x10-0x13) ...................................................................... 7-9

7.3.11. Clock Divider Registers (0x1C-0x1D) ...................................................................... 7-10

7.3.12. Index Register (0x20)............................................................................................... 7-10

7.3.13. Type of Service Register (TOS) (0x21).................................................................... 7-10

7.3.14. Socket Config Status Low Register (0x22)............................................................... 7-11

7.3.15. Socket Status Mid Register (0x23)........................................................................... 7-13

7.3.16. Socket Activate Register (0x24)............................................................................... 7-14

7.3.17. Socket Interrupt Register (0x26) .............................................................................. 7-14

7.3.18. Socket Data Available Register (0x28)..................................................................... 7-15

7.3.19. Socket Interrupt Mask Low Register (0x2A).............................................................7-16

7.3.20. Socket Interrupt Mask High Register (0x2B)............................................................ 7-16

7.3.21. Socket Interrupt Low Register (0x2C)...................................................................... 7-17

7.3.22. Socket Interrupt High Register (0x2D) ..................................................................... 7-17

7.3.23. Socket Data Register (0x2E).................................................................................... 7-18

7.3.24. TCP Data Send and Buffer Out Length Registers (0x30-0x31)............................... 7-18

7.3.25. Buffer In Length Registers (0x32-0x33) ................................................................... 7-18

7.3.26. Urgent Data Pointer Registers (0x34-0x35)............................................................. 7-18

7.3.27. Their Port Registers (0x36-0x37)............................................................................. 7-19

7.3.28. Our Port Registers (0x38-0x39) ............................................................................... 7-19

7.3.29. Socket Status High Register (0x3A)......................................................................... 7-19

7.3.30. Their IP Address Registers (0x3C-0x3F) ................................................................. 7-20

7.3.31. PPP Control and Status Register (0x60).................................................................. 7-21

7.3.32. PPP Interrupt Code (0x61)....................................................................................... 7-22

7.3.33. PPP Max Retry, (0x62).............................................................................................. 7-22

7.3.34. PAP String (0x64)..................................................................................................... 7-23

Hardware Specification Revision 1.3

8. DATA COMMUNICATIONS.......................................................................................................... 8-1

8.1. O

8.2. S

VERVIEW

ERIAL PORT REGISTER MAP

............................................................................................................................... 8-1

................................................................................................... 8-1

8.2.1. Hardware Flow Control (RTS/CTS Handshaking) .......................................................... 8-2

8.2.2. Serial Port Control........................................................................................................... 8-2

8.3. TCP/UDP D

ATA COMMUNICATIONS

.......................................................................................... 8-3

8.3.1. TCP Data Communications............................................................................................ 8-3

8.3.2. UDP Data Communications............................................................................................ 8-4

9. RESET FUNCTIONS .................................................................................................................... 9-1

9.1. O

VERVIEW

............................................................................................................................... 9-1

9.1.1. Hardware Reset Function............................................................................................... 9-1

9.1.2. Software Reset Function................................................................................................. 9-1

10. APPLICATION EXAMPLES........................................................................................................ 10-1

10.1.1. In Case of x80 Family MPU with LCD Controller.......................................................... 10-1

10.1.2. In Case of 68k Family MPU with LCD Controller.......................................................... 10-2

10.1.3. In Case of Serial Interface with LCD Controller ............................................................ 10-3

Seiko Instruments Inc.

Page 5

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

LIST OF FIGURES

IGURE

IGURE IGURE

F F

IGURE

IGURE IGURE

F F

IGURE

IGURE IGURE

F F

IGURE

2-1 B 3-1 P 3-2 P 3-3 C

LOCK DIAGRAM IN ASSIGNMENT ACKAGE DIMENSIONS ONFIGURATION OF EACH PIN

5-1 68K F 5-2 68K F 5-3X80 F 5-4X80 F 5-5 S 5-6 S

ERIAL INTERFACE WRITE TIMING ERIAL INTERFACE READ TIMING

5-7 INT1 I 6-1 M 8-1 S 9-1 H 9-2 S 10-1 E 10-2 E 10-3 E

EMORY INTERFACE ARCHITECTURE ERIAL DATA FORMAT ARDWARE RESET TIMING OFTWARE RESET TIMING XAMPLE FOR X XAMPLE FOR 68K FAMILY XAMPLE FOR SERIAL INTERFACE

............................................................................................................... 2-1

.............................................................................................................. 3-1

MPU W

AMILY

MPU R

AMILY

MPU W

AMILY

MPU R

AMILY

NTERRUPT TIMING

RITE TIMING

EAD TIMING

RITE CYCLE TIMING

EAD CYCLE TIMING

80 F

AMILY

...................................................................................................... 3-2

........................................................................................... 3-4

....................................................................................... 5-2

......................................................................................... 5-3

............................................................................ 5-4

.............................................................................. 5-5

..................................................................................... 5-6

....................................................................................... 5-7

................................................................................................... 5-8

................................................................................. 6-1

....................................................................................................... 8-1

................................................................................................ 9-1

................................................................................................. 9-1

MPU...................................................................................... 10-1

MPU...................................................................................... 10-2

.................................................................................... 10-3

Seiko Instruments Inc.

iii

Page 6

TCP/IP Network Stack LSI

S-7600A

3-1 P

ABLE

3-2 P

ABLE

4-1 A

ABLE

4-2 R

ABLE

4-3 DC C

ABLE

4-4 P

ABLE

5-1 I

ABLE

5-2 C

ABLE

5-3 68K F

ABLE

5-4 68K F

ABLE

5-5 X80 F

ABLE

5-6 X80 F

ABLE

5-7 S

ABLE

5-8 S

ABLE

5-9 I

ABLE

6-1 S-7600A M

ABLE

6-2 S-7600A M

ABLE

7-1 IAPI R

ABLE

7-2 IAPI R

ABLE

7-3 R

ABLE

7-4 R

ABLE

7-5 G

ABLE

7-6 G

ABLE

7-7 G

ABLE

7-8 G

ABLE

7-9 M

ABLE

7-10 M

ABLE

7-11 C

ABLE

7-12 C

ABLE

7-13 S

ABLE

7-14 S

ABLE

7-15 S

ABLE

7-16 S

ABLE

7-17 O

ABLE

7-18 O

ABLE

7-19 O

ABLE

7-20 O

ABLE

7-21 I

ABLE

7-22 I

ABLE

7-23 S

ABLE

7-24 S

ABLE

7-25 S

ABLE

7-26 S

ABLE

7-27 S

ABLE

7-28 S

ABLE

7-29 S

ABLE

7-30 S

ABLE

7-31 S

ABLE

7-32 S

ABLE

7-33 S

ABLE

7-34 S

ABLE

7-35 S

ABLE

7-36 S

ABLE

7-37 S

ABLE

7-38 S

ABLE

7-39 S

ABLE

IN ASSIGNMENT IN DESCRIPTION BSOLUTE MAXIMUM RATINGS ECOMMENDED OPERATING CONDITIONS

HARACTERISTICS

OWER CURRENT CONSUMPTION

NTERFACE SELECTION

ONNECTION RELATIONSHIP BETWEEN

AMILY AMILY AMILY

AMILY ERIAL INTERFACE WRITE CYCLE TIMING ERIAL INTERFACE READ CYCLE TIMING

NTERRUPT SELECTION TABLE

EGISTER MAP

EGISTER MAP (CONTINUED EVISION REGISTER BIT DEFINITIONS EVISION REGISTER DESCRIPTION

ENERAL CONTROL REGISTER BIT DEFINITIONS ENERAL CONTROL REGISTER DESCRIPTION ENERIC SOCKET LOCATION REGISTER BIT DEFINITIONS ENERIC SOCKET LOCATION REGISTER DESCRIPTION ASTER INTERRUPT REGISTER BIT DEFINITIONS

ASTER INTERRUPT REGISTER DESCRIPTIONS (CONTINUED ONF STATUS REGISTER BIT DEFINITIONS ONF STATUS REGISTER DESCRIPTION ERIAL PORT INTERRUPT REGISTER BIT DEFINITIONS ERIAL PORT INTERRUPT REGISTER DESCRIPTION ERIAL PORT INTERRUPT MASK REGISTER BIT DEFINITIONS ERIAL PORT INTERRUPT MASK REGISTER DESCRIPTION

IP A

NDEX REGISTER BIT DEFINITION NDEX REGISTER DESCRIPTION

OCKET CONFIG STATUS LOW REGISTER BIT DEFINITIONS OCKET CONFIG STATUS LOW REGISTER DESCRIPTION OCKET STATUS MID REGISTER BIT DEFINITIONS OCKET STATUS MID REGISTER DESCRIPTION OCKET ACTIVATE REGISTER BIT DEFINITIONS OCKET ACTIVATE REGISTER DESCRIPTION OCKET INTERRUPT REGISTER BIT DEFINITIONS OCKET INTERRUPT REGISTER DESCRIPTION OCKET DATA AVAIL REGISTER BIT DEFINITIONS OCKET DATA AVAIL REGISTER DESCRIPTION OCKET INTERRUPT MASK LOW REGISTER BIT DEFINITIONS OCKET INTERRUPT MASK LOW REGISTER DESCRIPTION OCKET INTERRUPT MASK HIGH REGISTER BIT DEFINITIONS OCKET INTERRUPT MASK HIGH REGISTER DESCRIPTION OCKET INTERRUPT LOW REGISTER BIT DEFINITIONS OCKET INTERRUPT LOW REGISTER DESCRIPTION OCKET INTERRUPT HIGH REGISTER BIT DEFINITIONS

.................................................................................................................. 3-1

.................................................................................................................. 3-3

MPU W MPU R MPU W MPU R

EMORY MAP (BANK EMORY MAP (BANK

DDRESS REGISTER BIT DEFINITIONS (0X DDRESS REGISTER BIT DEFINITIONS (0X DDRESS REGISTER BIT DEFINITIONS (0X DDRESS REGISTER BIT DEFINITIONS (0X

Hardware Specification Revision 1.3

LIST OF TABLES

.............................................................................................. 4-1

.............................................................................. 4-1

.......................................................................................................... 4-2

.......................................................................................... 4-2

.......................................................................................................... 5-1

MPU

AND PINS

RITE CYCLE TIMING

EAD CYCLE TIMING

RITE CYCLE TIMING

EAD CYCLE TIMING

................................................................................ 5-2

................................................................................. 5-3

................................................................................ 5-4

................................................................................. 5-5

.............................................................................. 5-6

................................................................................ 5-7

............................................................................................... 5-8

0)......................................................................................... 6-2

1)......................................................................................... 6-2

............................................................................................................. 7-2

)........................................................................................ 7-3

.................................................................................... 7-4

........................................................................................ 7-4

......................................................................... 7-4

........................................................................... 7-6

............................................................................... 7-7

....................................................................................... 7-10

.......................................................................................... 7-10

................................................................... 7-13

....................................................................... 7-14

.................................................................... 7-15

................................................................... 7-15

.......................................................... 5-1

.................................................................... 7-4

....................................................... 7-5

........................................................... 7-5

.................................................................... 7-5

)............................................... 7-6

.......................................................... 7-8

............................................................... 7-8

................................................. 7-8

..................................................... 7-8

10) .......................................................... 7-9

11) .......................................................... 7-9

12) ........................................................ 7-10

13) ........................................................ 7-10

................................................ 7-11

..................................................... 7-12

.............................................................. 7-13

.................................................................. 7-14

................................................................ 7-14

............................................................... 7-15

.............................................. 7-16

................................................... 7-16

.............................................. 7-16

.................................................. 7-16

........................................................ 7-17

............................................................. 7-17

....................................................... 7-17

Seiko Instruments Inc.

Page 7

TCP/IP Network Stack LSI

S-7600A

7-40 S

ABLE ABLE

T T

ABLE

ABLE ABLE

T T

ABLE

ABLE ABLE

T T

ABLE

ABLE ABLE

T T

ABLE

7-41 T 7-42 T 7-43 O 7-44 O 7-45 S 7-46 S 7-47 T 7-48 T 7-49 T 7-50 T 7-51 PPP C 7-52 PPP C 7-53 PPP I 7-54 PPP I 7-55 PPP M 7-56 PAP S 7-57 PAP S 8-1 S 8-12 H

OCKET INTERRUPT HIGH REGISTER DESCRIPTION

HEIR PORT REGISTER BIT DEFINITIONS (0X HEIR PORT REGISTER BIT DEFINITIONS (0X

UR PORT REGISTER BIT DEFINITIONS (0X UR PORT REGISTER BIT DEFINITIONS (0X

OCKET STATUS HIGH REGISTER BIT DEFINITIONS OCKET STATUS HIGH REGISTER DESCRIPTION

IP A

HEIR HEIR HEIR HEIR

ERIAL PORT REGISTER MAP

EADER STRUCTURE

DDRESS REGISTER BIT DEFINITIONS (0X

IP A

DDRESS REGISTER BIT DEFINITIONS (0X

IP A

DDRESS REGISTER BIT DEFINITIONS (0X

IP A

DDRESS REGISTER BIT DEFINITIONS (0X ONTROL AND STATUS REGISTER BIT DEFINITIONS (0X ONTROL STATUS REGISTER DESCRIPTION

NTERRUPT CODE REGISTER BIT DEFINITIONS NTERRUPT ERROR CODES

AX RETRY REGISTER TRING FORMAT TRING EXAMPLE

Hardware Specification Revision 1.3

............................................................ 7-18

36) ................................................................ 7-19

37) ................................................................ 7-19

38)................................................................... 7-19

39)................................................................... 7-19

............................................................. 7-19

................................................................. 7-20

3C) ..................................................... 7-20

3D) ..................................................... 7-20

3E)...................................................... 7-20

3F)...................................................... 7-20

60) ........................................ 7-21

............................................................... 7-21

........................................................... 7-22

........................................................................................ 7-22

.............................................................................................. 7-22

....................................................................................................... 7-23

...................................................................................................... 7-23

................................................................................................ 8-1

.......................................................................................................... 8-5

Seiko Instruments Inc.

Page 8

Page 9

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

1. Introduction

1.1. Product Overview

The S-7600A is a LSI that integrates TCP/IP network stack. It offers your devices a quicker and easier connectivity to a network with its on-chip serial interface and a static RAM that operates as a buffer. Implementing this LSI into your system can significantly reduce y our software development cost. Also its low operating frequency gives benefits to the power consumption. The S-7600A also supports a microprocessor interface via the iReady iAPI to Physical Transport Layer Interface. iAPI consists of a set of register and operating definitions that allow any micro controller system to interface with the internal modules.

1.2. Features

z Industry standard protocols support :

TCP/IP (Ver. 4.0) PPP (STD-51-compliant) UDP

z General purpose sockets :

Configured for two sockets

z MPU interface :

68k/x80(MOTO/Intel) bus interface or Synchronous serial interface

z Physical Transport Layer Interface :

Universal Asynchronous Receiver/Transmitter (UART)

z Low clock rate :

Multiplied four by the bit-rate

z Operating frequency :

256kHz typical

z Low power consumption :

Full-transmitting Operating current consumption : 0.9mA typ. Non-transmitting Operating current consumption : 150µA typ. Standby current consumption : 1.0µA typ.

z Stand-by mode :

held by RESET signal

z Wide operating voltage range :

2. 4V to 3.6V

z Easier application development :

portable iAPI

support

1.3. Benefits

z Off-loads MIPS allowing system to operate with low end and low cost processors. z Consumes minimal power-up to 1/100 of competing solution.

Seiko Instruments Inc.

1-1

Page 10

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

1.4. Trademarks

iReady iAPITM and iAPITM is a trademark of iReady Corporation. All other products and brand names are trademarks and registered trademarks of their respective companies.

1.5. Definitions

z IP Internet Protocol z PPP Point-to-Point Protocol z TCP Transmission Control Protocol z UDP User Datagram Protocol z API Application Programming Interface

1.6. Applicable Documents

z S-7600A Functional Specification z S-7600A API Application Manual

1.7. Cautions

1. DO NOT apply a voltage or current that exceeds the absolute maximum ratings to terminals. If applied, the IC may malfunction or be destroyed. The standard values are set with sufficient margins, but use the IC within the recommended operating conditions to optimize device quality.

2. Measures against static electricity

2.1 When transporting or storing ICs, use conductive containers or metal coated boxes.

2.2 Check that there is no current leakage in electrical facilities, and be sure to ground them. Also ensure that workbenches and people who handle ICs are grounded.

3. Excessive external noise to the power supply or I/O terminals of CMOS ICs causes latch-up, leading to faults and damage. If latch-up has occurred, immediately turn off the device, eliminate the cause, and turn on the device again.

4. Keep the IC away from mechanical vibration, shock, and sudden changes in temperature. These may cause wires to break.

5. Environment

5.1 Use and store ICs below the absolute maximum rated temperature.

5.2 DO NOT use or store ICs where condensation can occur.

5.3 DO NOT use ICs where they are directly exposed to dust, salt, or acid gas such as SO These may cause leaks between element leads and cause corrosion.

5.4 To store ICs for a long time, DO NOT process them. During storage, DO NOT apply any load to ICs.

1-2

Seiko Instruments Inc.

Page 11

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

2. Functional Block Diagram

Figure 2-1 shows a functional block diagram of the S-7600A. There are blocks of the Network Stack and other functions related to it. The S-7600A has the interface for a host MPU and a Physical layer for various data terminal equipment.

SD(7:0) CS

PSX C86 RS READX WRITEX BUSYX INTCTL INT1 INT2X

CLK

RESETX

MPU Interface

Network Stack

UDP TCP

PPP

Physical Layer

Interface

16-byte

FIFO

1-byte

BUFFER

SRAM

10Kbytes

SRAM Interface

S2P

DSRXRIRXD

RTSX

The transport and network layers contain:

z Two general sockets that provide connectivity between the application layer and the transport layer. z TCP/UDP module that allows for reliable (retransmission) and unreliable (no retransmission)

datagram deliveries.

z IP module that provides connectionless packet delivery. z PPP module that provides point-to-point connection link between two hosts.

Figure 2-1 Block Diagram

Seiko Instruments Inc.

P2S

DCD

DTRX

TXD

CTSX

2-1

Page 12

TCP/IP Network Stack LSI

S-7600A

3. Terminals

Hardware Specification Revision 1.3

3.1.

Pin Assignment

Figure 3-1 shows Pin Assignment in Package.

36 25

INT1

INT2X

BUSYX

SD7

NC TI2 SD6 TI1 VDD SD5 SD4 SD3 SD2 SD1

SD0

RESETX

CLK

TEST

Figure 3-1Pin Assignment

INTCTRL

VSS

WRITEX

CTSX

READX

C86

VSS

PSX

TI4

TI5 TI6 TI7 VDD TO1 TO2 TO3 TO4 TO5 TO6 TO7

TXD

RTSX

DTRX

DCD

RXD

DSRX

TI3

Table 3-1 shows signal names, listed by Pin Number.

Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name

1 RESETX 13 TO7 25 TI3 37 SD7 2 TEST 14 TO6 26 RS 38 NC 3 CLK 15 TO5 27 CS 39 TI2 4 VSS 16 TO4 28 C86 40 SD6 5 CTSX 17 TO3 29 READX 41 TI1 6 DSRX 18 TO2 30 VSS 42 VDD 7 RI 19 TO1 31 PSX 43 SD5 8 RXD 20 VDD 32 WRITEX 44 SD4

9 DCD 21 TI7 33 INTCTRL 45 SD3 10 DTRX 22 TI6 34 INT1 46 SD2 11 RTSX 23 TI5 35 INT2X 47 SD1 12 TXD 24 TI4 36 BUSYX 48 SD0

Table 3-1 Pin Assignment

3-1

Seiko Instruments Inc.

Page 13

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

3.2. Package Dimensions

S-7600A is housed in a 48-pin QFP package with 0.5mm pin pitch spacing. The package layout is depicted in Figure 3-2.

9.0±0 .3

.3 0

7.0

2536

5±

.3 0

0±

112

0 .2

0 0±

1. .

0.15

+0.10

-0.06

+0.10

0.20

-0.05

Figure 3-2 Package Dimensions

0.50

Seiko Instruments Inc.

0 2

0. 0~

max

1.7

UNIT:mm

3-2

Page 14

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

3.3. Pin Description

The pins and signal descriptions are listed by function in Table 3-2.

Name I/O Description Type VDD1,VDD2 - Positive power supply VSS1,VSS2 - GND potential RESETX I Reset input A TEST,

TI1 to TI7 TO1 to TO7 O Test output

CLK I Clock input C CTSX I Clear to send input C DSRX I Data set ready input C RI I Ring indicator input C RXD I Serial received data input C DCD I Data carrier detect input C DTRX O Data terminal ready output D RTSX O Request to send output D TXD O Serial transmit data output D RS I Register selection input C CS I Chip selection input C C86 I MPU interface mode selection input

READX I x80 mode : read requirement input PSX I parallel/serial interface selection input C

WRITEX I x80 mode : write requirement input INTCTRL I INT1/INT2X drive type(CMOS/OD) selection input C

INT1 *OT Interrupt output(active High) from S-7600A chip to MPU E INT2X *OT Interrupt output(active Low) from S-7600A chip to MPU E BUSYX O busy indicator output D SD7 *B x80/68k mode : data bus

SD6 *B x80/68k mode : data bus SD5 *B x80/68k mode : data bus SD0 to SD4 *B Data bus F

I Test input (pull-down resistor is built in)

When normal use, connect to V When normal use, open

68k mode : 1 x80 mode : 0

68k mode : enable input

68k/Serial mode : read/write selection input

Serial mode : serial data input Serial mode : serial clock input Serial mode : serial data output

*OT : Tri-state output *B : bi-directional

Table 3-2 Pin Description

or open

B D

F F F

3-3

Seiko Instruments Inc.

Page 15

TCP/IP Network Stack LSI

S-7600A

3.4. Pin Configuration

Figure 3-3 shows configuration of each pin.

pad pad

cin

Hardware Specification Revision 1.3

cin

Vss

pad

cin

pad

cin

padpad

inin

oenoen

Figure 3-3 Configuration of Each Pin

Seiko Instruments Inc.

3-4

Page 16

TCP/IP Network Stack LSI

S-7600A

4. Electrical Characteristics

4.1. Absolute Maximum Ratings

Parameter Symbol Conditions Rating Unit

Hardware Specification Revision 1.3

Storage temperature T

Operating temperature T

Power supply voltage V

Input voltage V

Output voltage V

Table 4-1 Absolute Maximum Ratings

sta

opr

OUT

-40 to +125

-40 to +85

Ta=25°C

4.2. Recommended Operating Conditions

Parameter Symbol Conditions Min. Typ. Max. Unit Note

Operating Frequency

range

Clock Pulse

width

Operating voltage

range

OPR

Ta=-40 to +85°C

°C

-0.3 to +4.0 V

-0.3 to VDD+0.3 V

to V

- 0.256 5 MHz 1

80 - - nS

2.4 - 3.6 V

Input voltage V

Note1: The clock is given by the CLK pin and needs to be as four times or more fast as the BAUD rate.

(The multiplier is an integer whose tolerance is <±2%)

Ta=-40 to +85°C

0 - V

Table 4-2 Recommended Operating Conditions

4-1

Seiko Instruments Inc.

Page 17

TCP/IP Network Stack LSI

S-7600A

4.3. DC Characteristics

Parameter Symbol Conditions Min. Typ. Max. Unit

Hardware Specification Revision 1.3

Unless otherwise specified: VDD=3.0V, VSS=0V, Ta=25°C

Low level input

voltage

High level input

voltage

Low level input leakage current High level input leakage current

High level input

current

Low level output

current

High level output

current

Schmitt Hysteresis

voltage

All input terminals without

0.2× V

- -

VIN=V

-1.0 - 1.0 µA

- - V

0.8× V

pull-down resister

IN=VDD

All input terminals with

18 70 220 µA

pull-down resister

IN=VDD

VOL=0.4V 5.0 - - mA

VOH=2.6V - - -3.5 mA

- 0.46 - V

Table 4-3 DC Characteristics

4.4. Power Current Consumption

Parameter Symbol Conditions Min. Typ. Max. Unit

Full-transmitting

Operating current

consumption

Non-transmitting

Operating current

consumption

Standby current

consumption

DD1

DD2

Table 4-4 Power Current Consumption

Unless otherwise specified: VDD=3.0V, VSS=0V, Ta=25°C

Ta=-40 to +85°C

=256KHz

OPR

Ta=-40 to +85°C

=256KHz

OPR

RESETX=V

Ta=-10 to +70°C

- 0.9 2.2 mA

- 150 300 µA

- 1.0 15.0

µA

Ta=-40 to +85°C

30.0

Seiko Instruments Inc.

4-2

Page 18

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

5. MPU Interface

5.1. Overview

The S-7600A supports two MPU interfaces: parallel and serial. In parallel interface mode, S-7600A can interface with x80 Family MPU or 68k Family MPU.

PSX CS RS READXWRITEX BUSYX C86 SD7 SD6 SD5 SD4 to SD0

parallel x80

parallel 68k

serial

CS RS READXWRITEX BUSYX

CS RS

CS RS H or L R/WX BUSYX H or L SI SCL SO

E R/WX BUSYX H D7 D6 D5 D4 to D0

Table 5-1 Interface Selection

L D7 D6 D5 D4 to D0

Hi-Z

5.2. Parallel Interface

Setting PSX to “H” select the parallel interface. In parallel interface mode the S-7600A can interface with either x80 Family MPU or 68k Family MPU. The desired MPU mode can be selected by setting the C86 pin to “H” or “L”.

RS 68k Family MPU

R/WX

1 1 0 0

1 0 1 0

Table 5-2 Connection Relationship between MPU and Pins

x80 Family MPU

READX WRITEX

0 1 0 1

1 0 1 0

Function

Read Register Write Register Read Index Register Write Index Register

5-1

Seiko Instruments Inc.

Page 19

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

5.2.1. 68k Family MPU Mode

This mode can be selected by pulling the C86 input pin “H” and the PSX input pin “H”. In this mode, the address and data are muxed into a single 8-bit bus. All cycles start by placing an address on the bus and setting the RS pin to “L”. In this mode WRITEX signal works as read/write(R/WX) signal and READX is the enable(E) signal for 68k Family MPU interface. After the address cycle, the MPU generates a read or writes strobe by setting the READX and WRITEX pins. The S-7600A MPU interface logic assert a BUSYX signal low during data write and read phases. The MPU samples the BUSYX signal before starting a new cycle. The can initiate a new cycle if the bit is “H”.

5.2.1.1. Write Cycle Timing

WRITEX (R/WX)

READX (E)

AW6

DS6

AH6

DH6

AW6

CYC6

DS6

AH6

DH6

SD7 to 0

BUSYX

CLK

Address

Figure 5-1 68k Family MPU Write Timing

Symbol

CYC6

AH6

AW6

DS6

DH6

BD6

BC6

BOD6

Description

System Cycle Time Address Hold Time Address Setup Time Data Setup time Data Hold Time Enable Pulse Width BUSYX Delay Time BUSYX Pulse Width BUSYX Output Disable Time

NOTES: • CLK is the clock of S-7600A

• Timing is specified of 50% of the signal waveform.

• Rise/fall time(20%,80%) of the input signal is 15nsec or less.

Table 5-3 68k Family MPU Write Cycle Timing

BD6

Min

100 ns 20ns 20ns 20ns 20 ns 40 ns

2CLK

Data

Max

1.9CLK 30ns

30ns

BC6

Notes

BOD6

CL=80pF

Seiko Instruments Inc.

5-2

Page 20

TCP/IP Network Stack LSI

S-7600A

5.2.1.2. Read Cycle Timing

Hardware Specification Revision 1.3

AW6

AH6

WRITEX (R/WX)

READX (E)

SD7 to 0

BUSYX

CLK

Symbol Description

CYC6

AH6

AW6

DS6

DH6

ACC6

OH6

BD6

BC6

BOD6

AW6

System Cycle Time Address Hold Time Address Setup Time Data Setup time Data Hold Time Access time Output Disable Time Enable Pulse Width BUSYX Delay Time BUSYX Pulse Width BUSYX Output Disable Time

DS6

Address

Figure 5-2 68k Family MPU Read Timing

NOTES: • CLK is the clock of S-7600A

• Timing is specified of 50% of the signal waveform.

• Rise/fall time(20%,80%) of the input signal is 15nsec or less.

Table 5-4 68k Family MPU Read Cycle Timing

ACC6

BOD

Data

Notes

CL=80pF CL=80pF

CL=80pF

AH6

OH6

AH6

CYC6

DH6

ACC6

Address

BD6

Min

100 ns 20ns 20ns 20ns 20 ns

20 ns 40 ns

2CLK

AW6

OH6

BC6

Max

30ns

1.9CLK 30ns

30ns

5-3

Seiko Instruments Inc.

Page 21

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

5.2.2. x80 Family MPU Mode

This mode is s elected by pulling the C86 input pin “L” and the PSX input pin “H”. In this mode, the address and data are muxed onto a single 8-bit bus. All cycles start with the address placed on the bus. This address is then latc hed internally on the rising edge of WRITEX. The RS pin “L” indicates that the

WRITEX strobe is for the address phase. In the next phase, data is either written or read by generating WRITEX or READX strobe. The MPU interface logic will assert the BUSYX signal after READX or WRITEX strobes are de-asserted. The BUSYX signal is de-asserted after the S-7600A complete a read

or writes operation. The MPU samples the BUSYX signal befor e starting a new cycle. The MPU can initiate a new cycle after the BUSYX signal gets de-asserted.

5.2.2.1. Wr i t e Cycl e Timing

READX

AW8

CC8

AH8

AW8

CYC8

CC8

AH8

WRITEX

SD 7 to 0

BUSYX

CLK

DS8

Address

read

Figure 5-3 x80 Family MPU Write Cycle Timing

Symbol

CYC8

AH8

AW8

DS8

DH8

CC8

BD8

BC8

BOD8

Description

System Cycle Time Address Hold Time Address Setup Time Data Setup time Data Hold Time Control Pulse Width BUSYX Delay Time BUSYX Pulse Width BUSYX Output Disable Time -

NOTES: • CLK is the clock of S-7600A

• Timing is specified of 50% of the signal waveform.

• Rise/fall time(20%,80%) of the input signal is 15nsec or less.

Table 5-5 x80 Family MPU Write Cycle Timing

DH8

BD8

Min

100 ns 20ns 20ns 20ns 20 ns 40 ns

2CLK -

DS8

Data read

Max

1.9CLK 30ns

30ns

DH8

BC8

Notes

BOD8

CL=80pF

Seiko Instruments Inc.

5-4

Page 22

TCP/IP Network Stack LSI

S-7600A

5.2.2.2. Read Cycle Timing

Hardware Specification Revision 1.3

AW8

CC8

AH8

READX

WRITEX

SD7 to 0

BUSYX

CLK

Symbol

T T T T T T T T T T T

CYC8

AH8

AW8

DS8

DH8

ACC8

OH8

CC8

BD8

BC8

BOD8

AW8

Description

System Cycle Time Address Hold Time Address Setup Time Data Setup time Data Hold Time Access time Output Disable Time Control Pulse Width BUSYX Delay Time BUSYX Pulse Width BUSYX Output Disable Time

CC8

CYC8

DS8

Address

Figure 5-4 x80 Family MPU Read Cycle Timing

NOTES: • CLK is the clock of S-7600A

• Timing is specified of 50% of the signal waveform.

• Rise/fall time(20%,80%) of the input signal is 15nsec or less.

Table 5-6 x80 Family MPU Read Cycle Timing

AH8

ACC8

Address

BD8

Min

100 ns 20ns 20ns 20ns 20 ns

20 ns 40 ns

2CLK

AW8

OH8

BC8

Max

ACC8

BOD

CC8

Data

Notes

AH8

OH8

30ns

1.9CLK 30ns

30ns

CL=80pF CL=80pF

CL=80pF

5-5

Seiko Instruments Inc.

Page 23

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

5.3. Serial Interface

This mode is selected by pulling the PSX input pin “L”. In this mode Bit 6 of the Data Bus is used as the serial clock and bit 5 and 7 are used as Data Input and Data Output. Bit 0 to 4 are high impedance. By pulling WRITEX signal to “H” or “L”, the MPU performs a read or write operation.

5.3.1. Write Cycle Timing

WRITEX (R/WX)

SD6 (SCL)

SD7 (SI)

BUSYX

CLK

ASS

Symbol

CYCS

CLLS

CLHS

ASS

AHS

DSS

DHS

BDS

BCS

BODS

CLLS

CYCS

CLHS

A6 A5 A4

Description

System Cycle Time Clock L Time Clocl H Time Address Setup Time Address Hold Time Data Setup time Data Hold Time BUSYX Delay Time BUSYX Pulse Width BUSYX Output Disable Time

A3 A2 A1 A0

Figure 5-5 Serial Interface Write Timing

DSS

NOTES: • CLK is the clock of S-7600A

• Timing is specified of 50% of the signal waveform.

• Rise/fall time(20%,80%) of the input signal is 15nsec or less.

Table 5-7 Serial Interface Write Cycle Timing

AHS

DHS

ASS

D7 D6 D5 D4

Min

100 ns 1.9CLK 40ns 40 ns 20ns 20ns 20ns 20 ns

2CLK

Max

30ns

D3 D2 D1 D0

BDS

Notes

CL=80pF

AHS

BCS

BODS

Seiko Instruments Inc.

5-6

Page 24

TCP/IP Network Stack LSI

S-7600A

5.3.2. Read Cycle Timing

Hardware Specification Revision 1.3

WRITEX (R/WX)

SD6 (SCL)

SD7 (SI)

SD5 (SO)

BUSYX

CLK

AHS

CLHS

DSS

Figure 5-6 Serial Interface Read Timing

ASS

DHS

DDS

A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

Symbol

CYCS

CLLS

CLHS

ASS

AHS

DSS

DHS

DDS

OHS

BDS

BCS

BODS

ASS

CYCS

CLLS

A7 A6 A5 A4 A3 A2 A1 A0

Description

System Cycle Time Clock L Time Clocl H Time Address Setup Time Address Hold Time Data Setup time Data Hold Time Data delay Time Output Disable Time BUSYX Delay Time BUSYX Pulse Width BUSYX Output Disable Time

NOTES: • CLK is the clock of S-7600A

• Timing is specified of 50% of the signal waveform.

• Rise/fall time(20%,80%) of the input signal is 15nsec or less.

Table 5-8 Serial Interface Read Cycle Timing

AHS

OHS

BDS

Min

100 ns 1.9CLK 40ns 40 ns 20ns 20ns 20ns 20 ns

2CLK

BCS

Max

30ns 20ns 30ns

30ns

ASS

DDS

BODS

Notes

CL=80pF CL=80pF CL=80pF

CL=80pF

AHS

OHS

5-7

Seiko Instruments Inc.

Page 25

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

5.4. Interrupt

The interrupt signal outputs an active level while the interrupt flag is set in the interrupt register in the S-7600A’s interrupt register. The interrupt signal returns to an inactive level if the flag clears. Show the interrupt timing in the Figure 5-7. The INT1 and INT2X can be Open Drain or CMOS output depending on the setting of INTCTL. The INT1 and INT2X outputs are CMOS if INTCTL is “H” otherwise outputs are Open Drain. Table 5-9 defines the interrupt selection.

WRITEX

SD7 to 0

BUSYX

CLK

Interrupt flag

Set

Set Reset Reset

Table 5-9 Interrupt Selection Table

Address

INTCTL

Data

INT1

H H

Hi-Z

INT2X

L L

Hi-Z

INT1

(x80 Family MPU mode, INTCTL=high)

Figure 5-7 INT1 Interrupt Timing

Seiko Instruments Inc.

5-8

Page 26

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

6. Memory Requirements

6.1. Overview

S-7600A contains two general sockets along with the TCP/UDP/IP and PPP protocols. Their total memory requirement is 10K bytes. This memory is included on the S-7600A chip.

6.2. Memory Interface Architecture

The Network Stack feeds all of its m em or y requests into a single Memory Arbiter inside of the Network Stack core. The arbiter then feeds out one memory request to the SRAM interface. This interface serves to translate the network stack's timing into signal timing required by the SRAM. This architecture is shown in Figure 6-1.

Network Stack

TCP / UDP

PPP

Serial Port

Figure 6-1 Memory Interface Architecture

Memory

Arbiter

SRAM

Interface

SRAM

6-1

Seiko Instruments Inc.

Page 27

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

6.3. Memory Map

The memory map has been configured to make the SRAM supporting the S-7600A compact. S-7600A has two 5 K byte memory banks (denoted as “0” and “1”). Their mapping addresses are given in Table 6-1 and Table 6-2. The actual capacity of the incoming buffer is 2047 bytes. The actual capacity of the outgoing buffer is 1023 bytes for TCP mode and 1015 bytes for UDP mode.

Table 6-1 S-7600A Memory Map (Bank 0)

Address

0x0000 - 0x07FF 0x0800 - 0x0BFF 0x0C00 - 0x0FFF 0x1000 - 0x13FF

Table 6-2 S-7600A Memory Map (Bank 1)

Address

0x0000 - 0x07FF 0x0800 - 0x0BFF 0x0C00 - 0x0FFF 0x1000 - 0x13FF

Size

2 K 1 K 1 K 1 K

Size

2 K 1 K 1 K 1 K

Contents

Socket 0 Receive Buffer Socket 0 Send Buffer TCP Data Base IP Buffer

Contents

Socket 1 Receive Buffer Socket 1 Send Buffer PPP Buffer PAP Buffer

Seiko Instruments Inc.

6-2

Page 28

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

7. S-7600A Register Definitions

7.1. Overview

This section covers the S-7600A's API r egist ers . The register are divided into three types: global, direct and indexed.

Global registers occupy the address space from 0x00 to 0x1D and 0x60 to 0x6F. Direct and indexed registers occupy the configuration space from 0x20 to 0x3F. Indexed register require the socket index to be set prior to accessing the registers.

7.2. iAPI Register Map

Table 7-1 and Table 7-2 shows the complete iAPI register m ap for the S-7600A chip. All regis ters not listed are reserved, and should not be accessed.

7-1

Seiko Instruments Inc.

Page 29

TCP/IP Network Stack LSI

S-7600A

Table 7-1 iAPI Register Map

Add Register Bit Definitions 0x00 Revision Major Revision Number Minor Revision Number 0x01 General_Control - - - - - - - SW_

Hardware Specification Revision 1.3

RST

0x02 General_Socket_

0 0 0 0 0 0 S1 S0

Location

0x04 Master_Interrupt - - - - -

0x08 Serial_Port_Config

0x09 Serial_Port_Int

0x0A Serial_Port_Int_

DCD

DA V

PT_

- - - - - - -

INT

PINT

DSINT_

_EN

DSR/ HWFC

CTS RI DTR RTS SCTL

- - - - - -

Mask 0x0B Serial_Port_Data Serial Data Register 0x0C - 0x0D BAUD_Rate_Div BAUD Rate Divider Registers 0x10 - 0x13 Our_IP_Address Our IP Address 0x1C Clock_Div_Low Low Byte for 1 kHz clock divider 0x1D Clock_Div_High High Byte for 1 kHz clock divider 0x20 Index Socket index 0x21 TOS* Type of Service Field

Buff_

0x22 Socket_

Config_Status_Low* 0x23 Socket_Status_Mid*

URG

Empty

RST

0x24 Socekt_Activate - 0x26 Socket_Interrupt - 0x28 Socket_Data_Avail - -

Buff_

Data_

Full

Avail/

RST

Term ConU

- - -

PT_ INT

LINK _INT

- Protocol_Type

TCP State

DAV1 DAV0

SOCK _INT

NOTE: 1)Reserved bits are signified by a dash (-). All reserved bits should be written as “0”.

2)Indexed registers are signified by an asterisk (*).

Seiko Instruments Inc.

7-2

Page 30

TCP/IP Network Stack LSI

S-7600A

Table 7-2 iAPI Register Map (Continued)

Add Register Bit Definitions

Buff_

0x2A Socket_Interrupt_

Mask_Low* 0x2B Socket_Interrupt_

TO_

URG_En RST_

Mask_High* 0x2C Socket_Interrupt_Low* TO

0x2D Socket_Interrupt_High* URG RST 0x2E Socket_Data* Socket 8-bit data 0x30 TCP_Data_Send (WO)* Any write causes data to be sent 0x30 - 0x31 Buffer_Out (RO)* Buffer Out Length 0x32 - 0x33 Buffer_In (RO)* Buffer In Length 0x34 - 0x35 Urgent_Data_Pointer* Urgent Data Offset Pointer 0x36 - 0x37 Their_Port* Target Port Address

Emp_

Buff_

Empty

Hardware Specification Revision 1.3

Buff_F

ull

Term_

ConU_

Buff_

Full

Term

Data_ Avail_

Data_

Avail

ConU

- - - -

0x38 - 0x39 Our_Port* Our Port Address 0x3A Socket_Status_High* - - - - - - - Snd

_bsy 0x3C - 0x3F Their_IP_Address* Target IP Address 0x60 PPP_Control_Status

PPP_Int Con_

Val

Use_

PAP

To_

Dis

PPP_

Int_En

Kick PPP_

PPP_

Up /

SRset

0x61 PPP_Interrupt_Code Interrupt Code 0x62 PPP_Max_Retry - PPP Maximum retry 0x64 PPP_String Pap user name and password

NOTE: 1)Reserved bits are signified by a dash (-). All reserved bits should be written as “0”.

2)Indexed registers are signified by an asterisk (*).

7-3

Seiko Instruments Inc.

Page 31

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

7.3. Register Definitions

7.3.1. Revision Register (0x00)

(Read-Only, Default 0x21)

This direct read-only register reports back the design revision. See the design revision form in T able 7-3 and Table 7-4.

Table 7-3 Revision Register Bit Definitions

Bit 7 6 5 4 3 2 1 0

Def.

Default

Table 7-4 Revision Register Description

Bit Bit Name Access Description 7:4 Major Revision

Number

3:0 Minor Revision

Number

Major Revision Number Minor Revision Number

0x2 0x1

R This nibble indicates the major revision number for

the S-7600A core.

R This nibble indicates the minor revision number for

the S-7600A core.

7.3.2. General Control Register (0x01)

(Read/Write, Default 0x00)

This direct register contains the master sof tware reset. See the register form at in Table 7-5 and Table 7-6.See the wave format in figure 9.-2.

Table 7-5 General Control Register Bit Definitions

Bit 7 6 5 4 3 2 1 0

Def.

Default

- - - - - - - SW_RST

0 0 0 0 0 0 0 0

NOTE: Reserved bits are signified by a dash (-). All reserved bits should be written as “0”.

Table 7-6 General Control Register Description

Bit Bit Name Access Description

0 SW_RST R/W Software Reset.

Seiko Instruments Inc.

This active high reset returns the S-7600A core to power-on reset settings. It is self-clearing and does not need to be written to “0” for proper operations.

0 = Normal operation 1 = Soft reset

7-4

Page 32

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

7.3.3. Generic Socket Location Register (0x02)

(Read-Only)

This register is used to report back the location of general sockets to the software layer. Only bits [1:0] will be set because the S-7600A chip is equipped with two general sockets.

Table 7-7 Generic Socket Location Register Bit Definitions

Bit 7 6 5 4 3 2 1 0

Def.

Value

Table 7-8 Generic Socket Location Register Description

Bit Bit Name Access Description

7 S7 R Not available 6 S6 R Not available 5 S5 R Not available 4 S4 R Not available 3 S3 R Not available 2 S2 R Not available 1 S1 R General socket 1 available 0 S0 R General socket 0 available

S7 S6 S5 S4 S3 S2 S1 S0

0 0 0 0 0 0 1 1

7.3.4. Master Interrupt (0x04)

(Read-Only, Default 0x00)

This direct register indicates the source of the S-7600A interrupt.

Table 7-9 Master Interrupt Register Bit Definitions

Bit 7 6 5 4 3 2 1 0

PT_INT LINK_INT SOCK_INT

Def.

Default

NOTE: Reserved bits are signified by a dash (-). All Reserved bits should be written as “0”.

- - - - -

0 0 0 0 0 0 0 0

7-5

Seiko Instruments Inc.

Page 33

TCP/IP Network Stack LSI

S-7600A

Table 7-10 Master Interrupt Register Descriptions (Continued)

Bit Bit Name Access Description

2 PT_INT R Physical Transport Interrupt

The physical transport triggers this interrupt. An application should check the Serial Port Int register to determine the actual cause of the interrupt.

1 LINK_INT R Link Layer Interrupt

The link layer triggers this interrupt. An application should check the PPP Interrupt Code register to determine the actual cause of the interrupt.

0 SOCK_INT R Socket Interrupt

One of the sockets that need servicing causes this interrupt. An application should check the Socket Interrupt register to determine the actual socket number.

Hardware Specification Revision 1.3

7.3.5. Serial Port Configuration / Status Register (0x08)

(Read/Write, Default 0X0XX110B)

This register configures the serial port as shown in Table 7-11 and Table 7-12.

Table 7-11 Conf Status Register Bit Definitions

Bit 7 6 5 4 3 2 1 0

Def.

Default

S_DAV DCD DSR/

HWFC

0 - 0 - - 1 1 0

CTS RI DTR RTS SCTL

Seiko Instruments Inc.

7-6

Page 34

TCP/IP Network Stack LSI

S-7600A

Table 7-12 Conf Status Register Description

Bit Bit Name Access Description

7 S_DAV R/W Serial Port Data Available

When read, bit indicates that Serial Port data is available.

This bit should be written 0.

6 DCD R/W Carrier Detect

This bit reflects the current state of the DCD bit on the serial port. It is independent of the SCTL bit setting.

This bit should be written 0.

5 DSR / HWFC R/W Data Send Ready / Hardware Flow Control

When read, this bit reflects the current state of the DSR bit on the serial port.

When this bit written: 0 = Hardware Flow control is deactivated

Hardware Specification Revision 1.3

1 = Hardware Flow control activated Refer to Chapter 8 for more information about

Hardware Flow Con trol.

4 CTS R Clear To Send

This read-only bit reflects the current state of the

CTS bit on the serial port. It is independent of the SCTL bit setting.

3 RI R Ring Indicator

This read-only bit reflects the current state of the RI bit on the serial port. It is independent of the SCTL bit setting.

2 DTR R/W Data Terminal Ready

Reading this bit follows the current state of the

DTR bit on the serial port. The MPU can control the DTR by writing to this bit.

1 RTS R/W Request To Send

Reading this bit follows the current state of the

RTS bit on the serial port. The MPU can control the RTS by writing to this bit.

0 SCTL R/W Serial Port Control

7-7

This bit determines who controls the serial port. When this bit is low (default), the MPU controls the port. When the SCTL bit is high, the network stack controls the serial serial port.

0 = MPU controls serial port 1 = Hardware controls serial port

Seiko Instruments Inc.

Page 35

TCP/IP Network Stack LSI

S-7600A

7.3.6. Serial Port Interrupt Register (0x09)

(Read-Only, Default 0X000000B)

This register indicates the state of the serial port interrupt.

Table 7-13 Serial Port Interrupt Register Bit Definitions

Bit 7 6 5 4 3 2 1 0

Hardware Specification Revision 1.3

Def.

Default

NOTE: Reserved bits are signified by a dash (-). All Reserved bits should be written as “0”.

Table 7-14 Serial Port Interrupt Register Description

Bit Bit Name Access Description

7 PT_INT R Port Transport Interrupt

PT_INT - - - - - - -

0 - 0 0 0 0 0 0

This bit indicates when the serial port interrupt is active. This condition depends on the states of the PINT_EN and DSINT_EN bits in the Serial Port Interrupt Mask Register.

When PINT_EN is 1, an interrupt will occur whenever data is available in the serial port input FIFO ("S_DAV" in the Serial Port Configuration/Status Register is 1). When DSINT_EN is 1, an interrupt will be active whenever the CPU can write to the Serial Port Data Register to transmit a byte of data. If both PINT_EN and DSINT_EN are enabled, the interrupt will be active if either condition is met.

7.3.7. Serial Port Interrupt Mask Register (0x0A)

(Read/Write, Default 0x00)

This register enables the serial port interrupts. The default for this register is 0x00 (interrupts disabled).

Table 7-15 Serial Port Interrupt Mask Register Bit Definitions

Bit 7 6 5 4 3 2 1 0

Def.

Default

NOTE: Reserved bits are signified by a dash (-). All Reserved bits should be written as “0”.

Table 7-16 Serial Port Interrupt Mask Register Description

Bit Bit Name Access Description

7 PINT_EN R/W Port Interrupt Enable

6 DSINT_EN R/W Data sent interrupt Enable.

PINT_EN DSINT_EN - - - - - -

0 0 0 0 0 0 0 0

This is the enable for the port interrupt.

This is enable for the data sent interrupt.

Seiko Instruments Inc.

7-8

Page 36

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

7.3.8. Serial Port Data Register (0x0B)

(Read/Write)

This register sends data to and reads data from the serial port UART. The data is valid when the S_DAV bit in the Serial Port Config register is set. Data can be written to this register when the PT_INT bit in the Serial Port Interrupt register is set. See the register description in Table 7.-14.

Note: This register should only be used when the SCTL bit in the Serial Port config register is low.

7.3.9. BAUD Rate Divider Registers (0x0C-0x0D)

(Read/Write, Default 0x0000)

These registers set the BAUD rate for the serial port. Calculate the value by using the following formula:

Program Value = [(clk Frequency) / (BAUD Rate)] - 1 Where clk is the clock for the S-7600A core Example: The clock rate of the S-7600A is 256 KHz and a BAUD rate of 64 Kbps is desired, the

programmed value should be:

(256 KHz / 64 k) - 1 = 4 - 1 = 3

Note: The lowest value that should be programmed into these registers is 0x0003.

7.3.10. Our IP Address Registers (0x10-0x13)

(Read/Write, Default 0x00000000)

These registers store our IP addres s or the IP addr es s of the loc al devic e. T he 0x 10 r egist er s tor es the least significant byte and the 0x13 register stores the most significant byte. If the system controller dose not write an IP address, it will be negotiated for during PPP negotiations (floating IP address). When a PPP connection is established (indicated by bit 0, register 60) these registers can be read to query the IP address obtained.

Table 7-17 Our IP Address Register Bit Definitions (0x10)

Bit 7 6 5 4 3 2 1 0

Def.

Default

Table 7-18 Our IP Address Register Bit Definitions (0x11)

Bit 7 6 5 4 3 2 1 0

Def.

Default

Least significant byte of the local IP address

0x00

3rd byte of the local IP address

0x00

7-9

Seiko Instruments Inc.

Page 37

TCP/IP Network Stack LSI

S-7600A

Table 7-19 Our IP Address Register Bit Definitions (0x12)

Bit 7 6 5 4 3 2 1 0

Def.

Default

Table 7-20 Our IP Address Register Bit Definitions (0x13)

Bit 7 6 5 4 3 2 1 0

Def.

Default

2nd byte of the local IP address

Most significant byte of the local IP address

0x00

Hardware Specification Revision 1.3

7.3.11. Clock Divider Registers (0x1C-0x1D)

(Read/Write, Default 0x03E7)

These registers progr am the 1kHz clock generator. This clock is used internally for various S-7600A timing functions. The following equation determines the value programmed into these registers:

(clk Freq/1 kHz) - 1 = Divide Count

Where clk Freq is S-7600A clock frequency. Therefore, for a 1 MHz clock, the divide count equals 1M / 1kHz - 1= 999 = 0x03e7.

7.3.12. Index Register (0x20)

(Read/Write, Default 0x00)

This register must be programmed prior to accessing indexed socket registers. Valid programmed values are 0x00 and 0x01. If the selected sock et number has not changed since the last ac cess, this register not need to be reprogrammed.

Table 7-21 Index Register Bit Definition

Bit 7 6 5 4 3 2 1 0

Def.

Default

Table 7-22 Index Register Description

Bit Bit Name Access Description

7:0

Socket_Index

R/W

Socket Index [7:0]

0x00

0x00 : General Socket 0 Selected 0x01: General Socket 1 Selected All other values are reserved

7.3.13. Type of Service Register (TOS) (0x21)

(Read/Write, Default 0x00)

This register conf igures the T OS field in the IP header for outgoing datagram s. It is an optional setting that defaults to 0x00.

Seiko Instruments Inc.

7-10

Page 38

TCP/IP Network Stack LSI

S-7600A

7.3.14. Socket Config Status Low Register (0x22)

(Read/Write, Default 0x40)

This register configures the socket.

Table 7-23 Socket Config Status Low Register Bit Definitions

Bit 7 6 5 4 3 2 1 0

Hardware Specification Revision 1.3

Def.

Default

NOTE: Reserved bits are signified by a dash ( - ). All reserved bits should be written as “0”.

TO Buff_

Empty

0 1 0 0 0 0

Buff_Full Data_

Avail / RST

- Protocol_Type

7-11

Seiko Instruments Inc.

Page 39

TCP/IP Network Stack LSI

S-7600A

Table 7-24 Socket Config Status Low Register Description

Bit Bit Name Access Description

7 TO R TCP Timeout

This bit indicates that a TCP timeout condition occurred while attempting to establish a TCP connection or while waiting for a TCP packet after the connection was established.

0 = Normal Operating Condition 1 = Timeout Occurred

This bit indicates whether or not a socket’s outgoing data buffer

6 Buff_Empty R

5 Buff_Full R This bit indicates whether the outgoing buffer is full

is empty. The bit sets on an empty condition. It then clears and remains clear as long as there is any data in the socket’s outgoing data buffer.

0 = Buffer Not Empty 1 = Buffer Empty

(1023 bytes or more). It also triggers an interrupt w hen the outgoing data buffer is full, and the Buff_Full_En bit in the Socket Interrupt Mask Low register (0x2A) is set. The Data Register should not be written to when this bit is a “1”.

Hardware Specification Revision 1.3

0 = Buffer Space Available 1 = No Buffer Space Available

4 Data_Avail / RST R/W Writing this bit resets all socket parameters to default

settings. It is self-clearing and dose not need to be written to low for proper operations. Before resetting, ensure that Snd_Bsy bit of Socket Status High register (0x3A) is 0. When read, this bit indicates that the socket has data available.

2:0 Protocol_Type R/W These bits are used to set the protocol of the socket.

All decodes not shown are reserved. 010 = TCP Client Mode 101 = UDP Mode 110 = TCP Server mode

Seiko Instruments Inc.

7-12

Page 40

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

7.3.15. Socket Status Mid Register (0x23)

(Read-Only, Default 0x00)

This read-only register reports other socket status conditions.

Table 7-25 Socket Status Mid Register Bit Definitions

Bit 7 6 5 4 3 2 1 0

Def.

Default

Table 7-26 Socket Status Mid Register Description

Bit Bit Name Access Description

7 URG R

6 RST R

5 Term R

4 ConU R

3:0 TCP State R

URG RST Term ConU TCP State

0 0 0 0 0x0

This bit indicates the arrival of urgent data. Writing a “1” to the

URG

bit in the Socket Interrupt register (bit 7) clears this bit.

0 = No urgent data present 1 = Urgent data present This bit indicates when the socket receives the RST signal from

the TCP peer. 0 = No RST received

1 = RST received This bit indicates when the socket terminates from the source

and triggers an interrupt if the Term_En bit is set in the Socket Interrupt Mask High register (0x2B). The interrupt mask setting does not effect the reporting of this status bit.

0 = Normal Operating Condition 1 = Socket terminated from source This bit becomes “1” when the S-7600A receives a TCP

segment with the has requested to close the TCP connection.

This bit indicates when the socket establishes a connection to a host machine. The bit clears when the connection terminates (by either end).

0 = No Connection Established 1 = Connection Established These bits indicate the current TCP state.

0 = CLOSED 1 = SYN_SENT 2 = ESTABLISHED 3 = CLOSE_WAIT 4 = LAST_ACK 5 = FIN_WAIT1 6 = FIN_WAIT2 7 = CLOSING 8 = TIME_WAIT 9 = LISTEN a = SYN_RECVD

FIN

flag on. This means that the remote peer

7-13

Seiko Instruments Inc.

Page 41

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

7.3.16. Socket Activate Register (0x24)

(Read/Write, Default 0x00)

This register is used to activate the sockets and also show the current status of each socket. Setting a bit to “1” activates the corresponding socket. This register defaults to 0x00 upon resets.

Table 7-27 Socket Activate Register Bit Definitions

Bit 7 6 5 4 3 2 1 0

Def.

Default

Table 7-28 Socket Activate Register Description

Bit Bit Name Access Description

1 S1 R/W This bit is used to activate general socket 1.

0 S0 R/W This bit is used to activate general socket 0.

- - - - - - S1 S0

0 0 0 0 0 0 0 0

0 = General socket 1 inactive 1 = General socket 1 active

0 = General socket 0 inactive 1 = General socket 0 active

7.3.17. Socket Interrupt Register (0x26)

(Read-Only, Default 0x00)

This register indicates which socket has interrupts pending. When identification of an interrupting socket occurs, the actual source of the interrupt is determined by examining the specific socket’s interrupt register.

Table 7-29 Socket Interrupt Register Bit Definitions

Bit 7 6 5 4 3 2 1 0

Def.

Default

- - - - - - I1 I0

0 0 0 0 0 0 0 0

Seiko Instruments Inc.

7-14

Page 42

TCP/IP Network Stack LSI

S-7600A

Table 7-30 Socket Interrupt Register Description

Bit Bit Name Access Description

1 I1 R This bit is used to indicate that socket 1 has an

interrupt pending. 0 = General socket 1 interrupt inactive 1 = General socket 1 interrupt active

0 I0 R This bit is used to indicate that socket 0 has an

interrupt pending. 0 = General socket 0 interrupt inactive 1 = General socket 0 interrupt active

Hardware Specification Revision 1.3

7.3.18. Socket Data Available Register (0x28)

(Read-Only, Default 0x00)

This read-only register indicates which socket has data pending in the input buffer. A “1” in a bit position indicates that the socket has data available. The bit remains set as long as there is data available.

Table 7-31 Socket Data Avail Register Bit Definitions

Bit 7 6 5 4 3 2 1 0

Def.

Default

Table 7-32 Socket Data Avail Register Description

Bit Bit Name Access Description

1 DAV1 R This bit is used to indicate that socket 1 has data

0 DAV0 R This bit is used to indicate that socket 0 has data

- - - - - - DAV1 DAV0

0 0 0 0 0 0 0 0

available. 0 = General socket 1 has no data available 1 = General socket 1 has data available

available. 0 = General socket 0 has no data available 1 = General socket 0 has data available

7-15

Seiko Instruments Inc.

Page 43

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

7.3.19. Socket Interrupt Mask Low Register (0x2A)

(Read/Write, Default 0x00)

This register reports certain interrupt conditions. Setting a bit enables the corresponding interrupt.

Table 7-33 Socket Interrupt Mask Low Register Bit Definitions

Bit 7 6 5 4 3 2 1 0

Buff_

Def.

TO_En

Emp_En

Buff_Full_En Data_Avail_En - - - -

Default

NOTE: Reserved bits are signified by a dash (-). All reserved bits should be written as “0”.

0 0 0 0 0 0 0 0

Table 7-34 Socket Interrupt Mask Low Register Description

Bit Bit Name Access Description

7 TO_En R/W Writing a “1” enables the Timeout interrupt. 6 Buff_Empty_En R/W Writing a “1” enables the Buffer Empty interrupt. 5 Buff_Full_En R/W Writing a “1” enables the Buffer Full interrupt. 4 Data_Avail_En R/W Writing a “1” enables the Data Available interrupt.

7.3.20. Socket Interrupt Mask High Register (0x2B)

(Read/Write, Default 0x00)

This register enables certain types of interrupt conditions. Setting bits enables their corresponding interrupts.

Table 7-35 Socket Interrupt Mask High Register Bit Definitions

Bit 7 6 5 4 3 2 1 0

Def.

URG_En RST_En Term_En ConU_En - - - -

Default

NOTE: Reserved bits are signified by a dash (-). All reserved bits should be written as “0”.

Table 7-36 Socket Interrupt Mask High Register Description

0 0 0 0 0 0 0 0

Bit Bit Name Access Description

7 URG_En R/W Writing a “1” to enable the Urgent Data interrupt. 6 RST_En R/W Writing a “1” to enable the Connection Reset interrupt. 5 Term_En R/W Writing a “1” to enable the Socket Termination interrupt. 4 ConU_En R/W Writing a “1” to enable the Connection Up interrupt.

Seiko Instruments Inc.

7-16

Page 44

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

7.3.21. Socket Interrupt Low Register (0x2C)

(Read/Write, Default 0x00)

This register reports certain interrupt conditions. When an interrupt condition occurs and its enable bit is set, the hardware sets the corresponding bit. Writing a "1" to the bit clears it. Disabling the corresponding enable bit prevents the interrupt from showing.

Table 7-37 Socket Interrupt Low Register Bit Definitions

Bit 7 6 5 4 3 2 1 0

Def.

TO Buff_Emplty Buff_Full Data_Avail - - - -

Default

NOTE: Reserved bits are signified by a dash (-). All reserved bits should be written as “0”.

Table 7-38 Socket Interrupt Low Register Description

Bit Bit Name Access Description

7 TO R/W This interrupt is generated when a timeout condition

6 Buff_Empty R/W This interrupt is generated when outgoing buffer is

5 Buff_Full R/W This interrupt is generated when the outgoing buffer is

4 Data_Avail R/W This interrupt is generated when data is available from

0 0 0 0 0 0 0 0

occurred while trying to establish a connection. Writing a “1” to this bit clears the interrupt.

empty. Writing a “1” to this bit clears the interrupt.

full (1023 bytes). Writing a “1” to this bit clears the interrupt. Do not use this bit in UDP.

the incoming buffer. Writing a “1” to this bit clears the interrupt.

7.3.22. Socket Interrupt High Register (0x2D)

(Read/Write, Default 0x00)

Table 7-39 Socket Interrupt High Register Bit Definitions

Bit 7 6 5 4 3 2 1 0

URG RST Term ConU - - - -

0 0 0 0 0 0 0 0

Seiko Instruments Inc.

7-17

Def.

Default

NOTE: Reserved bits are signified by a dash (-). All reserved bits should be written as “0”.

Page 45

TCP/IP Network Stack LSI

S-7600A

Table 7-40 Socket Interrupt High Register Description

Bit Bit Name Access Description

7 URG R/W This interrupt is generated when urgent data arrives.

The system interface should read the Urgent Data Pointer register to see the location of the data. Writing a “1” to this bit clears the interrupt.

6 RST R/W This interrupt is generated when a TCP peer sends

the socket RST flag indicating that the current TCP session is not valid. Writing a “1” to this bit clears this interrupt. When this condition occurs, the hardware no longer operates and re-initializing the socket is recommended.

5 Term R/W This interrupt is generated when the socket

connection is terminated and a TCP FIN flag is received. Writing a “1” to this bit clears the interrupt.

4 ConU R/W This interrupt is generated when a connection is

established. Writing a “1” to this bit clears the interrupt.

Hardware Specification Revision 1.3

7.3.23. Socket Data Register (0x2E)

(Memory Mapped Read/Write, Default 0x00)

This register is used by a system controller to read incoming data packets and write outgoing data. Data transmissions start for TCP connections only after a write occurs at 0x30.

7.3.24. TCP Data Send and Buffer Out Length Registers (0x30-0x31)

(Read/Write, Default 0x03FF)

When read, thes e registers repor t the amount of space available in the outgoing buffer. Register 0x30 stores the least significant byte; 0x31 stores the most signif icant byte. Writing any data to 0x30 causes data transmissions to start on TCP connections.

7.3.25. Buffer In Length Registers (0x32-0x33)

(Read-Only, Default 0x0000)

These read-only registers report the amount of data available in the received data buffer . 0x32 stores the least significant byte; 0x33 stores the most significant byte.

7.3.26. Urgent Data Pointer Registers (0x34-0x35)

(Read-Only, Default 0x0000)

These read-only registers report the offset to the start of urgent data (as marked through the TCP header) relative to the incoming data buff er. Register 0x34 stores the least s ignif icant byte; 0x35 st ores the most significant byte.

Seiko Instruments Inc.

7-18

Page 46

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

7.3.27. Their Port Registers (0x36-0x37)

(Read/Write, Default 0x0000)

These registers specify the destination port for an outgoing data packets. For TCP client or UDP mode, this value must be set prior to activating the socket. For TCP server mode, these registers are automatically setup on a connection with the peer’s port number. Register 0x36 stores the least significant byte and 0x37 stores the most significant byte.

Table 7-41 Their Port Register Bit Definitions (0x36)

Bit 7 6 5 4 3 2 1 0

Def.

Default

Table 7-42 Their Port Register Bit Definitions (0x37)

Bit 7 6 5 4 3 2 1 0

Def.

Default

Least significant byte of the target port number

0x00

Most significant byte of the target port number

0x00

7.3.28. Our Port Registers (0x38-0x39)

(Read/Write, Default 0x0000)

These registers are used it indicate the source port for an outgoing data packet. W hen setting a TCP client or sending data using UDP, thes e registers should be set to the proper value. Normally in client applications, the software increm ents the value of this register. The TCP and UDP server application should set these registers to be the value used by the server applications. Register 0x38 stores the least significant byte; 0x39 stores the most significant byte.

Table 7-43 Our Port Register Bit Definitions (0x38)

Bit 7 6 5 4 3 2 1 0

Def.

Default

Table 7-44 Our Port Register Bit Definitions (0x39)

Bit 7 6 5 4 3 2 1 0

Def.

Default

Least significant byte of the local port number

0x00

Most significant byte of the local port number

0x00

7.3.29. Socket Status High Register (0x3A)

(Read-Only, Default 0x00)

This register reports the busy status of the socket.

Table 7-45 Socket Status High Register Bit Definitions

Bit 7 6 5 4 3 2 1 0

- - - - - - - Snd_Bsy

0 0 0 0 0 0 0 0

Seiko Instruments Inc.

7-19

Def.

Default

NOTE: Reserved bits are signified by a dash (-). All reserved bits should be written as “0”.

Page 47

TCP/IP Network Stack LSI

S-7600A

Table 7-46 Socket Status High Register Description

Bit Bit Name Access Description

0 Snd_Bsy R This bit indicates that the current socket is busy

sending TCP segments. Before the socket is reset, this bit should be 0.

0 = Socket not busy 1 = Socket busy

Hardware Specification Revision 1.3

7.3.30. Their IP Address Registers (0x3C-0x3F)

(Read/Write, Default 0x00000000)

These registers indicate the destination IP address for the socket. For TCP client or UDP mode, this value must be set prior to activating the s ock et. For TCP s erver m ode, thes e register are autom atically setup on a connection with the peer’s IP address The registers can be written in any order.

Table 7-47 Their IP Address Register Bit Definitions (0x3C)

Bit 7 6 5 4 3 2 1 0

Def.

Default

Table 7-48 Their IP Address Register Bit Definitions (0x3D)

Least significant byte of Destination IP address

0x00

Bit 7 6 5 4 3 2 1 0

Def.

Default

Table 7-49 Their IP Address Register Bit Definitions (0x3E)

Bit 7 6 5 4 3 2 1 0

Def.

Default

Table 7-50 Their IP Address Register Bit Definitions (0x3F)

Bit 7 6 5 4 3 2 1 0

Def.

Default

3rd byte of Destination IP address

0x00

2nd byte of Destination IP address

0x00

Most significant byte of Destination IP address

0x00

Seiko Instruments Inc.

7-20

Page 48

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

7.3.31. PPP Control and Status Register (0x60)

(Read/Write, Default 0x00)

This register control the PPP layer and reports its status.

Table 7-51 PPP Control and Status Register Bit Definitions (0x60)

Bit 7 6 5 4 3 2 1 0

Def.

PPP_Int Con_Val Use_

PAP

TO_Dis PPP_Int_En Kick PPP_En PPP_Up

/SRst

Default

Table 7-52 PPP Control Status Register Description

0 0 0 0 0 0 0 0

Bit Bit Name Access Description

7 PPP_Int R/W

6 Con_Val R/W

5 Use_PAP R/W

4 TO_Dis R/W

3 PPP_Int_En R/W

2 Kick W

1 PPP_En R/W

PPP Interrupt This bit indicates that the PPP triggered an interrupt condition.

Read the PPP interrupt code register to determine the cause. Writing a “1” to this bit position clears the interrupt.

Connection Valid This bit indicates to the network stack that the underlying

connection is up and valid. 0 = Connection down

1 = Connection up This bit enables PAP authentication within the PPP protocol. If

enabled, a PAP request is issued after PAP authentication is negotiated. The PAP string enters through register 0x64.

0 = PAP disabled (default) 1 = PAP enabled

Timeouts Disabled This bit disables the PPP block from timeouts for diagnostic

purposes. It should remain enable for normal operations. 0 = Timeouts enabled (default)

1 = Timeouts disabled PPP Interrupt Enable This bit enables the PPP interrupt. 0 = PPP Interrupt disabled (default)

1 = PPP Interrupt enabled PPP Kick Start When written to a 1, this bit will start the PPP if it falls into a

timeout condition. It clears once the kick operation performs. This bit is self-clearing.

PPP Enable This bit enables the PPP layer. The bit must be set before any

transmissions occur. 0 = PPP disabled (default)

1 = PPP enabled

7-21

Seiko Instruments Inc.

Page 49

TCP/IP Network Stack LSI

S-7600A

Bit Bit Name Access Description

0 PPP_UP/SRst R/W

When read, this bit indicates when the PPP layer establishes a connection.

0 = PPP Connection down 1 = PPP Connection established When written, this bit will reset the PPP engine. It is self-clearing

and goes not need to be written low for normal operations. 0 = PPP Normal operation 1 = PPP Reset

Hardware Specification Revision 1.3

7.3.32. PPP Interrupt Code (0x61)

(Read-Only, Default 0x00)

This register indicates the interrupt condition that causes the PPP interrupt to trigger.

Table 7-53 PPP Interrupt Code Register Bit Definitions

Bit 7 6 5 4 3 2 1 0

Def.

Default

PPP Interrupt Code

Table 7-54 PPP Interrupt Error Codes

Error Code Definition

0x00 Reserved 0x01 PPP Failed initial LCP negotiations 0x02 PPP Failed NCP negotiations 0x05 PAP Failed negotiations

7.3.33. PPP Max Retry, (0x62)

(Read/Write, Default 0x0A)

This register configures the maxim um retry number. This number is used to deter mine the maxim um number of configuration requests that are sent during the PPP negotiation stage.

Table 7-55 PPP Max Retry Register

Bit 7 6 5 4 3 2 1 0

Def.

- PPP Maximum Retry

Default

NOTE: Reserved bits are signified by a dash (-).

0x0 0xA

Seiko Instruments Inc.

7-22

Page 50

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

7.3.34. PAP String (0x64)

(Write-Only)

This write-only register enters the string for the PAP configuration request packet. Enter the string according to the format shown Table 7-56.

Table 7-56 PAP String Format

Byte String

[0] Length of username [1] First byte of username [2] Second byte of username

[n] Last byte of username (where n is the length of the username string) [n+1] Length of password [n+2] First byte of password

[n+m+1] Last byte of password (where m is the length of the password string)

As an example, if the username string is “joe” and the password is “public”, enter the bytes as shown in Table 7-57.

Table 7-57 PAP String Example

byte:0 0x03 Length of username string byte:1 0x6a Character “j” byte:2 0x6f Character “o” byte:3 0x65 Character “e” byte:4 0x06 Length of password string byte:5 0x70 Character “p” byte:6 0x75 Character “u” byte:7 0x62 Character “b” byte:8 0x6C Character “l” byte:9 0x69 Character “I” byte:a 0x63 Character “c”

If PAP is used, the Use_PAP bit must be set in the PPP Control and Status register (0x60) prior to entering the PAP string.

7-23

Seiko Instruments Inc.

Page 51

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

8. Data Communications

8.1. Overview

The S-7600A chip contains a on-board serial port for physical transports. The data format of the serial port is fixed at 1 start bit (logic "0"), 8 data bits, 1 stop bit (logic "1") and no parity bits. The data bits are sent out, least significant bit first. This data format is shown in Figure 8-1. Also included with the serial port is a 16- byte Receive FIFO and 1-byte Send Buffer.

Figure 8-1 Serial Data Format

rxd / txd start

D0 D1 D2 D3 D4 D5 D6 D7

8.2. Serial Port Register Map

The following registers are used to communicate with the serial port.

stop

Table 8-1 Serial Port Register Map

Add Register Bit Definitions

0x08 Serial_Port_Config S_DAV DCD DSR/

0x09 Serial_Port_Int PT_INT - - - - - - 0x0A Serial_Port_Int_

Mask 0x0B Serial_Port_Data Serial Port Data Register 0x0C -

0x0D

BAUD_Rate_Div BAUD Rate Divider Registers

PINT_EN DSINT_EN - - - - - -

HWFC

CTS RI DTR RTS SCTL

Seiko Instruments Inc.

8-1

Page 52

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

8.2.1. Hardware Flow Control (RTS/CTS Handshaking)

The Hardware Flow Control is turned off by default. In this mode, data is transmitted independent of the state of the CTSX signal. While the MPU is in control of the serial port, it can monitor the state of all the serial port control signals and control when data gets sent or received, either through polling the status bits or interrupts. It can also control the RTSX signal by asserting the RTS bit in the Serial Port Config register. When the S-7600A controls the serial port, data will be sent out as soon as it is available from the PPP layer. When receiving data, the software in the MPU control mode should read the data out of the 16-byte FIFO fast enough to prevent buffer overflow.

Hardware Flow Control can be turned on by writing a "1" to bit 5 (DSR/HWFC) of the Serial Port Config Register (0x08). With the hardware flow control turned on, full RTS/CTS handshaking is supported. When the serial port detects that CTS is de-asserted, it will stop sending data until CTS is reasserted. Any byte output at the time CTS is de-asserted will complete, but no further bytes will be sent until CTS is asserted.

In the other direction, the S-7600A will de-assert RTS if the serial port’s 16-byte FIFO is half full. This indicates to the machine on the other end of the serial line to stop transmitting data. The RTS bit will reassert when the MPU or the S-7600A has read data out of the Receive FIFO and room becomes empty. If the machine communicating with the S-7600A over the serial port does not support RTS/CTS handshaking, the Receive FIFO may overflow and data loss will occur.

8.2.2. Serial Port Control

The control of the serial port is turned over to the MPU by default and after any reset condition. In this mode, any data written to the Serial Port Data register will be sent out and all data received will be made available to the MPU via this same register. Prior to using the data register, the MPU should set the BAUD Rate Div register to the proper setting. An interrupt can be triggered when data is available from the serial port by asserting the PINT_EN bit. When this bit is asserted, an interrupt will trigger any time that there is data available to be read from the port. If there is more than one byte in the Receive FIFO, the interrupt will remain active until all bytes are read. An interrupt can also trigger indicating that the outgoing data byte has been sent, by asserting the DSINT_EN bit. This interrupt will trigger whenever there is no more data to be sent.

The MPU turns over control to the S-7600A by asser ting the SCTL bit in the Serial Port Config register. When the S-7600A controls the port, the MPU should not access the Serial Port Data register. The S7600A chip will automatically send PPP packets to the serial port and read incoming bytes from the serial port. The serial port interrupts are not valid when the S-7600A controls the port.

8-2

Seiko Instruments Inc.

Page 53

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

8.3. TCP/UDP Data Communications

8.3.1. TCP Data Communications

TCP data communications can be performed if the SCTL-bit of the Serial Port Config register (0x08) is set to “1.” For data transmission, data is written to the Socket Data register (0x2E). The S-7600A stores data in its outgoing buffer via the Socket Data Register. The address of the outgoing buffer is specified by the Buffer Out Length register (0x30-0x31). The value of the Buffer Out Length register is 0x03ff when the outgoing buffer is empty. The value of the Buffer Out Length register decrements each time a byte of data is written to the Socket Data register (0x2E). After the data is written, if any data is written to the TCP Data Send register (0x30), the data in the outgoing buffer is processed by TCP protocols and transmitted. The value of the Buffer Out Length register increases by the value of the number of bytes of transmitted data and returns to 0x03ff when all data has been sent. In TCP data transmission, the outgoing buffer has a capacity of 1023 bytes. Datagrams longer than 1023 bytes are split by the MPU and transmitted in chunks. When the outgoing buffer becomes full (i.e., comes to contain 1023 bytes of data), the value of the Buffer Out Length register becomes 0x0000. This can be confirmed by checking the Buff_Full bit in the Socket Config Status Low register (0x22). It can also be confirmed by examining the Buff_Full bit in the Socket Interrupt Low register (0x2C) following an interrupt. No more than 1023 bytes of data are permitted in the Socket Data register. If data is written to the TCP Data Send register under these conditions, the data in the outgoing buffer is transmitted. The MPU repeats the procedure of sending residual data after verifying that the Buffer Out Length register has been reset to 0x03ff. Transmission of all data in the outgoing buffer can be confirmed by checking the Buff_Empty bit in the Socket Config Status Low register (0x22), as well as the Buff_Empty bit in the Socket Interrupt Low register (0x2C) following an interrupt.

When the S-7600A receives TCP data, it applies TCP protocol processing and stores data in the incoming buffer. The address of the incoming buffer is specified by the Buffer In Length register (0x320x33). The value of the Buffer In Length register is 0x0000 when the incoming buffer is empty. Otherwise, it increments by a value equal to the number of bytes of the stored data. Data reception is detected by checking the Data_Avail bit in the Socket Config Status Low register (0x22), Socket Data Available register (0x28), and the Data_Avail bit in the Socket Interrupt Low register (0x2C) following an interrupt. Read the Socket Data register (0x2E) while monitoring the Data_Avail bit in the Socket Config Status Low register. This reads in the received data from the incoming buffer. Each time a byte of data is read out from the Socket Data register, the value of the Buffer In Length register decrements. When all data is read out, its value returns to 0x0000. The incoming buffer can hold up to 2047 bytes of data for TCP data reception. The S-7600A and its peer apply TCP protocols to prevent overflowing incoming buffers during data reception.

Seiko Instruments Inc.

8-3

Page 54

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

8.3.2. UDP Data Communications

UDP data communications are performed if the SCTL-bit of the Serial Port Config register (0x08) is set to “1.” For data transmission, data is written to the Socket Data register (0x2E). The S-7600A stores data in its outgoing buffer via the Socket Data register. The address of the outgoing buffer is specified by the Buffer Out Length register (0x30-0x31). The value of the Buffer Out Length register is 0x03ff when the outgoing buffer is empty. The value of the Buffer Out Length register decrements each time a byte of data is written to the Socket Data register (0x2E). After the data is written, if any data is written to the TCP Data Send register (0x30), the data stored in the outgoing buffer is processed by UDP protocols and transmitted. Since the value of the Buffer Out Length register increases by the value of the number of bytes of transmitted data, it is reset to 0x03ff when all data has been sent. For UDP data transmission, the outgoing buffer can hold up to 1015 by tes of data. Datagrams longer than 1015 bytes are split by the MPU and transmitted in chunks. When the outgoing buffer accumulates 1015 bytes of data, the value of the Buffer Out Length register becomes 0x0008. No more than 1015 bytes of data are permitted in the Socket Data register. Since this condition is not indicated by the Buff_Full bit in the Socket Config Status Low register (0x22) or by the Buff_Full bit in the Socket Interrupt Low register (0x2C), the Buffer Out Length register must be monitored, or supervised in the application layer. If data is written to the TCP Data Send register under these conditions, the data in the outgoing buffer is transmitted. The MPU repeats the procedure of sending residual data after checking that the Buffer Out Length register has been restored to 0x03ff. The transmission of all data in the outgoing buffer can be confirmed by checking the Buff_Empty bit in the Socket Config Status Low register (0x22) and the Buff_Empty bit in the Socket Interrupt Low register (0x2C) following an interrupt. When the S-7600A receives UDP data, it applies UDP protocol processing and stores the processed data in the incoming buffer after adding 12 by tes of header information. Data reception can be determined by checking whether the value of the Buffer In Length register equals 0x0000 or a different value. The Data_Avail bit in the Socket Config Status Low register (0x22), the Socket Data Available register (0x28), and the Data_Avail bit following an interrupt in the Socket Interrupt Low register (0x2C) can all indicate data reception. Read the Socket Data register (0x2E) while monitoring the Data_Avail bit in the Socket Config Status Low register. This fetches the 12 byte header from the incoming buffer, followed by the data. Table 8-2 shows the header structure.

8-4

Seiko Instruments Inc.

Page 55

TCP/IP Network Stack LSI

S-7600A

Table 8-12 Header Structure

Byte position from head Implication of each byte Remarks 0 The most significant byte of their IP

address

1 The second significant byte of their IP

address

2 The third significant byte of their IP

address

3 The least significant byte of their IP

address

4 The most significant byte of their port

number

5 The least significant byte of their port

number

6 The most significant byte of our port

number

Hardware Specification Revision 1.3

7 The least significant byte of our port

number

8 The most significant byte of UDP

datagram size

9 The least significant byte of UDP

datagram size

10 The most significant byte of UDP

checksum

11 The least significant byte of UDP

checksum

Each time a byte of data is read out from the Socket Data register, the value of the Buffer In Length register decrements. When all data is read out, the register value returns to 0x0000. In UDP data reception, the incoming buffer has a maximum capacity of 2047 bytes, including the 12-byte header. The application layer is responsible for using the header information and the buffer control to prevent any overflow in the two incoming buffers.

8 bytes of UDP header are not included here

Seiko Instruments Inc.

8-5

Page 56

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

9. Reset Functions

9.1. Overview

The S-7600A has two reset functions which are hardware reset and software reset.

9.1.1. Hardware Reset Function

The S-7600A operates to be synchronous to the CLK signal( cloc k input). When the RESETX pin set to low level in two clock period m inimum, the S-7600A accept hardware res et input and starts initializing internal circuit at positive edge timing of forth clock. After the RESETX pin return to high level, the S7600A maintains initialized state and turns normal state at positive edge timing of forth clock.

See the Figure 9-1.

Min. 2 clock

RESETX

4th

2nd1st

initialized

3rd

4th

normal

CLK

2nd

1st

Figure 9-1 Hardware Reset Timing

3rd

9.1.2. Software Reset Function

The S-7600A is able to initialize the internal circuit by the General Control Register(0x01). Show the reset timing in case of x80 Family MPU mode. See the Figure 9-2.

WRITEX

SD7 to 0

Address

Data h01

9-1

BUSYX

CLK

normal state

x80 Family MPU mode

Figure 9-2 Software Reset Timing

Seiko Instruments Inc.

initialized state

normal state

Page 57

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

10. Application Examples

10.1.1. In Case of x80 Family MPU with LCD Controller

S-7600A x80 Family

MPU

A1 to A7

IORQ

D0 to D7

RD WR

RES

Decoder

RS CS

SD0 to SD7 READX WRITEX

PSX

C86

Driver/

Receiver

-Personal Computer

-MODEM

-PDC

-PIAFS

LCD Controller

(S-4592,etc.)

RS CS

D0 to D7 RD WR

RESET C86

Figure 10-1 Example for x80 Family MPU

RES

Seiko Instruments Inc.

10-1

Page 58

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

10.1.2. In Case of 68k Family MPU with LCD Controller

S-7600A 68k Family

MPU

A1 to A7

VMA

D0 to D7

R/W

RES

Decoder

RS CS

SD0 to SD7 E (READX) R/WX (W RITEX)

PSX C86

Driver/

Receiver

-Personal Computer

-MODEM

-PDC

-PIAFS

LCD Controller

(S-4592,etc.)

RS CS

D0 to D7 RD WR

RESET

Figure 10-2 Example for 68k Family MPU

RES

C86

10-2

Seiko Instruments Inc.

Page 59

TCP/IP Network Stack LSI

S-7600A

10.1.3. In Case of Serial Interface with LCD Controller

Hardware Specification Revision 1.3

MPU

PORT1 PORT2

PORT3

SOUT

SIN

SCLK

RES

S-7600A

RS CS

BUSY SI (SD7)

SO (SD5) SCL (SD6)

READX

C86

PSX

LCD Controller

(S-4592,etc.)

RS CS

C86

Driver/

Receiver

-Personal Computer

-MODEM

-PDC

-PIAFS

SO SCL

RESET

Figure 10-3 Example for Serial Interface

RES

Seiko Instruments Inc.

10-3

Page 60

TCP/IP Network Stack LSI

S-7600A

Seiko Instruments Inc.

1-8, Nakase, Mihama-ku, Chiba-shi, Chiba 261, Japan Components Sales Div. Telephone : +81-43-211-1196 Facsimile : +81-43-211-8032 E-mail :

http://www.sii.co.jp/compo/s7600a/S7600A_TOP.html

Seiko Instruments USA Inc.

Electronic Components Div. 2990 W. Lomita Blvd , Torrance, CA 90505, USA Telephone : +1-909-934-9334 Facsimile : +1-909-975-5699 E-mail : seiko-ecd@salessupport.com hrrp://www.seiko-usa-ecd.com

The S7600A TCP/IP Network Stack LSI is based upon iReady's Internet Tuner® technology. The URL for iReady’s Web site is,

http://www.iready.com

• The information herein is subject to change without notice.

• Seiko Instruments Inc. is not responsible for any problems caused by circuits or other diagrams

described herein whose industrial properties, patents or other rights belong to third parties.

• When the products described herein include Regulated Products subject to The Wassenaar Arrangement etc., they may not be exported without authorization form the appropriate governmental authority.

• The products described herein cannot be used as part of any device or equipment which influences the human body, such as physical exercise equipment, medical equipment, security system, gas equipment, vehicle or airplane, without prior written permission of Seiko Instruments Inc.

component@sii.co.jp

Hardware Specification Revision 1.3

10-4

Seiko Instruments Inc.

Datasheet S-7600A Datasheet (Epson)

Specifications and Main Features

Frequently Asked Questions

User Manual