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S6C0678
written permission of LCD Driver IC Team.
6 BIT 420 CHANNEL TFT-LCD SOURCE DRIVER
Contents in this document are subject to change without notice. No part of this document may be reproduced
or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express
November. 1999.
Ver. 0.2
Prepared by: Si-Wang, Sung
mail to : [email protected]
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S6C0678 6 BIT 420 CHANNEL TFT-LCD SOURCE DRIVER
S6C0678 Specification Revision History
Version Content Date
0.0 Original Aug.1999
0.1 The content of page 17 has been modified Aug.1999
0.2 The content of page 18 has been modified Nov.1999
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6 BIT 420 CHANNEL TFT-LCD SOURCE DRIVER S6C0678
CONTENTS
INTRODUCTION..................................................................................................................................................4
FEATURES .........................................................................................................................................................4
BLOCK DIAGRAM..............................................................................................................................................5
PIN ASSIGNMENTS............................................................................................................................................6
PIN DESCRIPTIONS ...........................................................................................................................................7
OPERATION DESCRIPTION...............................................................................................................................8
DISPLAY DATA TRANSFER............................................................................................................................8
EXTENSION OF OUTPUT................................................................................................................................8
RELATIONSHIP BETWEEN INPUT DATA VALUE AND OUTPUT VOLTAGE ..................................................8
ABSOLUTE MAXIMUM RATINGS.....................................................................................................................15
RECOMMENDED OPERATION CONDITIONS .................................................................................................. 15
DC CHARACTERISTICS................................................................................................................................... 16
AC CHARACTERISTICS................................................................................................................................... 17
WAVEFORMS................................................................................................................................................... 18
RELATIONSHIPS BETWEEN CLK1, START PULSE (DIO1, DIO2) AND BLANKING PERIOD........................19
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S6C0678 6 BIT 420 CHANNEL TFT-LCD SOURCE DRIVER
INTRODUCTION
The S6C0678 is a 420 channel output, TFT-LCD source driver for 64 gray scale displays. Data input is based on
digital input consisting of 6 bits by 6 dots, which can realize a full-color display of 260,000 colors by output of 64
values gamma-corrected.
This device has an internal D/A (Digital-to-Analog) converter for each output and 10 (5-by-2) external power
supplies. Because the output dynamic range is as large as 4.8 - 7.8 Vp-p, it is unnecessary to operate level
inversion of the LCD's common electrode. Besides, to be able to deal with dot-line inversion when mounted on a
single-side, output gray scale voltages with different polarity can be output to the odd number output pins and the
even output pins.
S6C0678 can be adopted to larger panel, and SHL (shift direction selection) pin makes use of the LCD panel
connection conveniently. Maximum operation clock frequency is 45 MHz at a 2.7 V logic operation. it can be
applied to the TFT-LCD panel of SXGA+(1400 * RGB) standards.
FEATURES
• TFT active matrix LCD source driver LSI
• 64 Gary-scale is possible through 10 (5 by 2) external power supply and D/A converter
• Both dot inversion display and N-line inversion display are possible
• CMOS level input
• Compatible with gamma-correction
• Input data inversion function (DATPOL1, 2)
• Logic supply voltage: 2.7 - 3.6 V
• LCD driver supply voltage: 5.0 - 8.0 V
• Output dynamic range: 4.8 - 7.8 Vp-p
• Maximum operating frequency: fMAX = 45 MHz (internal data transmission rate at 2.7 V operation)
• Output: 420 outputs
• TCP available
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6 BIT 420 CHANNEL TFT-LCD SOURCE DRIVER S6C0678
Y001
BLOCK DIAGRAM
POL
VGMA1 -
VGMA10
CLK1
RPO2 RPO1
Line Repair
Amp
RPI2
RPI1
10
Y420
6 6 6 6 6 6
6 6 6 6 6 6
Y419
Y418
Output Buffer
D/A Converter
Data Latch
Y003
Y002
DATPOL1
DATPOL2
D00 - D05
D10 - D15
D20 - D25
D30 - D35
D40 - D45
D50 - D55
CLK2
Data Register
6
6
6
6
6
6
18
18
Data Control
70bit Shift Register
DIO2 DIO1
SHL
TEST
Figure 1. S6C0678 Block Diagram
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S6C0678 6 BIT 420 CHANNEL TFT-LCD SOURCE DRIVER
PIN ASSIGNMENTS
Y001
Y002
Y003
Y004
Y417
Y418
Y419
Y420
(Top View)
S6C0678
RPI1
RPO1
DIO1
D00
D01
D02
D03
D04
D05
D10
D11
D12
D13
D14
D15
D20
D21
D22
D23
D24
D25
TEST
DATPOL2
DATPOL1
POL
CLK1
CLK2
VSS1
VGMA1
VGMA2
VGMA3
VGMA4
VGMA5
VSS2
VDD2
VGMA6
VGMA7
VGMA8
VGMA9
VGMA10
SHL
VDD1
D30
D31
D32
D33
D34
D35
D40
D41
D42
D43
D44
D45
D50
D51
D52
D53
D54
D55
DIO2
RPO2
RPI2
Figure 2. S6C0678 Pin Assignments
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6 BIT 420 CHANNEL TFT-LCD SOURCE DRIVER S6C0678
pulse (DIO1, DIO2) and blanking period" of the switching characteristic
PIN DESCRIPTIONS
Symbol Pin Name Description
VDD1 Logic power supply 2.7 - 3.6 V
VDD2 Driver power supply 5.0 - 8.0 V
VSS1 Logic ground Ground (0 V)
VSS2 Driver ground Ground (0 V)
Y1 to Y420
D0<0:5>
- D5<0:5>
SHL
DIO1 Start pulse input / output
DIO2 Start pulse input / output
DATPOL1
DATPOL2
POL Polarity input
CLK2 Shift clock input
CLK1 Latch input
VGMA1
–
VGMA10
RPI1, RPO1
RPI2, RPO2
TEST Test input
Driver outputs The D/A converted 64 gray-scale analog voltage is output.
Display data input
Shift direction control
input
Data inversion input
Gamma corrected power
supplies
Line-repair AMP input /
output
The display data is input with a width of 36 bits,
gray-scale data (6 bits) by 6 dots (R,G,B) DX0: LSB, DX5: MSB
This pin controls the direction of shift register in cascade connection.
The shift direction of the shift registers is as follows.
SHL = H: DIO1 input, Y1 → Y420, DIO2 output
SHL = L: DIO2 input, Y420 → Y1, DIO1 output
SHL = H: Used as the start pulse input pin.
SHL = L: Used as the start pulse output pin.
SHL = H: Used as the start pulse output pin.
SHL = L: Used as the start pulse input pin.
DATPOL1, 2 = L: Display data is not inverted
DATPOL1 = H: Display data of D0<0:5> - D2<0:5> is inverted
DATPOL2 = H: Display data of D3<0:5> - D5<0:5> is inverted
POL = H: The reference voltage for odd number outputs are VGMA1 –
VGMA5 and those for even number outputs are VGMA6 – VGMA10.
POL = L: The reference voltage for odd number outputs are VGMA6 –
VGMA10 and those for even number outputs are VGMA1 – VGMA5.
Refer to the shift register's shift clock input. The display data is loaded
to the data register at the rising edge of CLK2.
Latches the contents of the data register at rising edge and transfers
them to the D/A converter. Also, after CLK1 input, clears the internal
shift register contents. After 1 pulse input on start, operates normally.
CLK1 input timing refers to the "Relationships between CLK1 start
waveform. Outputs the G/S data at falling edge.
Input the gamma corrected power supplies from external source.
VDD2 > VGMA1 > VGMA2 > ……… > VGMA9 > VGMA10 > VSS2
Keep gray-scale power supply unchanged during the gray-scale
voltage output.
The Structure of the line-repair amp is the same as that of the analog
output.
RPI1 (RPI2) → impedance changed → RPO1 (RPO2)
TEST = L: Normal operation mode
TEST = H: Test mode (OP AMP CUT-OFF, Rpd = 15kΩ)
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S6C0678 6 BIT 420 CHANNEL TFT-LCD SOURCE DRIVER
OPERATION DESCRIPTION
DISPLAY DATA TRANSFER
When DIO1 (or DIO2) pulse is loaded into internal latch on the rising edge of CLK2, DIO1 (or DIO2) pulse
enables the operation of data transfer, so display data is valid on the next rising edge of CLK2. Once all the
data of 420 channels are loaded into internal latch, it goes into stand-by state automatically, and any new data
is not accepted even though CLK2 is provided until next DIO1 (or DIO2) input. When next DIO1 (or DIO2) is
provided, new display data is valid on the 2nd rising edge of CLK2 after the rising edge of DIO1 (or DIO2).
EXTENSION OF OUTPUT
Output pin can be adjusted to an extended screen by cascade connection.
(1) SHL = "L"
Connect DIO1 pin of previous stage to the DIO2 pin of next stage and all the input pins
except DIO1 and DIO2 are connected together in each device.
(2) SHL = "H"
Connect DIO2 pin of previous stage to the DIO1 pin of next stage and all the input pins
except DIO2 and DIO1 are connected together in each device.
RELATIONSHIP BETWEEN INPUT DATA VALUE AND OUTPUT VOLTAGE
The LCD drive output voltages are determined by the input data and 10 (5 by 2) gamma corrected power
supplies (VGMA1 - VGMA10). Besides, to be able to deal with dot line inversion when mounted on a singleside, gradation voltages with different polarity can be output to the odd number output pins and the even
number output pins. Among 5-by-2 gamma corrected voltages, input gray-scale voltages of the same polarity
with respect to the common voltage, for the respective 5 gamma corrected voltages of VGMA1 - VGMA5 and
VGMA6 - VGMA10.
SHL = H
OUTPUT
-
SHL = L
OUTPUT
-
Y1 Y2 Y3
First Last
D00 - D05 D10 - D15 D20 - D25 D30 - D35 D40 - D45 D50 - D55DATA
Y1
D00 - D05 D10 - D15
Y2
Last
......
......
Y3 Y418
D20 - D25
......
......
Y418
D30 - D35 D40 - D45 D50 - D55DATA
Y419 Y420
Y419 Y420
First
Figure 3. Relationship between Shift Direction and Output Data
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6 BIT 420 CHANNEL TFT-LCD SOURCE DRIVER S6C0678
VDD2
VGMA1
VGMA2
VGMA3
VGMA4
VGMA5
VGMA6
VGMA7
VGMA8
VGMA9
VGMA10
VSS2
00H 08H 10H 18H 20H 28H 30H 38H 3FH
Figure 4. Gamma Correction Curve
VCOM
Input data
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S6C0678 6 BIT 420 CHANNEL TFT-LCD SOURCE DRIVER
Table 1. Resistor Strings (R0 - R62, unit: Ω)
Name Value Name Value Name Value Name Value
R0 500 R16 330 R32 175 R48 210
R1 500 R17 330 R33 175 R49 220
R2 500 R18 330 R34 170 R50 230
R3 500 R19 320 R35 170 R51 240
R4 500 R20 300 R36 165 R52 250
R5 500 R21 280 R37 165 R53 260
R6 500 R22 270 R38 165 R54 270
R7 500 R23 260 R39 165 R55 290
R8 500 R24 250 R40 170 R56 300
R9 500 R25 240 R41 170 R57 310
R10 500 R26 230 R42 170 R58 320
R11 500 R27 220 R43 175 R59 340
R12 450 R28 210 R44 175 R60 340
R13 450 R29 200 R45 175 R61 340
R14 400 R30 190 R46 180 R62 340
R15 370 R31 180 R47 200
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6 BIT 420 CHANNEL TFT-LCD SOURCE DRIVER S6C0678
Table 2. Relationship between Input Data and Output Voltage Value
Input data
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
DX5 DX4 DX3 DX2 DX1 DX0
0 0 0 0 0 0
0 0 0 0 0 1
0 0 0 0 1 0
0 0 0 0 1 1
0 0 0 1 0 0
0 0 0 1 0 1
0 0 0 1 1 0
0 0 0 1 1 1
0 0 1 0 0 0
0 0 1 0 0 1
0 0 1 0 1 0
0 0 1 0 1 1
0 0 1 1 0 0
0 0 1 1 0 1
0 0 1 1 1 0
0 0 1 1 1 1
0 1 0 0 0 0
0 1 0 0 0 1
0 1 0 0 1 0
0 1 0 0 1 1
0 1 0 1 0 0
0 1 0 1 0 1
0 1 0 1 1 0
0 1 0 1 1 1
0 1 1 0 0 0
0 1 1 0 0 1
0 1 1 0 1 0
0 1 1 0 1 1
0 1 1 1 0 0
0 1 1 1 0 1
0 1 1 1 1 0
0 1 1 1 1 1
G/S Output voltage
VH0
VH1
VH2
VH3
VH4
VH5
VH6
VH7
VH8
VH9
VH10
VH11
VH12
VH13
VH14
VH15
VH16
VH17
VH18
VH19
VH20
VH21
VH22
VH23
VH24
VH25
VH26
VH27
VH28
VH29
VH30
VH31
VGMA1 + (VGMA2 - VGMA1) × 500 / 7670
VGMA1 + (VGMA2 - VGMA1) × 1000 / 7670
VGMA1 + (VGMA2 - VGMA1) × 1500 / 7670
VGMA1 + (VGMA2 - VGMA1) × 2000 / 7670
VGMA1 + (VGMA2 - VGMA1) × 2500 / 7670
VGMA1 + (VGMA2 - VGMA1) × 3000 / 7670
VGMA1 + (VGMA2 - VGMA1) × 3500 / 7670
VGMA1 + (VGMA2 - VGMA1) × 4000 / 7670
VGMA1 + (VGMA2 - VGMA1) × 4500 / 7670
VGMA1 + (VGMA2 - VGMA1) × 5000 / 7670
VGMA1 + (VGMA2 - VGMA1) × 5500 / 7670
VGMA1 + (VGMA2 - VGMA1) × 6000 / 7670
VGMA1 + (VGMA2 - VGMA1) × 6450 / 7670
VGMA1 + (VGMA2 - VGMA1) × 6900 / 7670
VGMA1 + (VGMA2 - VGMA1) × 7300 / 7670
VGMA2 + (VGMA3 - VGMA2) × 330 / 4140
VGMA2 + (VGMA3 - VGMA2) × 660 / 4140
VGMA2 + (VGMA3 - VGMA2) × 990 / 4140
VGMA2 + (VGMA3 - VGMA2) × 1310 / 4140
VGMA2 + (VGMA3 - VGMA2) × 1610 / 4140
VGMA2 + (VGMA3 - VGMA2) × 1890 / 4140
VGMA2 + (VGMA3 - VGMA2) × 2160 / 4140
VGMA2 + (VGMA3 - VGMA2) × 2420 / 4140
VGMA2 + (VGMA3 - VGMA2) × 2670 / 4140
VGMA2 + (VGMA3 - VGMA2) × 2910 / 4140
VGMA2 + (VGMA3 - VGMA2) × 3140 / 4140
VGMA2 + (VGMA3 - VGMA2) × 3360 / 4140
VGMA2 + (VGMA3 - VGMA2) × 3570 / 4140
VGMA2 + (VGMA3 - VGMA2) × 3770 / 4140
VGMA2 + (VGMA3 - VGMA2) × 3960 / 4140
VGMA1
VGMA2
NOTE: VDD2 > VGMA1 > VGMA2 > VGMA3 > VGMA4 > VGMA5
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S6C0678 6 BIT 420 CHANNEL TFT-LCD SOURCE DRIVER
Table 2. Relationship between Input Data and Output Voltage Value (Continued)
Input data
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
DX5 DX4 DX3 DX2 DX1 DX0
1
1
1
1
1
1
1
1
0 0 0 0 0
0 0 0 0 1
0 0 0 1 0
0 0 0 1 1
0 0 1 0 0
0 0 1 0 1
0 0 1 1 0
0 0 1 1 1
1 0 1 0 0 0
1 0 1 0 0 1
1 0 1 0 1 0
1 0 1 0 1 1
1 0 1 1 0 0
1 0 1 1 0 1
1 0 1 1 1 0
1 0 1 1 1 1
1 1 0 0 0 0
1 1 0 0 0 1
1 1 0 0 1 0
1 1 0 0 1 1
1 1 0 1 0 0
1 1 0 1 0 1
1 1 0 1 1 0
1 1 0 1 1 1
1 1 1 0 0 0
1 1 1 0 0 1
1 1 1 0 1 0
1 1 1 0 1 1
1 1 1 1 0 0
1 1 1 1 0 1
1 1 1 1 1 0
1 1 1 1 1 1
G/S Output voltage
VH32
VH33
VH34
VH35
VH36
VH37
VH38
VH39
VH40
VH41
VH42
VH43
VH44
VH45
VH46
VH47
VH48
VH49
VH50
VH51
VH52
VH53
VH54
VH55
VH56
VH57
VH58
VH59
VH60
VH61
VH62
VH63
VGMA3 + (VGMA4 - VGMA3) × 175 / 2765
VGMA3 + (VGMA4 - VGMA3) × 350 / 2765
VGMA3 + (VGMA4 - VGMA3) × 520 / 2765
VGMA3 + (VGMA4 - VGMA3) × 690 / 2765
VGMA3 + (VGMA4 - VGMA3) × 855 / 2765
VGMA3 + (VGMA4 - VGMA3) × 020 / 2765
VGMA3 + (VGMA4 - VGMA3) × 1185 / 2765
VGMA3 + (VGMA4 - VGMA3) × 1350 / 2765
VGMA3 + (VGMA4 - VGMA3) × 1520 / 2765
VGMA3 + (VGMA4 - VGMA3) × 1690 / 2765
VGMA3 + (VGMA4 - VGMA3) × 1860 / 2765
VGMA3 + (VGMA4 - VGMA3) × 2035 / 2765
VGMA3 + (VGMA4 - VGMA3) × 2210 / 2765
VGMA3 + (VGMA4 - VGMA3) × 2385 / 2765
VGMA3 + (VGMA4 - VGMA3) × 2565 / 2765
VGMA4 + (VGMA5 - VGMA4) × 210 / 4260
VGMA4 + (VGMA5 - VGMA4) × 430 / 4260
VGMA4 + (VGMA5 - VGMA4) × 660 / 4260
VGMA4 + (VGMA5 - VGMA4) × 900 / 4260
VGMA4 + (VGMA5 - VGMA4) × 1150 / 4260
VGMA4 + (VGMA5 - VGMA4) × 1410 / 4260
VGMA4 + (VGMA5 - VGMA4) × 1680 / 4260
VGMA4 + (VGMA5 - VGMA4) × 1970 / 4260
VGMA4 + (VGMA5 - VGMA4) × 2270 / 4260
VGMA4 + (VGMA5 - VGMA4) × 2580 / 4260
VGMA4 + (VGMA5 - VGMA4) × 2900 / 4260
VGMA4 + (VGMA5 - VGMA4) × 3240 / 4260
VGMA4 + (VGMA5 - VGMA4) × 3580 / 4260
VGMA4 + (VGMA5 - VGMA4) × 3920 / 4260
VGMA3
VGMA4
VGMA5
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6 BIT 420 CHANNEL TFT-LCD SOURCE DRIVER S6C0678
Table 2. Relationship between Input Data and Output Voltage Value (Continued)
Input data
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
DX5 DX4 DX3 DX2 DX1 DX0
0 0 0 0 0 0
0 0 0 0 0 1
0 0 0 0 1 0
0 0 0 0 1 1
0 0 0 1 0 0
0 0 0 1 0 1
0 0 0 1 1 0
0 0 0 1 1 1
0 0 1 0 0 0
0 0 1 0 0 1
0 0 1 0 1 0
0 0 1 0 1 1
0 0 1 1 0 0
0 0 1 1 0 1
0 0 1 1 1 0
0 0 1 1 1 1
0 1 0 0 0 0
0 1 0 0 0 1
0 1 0 0 1 0
0 1 0 0 1 1
0 1 0 1 0 0
0 1 0 1 0 1
0 1 0 1 1 0
0 1 0 1 1 1
0 1 1 0 0 0
0 1 1 0 0 1
0 1 1 0 1 0
0 1 1 0 1 1
0 1 1 1 0 0
0 1 1 1 0 1
0 1 1 1 1 0
0 1 1 1 1 1
G/S Output voltage
VL0
VL1
VL2
VL3
VL4
VL5
VL6
VL7
VL8
VL9
VL10
VL11
VL12
VL13
VL14
VL15
VL16
VL17
VL18
VL19
VL20
VL21
VL22
VL23
VL24
VL25
VL26
VL27
VL28
VL29
VL30
VL31
VGMA10 + (VGMA9 - VGMA10) × 500 / 7670
VGMA10 + (VGMA9 - VGMA10) × 1000 / 7670
VGMA10 + (VGMA9 - VGMA10) × 1500 / 7670
VGMA10 + (VGMA9 - VGMA10) × 2000 / 7670
VGMA10 + (VGMA9 - VGMA10) × 2500 / 7670
VGMA10 + (VGMA9 - VGMA10) × 3000 / 7670
VGMA10 + (VGMA9 - VGMA10) × 3500 / 7670
VGMA10 + (VGMA9 - VGMA10) × 4000 / 7670
VGMA10 + (VGMA9 - VGMA10) × 4500 / 7670
VGMA10 + (VGMA9 - VGMA10) × 5000 / 7670
VGMA10 + (VGMA9 - VGMA10) × 5500 / 7670
VGMA10 + (VGMA9 - VGMA10) × 6000 / 7670
VGMA10 + (VGMA9 - VGMA10) × 6450 / 7670
VGMA10 + (VGMA9 - VGMA10) × 6900 / 7670
VGMA10 + (VGMA9 - VGMA10) × 7300 / 7670
VGMA9 + (VGMA8 - VGMA9) × 330 / 4140
VGMA9 + (VGMA8 - VGMA9) × 660 / 4140
VGMA9 + (VGMA8 - VGMA9) × 990 / 4140
VGMA9 + (VGMA8 - VGMA9) × 1310 / 4140
VGMA9 + (VGMA8 - VGMA9) × 1610 / 4140
VGMA9 + (VGMA8 - VGMA9) × 1890 / 4140
VGMA9 + (VGMA8 - VGMA9) × 2160 / 4140
VGMA9 + (VGMA8 - VGMA9) × 2420 / 4140
VGMA9 + (VGMA8 - VGMA9) × 2670 / 4140
VGMA9 + (VGMA8 - VGMA9) × 2910 / 4140
VGMA9 + (VGMA8 - VGMA9) × 3140 / 4140
VGMA9 + (VGMA8 - VGMA9) × 3360 / 4140
VGMA9 + (VGMA8 - VGMA9) × 3570 / 4140
VGMA9 + (VGMA8 - VGMA9) × 3770 / 4140
VGMA9 + (VGMA8 - VGMA9) × 3960 / 4140
VGMA10
VGMA9
NOTE: VGMA6 > VGMA7 > VGMA8 > VGMA9 > VGMA10 > VSS2
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S6C0678 6 BIT 420 CHANNEL TFT-LCD SOURCE DRIVER
Table 2. Relationship between Input Data and Output Voltage Value (Continued)
Input data
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
DX5 DX4 DX3 DX2 DX1 DX0
1
1
1
1
1
1
1
1
0 0 0 0 0
0 0 0 0 1
0 0 0 1 0
0 0 0 1 1
0 0 1 0 0
0 0 1 0 1
0 0 1 1 0
0 0 1 1 1
1 0 1 0 0 0
1 0 1 0 0 1
1 0 1 0 1 0
1 0 1 0 1 1
1 0 1 1 0 0
1 0 1 1 0 1
1 0 1 1 1 0
1 0 1 1 1 1
1 1 0 0 0 0
1 1 0 0 0 1
1 1 0 0 1 0
1 1 0 0 1 1
1 1 0 1 0 0
1 1 0 1 0 1
1 1 0 1 1 0
1 1 0 1 1 1
1 1 1 0 0 0
1 1 1 0 0 1
1 1 1 0 1 0
1 1 1 0 1 1
1 1 1 1 0 0
1 1 1 1 0 1
1 1 1 1 1 0
1 1 1 1 1 1
G/S Output voltage
VL32
VL33
VL34
VL35
VL36
VL37
VL38
VL39
VL40
VL41
VL42
VL43
VL44
VL45
VL46
VL47
VL48
VL49
VL50
VL51
VL52
VL53
VL54
VL55
VL56
VL57
VL58
VL59
VL60
VL61
VL62
VL63
VGMA8 + (VGMA7 - VGMA8) × 175 / 2765
VGMA8 + (VGMA7 - VGMA8) × 350 / 2765
VGMA8 + (VGMA7 - VGMA8) × 520 / 2765
VGMA8 + (VGMA7 - VGMA8) × 690 / 2765
VGMA8 + (VGMA7 - VGMA8) × 855 / 2765
VGMA8 + (VGMA7 - VGMA8) × 1020 / 2765
VGMA8 + (VGMA7 - VGMA8) × 1185 / 2765
VGMA8 + (VGMA7 - VGMA8) × 1350 / 2765
VGMA8 + (VGMA7 - VGMA8) × 1520 / 2765
VGMA8 + (VGMA7 - VGMA8) × 1690 / 2765
VGMA8 + (VGMA7 - VGMA8) × 1860 / 2765
VGMA8 + (VGMA7 - VGMA8) × 2035 / 2765
VGMA8 + (VGMA7 - VGMA8) × 2210 / 2765
VGMA8 + (VGMA7 - VGMA8) × 2385 / 2765
VGMA8 + (VGMA7 - VGMA8) × 2565 / 2765
VGMA7 + (VGMA6 - VGMA7) × 210 / 4260
VGMA7 + (VGMA6 - VGMA7) × 430 / 4260
VGMA7 + (VGMA6 - VGMA7) × 660 / 4260
VGMA7 + (VGMA6 - VGMA7) × 900 / 4260
VGMA7 + (VGMA6 - VGMA7) × 1150 / 4260
VGMA7 + (VGMA6 - VGMA7) × 1410 / 4260
VGMA7 + (VGMA6 - VGMA7) × 1680 / 4260
VGMA7 + (VGMA6 - VGMA7) × 1970 / 4260
VGMA7 + (VGMA6 - VGMA7) × 2270 / 4260
VGMA7 + (VGMA6 - VGMA7) × 2580 / 4260
VGMA7 + (VGMA6 - VGMA7) × 2900 / 4260
VGMA7 + (VGMA6 - VGMA7) × 3240 / 4260
VGMA7 + (VGMA6 - VGMA7) × 3580 / 4260
VGMA7 + (VGMA6 - VGMA7) × 3920 / 4260
VGMA8
VGMA7
VGMA6
14
Page 15
6 BIT 420 CHANNEL TFT-LCD SOURCE DRIVER S6C0678
ABSOLUTE MAXIMUM RATINGS
Table 3. Absolute Maximum Ratings (VSS1 = VSS2 = 0 V)
Parameter Symbol Ratings Unit
Logic supply voltage VDD1 -0.3 to 5.5 V
Driver supply voltage VDD2 -0.3 to 9.0 V
VGMA1 - 10 -0.3 to VDD2 + 0.3
Input voltage
Output voltage
Operating power dissipation Pd 150 mW
Operation temperature Top -20 to 75
Storage temperature Tstg -55 to 125
RPI1, RPI2 -0.3 to VDD2 + 0.3
Others -0.3 to VDD1 + 0.3
DIO1, 2 -0.3 to VDD1 + 0.3
Y1 to Y420 -0.3 to VDD2 + 0.3
RPO1, RPO2 -0.3 to VDD2 + 0.3
V
V
°C
°C
CAUTIONS:
If LSIs are stressed beyond those listed above “absolute maximum ratings”, they may be permanently
destroyed. These are stress ratings only, and functional operation of the device at these or any other
condition beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute maximum rated conditions for extended periods may affect device reliability.
Turn on power order: VDD1 → control signal input → VDD2 → VGMA1 - VGMA10
or VDD1 & VDD2 → control signal input & VGMA1 - VGMA10
Turn off power order: VGMA1 - VGMA10 → VDD2 → control signal input → VDD1
RECOMMENDED OPERATION CONDITIONS
Table 4. Recommended Operation Conditions (Ta = -20 to 75 °C, VSS1 = VSS2 = 0 V)
Parameter Symbol Min. Typ. Max. Unit
Logic supply voltage VDD1 2.7 3.0 3.6 V
Driver supply voltage VDD2 5.0 7.0 8.0 V
Gamma corrected voltage
Driver part output voltage Vyo VSS2 + 0.1 - VDD2 - 0.1
Maximum clock frequency fmax VDD1 = 2.7 V 45 MHz
VGMA1 - VGMA5 0.5 VDD2 - VDD2 - 0.1
VGMA6 - VGMA10 VSS2 + 0.1 - 0.5 VDD2 V
V
V
Output load capacitance CL - - 150 pF/PIN
15
Page 16
S6C0678 6 BIT 420 CHANNEL TFT-LCD SOURCE DRIVER
DC CHARACTERISTICS
Table 5. DC Characteristics (Ta = -20 to 75 °C, VDD1 = 2.7 to 3.6 V, VDD2 = 5.0 to 8.0 V, VSS1 = VSS2 = 0 V)
Parameter Symbol
High level input voltage
Low level input voltage
Input leakage current IL -1 - 1
VIH 0.7VDD1 - VDD1
VIL 0 - 0.3VDD1
DATPOL2, DIO1 (DIO2)
Input Capacitance Cin
High level output
voltage
Low level output
voltage
Resistor R0 - R62
Driver output current
Line-repair Driver
VOH DIO1 (DIO2), IO = -1.0 mA VDD1-0.5 - -
VOL DIO1 (DIO2), IO = +1.0 mA
Refer to Table 1. Resistor
IVOH1
IVOL1
IVOH2
Vx = 2.5 V, Vyo = 7.5 V
Vx = 5.5 V, Vyo = 0.5 V
Vx = 2.5 V, Vyo = 7.5 V
output current
Output voltage
deviation
Output RMS voltage
deviation
IVOL2
∆VO
dVrms
Vx = 5.5 V, Vyo = 0.5 V
(2)
Condition Min. Typ. Max. Unit
SHL, CLK2, D00 - D55,
CLK1, POL, DATPOL1,
- 5 10 pF
- - 0.5
Strings
VDD2 = 8.0 V,
VDD2 = 8.0 V,
VDD2 = 8.0 V,
VDD2 = 8.0 V,
(1)
(1)
(1)
(1)
Input data : 00H to 3FH -
Input data : 00H to 3FH -
Rn × 0.7 - Rn × 1.3 Ω
- -1.0 -0.5 mA
0.5 1.0 - mA
- -3.0 -1.5 mA
1.5 3.0 - mA
±10 ±20
±5 ±15
V
µA
V
mV
Output voltage range Vyo Input data : 00H to 3FH VSS2 + 0.1
Logic part dynamic
current
IDD1 VDD1 = 3.0 V
(3)
- 4.0 5.5
- VDD2 - 0.1 V
VDD1 = 3.0 V,
Driver part dynamic
current
NOTES:
1. Vyo is the output voltage of analog output pins Y1 to Y420. Vx is the voltage applied to analog output pins Y1 to Y420.
2. dVrms is a maximum deviation value from ideal difference between high output and low output at the same gray scale.
3. CLK1 period is defined to be 15 µs at fCLK2 = 30.5 MHz, data pattern = 101010 (checkerboard pattern), Ta = 25 °C
4. The current consumption per driver when SXGA+ single-sided mounting (10 drivers) is connected in cascade
5. No load
16
IDD2
VDD2 = 8.0 V,
VGMA1 = 7.5 V,
VGMA5 = 4.5 V,
VGMA6 = 3.5 V,
VGMA10 = 0.5 V
(3) (4) (5)
- 4.0 7.0
mA
Page 17
6 BIT 420 CHANNEL TFT-LCD SOURCE DRIVER S6C0678
AC CHARACTERISTICS
Table 6. AC Characteristics (Ta = -20 to 75 °C, VDD1 = 2.7 to 3.6 V, VDD2 = 5.0 to 8.0 V, VSS1 = VSS2 = 0 V)
Parameter Symbol Condition Min. Typ. Max. Unit
Clock pulse width PWCLK - 22 - -
Clock pulse low period PWCLK(L) - 6 - -
Clock pulse high period PWCLK(H) - 6 - -
Data setup time tSETUP1 Refer to NOTE1 2 - -
Data hold time tHOLD1 Refer to NOTE1 2 - -
Start pulse setup time tSETUP2 Refer to NOTE1 2 - -
Start pulse hold time tHOLD2 Refer to NOTE1 2 - -
DATPOL-CLK2 setup time
DATPOL-CLK2 hold time
tSETUP4 Refer to NOTE1 2 - -
tHOLD4 Refer to NOTE1 2 - -
Start pulse delay time tPLH1 CL = 20pF - - 12
CLK1 setup time tSETUP3 - 1 - -
Driver output delay time1
Driver output delay time2
tPHL1 Refer to NOTE2, 4 - - 4
tPHL2 Refer to NOTE3, 4 - - 8
CLK1 pulse high period PWCLK1 - 0.2 - -
Data invalid period tINV
DIO1 (2) ↑ → CLK2 ↑
1
Last data timing tLDT - 1 - -
CLK1-CLK2 time tCLK1 - CLK2
POL-CLK1 time tPOL - CLK1
NOTES:
1. Input condition (VIH = 0.7 VDD1, VIL = 0.3 VDD1)
2. The value is specified when the drive voltage value reaches the target output voltage level of 90%
3. The value is specified when the drive voltage value reaches the target output voltage level of 6-bit accuracy.
4. Yout Load Condition
CLK1 ↑ → CLK2 ↑
POL ↑or ↓ → CLK1 ↑
8 - - ns
6 - - ns
ns
CLK2
period
µs
CLK2
period
YOUT
VCOM = 0.5VDD2
17
10k
Ω
20k
Ω
30pF 30pF 30pF
Figure 5. Yout Load Condition
20k
Ω
Page 18
S6C0678 6 BIT 420 CHANNEL TFT-LCD SOURCE DRIVER
INVALID DATA
(DIO1 output)
POL
tPOL-CLK1
WAVEFORMS (VIH = 0.7 VDD1, VIL = 0.3 VDD1)
PWCLK(H)
VIL
VIH
PWCLK(L)
1st LAST-1 LAST
tINV
tHOLD1
1st
DATA
tSETUP1
tHOLD4
tSETUP4
tHOLD2
tPLH1
Target output voltage
Target output voltage 90%
tPHL1
PWCLK1
tPHL2
HI-Z
tCLK1-CLK2
tLDT
0.5VDD1
LAST
DATA
PWCLK
tSETUP3
CLK1
DIO2 output
CLK2
Y(1:420)
CLK2
INVALID DATA
DXX
DATPOL1
DATPOL2
tSETUP2
DIO1 input
(DIO2 input)
Figure 6. Waveforms
18
CLK1
DXX
Page 19
6 BIT 420 CHANNEL TFT-LCD SOURCE DRIVER S6C0678
VGMA6 - VGMA10VGMA1 - VGMA5
number output
VGMA1 - VGMA5
RELATIONSHIPS BETWEEN CLK1, START PULSE (DIO1, DIO2) AND
BLANKING PERIOD
2nd
DATA
First data in
1st
the next line
DATA
VGMA6 - VGMA10
CLK2
1CLK2
0.5VDD1
DIO1 input
(DIO2 input)
3CLK2(Min.)
CLK1
INVALID DATA
tLDT
Nth
N-1th
DXX
blanking time = Min. 5CLK2
DATA
DATA
Last data
Figure 7. Waveforms
CLK1
HI-Z HI-Z HI-Z
HI-Z
POL
VGMA1 - VGMA5
VGMA6 - VGMA10
Y2N-1:odd
number output
Y2N:even
19
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