Datasheet S6C0666 Datasheet (Samsung)

Download

Page 1

6 BIT 384 CHANNEL RSDS TFT–LCD SOURCE DRIVER PREMILINARY VER 1.0 S6C0666

S6C0666

6 BIT 384 CHANNEL RSDS TFT-LCD SOURCE DRIVER

August. 1999.

Prepared by: Akira Kang

[email protected]

Ver. 0.0

Page 2

S6C0666 PREMILINARY VER 1.0 6 BIT 384 CHANNEL RSDS TFT–LCD SOURCE DRIVER

S6C0666 Specification Revision History

Version Content Date

0.0 Original Aug.1999

Page 3

6 BIT 384 CHANNEL RSDS TFT–LCD SOURCE DRIVER PREMILINARY VER 1.0 S6C0666

CONTENTS

INTRODUCTION .................................................................................................................................................4

FEATURES.........................................................................................................................................................4

BLOCK DIAGRAM..............................................................................................................................................5

PIN ASSINGMENTS............................................................................................................................................ 6

PIN DESCRIPTIONS...........................................................................................................................................7

OPERATION DESCRIPTION...............................................................................................................................8

RSDS RECEIVER AND DEMUX ......................................................................................................................8

RSDS DATA BUS INTERFACE CONTROL......................................................................................................8

DISPLAY DATA TRANSFER............................................................................................................................8

EXTENSION OF OUTPUT ...............................................................................................................................8

RELATIONSHIP BETWEEN INPUT DATA VALUE AND OUTPUT VOLTAGE..................................................8

ABSOLUTE MAXIMUM RATINGS ....................................................................................................................15

RECOMMENDED OPERATION CONDITIONS.................................................................................................. 15

DC CHARACTERISTICS ................................................................................................................................... 16

RSDS CHARACTERISTICS.............................................................................................................................. 17

AC CHARACTERISTICS ................................................................................................................................... 18

WAVEFORMS...................................................................................................................................................19

RSDS DATA TIMING DIAGRAM.......................................................................................................................20

Page 4

S6C0666 PREMILINARY VER 1.0 6 BIT 384 CHANNEL RSDS TFT–LCD SOURCE DRIVER

INTRODUCTION

The S6C0666 is a Source Driver suitable for Reduced Swing Differential Signaling (RSDS) digital interface. It converts 18-bit digital data into the analog voltage for 384 channels, charging each sub-pixel to the correct gray level corresponding to the digital value.

The RSDS path to the panel timing controller contributes toward lowering radiated EMI, reducing system power consumption and eliminates one of the two pixel busses used in typical XGA, SXGA TFT LCD panels. This single 9-bit differential bus conveys the 18-bit color data for XGA, SXGA panels.

FEATURES

• TFT active matrix LCD source driver LSI

• 64 G/S is possible through 10 (5 by 2) external power supply and D/A converter

• Both dot inversion display and N-line inversion display are possible

• Compatible with gamma-correction

• Logic supply voltage: 2.7 to 3.6 V

• LCD driver supply voltage: 7.0 to 10.5 V

• Output dynamic range: 6.8 to 10.3 Vp-p

• Maximum operating frequency: fmax = 65 MHz (internal data transmission rate at 2.7 V operation)

• Output: 384 outputs

• Reduced Swing Differential Signaling (RSDS) digital interface for low power consumption and low EMI.

• Minimum RSDS input swing level (CLKN, CLKP, DATAN, DATAP): 100mV

• Data bus interface control pin (DATPOL)

• TCP or COF available

Page 5

6 BIT 384 CHANNEL RSDS TFT–LCD SOURCE DRIVER PREMILINARY VER 1.0 S6C0666

BLOCK DIAGRAM

POL

VGMA1 to VGMA10

CLK1

D00P D00N D01P D01N

D22P D22N

RSDS Receiver

Data Register

6 6 6

Y1Y2Y3

Output Buffer

R-DAC

Data Latches

128 bit Shift Register

6 6 66 66

Y382

Y383

Y384

CLKP CLKN

RPI1

RPI2

DIO1

Line Repair AMP

Figure 1. S6C0666 Block Diagram

SHL

DIO2

RPO1

RPO2

Page 6

S6C0666 PREMILINARY VER 1.0 6 BIT 384 CHANNEL RSDS TFT–LCD SOURCE DRIVER

PIN ASSINGMENTS

Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12

Y372 Y373 Y374 Y375 Y376 Y377 Y378 Y379 Y380 Y381 Y382 Y383 Y384

S6C0666

RPI1 RPO1 DIO1 D00N D00P D01N D01P D02N D02P DATPOL POL CLK1 CLKN CLKP VSS1 VGMA1 VGMA2 VGMA3 VGMA4 VGMA5 VSS2 VDD2 VGMA6 VGMA7 VGMA8 VGMA9 VGMA10 SHL VDD1 D10N D10P D11N D11P D12N D12P D20N D20P D21N D21P D22N D22P DIO2 RPO2 RPI2

Output 384 Input 44

Figure 2. S6C0666 Pin Assignments

Page 7

6 BIT 384 CHANNEL RSDS TFT–LCD SOURCE DRIVER PREMILINARY VER 1.0 S6C0666

PIN DESCRIPTIONS

Symbol Pin Name Description

VDD1 Logic power supply 2.7 to 3.6 V VDD2 Driver power supply 7.0 to 10.5 V VSS1 Logic ground Ground (0 V) VSS2 Driver ground Ground (0 V)

Y1 to Y384 Driver outputs The D/A converted 64 gray-scale analog voltage is output.

D0P<0:2> D0N<0:2> D1P<0:2> D1N<0:2> D2P<0:2> D2N<0:2>

SHL

DIO1 Start pulse input / output

DIO2 Start pulse input / output

DATPOL Data inversion input

POL Polarity input

CLKP CLKN

CLK1 Latch input

VGMA1

to VGMA10

RPI1, RPO1 RPI2, RPO2

TEST Test input

RSDS data input

Shift direction

control input

RSDS shift clock input

Gamma corrected

power supplies

Line-repair AMP

input / output

Total data lines consist of 18 data bus. (6-bit digital, 3 colors (R, G, B) and 2 differential input pairs) The 3 - bit differential input pairs generate the internal 6 - bit data through the comparison between DxxP and DxxN.

This pin controls the direction of shift register in cascade connection. When SHL = H: DIO1 input, Y1 → Y384, DIO2 output When SHL = L: DIO2 input, Y384 → Y1, DIO1 output

SHL = H: Used as the start pulse input pin. SHL = L: Used as the start pulse output pin.

SHL = H: Used as the start pulse output pin. SHL = L: Used as the start pulse input pin.

DATPOL = L: No inversion DATPOL = H: Data polarity inversion (H↔L)

POL = H: The reference voltage for odd number outputs are VGMA1 to VGMA5 and those for even number outputs are VGMA6 to VGMA10. POL = L: The reference voltage for odd number outputs are VGMA6 to VGMA10 and those for even number outputs are VGMA1 to VGMA5.

The RSDS clock input pairs generate the internal shift clock, CLK2, through the comparison between CLKP and CLKN.

S6C0666 clears 128 shift registers at the rising edge of CLK1 and outputs the analog data to the each channel at the falling edge.

Input the gamma corrected power supplies from external source. VDD2 > VGMA1 > VGMA2 > …… > VGMA9 > VGMA10 > VSS2 Keep power supplies unchanged during the gray-scale voltage output.

The Structure of the line-repair amp is the same as that of the analog output. RPI1 (RPI2) → impedance changed → RPO1 (RPO2)

TEST = L: Normal operation mode TEST = H: Test mode (OP AMP CUT-OFF, Rpd = 15 kΩ)

Page 8

S6C0666 PREMILINARY VER 1.0 6 BIT 384 CHANNEL RSDS TFT–LCD SOURCE DRIVER

OPERATION DESCRIPTION

RSDS RECEIVER AND DEMUX

The S6C0666 adapts the RSDS interface for EMI solution. The internal RSDS receiver block operates the comparison between the transmitted differential input pair data. The input data lines from the timing controller to the RSDS receiver consist of 6-bit digital, 3 colors, 1 port, 2 differential pairs (DxxP / DxxN). The input common mode voltage range at the RSDS receiver is 1.2 V. The differential data and clock signals from the panel timing controller arrive at the S6C0666 as multiplexed, even and odd data fields. (i.e., the data is 2:1 multiplexed). The nominal peak to peak swing of this data is 200 mV across a termination resistor.

RSDS DATA BUS INTERFACE CONTROL

DATPOL controls the internal data inversion. When DATPOL = ”H”, the internal data is inverted. The inverted data is the same that the RSDS receiver operates the comparison between the cross-transmitted differential input pair data. Using the data inversion input pin, DATPOL, the RSDS data bus interface can be changed.

DISPLAY DATA TRANSFER

When DIO1 (or DIO2) pulse is loaded into the internal latch on the falling edge of CLKP, DIO1 (or DIO2) pulse enables the operation of data transfer, so display data is valid on the 2nd falling edge of CLKP. Once all the data of 384 channels is loaded into internal latch, it goes into stand-by state automatically, and any new data is not accepted even though CLKP is provided until next DIO1 (or DIO2) input. When next DIO1 (or DIO2) is provided, new display data is valid on the 2nd falling edge of CLKP after the rising edge of DIO1 (or DIO2).

EXTENSION OF OUTPUT

Output pin can be adjusted to an extended screen by cascade connection. When SHL = "L", Connect DIO1 pin of the previous stage to the DIO2 pin of the next stage and all the input pins except DIO1 and DIO2 are connected together in each device. When SHL = "H", Connect DIO2 pin of the previous stage to the DIO1 pin of the next stage and all the input pins except DIO2 and DIO1 are connected together in each device.

RELATIONSHIP BETWEEN INPUT DATA VALUE AND OUTPUT VOLTAGE

The LCD drive output voltages are determined by the input data and 10 (5 by 2) gamma corrected power supplies (VGMA1 to VGMA10). Besides, to be able to deal with dot line inversion when mounted on a singleside, gradation voltages with different polarity can be output to the odd number output pins and the even number output pins. Among 5 by 2 gamma corrected voltages, input gray scale voltages of the same polarity with respect to the common voltage, for the respective 5 gamma corrected voltages of VGMA1 to VGMA5 and VGMA6 to VGMA10.

Page 9

6 BIT 384 CHANNEL RSDS TFT–LCD SOURCE DRIVER PREMILINARY VER 1.0 S6C0666

VDD2

VGMA1

VGMA2

VGMA3 VGMA4

VGMA5 VGMA6

VGMA7 VGMA8

VGMA9

VGMA10

VSS2

00H 08H 10H 18H 20H 28H 30H 38H 3FH

Figure 3. Gamma Correction Curve

VCOM

Input data

Page 10

S6C0666 PREMILINARY VER 1.0 6 BIT 384 CHANNEL RSDS TFT–LCD SOURCE DRIVER

Table 1. Resistor Strings (R0 to R62, unit: Ω)

Name Value Name Value Name Value Name Value

R0 500 R16 330 R32 175 R48 210 R1 500 R17 330 R33 175 R49 220 R2 500 R18 330 R34 170 R50 230 R3 500 R19 320 R35 170 R51 240 R4 500 R20 300 R36 165 R52 250 R5 500 R21 280 R37 165 R53 260 R6 500 R22 270 R38 165 R54 270 R7 500 R23 260 R39 165 R55 290 R8 500 R24 250 R40 170 R56 300

R9 500 R25 240 R41 170 R57 310 R10 500 R26 230 R42 170 R58 320 R11 500 R27 220 R43 175 R59 340 R12 450 R28 210 R44 175 R60 340 R13 450 R29 200 R45 175 R61 340 R14 400 R30 190 R46 180 R62 340 R15 370 R31 180 R47 200

Page 11

6 BIT 384 CHANNEL RSDS TFT–LCD SOURCE DRIVER PREMILINARY VER 1.0 S6C0666

Table 2. Relationship between Input Data and Output Voltage Value

Input Data

00H 01H 02H 03H 04H 05H 06H 07H

08H

09H 0AH 0BH 0CH 0DH 0EH 0FH

10H

11H

12H

13H

14H

15H

16H

17H

18H

19H 1AH 1BH 1CH 1DH 1EH 1FH

DX5 DX4 DX3 DX2 DX1 DX0

0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 1 1 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 0 1 0 1 1 0 0 1 1 0 0 0 0 1 1 0 1 0 0 1 1 1 0 0 0 1 1 1 1 0 1 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 1 0 1 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 0 1 0 1 1 1 0 1 1 0 0 0 0 1 1 0 0 1 0 1 1 0 1 0 0 1 1 0 1 1 0 1 1 1 0 0 0 1 1 1 0 1 0 1 1 1 1 0 0 1 1 1 1 1

G/S Output Voltage

VH0 VH1 VH2 VH3 VH4 VH5 VH6 VH7

VH8

VH9 VH10 VH11 VH12 VH13 VH14 VH15

VH16 VH17 VH18 VH19 VH20 VH21 VH22 VH23

VH24 VH25 VH26 VH27 VH28 VH29 VH30 VH31

VGMA1+(VGMA2 - VGMA1) × 500/7670 VGMA1+(VGMA2-VGMA1) × 1000/7670 VGMA1+(VGMA2-VGMA1) × 1500/7670 VGMA1+(VGMA2-VGMA1) × 2000/7670 VGMA1+(VGMA2-VGMA1) × 2500/7670 VGMA1+(VGMA2-VGMA1) × 3000/7670 VGMA1+(VGMA2-VGMA1) × 3500/7670

VGMA1+(VGMA2-VGMA1) × 4000/7670 VGMA1+(VGMA2-VGMA1) × 4500/7670 VGMA1+(VGMA2-VGMA1) × 5000/7670 VGMA1+(VGMA2-VGMA1) × 5500/7670 VGMA1+(VGMA2-VGMA1) × 6000/7670 VGMA1+(VGMA2-VGMA1) × 6450/7670 VGMA1+(VGMA2-VGMA1) × 6900/7670 VGMA1+(VGMA2-VGMA1) × 7300/7670

VGMA2+(VGMA3-VGMA2) × 330/4140 VGMA2+(VGMA3-VGMA2) × 660/4140

VGMA2+(VGMA3-VGMA2) × 990/4140 VGMA2+(VGMA3-VGMA2) × 1310/4140 VGMA2+(VGMA3-VGMA2) × 1610/4140 VGMA2+(VGMA3-VGMA2) × 1890/4140 VGMA2+(VGMA3-VGMA2) × 2160/4140

VGMA2+(VGMA3-VGMA2) × 2420/4140 VGMA2+(VGMA3-VGMA2) × 2670/4140 VGMA2+(VGMA3-VGMA2) × 2910/4140 VGMA2+(VGMA3-VGMA2) × 3140/4140 VGMA2+(VGMA3-VGMA2) × 3360/4140 VGMA2+(VGMA3-VGMA2) × 3570/4140 VGMA2+(VGMA3-VGMA2) × 3770/4140 VGMA2+(VGMA3-VGMA2) × 3960/4140

VGMA1

VGMA2

NOTE: VDD2 > VGMA1 > VGMA2 > VGMA3 > VGMA4 > VGMA5

Page 12

S6C0666 PREMILINARY VER 1.0 6 BIT 384 CHANNEL RSDS TFT–LCD SOURCE DRIVER

Table 2. Relationship between Input Data and Output Voltage Value (Continued)

Input Data

20H 21H 22H 23H 24H 25H 26H 27H

28H

29H 2AH 2BH 2CH 2DH 2EH 2FH

30H

31H

32H

33H

34H

35H

36H

37H

38H

39H 3AH 3BH 3CH 3DH 3EH 3FH

DX5 DX4 DX3 DX2 DX1 DX0

0 0 0 0 0

0 0 0 0 1

0 0 0 1 0

0 0 0 1 1

0 0 1 0 0

0 0 1 0 1

0 0 1 1 0

0 0 1 1 1

1 1 0 1 0 0 0 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 1 0 0 1 0 1 1 0 1 1 0 1 1 1 0 1 0 1 1 1 1 1 1 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 0 1 1 0 0 1 1 1 1 0 1 0 0 1 1 0 1 0 1 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 0 0 0 1 1 1 0 0 1 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1

G/S Output Voltage

VH32 VH33 VH34 VH35 VH36 VH37 VH38 VH39

VH40 VH41 VH42 VH43 VH44 VH45 VH46 VH47

VH48 VH49 VH50 VH51 VH52 VH53 VH54 VH55

VH56 VH57 VH58 VH59 VH60 VH61 VH62 VH63

VGMA3+(VGMA4-VGMA3) × 175/2765 VGMA3+(VGMA4-VGMA3) × 350/2765 VGMA3+(VGMA4-VGMA3) × 520/2765 VGMA3+(VGMA4-VGMA3) × 690/2765

VGMA3+(VGMA4-VGMA3) × 855/2765 VGMA3+(VGMA4-VGMA3) × 1020/2765 VGMA3+(VGMA4-VGMA3) × 1185/2765

VGMA3+(VGMA4-VGMA3) × 1350/2765 VGMA3+(VGMA4-VGMA3) × 1520/2765 VGMA3+(VGMA4-VGMA3) × 1690/2765 VGMA3+(VGMA4-VGMA3) × 1860/2765 VGMA3+(VGMA4-VGMA3) × 2035/2765 VGMA3+(VGMA4-VGMA3) × 2210/2765 VGMA3+(VGMA4-VGMA3) × 2385/2765 VGMA3+(VGMA4-VGMA3) × 2565/2765

VGMA4+(VGMA5-VGMA4) × 210/4260

VGMA4+(VGMA5-VGMA4) × 430/4260

VGMA4+(VGMA5-VGMA4) × 660/4260

VGMA4+(VGMA5-VGMA4) × 900/4260 VGMA4+(VGMA5-VGMA4) × 1150/4260 VGMA4+(VGMA5-VGMA4) × 1410/4260 VGMA4+(VGMA5-VGMA4) × 1680/4260

VGMA4+(VGMA5-VGMA4) × 1970/4260 VGMA4+(VGMA5-VGMA4) × 2270/4260 VGMA4+(VGMA5-VGMA4) × 2580/4260 VGMA4+(VGMA5-VGMA4) × 2900/4260 VGMA4+(VGMA5-VGMA4) × 3240/4260 VGMA4+(VGMA5-VGMA4) × 3580/4260 VGMA4+(VGMA5-VGMA4) × 3920/4260

VGMA3

VGMA4

VGMA5

Page 13

6 BIT 384 CHANNEL RSDS TFT–LCD SOURCE DRIVER PREMILINARY VER 1.0 S6C0666

Table 2. Relationship between Input Data and Output Voltage Value (Continued)

Input Data

00H 01H 02H 03H 04H 05H 06H 07H

08H

09H 0AH 0BH 0CH 0DH 0EH 0FH

10H

11H

12H

13H

14H

15H

16H

17H

18H

19H 1AH 1BH 1CH 1DH 1EH 1FH

DX5 DX4 DX3 DX2 DX1 DX0

G/S Output Voltage

VL0 VL1 VL2 VL3 VL4 VL5 VL6 VL7

VL8

VL9 VL10 VL11 VL12 VL13 VL14 VL15

VL16 VL17 VL18 VL19 VL20 VL21 VL22 VL23

VL24 VL25 VL26 VL27 VL28 VL29 VL30 VL31

VGMA10+(VGMA9-VGMA10) × 500/7670 VGMA10+(VGMA9-VGMA10) × 1000/7670 VGMA10+(VGMA9-VGMA10) × 1500/7670 VGMA10+(VGMA9-VGMA10) × 2000/7670 VGMA10+(VGMA9-VGMA10) × 2500/7670 VGMA10+(VGMA9-VGMA10) × 3000/7670 VGMA10+(VGMA9-VGMA10) × 3500/7670

VGMA10+(VGMA9-VGMA10) × 4000/7670 VGMA10+(VGMA9-VGMA10) × 4500/7670 VGMA10+(VGMA9-VGMA10) × 5000/7670 VGMA10+(VGMA9-VGMA10) × 5500/7670 VGMA10+(VGMA9-VGMA10) × 6000/7670 VGMA10+(VGMA9-VGMA10) × 6450/7670 VGMA10+(VGMA9-VGMA10) × 6900/7670 VGMA10+(VGMA9-VGMA10) × 7300/7670

VGMA9+(VGMA8-VGMA9) × 330/4140 VGMA9+(VGMA8-VGMA9) × 660/4140

VGMA9+(VGMA8-VGMA9) × 990/4140 VGMA9+(VGMA8-VGMA9) × 1310/4140 VGMA9+(VGMA8-VGMA9) × 1610/4140 VGMA9+(VGMA8-VGMA9) × 1890/4140 VGMA9+(VGMA8-VGMA9) × 2160/4140

VGMA9+(VGMA8-VGMA9) × 2420/4140 VGMA9+(VGMA8-VGMA9) × 2670/4140 VGMA9+(VGMA8-VGMA9) × 2910/4140 VGMA9+(VGMA8-VGMA9) × 3140/4140 VGMA9+(VGMA8-VGMA9) × 3360/4140 VGMA9+(VGMA8-VGMA9) × 3570/4140 VGMA9+(VGMA8-VGMA9) × 3770/4140 VGMA9+(VGMA8-VGMA9) × 3960/4140

VGMA10

VGMA9

NOTE: VGMA6 > VGMA7 > VGMA8 > VGMA9 > VGMA10 > VSS2

Page 14

S6C0666 PREMILINARY VER 1.0 6 BIT 384 CHANNEL RSDS TFT–LCD SOURCE DRIVER

Table 2. Relationship between Input Data and Output Voltage Value (Continued)

Input Data

20H 21H 22H 23H 24H 25H 26H 27H

28H

29H 2AH 2BH 2CH 2DH 2EH 2FH

30H

31H

32H

33H

34H

35H

36H

37H

38H

39H 3AH 3BH 3CH 3DH 3EH 3FH

DX5 DX4 DX3 DX2 DX1 DX0

0 0 0 0 0

0 0 0 0 1

0 0 0 1 0

0 0 0 1 1

0 0 1 0 0

0 0 1 0 1

0 0 1 1 0

0 0 1 1 1

G/S Output Voltage

VL32 VL33 VL34 VL35 VL36 VL37 VL38 VL39

VL40 VL41 VL42 VL43 VL44 VL45 VL46 VL47

VL48 VL49 VL50 VL51 VL52 VL53 VL54 VL55

VL56 VL57 VL58 VL59 VL60 VL61 VL62 VL63

VGMA8+(VGMA7-VGMA8) × 175/2765 VGMA8+(VGMA7-VGMA8) × 350/2765 VGMA8+(VGMA7-VGMA8) × 520/2765 VGMA8+(VGMA7-VGMA8) × 690/2765

VGMA8+(VGMA7-VGMA8) × 855/2765 VGMA8+(VGMA7-VGMA8) × 1020/2765 VGMA8+(VGMA7-VGMA8) × 1185/2765

VGMA8+(VGMA7-VGMA8) × 1350/2765 VGMA8+(VGMA7-VGMA8) × 1520/2765 VGMA8+(VGMA7-VGMA8) × 1690/2765 VGMA8+(VGMA7-VGMA8) × 1860/2765 VGMA8+(VGMA7-VGMA8) × 2035/2765 VGMA8+(VGMA7-VGMA8) × 2210/2765 VGMA8+(VGMA7-VGMA8) × 2385/2765 VGMA8+(VGMA7-VGMA8) × 2565/2765

VGMA7+(VGMA6-VGMA7) × 210/4260

VGMA7+(VGMA6-VGMA7) × 430/4260

VGMA7+(VGMA6-VGMA7) × 660/4260

VGMA7+(VGMA6-VGMA7) × 900/4260 VGMA7+(VGMA6-VGMA7) × 1150/4260 VGMA7+(VGMA6-VGMA7) × 1410/4260 VGMA7+(VGMA6-VGMA7) × 1680/4260

VGMA7+(VGMA6-VGMA7) × 1970/4260 VGMA7+(VGMA6-VGMA7) × 2270/4260 VGMA7+(VGMA6-VGMA7) × 2580/4260 VGMA7+(VGMA6-VGMA7) × 2900/4260 VGMA7+(VGMA6-VGMA7) × 3240/4260 VGMA7+(VGMA6-VGMA7) × 3580/4260 VGMA7+(VGMA6-VGMA7) × 3920/4260

VGMA8

VGMA7

VGMA6

Page 15

6 BIT 384 CHANNEL RSDS TFT–LCD SOURCE DRIVER PREMILINARY VER 1.0 S6C0666

ABSOLUTE MAXIMUM RATINGS

Table 3. Absolute Maximum Ratings (VSS1 = VSS2 = 0 V)

Parameter Symbol Ratings Unit

Logic supply voltage VDD1 -0.3 to 5.0 V

Driver supply voltage VDD2 -0.3 to 12.0 V

VGMA1 to 10 -0.3 to VDD2 + 0.3

Input voltage

Output voltage

Operating power dissipation Pd 150 mW

Operation temperature Top -20 to 75

Storage temperature Tstg -55 to 125

RPI1, RPI2 -0.3 to VDD2 + 0.3

Others -0.3 to VDD1 + 0.3

DIO1, DIO2 -0.3 to VDD1 + 0.3

Y1 to Y384 -0.3 to VDD2 + 0.3

RPO1, RPO2 -0.3 to VDD2 + 0.3

°C °C

CAUTIONS:

If LSIs are stressed beyond those listed above “absolute maximum ratings”, they may be permanently destroyed. These are stress ratings only, and functional operation of the device at these or any other condition beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Turn on power order: VDD1 → control signal input → VDD2 → VGMA1 to VGMA10 Turn off power order: VGMA1 to VGMA10 → VDD2 → control signal input → VDD1

RECOMMENDED OPERATION CONDITIONS

Table 4. Recommended Operation Conditions (Ta = - 20 to 70 °C, VSS1 = VSS2 = 0 V)

Parameter Symbol Min. Typ. Max. Unit

Logic supply voltage VDD1 2.7 3.0 3.6 V

Driver supply voltage VDD2 7.0 - 10.5 V

VGMA1 to VGMA5 0.5VDD2 - VDD2 - 0.1 V

Gamma corrected voltage

VGMA6 to VGMA10 + 0.1 - 0.5VDD2 V

Driver part output voltage Vyo + 0.1 - VDD2 - 0.1 V

VDD1 = 2.7V - - 65

Maximum clock frequency fmax

VDD1 = 3.0V - - 75

Output load capacitance CL - - 150 pF / PIN

MHz

Page 16

S6C0666 PREMILINARY VER 1.0 6 BIT 384 CHANNEL RSDS TFT–LCD SOURCE DRIVER

DC CHARACTERISTICS

Table 5 . DC Characteristics

(Ta = -20 to 75 °C, VDD1 = 2.7 to 3.6 V, VDD2 = 7.0 to 10.5 V, VSS1 = VSS2 = 0)

Parameter Symbol Condition Min. Typ. Max. Unit

High level input voltage VIH 0.7VDD1 - VDD1

Low level input voltage VIL 0 - 0.3VDD1

Input leakage current IL1

SHL, CLK1, POL, DIO1

(DIO2)

- 1 - 1 Repair input leak current IL2 RPI1(RPI2) - 1 - 1 High level output voltage VOH DIO1(DIO2), IO = - 1.0 mA VDD1 - 0.5 - -

Low level output voltage VOL DIO1(DIO2), IO = + 1.0 mA - - 0.5

Resistance between

gamma voltage

R0 to

R62

IVOH1

Refer to Table 1. Resistor

Strings

VDD2 = 8.0 V,

(1)

= 4.0 V, Vyo

(2)

= 7.0 V

Rn × 0.7 Rn × 1.3 Ω

- - 0.8 - 0.4

Driver output current

IVOL1

IVOH2

Line-repair Driver output

current

IVOL2

Output voltage deviation DVO Input data: 00H to 3FH -

Output swing voltage

difference deviation

dVrms

(3)

(1)

= 4.0 V, Vyo

VDD2 = 8.0 V,

(2)

VDD2 = 8.0 V,

(2)

VDD2 = 8.0 V,

(2)

= 1.0 V

= 7.0 V

= 1.0 V

0.4 0.8 -

- -2.0 -1.0

1.0 2.0 ± 10 ± 20

Input data: 00H to 3FH - ± 5 ± 15

Output voltage range VYO Input data: 00H to 3FH VSS2 + 0.1 - VDD2 - 0.1 V

Logic part dynamic

current

IDD1

VDD1 = 3.0 V

(4)

- 6.0 8.0

VDD1 = 3.0 V, VDD2 = 9.0 V,

Driver part dynamic

current

IDD2

VGMA1 = 8.5 V, VGMA5 = 5.0 V,

- 6.0 9.0

VGMA6 = 4.0 V,

VGMA10 = 0.5 V

(4) (5)

µA

NOTES:

1. Vx is the voltage applied to analog output pins Y1 to Y384.

2. Vyo is the output voltage of analog output pins Y1 to Y384.

3. dVrms = max. deviation of (VHx-VLx) VHx; the x gray level positive polarity driver output voltage VLx; the x gray level negative polarity driver output voltage

4. CLK1 period = 20 µs at fCLKP = 33 MHz, data pattern = 1010……, (checkerboard pattern), Ta = 25 °C

5. Yout load condition (refer to Figure 4. Yout Load Condition) applied.

Page 17

6 BIT 384 CHANNEL RSDS TFT–LCD SOURCE DRIVER PREMILINARY VER 1.0 S6C0666

RSDS CHARACTERISTICS

Table 6 . RSDS Characteristics

(Ta = - 20 to 75 °C, VDD1 = 2.7 to 3.6 V, VDD2 = 7.0 to 10.5 V, VSS1 = VSS2 = 0)

Parameter Symbol Condition Min. Typ. Max. Unit

RSDS high input voltage VIHRSDS

RSDS low input voltage VIHRSDS

RSDS common mode

input voltage range

RSDS input leakage

current

NOTES:

1. VCMRSDS = (VCLKP + VCLKN) / 2 or VCMRSDS = (VDxxP + VDxxN) / 2

2. VDIFFRSDS = VCLKP - VCLKN or VDIFFRSDS = VDxxP - VDxxN

VCMRSDS

IDL DxxP, DxxN, CLKP, CLKN - 10 - 10 µA

VCMRSDS = + 1.2 V VCMRSDS = + 1.2 V

VDIFFRSDS = + 200 mV

(1) (1)

100 200

- 200 - 100

(2)

VSS1 + 0.1 - VDD1 - 1.5 V

YOUT

VCOM=0.5VDD2

10k

Ω

20k

Ω

20pF 20pF 20pF

Figure 4. Yout Load Condition

20k

Ω

Page 18

S6C0666 PREMILINARY VER 1.0 6 BIT 384 CHANNEL RSDS TFT–LCD SOURCE DRIVER

AC CHARACTERISTICS

Table 6. AC Characteristics (Ta = - 20 to 75 °C, VDD2 = 7.0 to 10.5 V, VSS1 = VSS2 = 0 V)

Parameter Symbol Condition Min. Typ. Max. Unit

Clock pulse width PWCLK - 15 - -

Clock pulse low period PWCLK(L) - 6 - -

Clock pulse high period PWCLK(H) - 6 - -

Data setup time tSETUP1 - 2 - -

Data hold time tHOLD1 - 0 - -

Start pulse setup time tSETUP2 - 4 - -

Start pulse hold time tHOLD2 - 2 - -

Start pulse delay time tPLH1 CL = 15pF - - 12

DIO signal pulse width PWDIO 1CLKP - 2CLKP

CLK1 setup time tSETUP3 - 2CLKP - -

CLK1 high pulse width PWCLK1 - 5CLKP - 2 Driver output delay time1 tPHL1 Driver output delay time2 tPHL2

(1) (3) (2) (3)

- - 6

- 10 Repair output delay time1 tPHL3 CL = 150pF - - 6 Repair output delay time2 tPHL4 CL = 150pF - 10

Last data timing tLDT - 1CLKP - -

CLK1-CLK2 time tCLK1-CLK2

POL-CLK1 time tPOL-CLK1 CLK1-POL time tCLK1-POL

CLK1 ↑ → CLKP ↓ POL ↑ or ↓ → CLK1 ↑ CLK1 ↓ → POL ↑ or ↓

4 - 14 - 10 - -

CLKP

period

µs

CLKP

period

NOTES:

1. The value is specified when the drive voltage value reaches the target output voltage level of 90%

2. The value is specified when the drive voltage value reaches the target output voltage level of 6-bit accuracy.

3. Yout load condition (refer to Figure 4. Yout Load Condition)

Page 19

6 BIT 384 CHANNEL RSDS TFT–LCD SOURCE DRIVER PREMILINARY VER 1.0 S6C0666

CLKP-CLKN

(RSDS)

Input

DIO1; SHL=H

DIO2; SHL=L

DxxP-DxxN

(RSDS)

Output

DIO1; SHL=H

DIO2; SHL=L

CLKP-CLKN

VILRSDS

DxxP-DxxN

Input

DIO1; SHL=H

DIO2; SHL=L

CLK1

POL

Y1 to Y384

RPO1, RPO2

WAVEFORMS

tPHL4

90%

Invalid

90%

tCLK1-CLK2

PWCLK1

10%10%

tCLK1-POL

10%

90%

tPHL1

VIHRSDS0VVILRSDS

90%

tPHL3

tPHL2

tHOLD1

tSETUP1

VIHRSDS

PWCLK(H)

PWCLK(L)

PWCLK

tLDT

tPLH1

tPHL1

ODDEVENODD EVEN ODDEVEN

EVEN ODD EVEN ODD

1st Data 2nd Data

90%

10%

90%

10%

90%

tPOL-CLK1

tHOLD1

CLKP-CLKN

VIHRSDS0VVILRSDS

tSETUP1

tHOLD2

90%

PWDIO

Invalid

Figure 5. Waveforms

90%

tSETUP2

Page 20

S6C0666 PREMILINARY VER 1.0 6 BIT 384 CHANNEL RSDS TFT–LCD SOURCE DRIVER

RSDS DATA TIMING DIAGRAM

CLKP

Input DIO: SHL=H DOI: SHL=L

D00P/N

D01P/N

D02P/N

D10P/N

tSETUP2

tHOLD2

tHOLD1

tSETUP1

R[0]1R[1]1R[0]2R[1]2R[0]3R[1]3R[0]4R[1]

R[2]1R[3]1R[2]2R[3]2R[2]3R[3]3R[2]4R[3]

R[4]1R[5]1R[4]2R[5]2R[4]3R[5]3R[4]4R[5]

G[0]1G[1]1G[0]2G[1]2G[0]3G[1]3G[0]4G[1]

tSETUP1

tHOLD1

D11P/N

D12P/N

D20P/N

D21P/N

D22P/N

G[2]1G[3]1G[2]2G[3]2G[2]3G[3]3G[2]4G[3]

G[4]1G[5]1G[4]2G[5]2G[4]3G[5]3G[4]4G[5]

B[0]1B[1]1B[0]2B[1]2B[0]3B[1]3B[0]4B[1]

B[2]1B[3]1B[2]2B[3]2B[2]3B[3]3B[2]4B[3]

B[4]1B[5]1B[4]2B[5]2B[4]3B[5]3B[4]4B[5]

Figure 6. RSDS Data Timing Diagram