Page 1
SUMMIT MICROELECTRONICS, Inc. • 300 Orchard City Drive, Suite 131 • Campbell, CA 95008 • Telephone 408-378-6461 • Fax 408-378-6586 • www.summitmicro.com
1
© SUMMIT MICROELECTRONICS, Inc. 2000
2025 6.0 4/17/00
Characteristics subject to change without notice
FEATURES
• Precision Dual Voltage Monitor
–V
CC
Supply Monitor
- Dual reset outputs for complex
microcontroller systems
- Integrated memory write lockout function
- No external components required
• Second Voltage Monitor Output
– Separate V
LOW
output
– Generates interrupt to MCU
– Generates RESET for dual supply systems
- Guaranteed output assertion to VCC - 1V
• Watchdog Timer (S42WD42, S42WD61)
–1.6s
• Memory Internally Organized 2 x8
• Extended Programmable Functions
Available on SMS24
Dual V oltage Supervisory Circuit
With Watchdog Timer(S42WD61) (S42WD42)
S4242/S42WD42/S4261/S42WD61
• High Reliability
– Endurance: 100,000 erase/write cycles
– Data retention: 100 years
OVERVIEW
The S42xxx are a precision power supervisory circuit. It
automatically monitors the device’s VCC level and will
generate a reset output on two complementary open drain
outputs. In addition to the VCC monitoring, the S42xxx also
provides a second voltage comparator input. This input
has an independent open drain output that can be wireOR’ed with the RESET I/O or it can be used as a system
interrupt.
The S42xxx also has an integrated 4k/16k-bit nonvolatile
memory. The memory conforms to the industry standard
two-wire serial interface. In addition to the reset circuitry,
the S42WD42/S42WD61 also has a watchdog timer.
BLOCK DIAGRAM
PROGRAMMABLE
WATCHDOG
TIMER
+
–
GND
V
CC
8
4
RESET#
2
V
TRIP
RESET
CONTROL
RESET
7
1.26V
SCL
6
SDA
5
2025 T BD 2.0
WRITE
CONTROL
NONVOLATILE
MEMORY
ARRAY
PROGRAMMABLE
RESET PULSE
GENERATOR
+
–
VLOW#
UV
OV
V
SENSE
3
1
(S42WD42,
S42WD61)
Page 2
2
S4242/S42WD42/S4261/S42WD61
2025 6.0 4/17/00
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias ............................................................................................................................... -40°C to +85°C
Storage Temperature ..................................................................................................................................... -65°C to +125°C
Soldering Temperature (less than 10 seconds) ...................................................................................................................300°C
Supply Voltage ............................................................................................................................................................. 0 to 6.5V
Voltage on Any Pin ....................................................................................................................................... -0.3V to V
CC
+0.3V
ESD Voltage (JEDEC method) .......................................................................................................................................... 2,000V
NOTE: These are STRESS ratings only. Appropriate conditions for operating these devices are given elsewhere in this specification. Stresses
beyond those listed here may permanently damage the part. Prolonged exposure to maximum ratings may affect device reliability.
2.7V to 4.5V 4.5V to 5.5V
Symbol Parameter Conditions Min Max Min Max Units
fSCL SCL Clock Frequency 0 100 400 KHz
tLOW Clock Low Period 4.7 1.3 µs
tHIGH Clock High Period 4.0 0.6 µs
tBUF Bus Free Time Before New Transmission 4.7 1.3 µs
tSU:STA Start Condition Setup Time 4.7 0.6 µs
tHD:STA Start Condition Hold Time 4.0 0.6 µs
tSU:STO Stop Condition Setup Time 4.7 0.6 µs
tAA Clock to Output SCL Low to SDA Data Out Valid 0.3 3.5 0.2 0.9 µs
tDH Data Out Hold Time SCL Low to SDA Data Out Change 0.3 0.2 µs
tR SCL and SDA Rise Time 1000 300 ns
tF SCL and SDA Fall Time 300 300 ns
tSU:DAT Data In Setup Time 250 100 ns
tHD:DAT Data In Hold Time 0 0 ns
TI Noise Spike Width Noise Suppression Time Constant 100 100 ns
@ SCL, SDA Inputs
tWR Write Cycle Time 10 10 ms
AC ELECTRICAL CHARACTERISTICS
(over recommended operating conditions unless otherwise specified)
2025 PGM T3.0
2025 PGM T2.0
DC ELECTRICAL CHARACTERISTICS (over recommended operating conditions unless otherwise specified)
Symbol Parameter Conditions Min Max Units
SCL = CMOS Levels @ 100KHz V
CC
=5.5V 3 mA
I
CC
Supply Current (CMOS) SDA = Open
All other inputs = GND or V
CC
V
CC
=3.3V 2 mA
I
SB
Standby Current (CMOS) SCL = SDA = V
CC
V
CC
=5.5V 50 µA
All other inputs = GND
I
LI
Input Leakage VIN = 0 To V
CC
10 µA
I
LO
Output Leakage V
OUT
= 0 To V
CC
10 µA
V
IL
Input Low Voltage SCL, SDA, RESET# (pin 2) 0.3xV
CC
V
V
IH
Input High Voltage SCL, SDA, RESET (pin7) 0.7xV
CC
V
V
OL
Output Low Voltage IOL = 3mA SDA 0.4 V
V
CC
=3.3V 25 µA
Temperature Min Max
Commercial 0°C +70°C
Industrial -40°C +85°C
RECOMMENDED OPERATING CONDITIONS
2025 PGM T1.0
Page 3
S4242/S42WD42/S4261/S42WD61
3
2025 6.0 4/17/00
FIGURE 2. START AND STOP CONDITIONS
FIGURE 1. BUS TIMING
CAPACITANCE
TA = 25°C, f = 100KHz
Symbol Parameter Max Units
CIN Input Capacitance 5 pF
C
OUT
Output Capacitance 8 pF
2025 PGM T4.0
t
F
t
R
t
LOW
t
HIGH
t
HD:SDA
t
SU:SDA
t
BUF
t
DH
t
HD:DAT
t
SU:DAT
t
SU:STO
SCL
SDA In
SDA Out
t
AA
2025 Fig01 1.0
2025 Fig02 1.0
SCL
SDA In
START
Condition
STOP
Condition
Page 4
4
S4242/S42WD42/S4261/S42WD61
2025 6.0 4/17/00
FIGURE 3. RESET OUTPUT TIMING
RESET CIRCUIT AC and DC ELECTRICAL CHARACTERISTICS
TA=-40°C to +85°C
Symbol Parameter Part no. Min. Typ. Max. Unit
Suffix
V
TRIP
Reset Trip Point A (or) Blank 4.250 4.375 4.5 V
B 4.50 4.625 4.75 V
2.7 2.7 2.9 3.10 V
t
PURST
Reset Timeout 200 ms
t
RPD
V
TRIP
to RESET Output Delay 5 µs
V
RVALID
RESET Output Valid to VCC min. Guarantee 1 V
t
GLITCH
Glitch Reject Pulse Width note 1 30 ns
V
OLRS
RESET Output Low Voltage IOL = 1mA 0.4 V
V
OHRS
RESET High Voltage Output IOH = 800µA VCC-.75 V
V
ULH
V
SENSE
Under-voltage threshold low to high 1.20 1.25 1.30 V
V
UHL
V
SENSE
Under-voltage threshold high to low 1.20 1.25 1.30 V
V
OLH
V
SENSE
Over-voltage threshold low to high 1.20 1.25 1.30 V
V
OHL
V
SENSE
Over-voltage threshold high to low 1.20 1.25 1.30 V
t
VD1
Delay to V
LOW
Active 5 µs
t
VD2
Delay to V
LOW
Released 5 µs
t
WDTO
Watchdog timeout Period (S42WD61) 1600 ms
(S42WD42)
2025 PGM T5.2
V
CC
V
RVALID
V
TRIP
t
PURST
RESET
2025 T fig03 2.0
t
GLITCH
t
RPD
t
PURST
t
RPD
RESET#
Page 5
S4242/S42WD42/S4261/S42WD61
5
2025 6.0 4/17/00
FIGURE 4. V
SENSE
UNDER-VOLTAGE FUNCTION
FIGURE 5. RESET AS AN INPUT
2025 T fig05 2.0
t
PURST
t
PURST
RESET (out)
RESET# (in)
RESET# (out)
2025 T fig04 2.0
V
ULH
V
UHL
tVD2
tVD1
VSENSE
(Under-voltage detect)
VLOW#
Page 6
6
S4242/S42WD42/S4261/S42WD61
2025 6.0 4/17/00
PIN CONFIGURATIONS
FIGURE 6. TYPICAL SYSTEM CONFIGURATION USING A PUSH BUTTON RESET AND BATTERY MONITOR CIRCUIT
FIGURE 7. TYPICAL SYSTEM CONFIGURATION FOR DUAL RESET WITH VCC MONITOR AND 3.3VOLT MONITOR
V
LOW
#
RESET#
V
SENSE
GND
V
CC
RESET
SCL
SDA
1
2
3
4
8
7
6
5
8-Pin PDIP
or 8-Pin SOIC
2025 T PCon 2.0
PIN NAMES
VCC = 5.0V ±10%
V
LOW
#
RESET#
V
SENSE
GND
V
CC
RESET
SCL
SDA
S42xxx
RESET#
SCL
SDA
I2C Peripheral
SCL
SDA
RESET#
General
Purpose
MCU
2025 T fig07 2.0
SECOND CARD
VOLTAGE
3.0V ±5%
VCC = 3.0V or 5.0V
V
LOW
#
RESET#
V
SENSE
GND
V
CC
RESET
SCL
SDA
S42xxx
RESET#
SCL
SDA
I2C Peripheral
RST
SCL (P0.0)
SDA (P0.1)
INTO (P1.5)
8051 Type
MCU
PB_RST#
2025 T fig06 2.0
V
BAT
TRIP
VBAT TO
REGULATOR
lobmySniPnoitpircseD
V
WOL
#1
nehwevitca,tuptuoniardnepO
V
ESNES
V42.1<
#TESER2 O/IwolevitcA
V
ESNES
3
V.tupniegatlovrotinomdn2
WOL
#
V42.1<nehwtuptuo
DNG4 dnuorglatigid&golanA
ADS5 enilatadO/IyromemlaireS
LCS6 kcolcyromemlaireS
TESER7 O/IhgihevitcA
V
CC
8egatlovylppuS
Page 7
S4242/S42WD42/S4261/S42WD61
7
2025 6.0 4/17/00
ENDURANCE AND DATA RETENTION
The S42xxx is designed for applications requiring
100,000 erase/write cycles and unlimited read cycles. It
provides 100 years of secure data retention, with or
without power applied, after the execution of 100,000
erase/write cycles.
Reset Controller Description
The S42xxx provides a precision RESET controller that
ensures correct system operation during brown-out and
power-up/-down conditions. It is configured with two open
drain RESET outputs; pin 7 is an active high output and
pin 2 is an active low output. For proper operation pin 7
should be tied low through a pull-down resistor while pin
2 should be tied high through a resistor connected to V
CC
.
During power-up, the RESET outputs remain active until
VCC reaches the V
TRIP
threshold and will continue driving
the outputs for t
PURST
(200 msec)after reaching V
TRIP
.
The RESET outputs will be valid so long as VCC is > 1.0V.
During power-down, the RESET outputs will begin driving
active when VCC falls below V
TRIP
.
The RESET pins are I/Os; therefore, the S42xxx can act
as a signal conditioning circuit for an externally applied
reset. The inputs are edge triggered; that is, the RESET
input will initiate a reset timeout after detecting a low to
high transition and the RESET# input will initiate a reset
timeout after detecting a high to low transition. Refer to the
applications information section for more details on device operation as a reset conditioning circuit.
Voltage Sensor Description
V
SENSE
is an auxiliary voltage detection circuit. Its thresh-
old is set at 1.25V and it generates a V
LOW
# output for an
under-voltage condition. Because the V
LOW
# output is
open-drain, it can be wire-ORed with the RESET# output
or tied directly to an IRQ input on a microcontroller.
PIN DESCRIPTIONS
Serial Clock (SCL) - The SCL input is used to clock data
into and out of the device. In the WRITE mode, data must
remain stable while SCL is HIGH. In the READ mode, data
is clocked out on the falling edge of SCL.
Serial Data (SDA) - The SDA pin is a bidirectional pin
used to transfer data into and out of the device. Data may
change only when SCL is LOW, except START and STOP
conditions. It is an open-drain output and may be wireORed with any number of open-drain or open-collector
outputs.
RESET# - RESET# is an active low open-drain output. It
should be tied high through a pull-up resistor connected to
VCC. RESET# is an I/O, therefore it may also be used to
condition a RESET# signal generated by another device;
it can also be used to debounce a pushbutton input.
RESET - RESET is an active high open drain (PFET)
output. It should be tied low through a pull-down resistor
connected to ground. RESET is an I/O, therefore it may
also be used to condition a RESET signal generated by
another device.
V
SENSE
- The V
SENSE
input is used as a second voltage
sensing input. The pin is tied to a comparator that uses the
precision internal 1.25V reference.
V
LOW
# - V
LOW
# is an active low open drain output driven
low whenever V
SENSE
is below 1.25V. It is not a timed
output and only responds to the state of V
SENSE
.
Page 8
8
S4242/S42WD42/S4261/S42WD61
2025 6.0 4/17/00
FIGURE 8. ACKNOWLEDGE RESPONSE FROM RECEIVER
CHARACTERISTICS OF THE I2C BUS
General Description
The I
2
C bus was designed for two-way, two-line serial
communication between different integrated circuits. The
two lines are: a serial data line (SDA), and a serial clock
line (SCL). The SDA line must be connected to a positive
supply by a pull-up resistor, located somewhere on the
bus (See Figure 6). Data transfer between devices may
be initiated with a START condition only when SCL and
SDA are HIGH (bus is not busy).
Input Data Protocol
One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable during clock
HIGH time, because changes on the data line while SCL
is HIGH will be interpreted as start or stop condition, refer
to Figure 2.
START and STOP Conditions
When both the data and clock lines are HIGH, the bus is
said to be not busy. A HIGH-to-LOW transition on the data
line, while the clock is HIGH, is defined as the “START”
condition. A LOW-to-HIGH transition on the data line,
while the clock is HIGH, is defined as the “STOP” condition (See Figure 2).
DEVICE OPERATION
The S42xxx is a 16K-bit serial E2PROM. The device
supports the I2C bidirectional data transmission protocol.
The protocol defines any device that sends data onto the
bus as a “transmitter” and any device which receives data
as a “receiver.” The device controlling data transmission
is called the “master” and the controlled device is called
the “slave.” In all cases, the S42xxx will be a “slave”
device, since it never initiates any data transfers.
Acknowledge (ACK)
Acknowledge is a software convention used to indicate
successful data transfers. The transmitting device, either
the master or the slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver
FIGURE 9. SLAVE ADDRESS BYTE
will pull the SDA line LOW to ACKnowledge that it received
the eight bits of data (See Figure 8).
The S42xxx will respond with an ACKnowledge after
recognition of a START condition and its slave address
byte. If both the device and a write operation are selected,
the S42xxx will respond with an ACKnowledge after the
receipt of each subsequent 8-bit word.
In the READ mode, the S42xxx transmits eight bits of
data, then releases the SDA line, and monitors the line for
an ACKnowledge signal. If an ACKnowledge is detected,
and no STOP condition is generated by the master, the
S42xxx will continue to transmit data. If an ACKnowledge
is not detected, the S42xxx will terminate further data
transmissions and awaits a STOP condition before returning to the standby power mode.
Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most significant
four bits of the slave address are the device type identifier
(see figure 7). For the S42xxx this is fixed as 1010[B].
Word Address
The next three bits of the slave address are an extension
of the array’s address and are concatenated with the eight
bits of address in the word address field, providing direct
access to the 2,048 x8 array of the S4261 and S42WD61.
A10 and A9 are “Don’t Care” on S4242 and S42WD42.
Read/Write Bit
The last bit of the data stream defines the operation to be
performed. When set to “1,” a read operation is selected;
when set to “0,” a write operation is selected.
SCL from
Master
Data Output
from
Transmitter
Data Output
from
Receiver
Start
Condition
ACKnowledge
t
AA
t
AA
1
8
9
2025 ILL8.0
1 0 1 0
* *
A10 A9 A8 R/W
*S4261/S42WD61 only
DEVICE
IDENTIFIER
HIGH ORDER
WORD ADDRESS
2025 ILL9.1
Page 9
S4242/S42WD42/S4261/S42WD61
9
2025 6.0 4/17/00
FIGURE 10. PAGE/BYTE WRITE MODE
WRITE OPERATIONS
The S42xxx allows two types of write operations: byte
write and page write. The byte write operation writes a
single byte during the nonvolatile write period (tWR). The
page write operation allows up to 16 bytes in the same
page to be written during tWR.
Byte WRITE
After the slave address is sent (to identify the slave
device, specify high order word address and a read or
write operation), a second byte is transmitted which
contains the low 8 bit addresses of any one of the 2,048
words in the array.
Upon receipt of the word address, the S42xxx responds
with an ACKnowledge. After receiving the next byte of
data, it again responds with an ACKnowledge. The master then terminates the transfer by generating a STOP
condition, at which time the S42xxx begins the internal
write cycle.
While the internal write cycle is in progress, the S42xxx
inputs are disabled, and the device will not respond to any
requests from the master. Refer to Figure 10 for the
address, ACKnowledge and data transfer sequence.
Page WRITE
The S42xxx is capable of a 16-byte page write operation.
It is initiated in the same manner as the byte-write operation, but instead of terminating the write cycle after the first
data word, the master can transmit up to 15 more words
of data. After the receipt of each word, the S42xxx will
respond with an ACKnowledge.
The S42xxx automatically increments the address for
subsequent data words. After the receipt of each word,
the four low order address bits are internally incremented
by one. The high order five bits of the address byte remain
constant. Should the master transmit more than sixteen
words, prior to generating the STOP condition, the address counter will “roll over,” and the previously written
data will be overwritten. As with the byte-write operation,
all inputs are disabled during the internal write cycle.
Refer to Figure 10 for the address, ACKnowledge and
data transfer sequence.
D7D6D5D4D3D2D1D
0
D7D6D5D4D3D2D1D
0
A7A6A5A4A3A2A1A0D7D5D6D
4
D
0
D3D2D
1
S
T
A
R
T
Word Address Data Byte n Data Byte n+15
S
T
O
P
A
C
K
Acknowledges Transmitted from
42xxx to Master Receiver
Slave Address
Device
Type
Address
Read/Write
0= Write
A10,A9,A8
SDA
Bus
Activity
A
C
K
A
C
K
Master Sends Read
Request to Slave
Master Writes Word
Address to Slave
1 0 1 0
0
Data Byte n+1
A
C
K
Master Writes
Data to Slave
Master Transmitter
to
Slave Receiver
Slave Transmitter
to
Master Receiver
Slave Transmitter
to
Master Receiver
Master Transmitter
to
Slave Receiver
Master Transmitter
to
Slave Receiver
Shading Denotes
42xxx
SDA Output Active
Master Transmitter
to
Slave Receiver
Slave Transmitter
to
Master Receiver
Slave Transmitter
to
Master Receiver
Master Transmitter
to
Slave Receiver
Slave Transmitter
to
Master Receiver
Master Writes
Data to Slave
Master Writes
Data to Slave
Acknowledges Transmitted from
42xxx to Master Receiver
If single byte-write only,
Stop bit issued here.
A10A9R
W
A
C
K
A
8
2025 ILL10.1
Page 10
10
S4242/S42WD42/S4261/S42WD61
2025 6.0 4/17/00
FIGURE 12. CURRENT ADDRESS BYTE READ MODE
FIGURE 11. ACKNOWLEDGE POLLING
Acknowledge Polling
When the S42xxx is performing an internal WRITE operation, it will ignore any new START conditions. Since the
device will only return an acknowledge after it accepts the
START, the part can be continuously queried until an
acknowledge is issued, indicating that the internal WRITE
cycle is complete.
To poll the device, give it a START condition, followed by
a slave address for a WRITE operation (See Figure 9).
READ OPERATIONS
Read operations are initiated with the R/W bit of the
identification field set to “1.” There are four different read
options:
1. Current Address Byte Read
2. Random Address Byte Read
3. Current Address Sequential Read
4. Random Address Sequential Read
Current Address Byte Read
The S42xxx contains an internal address counter which
maintains the address of the last word accessed,
incremented by one. If the last address accessed (either
a read or write) was to address location n, the next read
operation would access data from address location n+1
and increment the current address pointer. When the
S42xxx receives the slave address field with the R/W bit
set to “1,” it issues an acknowledge and transmits the 8bit word stored at address location n+1.
The current address byte read operation only accesses a
single byte of data. The master does not acknowledge the
transfer, but does generate a stop condition. At this point,
the S42xxx discontinues data transmission. See
Figure 12 for the address acknowledge and data transfer
sequence.
Issue Start
Internal WRITE Cycle
In Progress;
Begin ACK Polling
Issue Slave
Address and
R/W = 0
ACK
Returned?
Next
operation a
WRITE?
Issue Byte
Address
Proceed with
WRITE
Issue Stop
Await Next
Command
Issue Stop
No
No
Yes (Internal WRITE Cycle is completed)
Yes
2025 ILL11.0
S
T
A
R
T
S
T
O
P
Slave Address
Device
Type
Address
Read/Write
1= Read
A10,A9,A8
SDA Bus Activity
D7D6D5D4D3D2D1D
0
Master sends Read
request to Slave
Slave sends
Data to Master
Master Transmitter
to
Slave Receiver
Slave Transmitter
to
Master Receiver
11100 1
Lack of ACK (low)
from Master
determines last
data byte to be read
1
Shading Denotes
42xxx
SDA Output Active
A9A
10RW
A
C
K
A
8
Data Byte
2025 ILL12.1
Page 11
S4242/S42WD42/S4261/S42WD61
11
2025 6.0 4/17/00
FIGURE 13. RANDOM ADDRESS BYTE READ MODE
Random Address Byte Read
Random address read operations allow the master to
access any memory location in a random fashion. This
operation involves a two-step process. First, the master
issues a write command which includes the start condition and the slave address field (with the R/W bit set to
WRITE) followed by the address of the word it is to read.
This procedure sets the internal address counter of the
S42xxx to the desired address.
After the word address acknowledge is received by the
master, the master immediately reissues a start condition
followed by another slave address field with the R/W bit
set to READ. The S42xxx will respond with an acknowledge and then transmit the 8-data bits stored at the
addressed location. At this point, the master does not
acknowledge the transmission but does generate the stop
condition. The S42xxx discontinues data transmission
and reverts to its standby power mode. See Figure 13 for
the address, acknowledge and data transfer sequence.
D7D6D5D4D3D2D1D
0
A7A6A5A4A3A2A1A
0
S
T
A
R
T
Word Address
* S4261/S42WD61 only
S
T
O
P
A
C
K
Slave Address
Slave Address
Device
Type
Address
Read/Write
0= Write
Device
Type
Address
A10,A9,A8
A10,A9,A8
SDA Bus
Activity
S
T
A
R
T
Read/Write
1= Read
A
C
K
A
C
K
Master sends Read
request to Slave
Master Writes Word
Address to Slave
Master Requests
Data from Slave
Slave sends
Data to Master
1010 1010 10
*
A
10
*
A
9
RWA
8
A9R
W
A10A
8
Lack of ACK (low)
from Master
determines last
data byte to be read
1
Slave Transmitter
to
Master Receiver
Slave Transmitter
to
Master Receiver
Shading Denotes
42xxx
SDA Output Active
Slave Transmitter
to
Master Receiver
Master Transmitter
to
Slave Receiver
Master Transmitter
to
Slave Receiver
Master Transmitter
to
Slave Receiver
Slave Transmitter
to
Master Receiver
Data Byte
2025 ILL13.1
Page 12
12
S4242/S42WD42/S4261/S42WD61
2025 6.0 4/17/00
FIGURE 14. SEQUENTIAL READ OPERATION (starting with a Random Address READ)
Sequential READ
Sequential READs can be initiated as either a current
address READ or random access READ. The first word is
transmitted as with the other byte read modes (current
address byte READ or random address byte READ);
however, the master now responds with an ACKnowledge,
indicating that it requires additional data from the
S42xxx. The S42xxx continues to output data for each
ACKnowledge received. The master terminates the sequential READ operation by not responding with an
ACKnowledge, and issues a STOP conditions.
During a sequential read operation, the internal address
counter is automatically incremented with each acknowledge signal. For read operations, all address bits are
incremented, allowing the entire array to be read using a
single read command. After a count of the last memory
address, the address counter will ‘roll-over’ and the
memory will continue to output data. See Figure 14 for the
address, acknowledge and data transfer sequence.
D7D6D5D4D3D2D1D
0
D7D6D5D4D3D2D1D
0
A7A6A5A4A3A2A1A
0
Shading Denotes
42xxx
SDA Output Active
S
T
A
R
T
Word Address
* S4261/S42WD61 only
S
T
O
P
A
C
K
Acknowledges from 42xxx
Slave AddressSlave Address
Device
Type
Address
Read/Write
0= Write
Device
Type
Address
A10,A9,A8
A10,A9,A80
SDA Bus
Activity
S
T
A
R
T
Read/Write
1= Read
A9R
W
A
10
Acknowledge from
Master Receiver
A
C
K
A
C
K
A
C
K
Master sends Read
request to Slave
Master Writes Word
Address to Slave
Master Requests
Data from Slave
Slave sends
Data to Master
Slave Transmitter
to
Master Receiver
Slave Transmitter
to
Master Receiver
Master Transmitter
to
Slave Receiver
1010 1010 10
Slave sends
Data to Master
*
A
10
*
A
9
R
W
*
A
8
A
8
Lack of ACK (low)
determines last
data byte to be read
1
Lack of
Acknowledge from
Master Receiver
Slave Transmitter
to
Master Receiver
Master Transmitter
to
Slave Receiver
Master Transmitter
to
Slave Receiver
Master Transmitter
to
Slave Receiver
Slave Transmitter
to
Master Receiver
Slave Transmitter
to
Master Receiver
Last Data Byte
First Data Byte
2025 ILL14.1
Page 13
S4242/S42WD42/S4261/S42WD61
13
2025 6.0 4/17/00
Watchdog Timer Operation
The S42WD42/S42WD61 has a watchdog timer with a
nominal timeout period of 1.6 seconds. Whenever the
watchdog times out it will generate a reset output on both
RESET# and RESET. The watchdog timer will reset to t
0
whenever the S42WD42/S42WD61 issues an ACKnowledge. Therefore, the host system will need to issue a start
condition, followed by a valid address and command. It
can be a normal command as in the sequence of reading
or writing to the memory, or it can be a dummy command
issued solely for the purpose of resetting the watchdog
timer. Refer to Figure 17 for detailed sequence of operations.
The watchdog timer will be held in the reset state during
power-on while VCC is less than V
TRIP
. Once VCC exceeds
FIGURE 17. SEQUENCE ONE
FIGURE 18. SEQUENCE TWO
V
TRIP
, the watchdog will continue to be held in a reset state
for the duration of t
PURST
. After t
PURST
, the timer will be
released and begin counting.
If either reset input is asserted the watchdog timer will be
reset and remain in the reset condition until either t
PURST
has expired or the reset input is released, whichever is
longer.
If the watchdog times out and no action is taken by the
host, the S42xxx will drive the reset outputs active for the
duration of t
PURST
at which point it will release the outputs
and begin the watchdog timer again. Refer to Figure 18 for
detailed sequence of operations.
S
T
A
R
T
1
0x10xx
A
C
K
S
T
O
P
R
W
S
T
A
R
T
1
0x10xx
A
C
K
S
T
O
P
R
W
SCL and SDA Idle
ACK response from S42xxx
Resets The Watchdog Timer
t < 1.6sec
S
T
A
R
T
1
0x10xx
S
T
O
P
R
W
SCL and SDA Idle
t > 1.6sec
A
C
K
t0 t0
t0
tPURST
2025 T fig17 2.0
RESET#
2025 T fig18 2.0
RESET#
S
T
A
R
T
1
0x10xx
A
C
K
S
T
O
P
R
W
A
C
K
SCL and SDA Idle
S
T
A
R
T
1
0x10xx
S
T
O
P
R
W
SCL and SDA Idle
t > 1.6sec
Watchdog Timer t0
t0
t > 1.6sec
tPURST
t0
No Affect On tPURST
Page 14
14
S4242/S42WD42/S4261/S42WD61
2025 6.0 4/17/00
.228 (5.80)
.244 (6.20)
.016 (.40)
.035 (.90)
.020 (.50)
.010 (.25)
x45°
.0192 (.49)
.0138 (.35)
.061 (1.75)
.053 (1.35)
.0098 (.25)
.004 (.127)
.05 (1.27) TYP.
.275 (6.99) TYP.
.030 (.762) TYP.
8 Places
.050 (1.27) TYP.
.050 (1.270) TYP.
8 Places
.157 (4.00)
.150 (3.80)
.196 (5.00)
1
.189 (4.80)
FOOTPRINT
8pn JEDEC SOIC ILL.2
8 Pin SOIC (Type S) Package JEDEC (150 mil body width)
8 Pin PDIP (Type P) Package
.375
(9.525)
PIN 1 INDICATOR
.015 (.381) Min.
.130 (3.302)
.100 (2.54)
TYP.
.018 (.457)
TYP.
.060 ± .005
(1.524) ± .127
TYP.
.130 (3.302)
SEATING PLANE
.070 (1.778)
.0375 (0.952)
.300 (7.620)
5°-7°TYP.
(4 PLCS)
.350 (8.89)
.009 ± .002
(.229 ± .051)
0°-15°
.250
(6.350)
8pn PDIP/P ILL.3
Page 15
S4242/S42WD42/S4261/S42WD61
15
2025 6.0 4/17/00
ORDERING INFORMATION
P = PDIP
S = SOIC
Package
S42
xxx
P
A
Base Part Number
Suffix
42 = 4k Bits
61 = 16k Bits
WD42 = 4k, Watchdog timer
WD61 = 16k, Watchdog timer
V
TRIP
A = 4.5V
B = 4.75V
2.7 = 2.7V
Blank = 4.5V
Prefix
Page 16
16
S4242/S42WD42/S4261/S42WD61
2025 6.0 4/17/00
NOTICE
SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve
design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described
herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent
infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon
a user’s specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc.
shall not be liable for any damages arising as a result of any error or omission.
SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety
or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written
assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and
(c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances.
I2C is a trademark of Philips Corporation.
© Copyright 2000 SUMMIT Microelectronics, Inc.
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