Datasheet S3C921F, S3P921F Datasheet (Samsung)

S3C921F/P921F PRODUCT OVERVIEW

1PRODUCT OVERVIEW

SAM88RCRI PRODUCT FAMILY

Samsung's SAM88RCRI family of 8-bit single-chip CMOS microcontrollers offer fast and efficient CPU, a wide
range of integrated peripherals, and supports OTP device.

A dual address/data bus architecture and bit- or nibble-configurable I/O ports provide a flexible programming
environment for applications with varied memory and I/O requirements. Timer/counters with selectable operating
modes are included to support real-time operations.

S3C921F/P921F MICROCONTROLLER

The S3C921F can be used for dedicated control functions in a variety of applications, and is especially designed
for application with voice synthesizer or etc.

The S3C921F/P921F single-chip 8-bit microcontroller is fabricated using an advanced CMOS process. It is built
around the powerful SAM88RCRI CPU core.

Stop and Idle power-down modes were implemented to reduce power consumption. To increase on-chip register
space, the size of the internal register file was logically expanded. The S3C921F/P921F has 64 Kbytes of
program ROM and 192 Kbytes of data ROM on-chip (S3C921F), and 720 bytes of RAM including 16 bytes of
working register and 128 bytes of LCD display RAM.

Using the SAM88RCRI design approach, the following peripherals were integrated with the SAM88RCRI core:
— Four configurable I/O ports including ports shared with segment/common drive outputs

— 8-bit programmable pins for external interrupts
— One 8-bit basic timer for oscillation stabilization and watch-dog functions
— One 8-bit and one 16-bit timer/counter with selectable operating modes
— Watch timer for real time
— Two PWM modules for direct speaker drive

OTP

The S3C921F microcontroller is also available in OTP (One Time Programmable) version. S3P921F
microcontroller has an on-chip 256 Kbyte one-time-programmable EPROM instead of masked ROM. The
S3P921F is comparable to S3C921F, both in function and in pin configuration.

1-1

PRODUCT OVERVIEW S3C921F/P921F

FEATURES

CPU

• SAM88RCRI CPU core

Memory

• 64K × 8 bits program memory(ROM)

• 192K × 8 bits data memory(ROM)

• 592 × 8 bits data memory(RAM)
(Excluding LCD data memory)

Instruction Set

• 41 instructions

• Idle and Stop instructions added for power-down
modes

32 I/O Pins

• I/O: 8 pins

• I/O: 24 pins(Sharing with segment drive outputs)

Interrupts

• 15 interrupt source and 1 vector

• One interrupt level

8-Bit Basic Timer

• Watchdog timer function

• 3 kinds of clock source

One 8-Bit Timer/Counter 0

• Programmable interval timer

• External event counter function

• PWM and Capture function

LCD Controller/Driver

• 64 segments and 16 common terminals

• 8, 12, and 16 common selectable

• Internal resistor circuit for LCD bias

Two PWM Modules

• 5/6/7/8-bits PWM Selectable

• Direct speaker drive

• 2-bit extendable

Voltage Level Detector

• Programmable low voltage detector

• Two criteria voltage(2.7 V, 4.0 V)

Two Power-Down Modes

• Idle: only CPU clock stops

• Stop: selected system clock and CPU clock stop

Oscillation Sources

• Crystal, ceramic, or RC for main clock

• Main clock frequency: 0.4 MHz - 8MHz

• 32.768 kHz crystal oscillation circuit for
sub clock

Instruction Execution Times

• 500nS at 8 MHz fx(minimum)

Operating Voltage Range

• 2.4 V to 5.5 V at 0.4 - 3MHz

• 2.7 V to 5.5 V at 0.4 - 4MHz

One 16-bit Timer/Counter 1

• One 16-bit Timer/Counter mode

• Two 8-bit Timer/Counters A/B mode

Watch Timer

• Interval time: 3.91mS, 0.25S, 0.5S, and 1S
at 32.768 kHz

• 2/4/8/16 kHz Selectable buzzer output

1-2

• 4.5 V to 5.5 V at 0.4 - 8MHz

Operating Temperature Range

• -40 °C to +85 °C

Package Type

• 100-pin QFP Package

S3C921F/P921F PRODUCT OVERVIEW

BLOCK DIAGRAM

RC/X-tal

XTOUT

P1.2/BUZ

P1.3/T0CK

P1.4/T0

P1.5/T1CK

P1.6/TA
P1.7/TB

PWM0
PWM1

OUT

X

XTIN

XIN

RESET

TEST

Watch

Timer 0

Timer 1

Timer A

Timer B

Module

Basic
Timer

Main
OSC

Sub

OSC

Timer

PWM

P4.0/SEG48-

P4.7/SEG55

Port 4 Port 3

Internal Bus

Port I/O and Interrupt

Control

SAM88RCRI CPU

64-Kbyte ROM

P3.0/SEG56-

P3.7/SEG63

592-Byte

Register File

Port 2

Port 1

LCD Driver/

Controller

P2.0/COM8­P2.3/COM11

P2.4/COM12­P2.7/COM15

P1.0/INT
P1.1/INT
P1.2/BUZ/INT
P1.3/T0CK/INT
P1.4/T0/INT
P1.5/T1CK/INT
P1.6/TA/INT
P1.7/TB/INT

VLC1
COM0-COM7

COM8/P2.0­COM15/P2.7

SEG0-SEG47
SEG48/P4.0-

SEG55/P4.7
SEG56/P3.0­SEG63/P3.7

Voltage

Level

Detector

192-Kbyte

Data

ROM

Figure 1-1. Block Diagram

1-3

PRODUCT OVERVIEW S3C921F/P921F

PIN ASSIGNMENTS

SEG21

SEG20

SEG19

SEG18

SEG17

SEG16

SEG15

SEG14

SEG13

SEG12

SEG11

SEG10

SEG9

SEG8

SEG7

SEG6

SEG5

SEG4

SEG3

SEG2

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

SEG1

SEG0
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0

VLC1

RC/X-tal

PWM0
PWM1

VDD

VSS

XOUT

XIN

TEST

XTIN

XTOUT

RESET

P1.0/INT
P1.1/INT

P1.2/BUZ/INT

P1.3/T0CK/INT

P1.4/T0/INT

P1.5/T1CK/INT

P1.6/TA/INT
P1.7/TB/INT

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

31

(SDAT)
(SCLK)

33

32

34

S3C921F

(100-QFP-1420C)

39

38

37

36

35

40

41

42

43

44

45

46

47

48

49

50

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
P4.0/SEG48
P4.1/SEG49
P4.2/SEG50
P4.3/SEG51

1-4

P3.1/SEG57

P3.2/SEG58

P3.3/SEG59

P3.4/SEG60

P3.5/SEG61

P3.6/SEG62

P3.7/SEG63

P2.0/COM8

P2.1/COM9

P2.2/COM10

P2.3/COM11

P2.4/COM12

P2.5/COM13

P2.6/COM14

P2.7/COM15

Figure 1-2. Pin Assignment (100 Pin)

P4.5/SEG53

P4.6/SEG54

P4.7/SEG55

P3.0/SEG56

P4.4/SEG52

S3C921F/P921F PRODUCT OVERVIEW

Table 1-1. Pin Descriptions

Pin Names Pin

P1.0, P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7

P2.0 - P2.7

P3.0 - P3.7

P4.0 - P4.7

PWM0
PWM1

V

LC1

INT

BUZ
T0CK
T0
T1CK
TA
TB
COM0-COM7
COM8-COM15
SEG0-SEG47

SEG48-SEG55
SEG56-SEG63

Type

I/O

I/O

I/O

I/O

O

I

I/O

I/O
I/O
I/O
I/O
I/O
I/O

O

I/O

O

I/O

Pin Description Circuit

I/O port with bit-programmable pins;
Schmitt trigger input or push-pull, open­drain output and software assignable pull­ups;
Alternately used for external interrupt
input(noise filters, interrupt enable and
pending control).

I/O port with nibble-programmable pins;
Schmitt trigger input or push-pull, open-

Number

E-2 23, 24

H-9 38 - 31 COM8-

Pin

Numbers

25
26
27
28
29
30

Share

Pins

INT

BUZ/INT

T0CK/INT

T0/INT

T1CK/INT

TA/INT
TB/INT

COM15
drain output and software assignable pull­ups.

I/O port with bit-programmable pins;
Schmitt trigger input or push-pull, open-

H-8 46 - 39 SEG56-

SEG63
drain output and software assignable pull­ups.

I/O port with nibble-programmable pins;
Schmitt trigger input or push-pull output

H-10 54 - 47 SEG48-

SEG55
and software assignable pull-ups.

PWM output pins. C 13

–

14

LCD power supply pin. – 11 –
External interrupt input pins. E-2 23, 24

25
26
27
28
29
30

P1.0, P1.1

P1.2/BUZ

P1.3/T0CK

P1.4/T0

P1.5/T1CK

P1.6/TA

P1.7/TB
Output pin for buzzer signal. E-2 25 P1.2/INT
Timer 0 clock input. E-2 26 P1.3/INT
Capture input or interval/PWM output. E-2 27 P1.4/INT
Timer 1/A external clock input. E-2 28 P1.5
Timer 1/A clock output. E-2 29 P1.6
Timer B clock output. E-2 30 P1.7
LCD common data outputs. H-4 10 - 3 –
LCD common data outputs. H-9 38 - 31 P2.0 - P2.7
LCD segment data outputs. H-5 2-1

–

100-55

LCD segment data outputs. H-10

H-8

54 - 47
46 - 39

P4.0 - P4.7
P3.0 - P3.7

1-5

PRODUCT OVERVIEW S3C921F/P921F

Table 1-1. Pin Descriptions (Continued)

Pin Names Pin

Pin Description Circuit

Type

RESET

XTIN,XT
XIN,X

OUT

OUT

I System reset pin B 22 –
– Crystal oscillator pins for sub clock. – 20, 21
– Main oscillator pins. – 18, 17

RC/X-tal – Main oscillator type selection pin

("High" for RC osc. and "Low" for X-tal)

TEST I Test input: it must be connected to V
VDD,V

SS

– Power input pins – 15, 16

SS

Number

– 12

– 19

Pin

Numbers

Share

Pins

–
–
–

–
–

1-6

S3C921F/P921F PRODUCT OVERVIEW

PIN CIRCUIT DIAGRAMS

VDD

P-Channel

In

N-Channel

Figure 1-3. Pin Circuit Type A

VDD

Pull-Up
Resistor

P-Channel

In

Pull-Up
Resistor
Enable

Data

Output

Disable

VDD

Pull-Up
Resistor

In

Schmitt Trigger

Figure 1-4. Pin Circuit Type B

VDD

P-Channel

Out

N-Channel

Schmitt Trigger

Figure 1-5. Pin Circuit Type A-3

Figure 1-6. Pin Circuit Type C

1-7

PRODUCT OVERVIEW S3C921F/P921F

VDD

Pull-up

VDD

Open-Drain

P-CH

Resistor

Resistor
Enable

Data

Output

Disable

External

Interrupt

Input

Noise

Filter

Figure 1-7. Pin Circuit Type E-2

Resistor

Enable

I/O

N-CH

VDD

Pull-up

Resistor

P-Channel

1-8

Data

Output

Disable

Circuit

Type C

Figure 1-8. Pin Circuit Type E-3

I/O

S3C921F/P921F PRODUCT OVERVIEW

VLC1

VLC2

COM Data

VLC5

VSS

VLC1

VLC3

Out

Figure 1-9. Pin Circuit Type H-4

SEG Data

VLC4

VSS

Out

Figure 1-10. Pin Circuit Type H-5

1-9

PRODUCT OVERVIEW S3C921F/P921F

VLC1

VLC2

COM

Output

Disable

VLC5

VSS

VLC1

VLC3

SEG

Output

Disable

VLC4

VSS

Figure 1-11. Pin Circuit Type H-6

Out

1-10

Figure 1-12. Pin Circuit Type H-7

S3C921F/P921F PRODUCT OVERVIEW

VDD

Pull-up

VDD

Open-Drain

P-CH

Resistor

Resistor
Enable

Data

Output Disable 1

Output Disable 2

Open-Drain

N-CH

SEG

Circuit

Type H-7

Figure 1-13. Pin Circuit Type H-8

VDD

P-CH

I/O

VDD

Pull-up
Resistor

Resistor
Enable

Data

Output Disable 1

Output Disable 2

N-CH

COM

Circuit

Type H-6

Figure 1-14. Pin Circuit Type H-9

I/O

1-11

PRODUCT OVERVIEW S3C921F/P921F

VDD

Pull-up

VDD

P-CH

Resistor

Resistor
Enable

Data

Output Disable 1

Output Disable 2

N-CH

SEG

Circuit

Type H-7

Figure 1-15. Pin Circuit Type H-10

I/O

1-12

S3C921F/P921F ELECTRICAL DATA

17 ELECTRICAL DATA

OVERVIEW

In this chapter, S3C921F electrical characteristics are presented in tables and graphs. The information is
arranged in the following order:

— Absolute maximum ratings
— D.C. electrical characteristics
— Data retention supply voltage in Stop mode
— Stop mode release timing when initiated by an external interrupt
— Stop mode release timing when initiated by a Reset
— I/O capacitance
— A.C. electrical characteristics
— Input timing for external interrupts (port 1)

— Input timing for RESET
— Oscillation characteristics
— Oscillation stabilization time

17-1

ELECTRICAL DATA S3C921F/P921F

Table 17-1. Absolute Maximum Ratings

(TA = 25°C)

Parameter Symbol Conditions Rating Unit

Supply voltage V
Input voltage V
Output voltage V
Output current

I

DD

IN

OH

Ports 1, 2, 3 and 4 – 0.3 to VDD + 0.3 V

O

All output pins – 0.3 to VDD + 0.3 V
One I/O pin active – 18 mA

– – 0.3 to + 6.5 V

High

All I/O pins active – 60

Output current

I

OL

One I/O pin active + 30 (Peak Value) mA

Low

Total pin current for ports 1-4 + 100 (Peak Value)

Operating

T

A

– – 40 to + 85

°

C

temperature
Storage

T

STG

– – 65 to + 150

°

C

temperature

17-2

S3C921F/P921F ELECTRICAL DATA

Table 17-2. D.C. Electrical Characteristics

(T

= – 40°C to + 85°C, V

A

= 2.4 V to 5.5 V)

DD

Parameter Symbol Conditions Min Typ Max Unit

Operating Voltage V

DD

fx = 8MHz

4.5 – 5.5 V

(Instruction clock = 2.0MHz)
fx = 4MHz

2.7 – 5.5

(Instruction clock = 1.0MHz)
fx = 3MHz

2.4 – 5.5

(Instruction clock = 0.75MHz)

Input High

V

IH1

Ports 1-4 0.8 V

DD

– V

DD

V

voltage

Input Low voltage V

Output High
voltage

V

IH2

V

IH3

IL1

V

IL2

V

IL3

V

OH

RESET

XIN, X

OUT

and XT

IN

Ports 1-4 – – 0.2 V

RESET

XIN, X
V

DD

and XT

OUT

= 4.5 to 5.5 V;

IN

IOH = –1 mA

0.7 V

DD

V

– 0.1 V

DD

V

DD
DD

0.2 V

0.1

V

– 1.0 – – V

DD

DD
DD

V

Ports 1-4

Output Low
voltage

V

OL

V

= 4.5 to 5.5 V;

DD

– – 2.0 V
IOL= 10 mA
Ports 1-4
V

= 2.4 to 5.5 V;

DD

0.4

IOL= 1.6 mA

Input High
leakage current

Input Low
leakage current

Output High
leakage current

Output Low
leakage current

I

LIH1

I

LIH2

I

LIL1

I

LIL2

I

LOH

I

LOL

VI = VDD;
All input pins except those

specified below for I

LIH2

VI = VDD;
X

X

,

IN

V

= 0 V; All input pins except

I

RESET, X
V

= 0 V;

I

X

X

,

IN

V

= V

O

OUT

OUT

DD

XT

,

IN

X

,

IN

XT

,

OUT

IN

XT

,

IN

All output pins
V

= 0 V

O

All output pins

– – 3 µA

20

– – –3

–20

– – 3

– – –3

17-3

ELECTRICAL DATA S3C921F/P921F

Table 17-2. D.C. Electrical Characteristics (Continued)

(T

= – 40°C to + 85°C, V

A

Parameter Symbol Conditions Min Typ Max

Pull-Up Resistor R

= 2.4 V to 5.5 V)

DD

V

L1

= 0 V; V

I

DD

= 5V

25 50 75

Unit

kΩ

Ports 1-4
V

= 3V 50 100 150

DD

LCD Voltage
Dividing Resistor

R

R

R

L2

LCD1

LCD2

V

= 0 V; V

I

V

= 3V 250 500 750

DD

= 5V; RESET

DD

TA = + 25 °C
When LCON.1 = "0"

TA = + 25 °C

150 250 350

38 54 70

19 27 35

kΩ

When LCON.1 = "1"

V



-COMi

LCD

V

DC

–15 uA per common pin – – 120 mV

Voltage Drop
(i = 0-15)

V



-SEGx

LCD

V

–15 uA per common pin – – 120

DS

Voltage Drop
(x = 0–63)

Middle Output
Voltage

(note)

V

LC2

V

=

DD

2.4 V to 5.5 V,

0.8VDD–0.2 0.8V

0.8VDD+ 0.2 V

DD

1/5 bias
LCD clock = 0Hz,

V

= V

LC1

V

LC3

V

LC4

V

LC5

DD

0.6VDD–0.2 0.6V

0.4VDD–0.2 0.4V

0.2VDD–0.2 0.2V

DD
DD
DD

0.6VDD+ 0.2

0.4VDD+ 0.2

0.2VDD+ 0.2

NOTE: It is middle output voltage when LCD controller/driver is 1/16 duty and 1/5 bias.

17-4

S3C921F/P921F ELECTRICAL DATA

Table 17-2. D.C. Electrical Characteristics (Continued)

(TA = – 40°C to + 85°C, V

= 2.4 V to 5.5 V)

DD

Parameter Symbol Conditions Min Typ Max

Supply current

(1)

I

DD1

(2)

V

= 5 V ± 10%

DD

8 MHz – 5.0 10.0 mA

Crystal oscillator
C1 = C2 = 22pF 4.19 MHz 3.0 6.4

4.0 MHz 1.4 2.8
8 MHz – 1.0 2.0

4.19 MHz 0.8 1.6

I

DD2

V

= 3 V ± 10%

DD

(2)

Idle mode
V

= 5 V ± 10%

DD

Crystal oscillator
C1 = C2 = 22pF

4 MHz 0.3 0.6

– 15 30 µA

I

DD3

V

= 3 V ± 10%

DD

(3)

VDD = 3 V ± 10%,
32 kHz crystal oscillator

(3)

I

DD4

Idle mode;
VDD = 3 V ± 10%,

– 6 15

32 kHz crystal oscillator

I

DD5

Stop mode;

OSCCON.2="1" – 0.3 3

VDD=5 V ± 10%,
VDD=3 V ± 10%,

0.1 1

Unit

NOTES:

1. Supply current does not include current drawn through internal pull-up resistors, PWM, or external output current loads.

2. I

3. I

4. Every values in this table is measured when bits 4-3 of the system clock control register (CLKCON.4-.3) is set to 11B.

DD1
DD3

and I
and I

include power consumption for sub clock oscillation.

DD2

are current when main clock oscillation stops and the sub clock is used.

DD4

17-5

ELECTRICAL DATA S3C921F/P921F

Table 17-3. Data Retention Supply Voltage in Stop Mode

(TA = – 40 °C to + 85 °C)

Parameter Symbol Conditions Min Typ Max Unit

Data retention supply

V

DDDR

–

2.2 – 5.5 V

voltage
Data retention supply

current
Oscillator stabilization

wait time

NOTES:

1. fx is the main oscillator frequency.

2. The duration of the oscillation stabilization time (t

the setting in the basic timer control register, BTCON.

I

DDDR

t

WAIT

Stop mode,
V

=2.2 V

DDDR

Released by RESET

Released by interrupt –

) when it is released by an interrupt is determined by

WAIT

– – 1 µA

–

216/fx

(2)

(1)

– ms

–

Idle Mode

(Basic Timer Active)

~

VDD

Interrupt

Request

~

~

~

Execution of

STOP Instruction

Stop Mode

Data Retention Mode

VDDDR

Normal
Operating Mode

0.8 VDD

tWAIT

Figure 17-1. Stop Mode Release Timing When Initiated by an External Interrupt

17-6

S3C921F/P921F ELECTRICAL DATA

VDD

RESET

~

~

~

~

Execution of

STOP Instrction

Stop Mode

Data Retention Mode

VDDDR

RESET

Occurs

tSRL

0.2 VDD

Oscillation

Stabilization

TIme

0.7 VDD

tWAIT

Figure 17-2. Stop Mode Release Timing When Initiated by a RESETRESET

Normal
Operating Mode

17-7

ELECTRICAL DATA S3C921F/P921F

Table 17-4. Input/Output Capacitance

(T

= – 40°C to + 85°C, V

A

DD

= 0 V)

Parameter Symbol Conditions Min Typ Max Unit

Input
capacitance

Output

C

C

OUT

IN

f = 1 MHz; unmeasured pins

are connected to V

SS

– – 10 pF

capacitance
I/O capacitance C

IO

Table 17-5. A.C. Electrical Characteristics

(T

= – 40°C to + 85°C)

A

Parameter Symbol Conditions Min Typ Max Unit

Interrupt input,
High, Low width

RESET input Low
width

t

INTH

t

INTL

t

RSL

,

P1.0 – P1.7
V

= 5 V

DD

Input
VDD = 5 V

150 200 – ns

10 – –

µs

External
Interrupt

tINTHtINTL

0.8 VDD

0.2 VDD

NOTE: The unit tCPU means one CPU clock period.

Figure 17-3. Input Timing for External Interrupts (P1.0–P1.7)

tRSL

RESET

0.2 VDD

17-8

Figure 17-4. Input Timing for RESETRESET

S3C921F/P921F ELECTRICAL DATA

Table 17-6. Main Oscillation Characteristics

(TA = – 40°C + 85°C)

Oscillator Clock

Configuration

Ceramic

XIN

XOUT

Oscillator

C1 C2

Crystal

XIN

XOUT

Oscillator

C1 C2

Parameter Test Condition Min Typ Max Units

Oscillation frequency

Stabilization time

(2)

Oscillation frequency

Stabilization time

(2)

(1)

RC/X-tal = 0 V 0.4 – 8.0 MHz

Stabilization occurs

– – 4 ms

when VDD is equal to
the minimum

oscillator voltage
range.

(1)

RC/X-tal = 0 V 0.4 – 8.0 MHz

VDD = 4.5 V to 5.5 V – – 10 ms

VDD = 1.8 V to 5.5 V – – 30

External

XIN XOUT

XIN input frequency

(1)

RC/X-tal = 0 V 0.4 – 8.0 MHz

Clock

XIN input high and low

– 62.0 – 1250 ns

level width (tXH, tXL)

RC

XIN XOUT

Frequency

Oscillator

R

NOTES:

1. Oscillation frequency and X

2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is
terminated.

input frequency data are for oscillator characteristics only.

IN

(1)

VDD = 2.7 V to 5.5 V
RC/X-tal = V

DD

VDD = 2.4 V to 5.5 V
RC/X-tal = V

DD

– 4 – MHz

– 2 –

17-9

ELECTRICAL DATA S3C921F/P921F

1/fx

tXtXL

XIN

VDD-0.1 V

0.1 V

Figure 17-5. Clock Timing Measurement at X

IN

17-10

S3C921F/P921F ELECTRICAL DATA

Table 17-7. Sub Oscillation Characteristics

(TA = – 40°C + 85°C, VDD = 2.4 V to 5.5 V)

Oscillator Clock

Parameter Test Condition Min Typ Max Units

Configuration

Crystal

XTIN

XTOUT

Oscillation frequency

(1)

– 32 32.768 35 kHz

Oscillator

C1 C2

Stabilization time

(2)

VDD = 4.5 V to 5.5 V – 1.0 2 s
VDD = 2.4 V to 4.5 V – – 10

External

XTINXT

OUT

XTIN input frequency

(1)

– 32 – 100 kHz

Clock

XTIN input high and low
level width (t

NOTES:

1. Oscillation frequency and XT

2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs .

input frequency data are for oscillator characteristics only.

IN

XTL

, t

XTH

)

– 5 – 15 us

XTIN

1/fxt

tXTHtXTL

VDD-0.1 V

0.1 V

Figure 17-6. Clock Timing Measurement at XT

IN

17-11

ELECTRICAL DATA S3C921F/P921F

Table 17-8. PWM0/PWM1 Electrical Characteristics

( TA = – 40 °C + 85 °C)

Parameter Symbol Conditions Min Typ Max Unit

PWM Output

V

PWM0

VDD = 2.4 V I

= –8mA VDD – 0.5 – – V

PWMh0

Voltage

I

= 15 mA – 0.5

PWMl0

V

PWM1

V

PWM2

V

PWM3

VDD = 2.4 V I

VDD = 2.4 V I

VDD = 2.4 V I

= –12mA VDD – 0.5 –

PWMh1

I

= 20 mA – 0.5

PWMl1

= –16mA VDD – 0.5 –

PWMh2

I

= 25 mA – 0.5

PWMl2

= –20mA VDD – 0.5 –

PWMh3

I

= 30 mA – 0.5

PWMl3

Table 17-9. VLD Electrical Characteristics

(T

= – 40 °C to + 85 °C, VDD = 2.4 V to 5.5 V)

A

Parameter Symbol Conditions Min Typ Max Unit

VLD Voltage V

VLD

BLDCON.4 = 0B 2.4 2.7 3.0 V
BLDCON.4 = 1B 3.7 4.0 4.3

VLD Circuit Response

TB fw = 32.768 kHz – – 1.0 mS

Time
VLD Operating Current IBL – 50 100 uA

17-12

S3C921F/P921F ELECTRICAL DATA

fx
(Main oscillation

Clock

frequency)

8.32 kHz

2 MHz

1.0 MHz
750 kHz

1 2 6

2.4 2.7
Supply Voltage (V)

Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16)

5.5

4.5

Figure 17-7. Operating Voltage Range

8 MHz
4 MHz

3 MHz

400 kHz

17-13

S3C921F/P921F MECHANICAL DATA

18 MECHANICAL DATA

OVERVIEW

The S3C921F microcontroller is currently available in a 100-pin QFP package.

23.90 ± 0.30

17.90 ± 0.30

14.00 ± 0.20

#100

0.65

#1

20.00 ± 0.20

100-QFP-1420C

+ 0.10

- 0.05

0.30

0.15 MAX

(0.58)

0-8

+ 0.10

- 0.05

0.15

0.10 MAX

0.80 ± 0.20

0.05 MIN

2.65

± 0.10

NOTE: Dimensions are in millimeters.

Figure 19-1. 100-QFP-1420C Package Dimensions

3.00 MAX

0.80 ± 0.20

18-1

S3C921F/P921F S3P921F OTP

19 S3P921F OTP

OVERVIEW

The S3P921F single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C921F

microcontroller. It has an on-chip OTP ROM instead of a masked ROM. The EPROM is accessed by serial data
format.

The S3P921F is fully compatible with the S3C921F, both in function in D.C. electrical characteristics and in pin
configuration. Because of its simple programming requirements, the S3P921F is ideal as an evaluation chip for
the S3C921F.

19-1

S3P921F OTP S3C921F/P921F

SEG21

SEG20

SEG19

SEG18

SEG17

SEG16

SEG15

SEG14

SEG13

SEG12

SEG11

SEG10

SEG9

SEG8

SEG7

SEG6

SEG5

SEG4

SEG3

SEG2

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

SEG1

SEG0
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0

VLC1

RC/X-tal

SDAT/PWM0
SCLK/PWM1

VDD/VDD

VSS/VSS

XOUT

XIN

VPP/TEST

XTIN

XTOUT

RESETRESET/RESET

P1.0/INT
P1.1/INT

P1.2/BUZ/INT

P1.3/T0CK/INT

P1.4/T0/INT

P1.5/T1CK/INT

P1.6/TA/INT
P1.7/TB/INT

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

31

32

33

34

S3P921F

(100-QFP-1420C)

39

38

37

36

35

40

41

42

43

44

45

46

47

48

49

50

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
P4.0/SEG48
P4.1/SEG49
P4.2/SEG50
P4.3/SEG51

P3.7/SEG63

P2.0/COM8

P2.1/COM9

P2.2/COM10

P2.3/COM11

P2.4/COM12

P2.5/COM13

P2.6/COM14

P2.7/COM15

Figure 19-1. S3P921F Pin Assignments (100-Pin QFP Package)

19-2

P3.3/SEG59

P3.4/SEG60

P3.5/SEG61

P3.6/SEG62

P4.7/SEG55

P3.0/SEG56

P3.1/SEG57

P3.2/SEG58

P4.4/SEG52

P4.5/SEG53

P4.6/SEG54

S3C921F/P921F S3P921F OTP

Table 19-1. Descriptions of Pins Used to Read/Write the EPROM

Main Chip During Programming

Pin Name Pin Name Pin No. I/O Function

PWM0 SDAT 13 I/O Serial data pin. Output port when reading and

input port when writing. Can be assigned as a
Input/push-pull output port.

PWM1 SCLK 14 I Serial clock pin. Input only pin.

TEST

V

PP

19 I Power supply pin for EPROM cell writing

(indicates that OTP enters into the writing mode).
When 12.5 V is applied, OTP is in writing mode
and when 5 V is applied, OTP is in reading mode.
(Option)

RESET RESET

VDD/V

SS

VDD/V

SS

22 I Chip Initialization

15/16 –

Logic power supply pin. V

should be tied to

DD

+5 V during programming.

Table 19-2. Comparison of S3P921F and S3C921F Features

Characteristic S3P921F S3C921F

Program Memory 64-Kbyte EPROM 64-Kbyte mask ROM
Data Memory 192-Kbyte EPROM 192-Kbyte mask ROM
Operating Voltage (VDD)

OTP Programming Mode

2.4 V to 5.5 V 2.4 V to 5.5 V
VDD = 5 V, V

(EA) = 12.5 V

PP

Pin Configuration 100 QFP 100 QFP
EPROM Programmability User Program 1 time Programmed at the factory

OPERATING MODE CHARACTERISTICS

When 12.5 V is supplied to the VPP (EA) pin of the S3P921F, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in

Table 21-3 below.

Table 19-3. Operating Mode Selection Criteria

VDD VPP

(EA)

REG/

MEMMEM

Address

(A17–A0)

R/W Mode

5 V 5 V 0 0000H 1 EPROM read

12.5 V 0 0000H 0 EPROM program

12.5 V 0 0000H 1 EPROM verify

12.5 V 1 0E3FH 0 EPROM read protection

NOTE: "0" means Low level; "1" means High level.

19-3

S3P921F OTP S3C921F/P921F

fx
(Main oscillation

Clock

frequency)

2 MHz

1.0 MHz
750 kHz

8.32 kHz
1 2 6

2.4 2.7
Supply Voltage (V)

Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16)

5.5

4.5

Figure 19-2. Operating Voltage Range

8 MHz
4 MHz

3 MHz

400 kHz

19-4