Datasheet S3C8639, S3C863A, S3P863A Datasheet (Samsung)

S3C8639/C863A/P863A PRODUCT OVERVIEW

1 PRODUCT OVERVIEW

SAM8 PRODUCT FAMILY

Samsung's SAM8 family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU with a wide
range of integrated peripherals, in various mask-programmable ROM sizes. Analog its major CPU features are:

— Efficient register-oriented architecture
— Selectable CPU clock sources
— Idle and Stop power-down mode release by interrupt
— Built-in basic timer with watchdog function

The sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more
interrupt sources and vectors. Fast interrupt processing (within a minimum of four CPU clocks) can be assigned
to specific interrupt levels.

S3C8639/C863A/P863A MICROCONTROLLERS

S3C8639/C863A/P863A single-chip 8-bit
microcontrollers are based on the powerful SAM8
CPU architecture. The internal register file is logically
expanded to increase the on-chip register space.
S3C8639/C863A/P863A contain 32/48 Kbytes of on­chip program ROM.

In line with Samsung's modular design approach, the
following peripherals are integrated with the SAM8
core:

— Four programmable I/O ports (total 27 pins)
— One 8-bit basic timer for oscillation stabilization

and watchdog functions

— One 8-bit general-purpose timer/counter with

selectable clock sources

— One interval timer

OTP

S3C8639/C863A microcontrollers are also available in OTP (One Time Programmable) version named,
S3P863A. S3P863A microcontroller has an on-chip 48-Kbyte one-time-programmable EPROM instead of
masked ROM. S3P863A is comparable to S3C8639/C863A, both in function and pin configuration except its
ROM size.

— One 12-bit counter with selectable clock sources,

including Hsync or Csync input
— PWM block with seven 8-bit PWM circuits
— Sync processor block (for Vsync and Hsync I/O,

Csync input, and Clamp signal output)
— DDC Multi-master and slave-only IIC-Bus
— 4-channel A/D converter (8-bit resolution)

S3C8639/C863A/P863A are a versatile
microcontrollers which are ideal for use in multi-sync
monitors or in general-purpose applications that
require sophisticated timer/counter, PWM, sync
signal processing, A/D converter, and multi-master
IIC-bus support with DDC. They are available in a
42-pin SDIP or a 44-pin QFP package.

1-1

PRODUCT OVERVIEW S3C8639/C863A/P863A

FEATURES

CPU

• SAM88RC CPU core

Memory

• S3C8639: 32-Kbyte internal program memory

(ROM)
S3C863A: 48-Kbyte internal program memory
(ROM)

• S3C8639: 784-byte general-purpose

register area
S3C863A: 1040-byte general-purpose
register area

Instruction Set

• 78 instructions

• IDLE and STOP instructions added for

power-down modes

Instruction Execution Time

• Minimum 333 ns (with 12 MHz CPU clock)

Interrupts

• Ten interrupt sources/vectors

• Eight interrupt level

• Fast interrupt feature

General I/O

• Four I/O Ports (total 27pins)

8-Bit Basic Timer

• Programmable timer for oscillation stabilization

interval control or watchdog timer function

• Three selective internal clock frequencies

Low Voltage Reset (LVR)

• LVR level is 2.4 V ± 200 mV

Pulse Width Modulator (PWM)

• 8-bit PWM: 7-CH

(6-bit basic frame with 2-bit extension)

Sync-Processor Block

• Vsync-I, Hsync-I, Csync-I input and Vsync-O,

Hsync-O, Clamp-O output pins

• Programmable Pseudo sync signal generation

• Auto SOG detection

• Auto H-/V-sync polarity detection

• Composite sync detection

DDC Multi-Master IIC-Bus 1-Ch

• Serial Peripheral Interface

• Support for Display Data Channel

(DDC1/DDC2B/DDC2Bi/DDC2B+)

Slave Only IIC-Bus 1-Ch

• Serial Peripheral Interface

A/D Converter

• 4-channel; 8-bit resolution

Oscillator Frequency

• 8 MHz to 12 MHz crystal operation

• Internal Max. 12 MHz CPU clock

Operating Temperature Range

• – 40 °C to + 85 °C

Timer/Counters

• One 8-bit Timer/Counter with several clock

sources (Capture mode)

• One 12-bit Counter with H-/C-sync and several

clock sources

• One Interval Timer

1-2

Operating Voltage Range

• 3.0 V to 5.5 V

Package Types

• 42-pin SDIP, 44-pin QFP

S3C8639/C863A/P863A PRODUCT OVERVIEW

BLOCK DIAGRAM

X

X

OUT

PWM0

PWM6

Vsync-I
Hsync-I

Csync-I
Vsync-O
Hsync-O

Clamp-O

TM0CAP

P0.0-P0.7/INT0-INT2

RESET

Port 0

INT0-INT2

IN

Main

Osc

P2.0-P2.7

Port 2

V

DD1

V

SS1

TEST

Port 1

, V

, V

DD2

SS2

P1.0-P1.2

I/O Port and Interrupt

Control

8-Bit

PWM

(7-Ch)

Port 3

P3.0-P3.7

SAM8 CPU

Sync-

Processor

8-Bit

Counter

(Timer M0)

32/48-

Kbyte

ROM

784/1040-

Byte

Register File

ADC

Slave

Only

IIC-Bus

AD0-AD3

SCL1

SDA1

* S3C8639

- 32 Kbyte ROM

- 784 Byte RAM
* S3C863A

- 48 Kbyte ROM

- 1040 Byte RAM

12-Bit

Counter

(Timer M1)

Interval

Timer

(Timer M2)

Figure 1-1. Block Diagram

Multi-master IIC-Bus

and DDC1/2B/2Bi/2B+

SCL0 SDA0

1-3

PRODUCT OVERVIEW S3C8639/C863A/P863A

PIN ASSIGNMENTS

P3.7

P0.0/INT0
P0.1/INT1
P0.2/INT2

P0.4/TM0CAP

TEST (GND)

P0.3
P0.5

P0.6
P0.7

P1.0/SDA1

P1.1/SCL1

V

DD1

V

SS1

X

OUT

X

SDA0

SCL0

RESET

P1.2
P2.0/PWM0
P2.1/PWM1

1
2
3
4
5
6
7
8
9
10
11
12
13

IN

14
15
16
17
18
19
20
21

S3C8639

/C863A

(42-SDIP)

42

P3.6

41

P3.5

40

P3.4

39

P3.3/AD3

38

P3.2/AD2

37

P3.1/AD1

36

P3.0/AD0

35

V

34
33
32
31
30
29
28
27
26
25
24
23
22

DD2

V

SS2

P2.7/Csync-I (SOG)
Hsync-I
Vsync-I
Vsync-O
Hsync-O
Clamp-O
P2.6/PWM6
P2.5/PWM5
P2.4/PWM4
P2.3/PWM3
P2.2/PWM2

1-4

NOTE: The TEST pin must connect to VSS (GND) in the normal operation mode.

Figure 1-2. S3C8639/C863A 42-SDIP Pin Assignment

S3C8639/C863A/P863A PRODUCT OVERVIEW

P0.4/TM0CAP

P0.3

P0.2/INT2

P0.1/INT1

N.C.

P0.0/INT0

P3.7

P3.6

P3.5

P3.4

P3.3/AD3

4443424140393837363534
P0.5
P0.6
P0.7

P1.0/SDA1

P1.1/SCL1

DD1

V

V

SS1

OUT

X

X

TEST (GND)

SDA0

1
2
3
4
5
6
7
8

IN

9

S3C8639

/C863A

44-QFP

(Top View)

10
11

33
32
31
30
29
28
27
26
25
24
23

P3.2/AD2
P3.1/AD1
P3.0/AD0

DD2

V
V

SS2

P2.7/Csync-I (SOG)
Hsync-I
Vsync-I
Vsync-O
Hsync-O
Clamp-O

1213141516171819202122

SCL0

RESET

P1.2

N.C.

P2.0/PWM0

P2.1/PWM1

P2.2/PWM2

P2.3/PWM3

P2.4/PWM4

P2.5/PWM5

P2.6/PWM6

NOTE: The TEST pin must connect to VSS (GND) in the normal operation mode.

Figure 1-3. S3C8639/C863A 44-QFP Pin Assignment

1-5

PRODUCT OVERVIEW S3C8639/C863A/P863A

PIN DESCRIPTIONS

Table 1-1. S3C8639/C863A Pin Descriptions

Pin

Names

P0.0
P0.1
P0.2
P0.3
P0.4

Pin

Type

Description

I/O General-purpose, 8-bit I/O port. Shared

functions include three external interrupt inputs
and I/O for timer M0. Selective configuration of
port 0 pins to input or output mode is

supported.
P0.5
P0.6
P0.7

P1.0
P1.1
P1.2

I/O General-purpose, 8-bit I/O port. Selective

configuration is available for port 1 pins to

input, push-pull output, n-channel open-drain

mode, or IIC-bus clock and data I/O.
P2.0

P2.1
P2.2
P2.3
P2.4

I/O General-purpose, 8-bit I/O port Selective

configuration of port 2 pins to input or output

mode is supported. The port 2 pin circuits are

designed to push-pull PWM output and Csync

(SOG) signal input.
P2.5
P2.6
P2.7

P3.0–P3.3
P3.4–P3.7

I/O General-purpose, 8-bit I/O port Selective

configuration port 3 pins to input or output

mode is supported. Multiplexed for alternative

use as A/D converter inputs AD0–AD3.
Hsync-I

Vsync-I
Clamp-O
Hsync-O
Vsync-O
SDA0
SCL0

V

, V

DD1

V

, V

DD2

XIN, X

OUT

RESET

SS1
SS2

,

I

The pins are sync processor signal I/O and IIC-

I

bus clock and data I/O.

O
O

O
I/O
I/O

– Power pins –

– System clock I/O pins – 14, 13 –

I System RESET pin B 18 –

TEST I Factory test pin input

0 V: Normal operation, 5 V: Factory test mode

Pin

Circuit

Type

D-1
D-1
D-1
D-1
D-1
D-1
D-1
D-1

E-1
E-1
E-1

D-1
D-1
D-1
D-1
E-1
E-1
E-1
D-1

E-1

E

A-3
A-3

A
A

A
G-3
G-3

SDIP Pin

Numbers

1
2
3
4
5
6
7
8

9
10
19

20
21
22
23
24
25
26
32

35–38
39–42

31
30
27
28
29
16
17

11, 12

–

34, 33

– 15 –

Shared

Functions

INT0
INT1
INT2

TM0CAP

SDA1
SCL1

PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6

Csync-I

AD0–AD3

–

–

1-6

S3C8639/C863A/P863A PRODUCT OVERVIEW

PIN CIRCUITS DIAGRAM

DD

V

VDD

Data

Output

VSS

Figure 1-4. Pin Circuit Type A

VDD

280 k

Ω

RESET

Noise

Filter

Input

Figure 1-5. Pin Circuit Type A-3

Data or

Other

Function

Output

Disable

Digital Input,

TTL Input

Output

300 k

Ω

Typical

SS

V

VSS

DD

V

Output

VSS

Figure 1-6. Pin Circuit Type B (RESET)

NOTE: The noise filter must be built in the

external interrupts.

Figure 1-7. Pin Circuit Type D-1

1-7

PRODUCT OVERVIEW S3C8639/C863A/P863A

VDD

Pull-up
Enable

Data

Open
Drain

Output

Disable

Input

Figure 1-8. Pin Circuit Type E

Typical

47 k

VDD

VSS

V

Ω

DD

Data

Output

Open

Drain

Output

Output

Disable

V

SS

Digital Input

or ADC Input

Figure 1-9. Pin Circuit Type E-1

1-8

Data

Input

Figure 1-10. Pin Circuit Type G-3

Output

V

SS

S3C8639/C863A/P863A ELECTRICAL DATA

19 ELECTRICAL DATA

OVERVIEW

In this section, S3C8639/C863A electrical characteristics are presented in tables and graphs. The information is
arranged in the following order:

— Absolute maximum ratings
— D.C. electrical characteristics
— Data retention supply voltage in stop mode
— Stop mode release timing when initiated by a reset
— I/O capacitance
— A/D Converter electrical characteristics
— A.C. electrical characteristics
— Input timing measurement points for P0.0–P0.2 and TM0CAP
— Oscillation characteristics
— Oscillation stabilization time
— Clock timing measurement points for X

— Schmitt trigger characteristics
— Power-on reset circuit characteristics

IN

19-1

ELECTRICAL DATA S3C8639/C863A/P863A

Table 19-1. Absolute Maximum Ratings

(TA = 25°C)

Parameter Symbol Conditions Rating Unit

Supply voltage
Input voltage

Output voltage
Output current

V

DD

V

I1

V

I2

V

O

I

OH

Type G-3 (n-channel open drain) – 0.3 to + 7.0
All port pins except V
All output pins
One I/O pin active – 10 mA

– – 0.3 to + 6.5 V

I1

– 0.3 to VDD + 0.3
– 0.3 to VDD + 0.3

High

All I/O pins active – 60

Output current

I

OL

One I/O pin active + 30

Low

Total pin current except port 3 + 100
Sync-processor I/O pins and IIC-bus

+ 150

clock and data pins

Operating

T

A

– – 40 to + 85

°

C

temperature
Storage

T

STG

– – 65 to + 150

temperature

Table 19-2. D.C. Electrical Characteristics

(T

= – 40 °C to + 85 °C, VDD = 3.0 V to 5.5 V)

A

Parameter Symbol Conditions Min Typ Max Unit

Input High
voltage

Input Low
voltage

Output High
voltage

V
V
V
V

V
V
V
V

V

V

All input pins except V

IH1

X

IH2
IH3
IH4

IL1
IL2
IL3
IL4

OH1

IN

TTL input (Hsync-I, Vsync-I, and Csync-I) 2.0
SCL0/SDA0, SCL1/SDA1
All input pins except V
X

IN

TTL input (Hsync-I, Vsync-I, and Csync-I) 0.8
SCL0/SDA0, SCL1/SDA1
VDD = 5 V ± 10%; I

, V

IH2

and V

IL2

= – 15 mA;

OH

IH3

and V

IL3

IH4

0.8 V

DD

VDD–0.5 V

0.7V

DD

–

V

– 1.0

DD

Port 3.6–3.7
VDD = 5 V ± 10%; I

OH2

= – 4 mA;

OH

–

V

V
V

0.2 V

DD
DD
DD
DD

DD

0.4

0.3V

DD

–

Port 1.2, Port 3.0–3.5

V

VDD = 5 V ± 10%; I

OH3

= – 2 mA;

OH

Port 0, 2, Clamp-O, H, and Vsync-O

V

VDD = 5 V ± 10%; IOH = – 6 mA;

OH4

Port 1.0–P1.1, SCL0 and SDA0

V

19-2

S3C8639/C863A/P863A ELECTRICAL DATA

Table 19-2. D.C. Electrical Characteristics (Continued)

(T

= – 40 °C to + 85 °C, V

A

= 3.0 V to 5.5 V)

DD

Parameter Symbol Conditions Min Typ Max Unit

Output Low
voltage

V

VDD = 5 V ± 10%; IOL = 15 mA

OL1

– – 0.4 V

Port 3.6–3.7

V

VDD = 5 V ± 10%; IOL = 4 mA

OL2

0.4

Port 3.0–3.5 and Port 1.2

V

VDD = 5 V ± 10%; IOL = 2 mA

OL3

0.4

Port 0, 2, Clamp-O, H, and Vsync-O

V

VDD = 5 V ± 10%; IOL = 6 mA

OL4

0.6

Port 1.0–1.1; SCL0 and SDA0

Input High
leakage current

Input Low
leakage current

Output High

I

LIH1

I

LIH2

I

LIH3

I

LIL1

I

LIL2

I

LIL3

I

LOH1

VIN = V

DD

All input pins except X
V

= V

X

IN

VIN = V
V

IN

X

OUT

V

IN

V

IN

V

OUT

;

DD

OUT

X

only

;

DD

IN

= 0 V; All input pins except X

RESET , HsyncI & VsyncI

,

= 0 V; X

= 0 V; X

= V

DD

OUT
IN

only

only

only

,

IN

X

OUT

– – 3 µA

– – 20

2.5 6 20

,

IN

– – – 3

– – – 20

– 2.5 – 6 – 20

– – 3

leakage current
Output Low

I

LOL1

V

OUT

= 0 V

– – – 3

leakage current
Pull-up resistor

R

U1

V

= 0 V; V

IN

= 5 V ± 10%

DD

20 47 80

kΩ

Ports 3.7–3.4

Pull-down
resistor

Supply current

(note)

R

R

I

DD1

V

U2

D

= 0 V; V

IN

RESET only

V

= 0 V; V

IN

= 5 V ± 10%

DD

= 5 V ± 10%

DD

HsyncI & VsyncI
VDD = 5 V ± 10%

Operation mode; 12 MHz crystal

150 280 480

150 300 500

– 10 20 mA

C1 = C2 = 22pF

I

DD2

VDD = 5 V ± 10%

4 8

Idle mode; 12 MHz crystal
C1 = C2 = 22pF

I

DD3

VDD = 5 V ± 10%

100 150 µA

Stop mode

NOTE: Supply current does not include drawn internal pull-up/pull-down resistors and external loads of output.

19-3

ELECTRICAL DATA S3C8639/C863A/P863A

Table 19-3. Data Retention Supply Voltage in Stop Mode

(TA = – 40 °C to + 85 °C)

Parameter Symbol Conditions Min Typ Max Unit

Data retention

V

DDDR

Stop mode 2 – 5.5 V

supply voltage
Data retention

I

DDDR

Stop mode, V

DDDR

= 2.0 V

– – 5 µA

supply current

NOTES:

1. During the oscillator stabilization wait time (t

2. Supply current does not include drawn through internal pull–up resistors and external output current loads.

), all CPU operations must be stopped.

WAIT

V

RESET

DD

Execution of

STOP Instrction

NOTE: t

~

~

~

~

WAIT

is the same as 4096 x 16 x 1/f

Data Retention Mode

Stop Mode

V

DDDR

OSC

RESET

occurs

.

t

WAIT

Oscillation

Stabilzation

Time

Normal
Operating
Mode

Figure 19-1. Stop Mode Release Timing When Initiated by a Reset

Table 19-4. Input/Output Capacitance

(T

= –40 °C to + 85 °C, V

A

DD

= 0 V)

Parameter Symbol Conditions Min Typ Max Unit

C

C

OUT

IN

f = 1 MHz; unmeasured pins
are connected to V

SS

– – 10 pF

Input
capacitance

Output
capacitance

I/O capacitance

C

IO

19-4

S3C8639/C863A/P863A ELECTRICAL DATA

Table 19-5. A/D Converter Electrical Characteristics

(T

= – 40 °C to + 85 °C, VDD = 3.0 V to 5.5 V, VSS = 0 V)

A

Parameter Symbol Conditions Min Typ Max Unit

Resolution – 8 – bit
Total accuracy

VDD = 5 V

– –

± 2

LSB

Conversion time = 5 µs
AV

Integral linearity error ILE
Differential linearity error DLE
Offset error of top EOT

Offset error of bottom EOB
Conversion time

(1)

Analog input voltage
Analog input impedance
Analog reference voltage
Analog ground
Analog input current
Analog block Current

(2)

t

V

R

AV

AV
I

ADIN

I

CON

IAN

AN
REF

SS

ADC

= 5 V

REF

AV

= 0 V

SS

8 bit conversion
40 x n/f

OSC

(3)

–
– 2 1000 –
– 2.5 –
–

AV

= VDD = 5V

REF

AV

= VDD = 5V

REF

AV

= VDD = 3V

REF

AV

= VDD = 5V

REF

n=1,4,8,16

,

–
–

± 1
± 1

± 1 ± 2

± 0.5 ± 2

20 – 170

AV

V

SS

SS

–

–

AV

REF

V

DD

V

+ 0.3

SS

– – 10
– 1 3 mA

0.5 1.5 mA

100 500 nA

µs

V

MΩ

V
V

µA

When power down mode

NOTES:

1. "Conversion time" is the time required from the moment a conversion operation starts until it ends.

2. I

3. f

is an operating current during the A/D conversion.

ADC

is the main oscillator clock.

OSC

19-5

ELECTRICAL DATA S3C8639/C863A/P863A

Table 19-6. A.C. Electrical Characteristics

(T

= – 40 °C to + 85 °C, V

A

= 3.0 V to 5.5V)

DD

Parameter Symbol Conditions Min Typ Max Unit

Noise Filter

t

NF1H

t

NF1L

t

NF2

INT0–2 and TM0CAP (RC

300 – – ns

delay)

RESET only (RC delay) 1000 – –

t

t

NF1L

t

NF2

0.8 V

0.2 V

NF1H

DD

DD

Figure 19-2. Input Timing Measurement Points for P0.0–P0.2 and TM0CAP

19-6

S3C8639/C863A/P863A ELECTRICAL DATA

Table 19-7. Oscillation Characteristics

(TA = – 40 °C + 85 °C)

Oscillator Clock Circuit Conditions Min Typ Max Unit

V

Main crystal or
ceramic

External clock
(main)

NOTE: The maximum oscillator frequency is 12 MHz. If you use an oscillator frequency higher than 12 MHz, you cannot

select a non-divided CPU clock using CLKCON settings. That is, you must select one of the divide-by values.

C1

C2

X

X

IN

OUT

X

X

IN

OUT

= 3.0 V to 5.5 V

DD

V

= 3.0 V to 5.5 V

DD

8 – 12 MHz

8 – 12 MHz

Table 19-8. Oscillation Stabilization Time

(T

= – 40 °C + 85 °C, VDD = 3.0 V to 5.5 V)

A

Oscillator Test Condition Min Typ Max Unit

Crystal

VDD = 3.0 V to 5.5 V

– – 20 ms
Ceramic
External clock

VDD = 3.0 V to 5.5V
XIN input high and low level width

– – 10

25 – 500 ns

(tXH, tXL)

NOTE: Oscillation stabilization time is the time required for the CPU clock to return to its normal oscillation frequency after a

power-on occurs, or when Stop mode is released.

1/fx

t

t

XL

X

IN

Figure 19-3. Clock Timing Measurement Points for X

XH

V

DD

- 0.5 V

0.4 V

IN

19-7

ELECTRICAL DATA S3C8639/C863A/P863A

V

OUT

V

DD

A = 0.2 V
B = 0.4 V
C = 0.6 V
D = 0.8 V

V

SS

V

A B C D

IN

DD
DD
DD
DD

Figure 19-4. Schmitt Trigger Characteristics (Normal Port; except TTL Input)

Table 19-9. Power-on Reset Circuit Characteristics

(TA = – 40 °C to + 85 °C, VDD = 3.0 V to 5.5 V)

Parameter Symbol Conditions Min Typ Max Unit

Power-on reset release

V

ODLVD

voltage

Power-on reset detection

V

LVD

voltage
Power supply voltage

t

r

rise time
Power supply voltage off

t

off

time
Power-on reset circuit

consumption current

(2)

I

DDPR

VDD = 5 V ± 10%

VDD = 3 V

NOTES:

1. 216/f

2. Current contained when power-on reset circuit is provided internally.

(= 5.46 ms at f

OSC

OSC

/12MHz)

2.7 – 5.5 V

2.2 2.4 2.6 V

10 –

(1)

us

10 – – ms

100 150

60 100

µA

µA

19-8

S3C8639/C863A/P863A ELECTRICAL DATA

V

DD

V

LVD

t

off

V

DDLVD

t

r

Figure 19-5. Power-on Reset Timing

19-9

S3C8639/C863A/P863A MECHANICAL DATA

20 MECHANICAL DATA

OVERVIEW

The S3C8639/C863A microcontroller is available in a 42-pin SDIP package (Samsung part number 42-SDIP-

600) and a 44-QFP package (Samsung part number 44-QFP-1010B).

#42 #22

± 0.2

14.00

0.50

(1.77)

NOTE: Dimensions are in millimeters.

1.00

42-SDIP-600

39.50 MAX

39.10

±

±

0.1

0.1

±

0.2

1.778

0-15

15.24

#21#1

3.50 ± 0.2

5.08 MAX

3.30 ± 0.3

0.51 MIN

+ 0.1

0.25

- 0.05

Figure 20-1. 42-Pin SDIP Package Mechanical Data (42-SDIP-600)

20-1

MECHANICAL DATA S3C8639/C863A/P863A

13.20 ±

0.3

0-8

10.00

±

13.20 ± 0.3

0.2

±

10.00

0.2

44-QFP-1010B

+ 0.10

- 0.05

0.15

0.10 MAX

#44

0.20

±

0.80

#1

0.80

0.35

+ 0.10

- 0.05

(1.00)

0.05 MIN

2.05

2.30 MAX

NOTE: Dimensions are in millimeters.

Figure 20-2. 44-Pin QFP Package Mechanical Data (44-QFP-1010B)

±

0.10

20-2

S3C8639/C863A/P863A S3P863A OTP

21 S3P863A OTP

OVERVIEW

The S3P863A single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the

S3C8639/C863A microcontrollers. It has an on-chip EPROM instead of masked ROM. The EPROM is accessed
by serial data format.

The S3P863A is fully compatible with the S3C8639/C863A, both in function and in pin configuration. Because of
its simple programming requirements, the S3P863A is ideal for use as an evaluation chip for the
S3C8639/C863A.

P0.0/INT0
P0.1/INT1
P0.2/INT2

P0.4/TM0CAP

SDAT/P1.0/SDA1

SCLK/P1.1/SCL1

VPP/TEST (GND)

RESET

P0.3
P0.5

P0.6
P0.7

V

DD1

V

X

OUT

X

SDA0

SCL0

/RESET

P1.2
P2.0/PWM0
P2.1/PWM1

NOTE: The bolds indicate an OTP pin name.

SS

1
2
3
4
5
6
7
8
9
10
11
12
13

IN

14
15
16
17
18
19
20
21

S3P863A

42-SDIP

(Top View)

42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22

Figure 21-1. S3P863A Pin Assignments (42-SDIP Package)

P3.7
P3.6
P3.5
P3.4
P3.3/AD3
P3.2/AD2
P3.1/AD1
P3.0/AD0
V

DD2

V

SS2

P2.7/Csync-I (SOG)
Hsync-I
Vsync-I
Vsync-O
Hsync-O
Clamp-O
P2.6/PWM6
P2.5/PWM5
P2.4/PWM4
P2.3/PWM3
P2.2/PWM2

21-1

S3P863A OTP S3C8639/C863A/P863A

P0.4/TM0CAP

P0.3

P0.2/INT2

P0.1/INT1

N.C.

P0.0/INT0

P3.7

P3.6

P3.5

P3.4

P3.3/AD3

4443424140393837363534

P3.2/AD2

P0.5
P0.6
P0.7

SDAT/P1.0/SDA1

SCLK/P1.1/SCL1

V

DD1

V

SS1

X

OUT

X

VPP/TEST (GND)

SDA0

1
2
3
4
5
6
7
8
9

IN

S3P863A

44-QFP

(Top View)

10
11

33

P3.1/AD1

32

P3.0/AD0

31

V

30
29
28
27
26
25
24
23

DD2

V

SS2

P2.7/Csync-I (SOG)
Hsync-I
Vsync-I
Vsync-O
Hsync-O
Clamp-O

1213141516171819202122

SCL0

RESET

/

RESET

P1.2

N.C.

P2.0/PWM0

P2.1/PWM1

P2.2/PWM2

P2.3/PWM3

P2.4/PWM4

P2.5/PWM5

P2.6/PWM6

NOTE: The bolds indicate an OTP pin name.

Figure 21-2. S3P863A Pin Assignments (44-QFP Package)

21-2

S3C8639/C863A/P863A S3P863A OTP

Table 21-1. Descriptions of Pins Used to Read/Write the EPROM

Main Chip During Programming

Pin Name Pin Name Pin No. I/O Function

P1.0 SDAT 9 (4) I/O Serial data pin. Output port when reading and input

port when writing. Can be assigned as a
Input/push-pull output port.

P1.1 SCLK 10 (5) I Serial clock pin. Input only pin.

TEST

VPP (TEST)

15 (10) I Power supply pin for EPROM cell writing (indicates

that OTP enters into the writing mode). When 12.5
V is applied, OTP is in writing mode and when 5 V
is applied, OTP is in reading mode. (Option)

RESET RESET

V

DD1/VSS1

V

DD1/VSS1

18 (13) I Chip Initialization

11/12 (6/7) I

Logic power supply pin. VDD should be tied to +5 V
during programming.

NOTE: Parentheses indicate 44-QFP OTP pin number.

Table 21-2. Comparison of S3P863A and S3C8639/C863A Features

Characteristic S3P863A S3C8639/C863A

Program Memory 48-Kbyte EPROM 32/48-Kbyte mask ROM
Operating Voltage (VDD)

3.0 V to 5.5 V 3.0 V to 5.5V

OTP Programming Mode

VDD = 5 V, V

(TEST)=12.5V

PP

Pin Configuration 42SDIP, 44QFP 42SDIP, 44QFP
EPROM Programmability User Program 1 time Programmed at the factory

OPERATING MODE CHARACTERISTICS

When 12.5 V is supplied to the VPP(TEST) pin of the S3P863A, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in

Table 21-3 below.

Table 21-3. Operating Mode Selection Criteria

V

DD

V

(TEST) REG/MEM Address (A15–A0) R/W Mode

PP

5 V 5 V 0 0000H 1 EPROM read

12.5 V 0 0000H 0 EPROM program

12.5 V 0 0000H 1 EPROM verify

12.5 V 1 0E3FH 0 EPROM read protection

NOTE: "0" means Low level; "1" means High level.

21-3

S3P863A OTP S3C8639/C863A/P863A

D.C. ELECTRICAL CHARACTERISTICS

Table 21-4. D.C. Electrical Characteristics

(T

= – 40 °C to + 85 °C, V

A

Parameter Symbol Conditions Min Typ Max Unit

Input High

I

LIH1

leakage current

I

LIH2

I

LIH3

Input Low

I

LIL1

leakage current

I

LIL2

I

LIL3

Output High

I

LOH1

leakage current
Output Low

I

LOL1

leakage current
Pull-up resistor

Pull-down

R

U1

R

U2

R

D

resistor
Supply current

(note)

I

DD1

I

DD2

I

DD3

= 3.0 V to 5.5 V)

DD

VIN = V

DD

All input pins except X
V

= V

X

only

IN

VIN = V
V

IN

X

OUT

V

IN

V

IN

V

OUT

V

OUT

V

IN

;

DD

OUT

X

only

;

DD

IN

= 0 V; All input pins except X

RESET , Hsync-I and Vsync-I

,

= 0 V; X

= 0 V; X

= V

= 0 V

= 0 V; V

OUT

only

IN

DD

= 5 V ± 10%

DD

only

X

,

IN

OUT

Port 3.7–3.4
V

= 0 V; V

IN

RESET only

V

= 0 V; V

IN

= 5 V ± 10%

DD

= 5 V ± 10%

DD

Hsync-I and Vsync-I
VDD = 5 V ± 10%

Operation mode; 12 MHz crystal
C1 = C2 = 22pF

VDD = 5 V ± 10%
Idle mode; 12 MHz crystal

C1 = C2 = 22pF
VDD = 5 V ± 10%

Stop mode

– – 3 µA

– – 20

2.5 6 20

,

IN

– – – 3

– – – 20

– 2.5 – 6 – 20

– – 3

– – – 3

20 47 80

kΩ

150 280 480

150 300 500

– 10 20 mA

4 8

100 150 µA

NOTE: Supply current does not include drawn internal pull-up/pull-down resistors and external loads of output.

21-4