Datasheet S3C8615, S3C8618, S3P8615 Datasheet (Samsung)

S3C8618/C8615/P8615 PRODUCT OVERVIEW

1 PRODUCT OVERVIEW

SAM8 PRODUCT FAMILY

Samsung's SAM8 family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range
of integrated peripherals, and various mask-programmable ROM sizes. Important CPU features include:

— Efficient register-oriented architecture
— Selectable CPU clock sources
— Idle and Stop power-down mode release by interrupt
— Built-in basic timer with watchdog function

A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more
interrupt sources and vectors. Fast interrupt processing (within a minimum six CPU clocks) can be assigned to
specific interrupt levels.

S3C8618/C8615/P8615 MICROCONTROLLERS

The S3C8618/C8615/P8615 single-chip 8-bit
microcontroller is based on the powerful SAM8 CPU
architecture. The internal register file is logically
expanded to increase the on-chip register space. The
S3C8618/C8615/P8615 have 8/16 K bytes of on-chip
program ROM.

Following Samsung's modular design approach, the
following peripherals were integrated with the SAM8
core:

— Four programmable I/O ports (total 28 pins)
— One 8-bit basic timer for oscillation stabilization

and watchdog functions

— One 8-bit general-purpose timer/counter with

selectable clock sources

— One 8-bit counter with selectable clock sources,

including Hsync or Csync input
— One 8-bit timer for interval mode
— PWM block with seven 8-bit PWM circuits
— Sync processor block (for Vsync and Hsync I/O,

Csync input, and Clamp signal output)

— Multi master IIC-bus with DDC support.

The S3C8618/C8615/P8615 are a versatile
microcontroller that is ideal for use in multi-sync
monitors or in general-purpose applications that
require sophisticated timer/counter, PWM, sync
signal processing, and multi-master IIC-bus support
with DDC. It is available in a 42-pin SDIP or a 44-pin
QFP package.

Figure 1-1. S3C8618/C8615/P8615

Microcontrollers

1-1

PRODUCT OVERVIEW S3C8618/C8615/P8615

FEATURES

CPU

• SAM8 CPU core

Memory

• 8/16-Kbyte internal program memory (ROM)

• 272-byte general-purpose register area

Instruction Set

• 78 instructions

• IDLE and STOP instructions added for power­down modes

Instruction Execution Time

• 500 ns minimum (with 12 MHz CPU clock)

Interrupts

• Nine interrupt sources

• Nine interrupt vectors

• Six interrupt levels

• Fast interrupt processing for a select level

General I/O

• Four I/O ports (total 28 pins):

8-Bit Basic Timer

• Programmable timer for oscillation stabilization
interval control or watchdog timer functions

• Three selectable internal clock frequencies

Timer/Counters

• One 8-bit general-purpose timer/counter with
programmable operating modes and the following
clock source options:

— Two selectable internal clock frequencies

• One 8-bit timer with interval operating mode

• One 8-bit counter with the following clock source
options:

— Two selectable internal clock frequencies
— Hsync (or Csync) input from the sync

processor block

— External clock source

Pulse Width Modulator

• Seven 8-bit PWM modules:
— 8-bit basic frame
— Four push-pull and three n-channel,

open-drain output channels

— Selectable clock frequencies: 46.875 kHz at

12 MHz fosc.

Sync Processor

• Detection of sync input signals (Vsync-I, Hsync-I,
and Csync-I)

• Sync signal separation and output (Hsync-O,
Vsync-O, and Clamp-O)

• Pseudo sync signal output

• Programmable clamp signal output

DDC and Multi-Master IIC-Bus

• Serial peripheral interface

• Support for display data channel (DDC)

Oscillator Frequency

• 6 MHz to 12 MHz external crystal oscillator

• Interval Max. 12MHz CPU clock

Operating Temperature Range

• – 40°C to + 85°C

Operating Voltage Range

• 4.5 V to 5.5 V

Package Types

• 42-pin SDIP, 44-pin QFP

1-2

S3C8618/C8615/P8615 PRODUCT OVERVIEW

BLOCK DIAGRAM

XIN

X

OUT

PWM0
PWM1

•

•

•

PWM6

Vsync-I
Hsync-I
Csync-I

Vsync-O
Hsync-O
Clamp-O

T0CAP

RESET

INT0-INT2

CESSOR

TIMER 0

MAIN

OSC

8-BIT

PWM

(7-CH)

SYNC

PRO-

P0.0–P0.7/INT0-INT2

PORT 0

INTERNAL BUS

I/O PORT and INTERRUPT

CONTROL

SAM8 CPU

8/16-KBYTE MASK ROM

272-BYTE REGISTER FILE

P2.0–P2.7

PORT 2

TEST

PORT 1

PORT3

DDC and

Multi master

IIC-bus

P1.0–P1.3

P3.0–P3.7

SCL
SDA

8-blt

Counter

(TIMER 1)

T1CK

Interval

timer

(TIMER 2)

Figure 1-2. Block Diagram

1-3

PRODUCT OVERVIEW S3C8618/C8615/P8615

PIN ASSIGNMENTS

P3.1

P3.0
P0.0/INT0
P0.1/INT1
P0.2/INT2

P0.3

P0.4/T0CAP

P0.5/T1CK

VDD
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3

P2.0/PWM0
P2.1/PWM1
P2.2/PWM2
P2.3/PWM3
P2.4/PWM4
P2.5/PWM5

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

S3C8618/8615

42-SDIP

(Top View)

42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22

P3.2
VSS2
P3.3
P3.4
P3.5
P3.6
P3.7

RESET

XOUT
XIN
VSS1
P2.7/Csync-I
Hsync-I
Vsync-I (VCLK)
Clamp-O
Hsync-O
Vsync-O
SCL
SDA
TEST
P2.6/PWM6

1-4

Figure 1-3. Pin Assignment Diagram (42-SDIP Package)

S3C8618/C8615/P8615 PRODUCT OVERVIEW

P2.0/PWM0

P1.3

P1.2

P1.1

P1.0

P0.7

P0.6

VDD

P0.5/T1CK

P0.4/T0CAP

P0.3

4443424140393837363534

P2.1/PWM1
P2.2/PWM2
P2.3/PWM3
P2.4/PWM4
P2.5/PWM5

N.C.

P2.6/PWM6

TEST

SDA

SCL

Vsync-O

34
35
36
37
38
39
40
41
42
43
44

S3C8618/8615

44-QFP

(Top View)

1234567891011

Vsync-I

Hsync-O

Clamp-O

VSS1

Hsync-I

P2.7/Csync-I

XIN

XOUT

P3.7

RESET

P3.6

Figure 1-4. Pin Assignment Diagram (44-QFP Package)

33
32
31
30
29
28
27
26
25
24
23

P0.2/INT2
P0.1/INT1
P0.0/INT0
P3.0
P3.1
NC
P3.2
VSS2
P3.3
P3.4
P3.5

1-5

PRODUCT OVERVIEW S3C8618/C8615/P8615

PIN DESCRIPTIONS

Table 1-1. S3C8618/C8615/P8615 Pin Descriptions

Pin

Names

P0.0
P0.1
P0.2
P0.3
P0.4

Pin

Type

Pin

Description

I/O General-purpose, 8-bit I/O port. Share

functions include three external interrupt
inputs, I/O for timers 0 and 1. You can
selectively configure port 0 pins to input or

output mode.
P0.5
P0.6
P0.7

P1.0–P1.3 I/O General purpose, 8-bit I/O port. You can

selectively configure port 1 pins to input or

push-pull output mode.
P2.0

P2.1
P2.2
P2.3
P2.4

I/O General purpose, 8-bit I/O port. You can

selectively configure port 2 pins to input or

output mode. The port 2 pin circuit are

designed to push-pull PWM output and

Csync signal input.
P2.5
P2.6
P2.7

P3.0–P3.7 I/O General-purpose, 8-bit I/O port. You can

selectively configure port 3 pins to input or

output mode.
Hsync-I

Vsync-I
Clamp-O
Hsync-O
Vsync-O
SCL
SDA

V

DD

V

, V

SS1

XIN, X

OUT

RESET

SS2

I

The pins are sync processor signal I/O and

I

IIC-bus clock and data I/O

O
O

O
I/O
I/O

– Power supply pins – 9

– System clock input and output pins – 33, 34 –

I System reset pin B 35 –

TEST I Factory test pin input

0 V: normal operation
5 V: factory test mode

Circuit

Type

SDIP Pin

Numbers

Functions

D-1 3

4
5
6
7

8
10
11

D-1 12–15 –

D-1
D-1
D-1
D-1
E-1
E-1
E-1
D-1

16
17
18
19
20
21
22
31

E 2, 1, 42,

40–36

A
A
A
A

A
G-3
G-3

30
29
28
27
26
25
24

32, 41

– 23 –

Shared

INT0
INT1
INT2

T0CAP

T1CK

PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6

Csync-I

–

–

–

NOTE: See ‘Pin Circuit Diagrams’ on next two pages for detailed information on circuit types A, B, D-1, E, E-1,and G-3.

1-6

S3C8618/C8615/P8615 PRODUCT OVERVIEW

PIN CIRCUITS

Vdd

Vss

Figure 1-5. Pin Circuit Type A

Data or
Other
function

Output
Disable

Vdd

280 K

Ω

Noise Filter

RESET

Figure 1-6. Pin Circuit Type B (RESETRESET)

Vdd

Vss

Output

Digital Input

or TTL Input

Figure 1-7. Pin Circuit Type D-1

1-7

PRODUCT OVERVIEW S3C8618/C8615/P8615

Vdd

Typical

47-K

Ω

Pull-up

enable

Vdd

Data

Output

Open drain

Output

Disable

Vss

Input

Data

Open drain

Output

Disable

Input

Figure 1-7. Pin Circuit Type E

Vdd

IN/OUT

Vss

1-8

Figure 1-8. Pin Circuit Type E-1

S3C8618/C8615/P8615 PRODUCT OVERVIEW

Output

Data

Vss

Input

Figure 1-9. Pin Circuit Type G-3

1-9

S3C8618/C8615/P8615 ELECTRICAL DATA

16 ELECTRICAL DATA

OVERVIEW

In this section, S3C8618/C8615 electrical characteristics are presented in tables and graphs. The information is
arranged in the following order:

— Absolute maximum ratings
— D.C. electrical characteristics
— I/O capacitance
— A.C. electrical characteristics
— Oscillation characteristics
— Oscillation stabilization time
— Schmitt trigger characteristics

16-1

ELECTRICAL DATA S3C8618/C8615/P8615

Table 16-1. Absolute Maximum Ratings

(TA = 25 °C)

Parameter Symbol Conditions Rating Unit

Supply voltage V
Input voltage V

Output voltage V
Output current

DD

I

1

V

I2
O

I

OH

Type C (n-channel, open-drain) – 0.3 to + 10 V
All port pins except V
All output pins – 0.3 to VDD + 0.3 V
One I/O pin active – 10 mA

– – 0.3 to + 7.0 V

I1

– 0.3 to V

DD

+ 0.3

High

All I/O pins active – 60

Output current

I

OL1

One I/O pin active + 30 mA

Low

I
I

OL2
OL3

Total pin current except port 3 + 100
Sync-processor I/O pins and IIC-bus

+ 150

clock and data pins

Operating

T

A

– – 40 to + 85 °

C

temperature
Storage

T

STG

– – 65 to + 150 °

C

temperature

Table 16-2. D.C. Electrical Characteristics

(T

= – 40 °C to + 85 °C, VDD = 4.5 V to 5.5 V)

A

Parameter Symbol Conditions Min Typ Max Unit

Input High

V

IH1

All input pins except V

IH2

and V

IH3

0.8 V

DD

– V

DD

voltage

Input Low
voltage

Output High
voltage

V

V

V
V
V

V
V

OH1

OH2

IH2
IH3

IL1

IL2
IL3

XIN, X

OUT

TTL input (HsyncI, VsyncI and CsyncI) 2.0 V
All input pins except V

and V

IL3

XIN, X

OUT

IL2

V

– 0.5 V

DD

– – 0.2 V

DD
DD

0.4
TTL input (HsyncI, VsyncI and CsyncI) 0.8
VDD= 4.5 V to 5.5 V

V

– 1.0 – – V

DD

IOH = – 8 mA Port 1 only
VDD = 4.5 V to 5.5 V

V

– 1.0

DD

DD

IOH = – 2 mA Ports 0, 2, ClampO, H
and VsyncO

V

OH3

VDD = 4.5 V to 5.5 V

V

– 1.0

DD

IOH = – 6 mA, Port 3

V

V

16-2

S3C8618/C8615/P8615 ELECTRICAL DATA

Table 16-2. D.C. Electrical Characteristics (Continued)

(T

= – 40 °C to + 85 °C, VDD = 4.5 V to 5.5 V)

A

Parameter Symbol Conditions Min Typ Max Unit

Output Low
voltage

V

OL1

V

= 4.5 V to 5.5 V

DD

– – 0.4 V

IOL = 8 mA, port 1 only

V

V

Input High

I

leakage current

I

I

Input Low

I

leakage current

I
I

Output High

I

LOHL

leakage current
Output Low

I

leakage current
Pull-up resistor R

Supply current

(note)

I

OL2IOL

OL3IOL

LIH1

LIH2

LIH3

LIL1

LIL2
LIL3

LOL

L1

R

L2

DD1

= 2 mA

0.4

Port 0, 2, ClampO, HsyncO and
VsyncO

= 6 mA

0.4
Port 3, SCL and SDA
VIN = V

DD

All input pins except X

VIN = V
X

VIN = V
X

V

OUT

IN

= 0 V

IN

only

only

DD

DD

All input pins except X

X

,

IN

OUT

X

,

IN

OUT

– – 3 µA

– – 20

2.5 6 20

– – – 3 µA

and RESET
V

= 0 V; X

IN

V

= 0 V; X

IN

V

OUT

= V

DD

only – – – 20

OUT

only – 2.5 – 6 – 20

IN

– – 3 µA

All output pins except port 1
V

= 0 V – – – 3 µA

OUT

V

= 0 V;

IN

V

= 4.5 V to 5.5 V

DD

20 47 80

Port 3
V

= 0 V;

IN

V

= 4.5 V to 5.5 V

DD

150 280 480

RESET only
V

= 4.5 V to 5.5 V

DD

– 15 30 mA

12 MHz CPU clock

kΩ

I

DD2

Idle mode;

5 10

VDD = 4.5 V to 5.5 V
12 MHz CPU clock

I

DD3

NOTE: Supply current does not include drawn internal pull–up resistors and external loads of output.

Stop mode; V

= 5.0 V 1 10 µA

DD

16-3

ELECTRICAL DATA S3C8618/C8615/P8615

Table 16-3. Data Retention Supply Voltage in Stop Mode

(TA = – 40 °C to + 85 °C)

Parameter Symbol Conditions Min Typ Max Unit

Data retention

V

DDDR

Stop mode 2 – 6 V

supply voltage
Data retention

I

DDDR

Stop mode, V

= 2.0 V – – 5 µA

DDDR

supply current

NOTES:

1. During the oscillator stabilization wait time (t

2. Supply current does not include drawn through internal pull–up resistors and external output current loads.

), all CPU operations must be stopped.

WAIT

V

RESET

DD

EXECUTION OF

STOP INSTRUCTION

: t

NOTE

WAIT

Figure 16-1. Stop Mode Release Timing When Initiated by a Reset

≈≈

STOP MODE

DATA RETENTION MODE

VDDDR

is the same as 4096 × 32 × 1 / f

Table 16-4. Input/Output Capacitance

OSC

RESET

OCCURS

OSCILLATION

STABILIZATION

TIME

NORMAL
OPERATING
MODE

.

tWAIT

(T

= – 40 °C to + 85 °C, V

A

DD

= 0 V)

Parameter Symbol Conditions Min Typ Max Unit

Input
capacitance

Output

C

C

OUT

IN

f = 1 MHz; unmeasured pins

are connected to V

SS

– – 10 pF

capacitance
I/O capacitance C

16-4

IO

S3C8618/C8615/P8615 ELECTRICAL DATA

Table 16-5. A.C. Electrical Characteristics

(T

= – 40 °C to + 85 °C, V

A

= 4.5 V to 5.5V)

DD

Parameter Symbol Conditions Min Typ Max Unit

Noise Filter t

NF1H

t

NF1L

t

NF2

P0.2–P0.0, T0CAP and

,

T1CK (RC delay)
RESET only (RC delay)

300 – – ns

800 – –

1 tCPU

t

NF1L

t

NF1H

tNF2

0.8 VDD

0.2 V

DD

NOTE

: The unit t

means one CPU clock period.

CPU

Figure 16-2. Input Timing Measurement Points for P0.0–P0.2, T0CAP and T1CK

16-5

ELECTRICAL DATA S3C8618/C8615/P8615

Table 16-6. Oscillation Characteristics

(TA = – 40 °C + 85 °C)

Oscillator Clock Circuit Conditions Min Typ Max Unit

Main crystal or
ceramic

C1

C2

X

X

IN

OUT

V

= 4.5 V to 5.5 V 6 – 12 MHz

DD

External clock
(main)

NOTE: The maximum oscillator frequency is 12 MHz. If you use an oscillator frequency higher than 12 MHz, you cannot

select a non-divided CPU clock using CLKCON settings. That is, you must select one of the divide-by values.

X

X

IN

OUT

V

= 4.5 V to 5.5 V 6 – 12 MHz

DD

Table 16-7. Recommended Oscillator Constants

(T

= – 40 °C + 85 °C, VDD = 4.5 V to 5.5 V)

A

Manufacturer Product Name Load Cap (pF) Oscillator Voltage

Remarks

Range (V)

C1 C2 MIN MAX

TDK

FCR8.0MC5
FCR8.0M5 33 33 4.5 5.5

CCR8.0MC5

NOTE: On-chip C: 30 pF ± 20 % built in.

(note)

(note)

– – 4.5 5.5

– – 4.5 5.5

On-chip C Leaded Type
Leaded Type
On-chip C SMD Type

Table 16-8. Oscillation Stabilization Time

(T

= – 40 °C + 85 °C, VDD = 4.5 V to 5.5 V)

A

Oscillator Test Condition Min Typ Max Unit

Crystal VDD = 4.5 V to 5.5 V – – 20 ms
Ceramic VDD = 4.5 V to 5.5V – – 10
External clock XIN input High and Low level width

25 – 500 ns

(tXH, tXL)

NOTE: Oscillation stabilization time is the time required for the CPU clock to return to its normal oscillation frequency after

a power-on occurs, or when Stop mode is released.

16-6

S3C8618/C8615/P8615 ELECTRICAL DATA

f

1 /

OSC

XIN

tXL

tXH

VDD – 0.5 V

0.4 V

Figure 16-3. Clock Timing Measurement Points for X

V

out

V

DD

IN

A : 0.2 V
B : 0.4 V

DD
DD

C : 0.6 V
D : 0.8 V

V

SS

V

in

DD
DD

A B C D

Figure 16-4. Schmitt Trigger Characteristics (Normal Port; except TTL Input)

16-7

S3C8618/C8615/P8615 MECHANICAL DATA

17 MECHANICAL DATA

OVERVIEW

The S3C8615 microcontroller is available in a 42-pin SDIP package (Samsung part number 42-SDIP-600) and a
44-QFP package (Samsung part number 44-QFP-1010B).

14.00 ± 0.2

(1.77)

0.50 ± 0.1

42 22

42-SDIP-600

#1 21

39.10 ± 0.2

1.00 ± 0.1

1.778

15.24

5.08MAX

0.51MIN 3.50 ± 0.2

3.30 ± 0.3

+0.1

– 0.05

0.25

0 ~ 15 °

: Dimensions are in millimeters.

NOTE

Figure 17-1. 42-Pin SDIP Package Mechanical Data (42-SDIP-600)

17-1

MECHANICAL DATA S3C8618/C8615/P8615

13.20

10.00

± 0.3

± 0.2

0~8°

0.15

+0.10

- 0.05

±0.20

0.80

± 0.3

13.20

± 0.2

10.00

44-QFP-1010B

0.10 MAX

#44

0.80

: Dimensions are in millimeters.

NOTE

Figure 17-2. 44-Pin QFP Package Mechanical Data (44-QFP-1010B)

#1

0.35

+0.10

- 0.05

(1.00)

0.05 MIN

2.05

± 0.10

2.30 MAX

17-2

S3C8618/C8615/P8615 S3P8615 OTP

18 S3P8615 OTP

OVERVIEW

The S3P8615 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3P8615

microcontrollers. It has an on-chip EPROM instead of masked ROM. The EPROM is accessed by serial data
format.

The S3P8615 is fully compatible with the S3C8618/C8615, both in function and in pin configuration. Because of
its simple programming requirements, the S3P8615 is ideal for use as an evaluation chip for the
S3C8618/C8615.

P3.1

P3.0
P0.0/INT0
P0.1/INT1
P0.2/INT2

P0.3

P0.4/T0CAP

P0.5/T1CK

VDD/VDD

P0.6

P0.7

SCLK/P1.0
SDAT/P1.1

P1.2

P1.3

P2.0/PWM0
P2.1/PWM1
P2.2/PWM2
P2.3/PWM3
P2.4/PWM4
P2.5/PWM5

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

NOTE: The bolds indicate an OTP pin name.

S3P8618/8615

42-SDIP

(Top View)

42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22

P3.2
VSS2/VSS2
P3.3
P3.4
P3.5
P3.6
P3.7

RESET/RESETRESET

XOUT
XIN
VSS1/VSS1
P2.7/Csync-I
Hsync-I
Vsync-I (VCLK)
Clamp-O
Hsync-O
Vsync-O
SCL
SDA
TEST/VPP
P2.6/PWM6

Figure 18-1. S3P8615 Pin Assignments (42-SDIP Package)

18-1

S3P8615 OTP S3C8618/C8615/P8615

P2.0/PWM0

P1.3

P1.2

P1.1/SDAT

P1.0/SCLK

P0.7

P0.6

VDD/VDD

P0.5/T1CK

P0.4/T0CAP

P0.3

4443424140393837363534

P2.1/PWM1
P2.2/PWM2
P2.3/PWM3
P2.4/PWM4
P2.5/PWM5

N.C.

P2.6/PWM6

VPP/TEST

SDA

SCL

Vsync-O

34
35
36
37
38
39
40
41
42
43
44

S3C8618/8615

44-QFP

(Top View)

1234567891011

XIN

VSS1/VSS1

XOUT

RESET

RESET/RESET

Vsync-I

Hsync-O

Clamp-O

Hsync-I

P2.7/Csync-I

P3.7

33
32
31
30
29
28
27
26
25
24
23

P3.6

Figure 18-2. S3P8615 Pin Assignments (44-QFP Package)

P0.2/INT2
P0.1/INT1
P0.0/INT0
P3.0
P3.1
NC
P3.2
VSS2/VSS2
P3.3
P3.4
P3.5

18-2

S3C8618/C8615/P8615 S3P8615 OTP

Table 18-1. Descriptions of Pins Used to Read/Write the EPROM

Main Chip During Programming

Pin Name Pin Name Pin No. I/O Function

P1.1 SDAT 13 (*30) I/O Serial DATa Pin (Output when reading, Input

when writing) Input & Push-pull Output Port can
be assigned

P1.0 SCLK 12 (*29) I Serial CLocK Pin (Input Only Pin)

TEST V

(TEST) 23 (*41) I EPROM Cell Writing Power Supply Pin

PP

(Indicates OTP Mode Entering) When writing

12.5 V is applied and when reading 5V is
applied.(Option)

RESET RESET

VDD/V

SS1/VSS2

NOTE: * means the 44-QFP OTP pin number.

VDD/VSS/V

SS

35 (*9) I Chip Initialization

9 / 32 / 41

(*26 / 6 / 15)

I Logic Power Supply Pin. VDD should be tied to 5

V during programming.

Table 18-2. Comparison of S3P8615 and S3C8618/C8615 Features

Characteristic S3P8615 S3C8618/C8615

Program Memory 16 K byte EPROM 16 K byte mask ROM
Operating Voltage (VDD) 4.5 V to 5.5 V 4.5 V to 5.5V

OTP Programming Mode VDD = 5 V, V

(TEST)=12.5V

PP

Pin Configuration 42-SDIP, 44-QFP 42-SDIP, 44-QFP
EPROM Programmability User Program 1 time Programmed at the factory

OPERATING MODE CHARACTERISTICS

When 12.5 V is supplied to the VPP (TEST) pin of the S3P8615, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in

Table 16-3 below.

Table 18-3. Operating Mode Selection Criteria

V

DD

V

PP

(TEST)

REG/

MEMMEM

ADDRESS

(A15–A0)

R/WW

MODE

5 V 5 V 0 0000H 1 EPROM read

12.5 V 0 0000H 0 EPROM program

12.5 V 0 0000H 1 EPROM verify

12.5 V 1 0E3FH 0 EPROM read protection

NOTE: "0" means Low level; "1" means High level.

18-3

S3P8615 OTP S3C8618/C8615/P8615

D.C. ELECTRICAL CHARACTERISTICS

Table 18-4. D.C. Electrical Characteristics

(T

= – 40 °C to + 85 °C, VDD = 4.5 V to 5.5 V)

A

Parameter Symbol Conditions Min Typ Max Unit

Input High
leakage current

Input Low
leakage current

Output High
leakage current

I

LIH1

I

LIH2

I

LIH3

I

LIL1

I

LIL2

I

LIL3

I

LOH1

VIN = V

DD

;

All input pins except X
VIN = V
VIN = V
V

= 0 V;

IN

DD

DD;

X

;

only 20

OUT

X

only 2.5 6 20

IN

All input pins except X
and RESET
V

V
V

IN
IN
OUT

= 0 V; X
= 0 V; X

= V

DD

only – – – 20

OUT

only – 2.5 – 6 – 20

IN

– – 3 µA

X

,

IN

OUT

– – – 3 µA

X

,

IN

OUT

– – 3 µA

Output Low
leakage current

Supply current I

Data retention
supply voltage

Data retention
supply voltage

I

LOL1

DD1

I

DD2

I

DD3

V

DDDR

I

DDDR

V

= 0 V – – – 3 µA

OUT

Normal operating mode;

– 15 30 mA
12 MHz CPU clock
IDLE mode;

5 10

12 MHz CPU clock
Stop mode; V

= 5.0 V – 1 10 µA

DD

Stop mode 2 – 6 V

Stop mode; V

= 2V – – 5 µA

DDDR

18-4

S3C8618/C8615/P8615 S3P8615 OTP

START

Address= First Location

VDD=5V, VPP=12.5V

x = 0

Program One 1ms Pulse

Increment X

FAIL

Device Failed

Verify Byte

YES

x = 10

NO

FAIL

NO

FAIL

Verify 1 Byte

Last Address

V

= VPP= 5 V

DD

Compare All Byte

PASS

Device Passed

Figure 18-3. OTP Programming Algorithm

Increment Address

18-5