Datasheet S3C80E5, S3C80E7, S3P80E5, S3P80E7 Datasheet (Samsung)

S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) PRODUCT OVERVIEW

1 PRODUCT OVERVIEW

S3C8-SERIES MICROCONTROLLERS

Samsung's S3C8-series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range
of integrated peripherals and various mask-programmable ROM sizes. Important CPU features include:

— Efficient register-oriented architecture
— Selectable CPU clock sources
— Idle and Stop power-down mode release by interrupt
— Built-in basic timer with watchdog function

A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more
interrupt sources and vectors. Fast interrupt processing (within a minimum six CPU clocks) can be assigned to
specific interrupt levels.

S3C80E5/C80E7 MICROCONTROLLER

The S3C80E5/C80E7 single-chip CMOS
microcontroller is fabricated using a highly
advanced CMOS process, based on Samsung’s
newest CPU architecture.

The S3C80E5/C80E7 is the microcontroller which
has 16/24-Kbyte mask-programmable ROM. The
S3P80E5/P80E7 is the microcontroller which has
16/24-Kbyte one-time-programmable EPROM.

Using a proven modular design approach, Samsung
engineers developed the S3C80E5/C80E7 by
integrating the following peripheral modules with the
powerful SAM87 core:

— Four programmable I/O ports, including three

8-bit ports and one 2-bit port, for a total of 26
pins.

— Internal LVD circuit and twelve bit-

programmable pins for external interrupts.

— One 8-bit basic timer for oscillation stabilization

and watchdog functions (system reset).

— One 8-bit timer/counter and one 16-bit

timer/counter with selectable operating modes.

— One 8-bit counter with auto-reload function and

one-shot or repeat control.

The S3C80E5/C80E7 is a versatile general-purpose
microcontroller which is especially suitable for use
as unified remote transmitter controller. It is
currently available in a 32-pin SOP and SDIP
package for S3C80E5 and S3C80E7. And available
in 40 DIP package only for S3C80E7.

OTP

The S3P80E5/P80E7 is an OTP (One Time Programmable) version of the S3C80E5/C80E7 microcontroller. The
S3P80E5/P80E7 microcontroller has an on-chip 16/24-Kbyte one-time-programmable EPROM instead of a
masked ROM. The S3P80E5/P80E7 is comparable to the S3C80E5/C80E7, both in function and in pin
configuration.

1-1

PRODUCT OVERVIEW S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec)

FEATURES

CPU

• SAM87 CPU core

Memory

• 16-Kbyte internal program memory (ROM):
S3C80E5

• 24-Kbyte internal program memory (ROM):
S3C80E7

• 256-byte internal (RAM): 8000–80FFH

• Data memory: 317-byte internal register file

Instruction Set

• 78 instructions

• IDLE and STOP instructions added for power­down modes

Instruction Execution Time

• 750 ns at 8 MHz f

(minimum)

OSC

Interrupts

• Six interrupt levels and 18 interrupt sources

Carrier Frequency Generator

• One 8-bit counter with auto-reload function and
one-shot or repeat control (Counter A)

Back-up mode

• When reset pin is low level or when VDD is lower
than V

, the chip enters back-up mode to

LVD

reduce current consumption.

Low Voltage Detect Circuit

• Low voltage detect for reset or back-up mode
input.

• Low level detect voltage :

2.2 V (Typ) –100 mV/+ 200 mV

Operating Temperature Range

• – 40°C to + 85 °C

Operating Voltage Range

• 2.0 V to 5.5 V at 4 MHz f

• 2.1 V to 5.5 V at 8 MHz f

OSC
OSC

• 15 vectors (14 sources have a dedicated vector
address and four sources share a single vector)

• Fast interrupt processing feature (for one
selected interrupt level)

I/O Ports

• Three 8-bit I/O ports (P0–P2) and one 2-bit port
(P3) for a total of 26 bit-programmable pins

• Twelve input pins for external interrupts

Timers and Timer/Counters

• One programmable 8-bit basic timer (BT) for
oscillation stabilization control or watchdog timer
(software reset) function

• One 8-bit timer/counter (Timer 0) with three
operating modes; Interval, Capture, and PWM

• One 16-bit timer/counter (Timer 1) with two
operating modes; Interval and Capture

Package Type

• 32-pin SOP

• 32-pin SDIP

• 40-pin DIP

1-2

S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) PRODUCT OVERVIEW

BLOCK DIAGRAM

P0.0–P0.7

(INT0–INT4)

PORT 0

P1.0–P1.7

PORT 1

RESET

TEST

V

X

DD

X

IN

OUT

LVD

MAIN

OSC

8-BIT

BASIC

TIMER

8-BIT

TIMER/

COUNTER

16-BIT

TIMER/

COUNTER

INTERNAL BUS

I/O PORT and INTERRUPT

CONTROL

SAM87

CPU

PROGRAM

MEMORY

(16/24-Kbyte Program
Memory and 256-Byte

Program RAM)

317-BYTE

REGISTER

FILE

PORT2

PORT 3

CARRIER

GENERATOR

(COUNTER A)

P2.0–P2.3
(INT5–INT8)
P2.4–P2.7

P3.0/T0PWM/
T0CAP/T1CAP

P3.1/REM/T0CK

Figure 1-1. Block Diagram

1-3

PRODUCT OVERVIEW S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec)

PIN ASSIGNMENTS

V

SS

X

X

OUT

TEST
P2.0/INT5
P2.1/INT6
P2.2/INT7
P2.3/INT8
P0.0/INT0
P0.1/INT1
P0.2/INT2
P0.3/INT3
P0.4/INT4
P0.5/INT4
P0.6/INT4
P0.7/INT4

IN

1
2
3
4
5
6

S3C80E5

7

S3C80E7

8

32-SOP/SDIP

9
10

(Top View)

11
12
13
14
15
16

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

V

DD

RESET/BACK-UP MODE

P3.1/REM/T0CK
P3.0/T0PWM/T0CAP/T1CAP
P2.7
P2.6
P2.5
P2.4
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0

Figure 1-2. Pin Assignment (32-Pin SOP/SDIP Package)

V

SS

X

X

OUT

TEST

NC

NC
P2.0/INT5
P2.1/INT6
P2.2/INT7
P2.3/INT8
P0.0/INT0
P0.1/INT1
P0.2/INT2
P0.3/INT3

NC

NC
P0.4/INT4
P0.5/INT4
P0.6/INT4
P0.7/INT4

1

IN

2
3
4
5
6
7
8

S3C80E5

9

S3C80E7

10
11

40-DIP

12

(Top View)

13
14
15
16
17
18
19
20

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

V

DD

RESET/BACK-UP MODE

P3.1/REM/T0CK
P3.0/T0PWM/T0CAP/T1CAP

NC
NC
P2.7
P2.6
P2.5
P2.4
P1.7
P1.6
P1.5
P1.4
NC
NC
P1.3
P1.2
P1.1
P1.0

1-4

Figure 1-3. Pin Assignment (40-Pin DIP Package)

S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) PRODUCT OVERVIEW

Table 1-1. Pin Descriptions

Pin

Names

Pin

Type

Pin

Description

P0.0–P0.7 I/O I/O port with bit-programmable pins.

Configurable to input or push-pull output
mode. Pull-up resistors are assignable by
software. Pins can be assigned individually
as external interrupt inputs with noise filters,
interrupt enable/disable, and interrupt
pending control.

P1.0–P1.7 I/O I/O port with bit-programmable pins.

Configurable to C-MOS input mode or
output mode. Pin circuits are either push­pull or n-channel open-drain type. Pull-up
resistors are assignable by software.

P2.0–P2.3
P2.4–P2.7

I/O General-purpose I/O port with bit-

programmable pins. Configurable to C­MOS input mode, push-pull output mode, or
n-channel open-drain output mode. Pull-up
resistors are assignable by software. Lower
nibble pins, P2.3–P2.0, can be assigned as
external interrupt inputs with noise filters,
interrupt enable/disable, and interrupt
pending control.

Circuit

Type

1 9–16

2 17–24

3
4

Pin No.

(32-pin)

5–8,

25–28

Pin No.

(40-pin)

11–14,

17–20

21–24,

27–30

7–10,

31–34

Shared

Functions

INT0–INT4

–

INT5–INT8

–

P3.0
P3.1

I/O 2-bit I/O port with bit-programmable pins.

Configurable to C-MOS input mode, push­pull output mode, or n-channel open-drain
output mode. Pull-up resistors are
assignable by software. The two port 3 pins
have high current drive capability.

XIN, X

OUT

RESET/
BACK-UP
MODE

– System clock input and output pins – 2, 3 2, 3 –

I System reset signal input pin and back-up

mode input pin. The pin circuit is a C-MOS
input.

TEST I Test signal input pin (for factory use only;

must be connected to VSS).

V

DD

V

SS

– Power supply input pin – 32 40 –
– Ground pin – 1 1 –

5 29

30

37

38

T0PWM/

T0CAP/
T1CAP/

REM/T0CK

6 31 39 –

– 4 4 –

1-5

PRODUCT OVERVIEW S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec)

PIN CIRCUITS

V

DD

PULL-UP RESISTOR

(Typical 21 KΩ)

PULL-UP

ENABLE

V

DD

DATA

I/O

OUTPUT

DISABLE

INTERRUPT INPUT

IRQ6,7 (INT0-4)

NOTE:

To prevent and recover from abnormal stop status caused by battery bouncing, the S3P80E5
has a special logic_

input/output of universal remote controller. When these ports (P0, P1) are used as a normal
input pin, unexpected stop mode recovery can occur by input level switching. Hence, the user
should be aware of input level switching, if P0 and P1 are to be used as normal input ports.

STOP

V

NOISE

FILTER

NORMAL

INPUT

Oscillator Release (SED and R circuit)

SED and R circuit−related to P0 and P1. This is a specific function for key

SS

Figure 1-4. Pin Circuit Type 1 (Port 0)

1-6

S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) PRODUCT OVERVIEW

V

DD

PULL-UP RESISTOR

(Typical 21 KΩ)

PULL-UP

ENABLE

V

DD

DATA

I/O

OUTPUT

DISABLE

V

SS

NOTE:

NORMAL INPUT

STOP

NOISE

FILTER

Oscillator Release (SED and R circuit)

To prevent and recover from abnormal stop status caused by battery bouncing, the S3P80E5
has a special logic

SED and R circuit−related to P0 and P1. This is a specific function for key

−

input/output of universal remote controller. When these ports (P0, P1) are used as a normal
input pin, unexpected stop mode releasing can occur by input level switching. Hence, the user
should be aware of input level switching, if P0 and P1 are to be used as normal input ports.

Figure 1-5. Pin Circuit Type 2 (Port 1)

1-7

PRODUCT OVERVIEW S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec)

V

DD

PULL-UP RESISTOR

(Typical 21 KΩ)

PULL-UP

ENABLE

V

DD

DATA

I/O

OPEN-DRAIN

OUTPUT

DISABLE

V

SS

EXTERNAL

INTERRUPT

IRQ5 (INT5-8)

NOISE

FILTER

NORMAL INPUT

Figure 1-6. Pin Circuit Type 3 (Ports 2.0–2.3)

1-8

S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) PRODUCT OVERVIEW

V

DD

PULL-UP RESISTOR

(Typical 21 KΩ)

PULL-UP

ENABLE

V

DD

DATA

I/O

OPEN-DRAIN

OUTPUT

DISABLE

V

SS

NORMAL INPUT

Figure 1-7. Pin Circuit Type 4 (P2.4−−P2.7)

1-9

PRODUCT OVERVIEW S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec)

V

DD

PULL-UP RESISTOR

(Typical 21 KΩ)

PULL-UP

ENABLE

PORT 3 DATA

SELECT

M

DATA

V

DD

U

ALTERNATIVE

X

OUTPUT

I/O

OPEN-DRAIN

OUTPUT

DISABLE

NORMAL INPUT

ALTERNATIVE

INPUT

RESET/

BACK-UP

MODE

Figure 1-9. Pin Circuit Type 6 (RESETRESET/BACK-UP MODEBACK-UP MODE)

NOISE
FILTER

Figure 1-8. Pin Circuit Type 5 (P 3)

NOISE

FILTER

V

SS

BACK-UP MODE

SYSTEM

RESET

1-10

S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) ELECTRICAL DATA

14 ELECTRICAL DATA

OVERVIEW

In this section, the S3C80E5/C80E7 electrical characteristics are presented in tables and graphs. The information
is arranged in the following order:

— Absolute maximum ratings
— D.C. electrical characteristics
— Characteristics of low voltage detect circuit
— Data retention supply voltage in Stop mode
— Stop mode release timing when initiated by an external interrupt

— Stop mode release timing when initiated by a RESET
— Stop mode release timing when initiated by a LVD
— I/O capacitance
— A.C. electrical characteristics
— Input timing for external interrupts (port 0, P2.3–P2.0)

— Input timing for RESET
— Oscillation characteristics
— Oscillation stabilization time
— Operating voltage range

14-1

ELECTRICAL DATA S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec)

Table 14-1. Absolute Maximum Ratings

(TA = 25 °C)

Parameter Symbol Conditions Rating Unit

Supply voltage
Input voltage
Output voltage
Output current High

V

DD

V

IN

I

V

O

OH

All output pins
One I/O pin active – 18 mA

– – 0.3 to + 6.5 V
–

– 0.3 to VDD + 0.3

– 0.3 to VDD + 0.3

V
V

All I/O pins active – 60

Output current Low

I

OL

One I/O pin active + 30 mA
Total pin current for ports 0, 1, and 2 + 100

Total pin current for port 3 + 40

Operating

T

A

– – 40 to + 85

°

C

temperature
Storage

T

STG

– – 65 to + 150

°

C

temperature

Table 14-2. D.C. Electrical Characteristics

(T

= – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V)

A

Parameter Symbol Conditions Min Typ Max Unit

Operating Voltage

V

DD

f

OSC

8 MHz

=

2.1 – 5.5 V

(Instruction clock = 1.33 MHz)
f

OSC

4 MHz

=

2.0 – 5.5

(Instruction clock = 0.67 MHz)

Input High
voltage

Input Low voltage

Output High
voltage

V

V

V
V
V
V
V
V

IH1
IH2
IH3
IL1
IL2
IL3

OH1

OH2

All input pins except V

RESET

X

IN

All input pins except V

RESET

X

IN

V

= 2.4 V; IOH = – 6 mA

DD

Port 3.1 only; T
V

= 2.4 V; I

DD

Port 3.0 only; T

= 25 °C

A

= – 3 mA

OH

= 25 °C

A

IH2

IL2

and V

and V

IH3

IL3

0.8 V

DD

0.85 V

DD

V

– 0.3 V

DD

–

0 –

V

– 0.7

DD

V

– 0.7

DD

– – V

V

DD

V

DD
DD

0.2 V

0.4 V

0.3

DD
DD

V

V

14-2

S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) ELECTRICAL DATA

Table 14-2. D.C. Electrical Characteristics (Continued)

(T

= – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V)

A

Parameter Symbol Conditions Min Typ Max Unit

Output High
voltage

V

V

OH3

OH4

V

= 5 V; I

DD

Port 2.7 only; T
V

= 2 V; IOH = – 1 mA

DD

Port 2.7 only; T
V

= 3.0 V; IOH = – 1 mA

DD

= – 3 mA

OH

A

A

= 25°C

= 25°C

V

DD

V

– 0.25

DD

– 1

– – V

All output pins except P3 and P2.7

Output Low
voltage

Input High
leakage current

Input Low
leakage current

V

V

V

I

I

I

OL1

OL2

OL3

LIH1

LIH2
LIL1

port; T
V

DD

Port 3.1 only; T
V

DD

Port 3.0 only; T
I

OL

Port 0, 1, and 2; T
VIN = V

All input pins except X
VIN = VDD, X
V

IN

All input pins except XIN, X

= 25°C

A

= 2.4 V; IOL = 15 mA

= 25°C

A

= 2.4 V; IOL = 5 mA

= 25°C

A

= 1 mA

= 25°C

A

DD

and X

IN,

= 0 V

IN

OUT

and X

OUT

– 0.4 0.5 V

0.4 0.5

0.4 1

– – 1 µA

OUT

20

– – – 1 µA

,

and RESET

Output High
leakage current

Output Low
leakage current

Pull-up resistors

I

LIL2

I

LOH

I

LOL

R

L1

V

= 0 V

IN

X

and X

V

IN

OUT

= V

OUT

DD

All output pins
V

= 0 V

OUT

All output pins
V

= 0 V; V

IN

T

= 25 °C; Ports 0–3

A

V

= 5.5 V

DD

DD

= 2.4 V

– 20

– – 1 µA

– – – 1 µA

44 55 82

15 21 32

kΩ

14-3

ELECTRICAL DATA S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec)

Table 14-2. D.C. Electrical Characteristics (Concluded)

(T

= – 40 °C to + 85 °C, VDD = 2 V to 5.5 V)

A

Parameter Symbol Conditions Min Typ Max Unit

Supply current

(note)

I

DD1

Operating mode
V

= 5 V ± 10 %

DD

– 6 11 mA

8 MHz crystal
4 MHz crystal 4.5 9

I

DD2

Idle mode

1.8 3.5

VDD = 5 V ± 10 %
8 MHz crystal

4 MHz crystal 1.6 3

I

DD3

Stop mode
V

= 6.0 V

DD

V

= 5.5 V

DD

V

= 3.3 V

DD

V

= 0.7 V

DD

20 35

18 25
12 15

1.0 1.5

µA

NOTE: Supply current does not include the current drawn through internal pull-up resistors or external output current loads.

Table 14-3. Characteristics of Low Voltage Detect Circuit

(TA = – 40 °C to + 85 °C)

Parameter Symbol Conditions Min Typ Max Unit

Hysteresys Voltage of

∆V

LVDCON = 10001111B – 10 100 mV

LVD(Slew Rate of LVD)
Low level detect voltage

NOTE: The reset values of bit 1 and bit 0 are in a unknown status, so is recommended to input the value #8FH in LVDCON

for typical V

(2.2 V –100/+200 mV).

LVD

V

LVD

LVDCON = 10001111B 2.10 2.20 2.40 V

Table 14-4. Data Retention Supply Voltage in Stop Mode

(TA = – 40 °C to + 85 °C)

Parameter Symbol Conditions Min Typ Max Unit

Data retention supply

V

DDDR

– 1.0 – 5.5 V

voltage
Data retention supply

current

I

DDDR

V

= 1.0 V

DDDR

Stop mode

– – 1 µA

14-4

S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) ELECTRICAL DATA

IDLE MODE

(Basic Timer active)

~

~

STOP MODE

NORMAL
OPERATING

DATA RETENTION MODE

V

DD

~

~

V

DD > VLVD

MODE

EXECUTION OF

STOP INSTRUCTION

EXT

INT

0.2 V

DD

t

WAIT

0.8 V

DD

V

DD

RESET

NOTE:

Figure 14-1. Stop Mode Release Timing When Initiated by an External Interrupt

OSCILLATION

STABILIZATION

EXECUTION OF

STOP INSTRUCTION

t

is the same as 4096 x 16 x

WAIT

RESET

OCCURS

~

~

~

~

1/f

STOP MODE

DATA RETENTION MODE

V

DD > VLVD

.

OSC

t

WAIT

TIME

NORMAL
OPERATING
MODE

Figure 14-2. Stop Mode Release Timing When Initiated by a RESETRESET

14-5

ELECTRICAL DATA S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec)

OSCILLATION

STABILIZATION

NORMAL
OPERATING
MODE

t

WAIT

V

V

LVD

DD

~

~

~

EXECUTION OF

STOP INSTRUCTION

t

NOTE:

is the same as 4096 x 16 x 1/f

WAIT

RESET OCCUR

~

STOP MODE

BACK-UP MODE

~

~

V

DDDR

DATA RETENTION MODE

.

OSC

(T

= – 40 °C to + 85 °C, V

A

Parameter Symbol Conditions Min Typ Max Unit

Input capacitance

Output capacitance
I/O capacitance

(T

= – 40 °C to + 85 °C)

A

Parameter Symbol Conditions Min Typ Max Unit

Interrupt input, High,
Low width

RESET input Low
width

Figure 14-3. Stop Mode Release Timing When Initiated by a LVD

Table 14-5. Input/output Capacitance

= 0 V)

DD

C

C

OUT

C

IN

IO

f = 1 MHz; unmeasured pins
are connected to V

SS

– – 10 pF

Table 14-6. A.C. Electrical Characteristics

t

INTH

t

INTL

t

RSL

P0.0–P0.7, P2.3–P2.0

,

V

= 5 V

DD

Input
V

= 5 V

DD

200 300 – ns

1000 – –

14-6

S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) ELECTRICAL DATA

NOTE

t

INTL

0.2 V

: The unit t

0.8 V

DD

means one CPU clock period.

CPU

DD

t

INTH

Figure 14-4. Input Timing for External Interrupts (Port 0, P2.3–P2.0)

RESET

NORMAL

OCCRURRS

OPERATING
MODE

Back-Up Mode (STOP MODE)

V

DD

OSCILLATION
STABILIZATION
TIME

NORMAL
OPERATING
MODE

RESET

NOTE:

t

is the same as 4096 x 16 x 1/f

WAIT

t

WAIT

.

OSC

Figure 14-5. Input Timing for RESETRESET

14-7

ELECTRICAL DATA S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec)

S3C80E5

S3C80E7

Table 14-7. Oscillation Characteristics

(TA = – 40 °C + 85 °C)

Oscillator Clock Circuit Conditions Min Typ Max Unit

Crystal

Ceramic

External clock

C1

C2

C1

C2

EXTERNAL

CLOCK
OPEN PIN

X

X

IN

OUT

X

X

X

X

IN

OUT

IN

OUT

CPU clock oscillation
frequency

CPU clock oscillation
frequency

X

input frequency

IN

1 – 8 MHz

1 – 8 MHz

1 – 8 MHz

Table 14-8. Oscillation Stabilization Time

(T

= – 40 °C + 85 °C, VDD = 4.5 V to 5.5 V)

A

Oscillator Test Condition Min Typ Max Unit

f

Main crystal
Main ceramic

> 400 kHz

OSC

Oscillation stabilization occurs when VDD is equal

– – 20 ms
– – 10 ms

to the minimum oscillator voltage range.

External clock

XIN input High and Low width (tXH, tXL)

25 – 500 ns

(main system)
Oscillator

t

when released by a reset

WAIT

(1)

–

216/f

OSC

– ms

stabilization
Wait time

t

when released by an interrupt

WAIT

(2)

– – – ms

NOTES:

1. f

is the oscillator frequency.

OSC

2. The duration of the oscillation stabilization time (t
in the basic timer control register, BTCON.

14-8

) when it is released by an interrupt is determined by the setting

WAIT

S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) ELECTRICAL DATA

f

INSTRUCTION

CLOCK

OSC

(Main oscillation
frequency)

1.33 MHz

1.00 MHz

670 kHz

500 kHz

250 kHz

8.32 kHz

8 MHz

6 MHz

4 MHz

400 kHz

1 2 3 4 5 6 7

2.1 5.5

SUPPLY VOLTAGE (V)

INSTRUCTION CL OCK = 1/6n x oscillator frequency (n = 1, 2, 8, 16)

Figure 14-6. Operating Voltage Range of S3P80E5/P80E7

14-9

S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) MECHANICAL DATA

± 0.20

15 MECHANICAL DATA

OVERVIEW

The S3C80E5/C80E7 microcontroller is currently available in 32-pin SOP and SDIP package. The S3C80E7 is
also available in 40 DIP package.

0−8°

#32 #17

12.00 ± 0.2

#1 #16

(0.43) 0.40

NOTE: Dimensions are in millimeters.

Figure 15-1. 32-Pin SOP Package Mechanical Data

32-SOP-450A

19.90

± 0.05

± 0.1

1.27

0.25

± 0.1

2.00

0.10 MAX

0.05 MIN

8.34 ± 0.2

+0.10

- 0.05

2.30MAX

10.02 ± 0.1

0.90

15-1

MECHANICAL DATA S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec)

#32 #17

0.20

±

9.10

32-SDIP-400

10.16

+0.1

0.25

0 – 15

0.05

–

*

#1 #16

29.80 MAX

±

29.40

0.2

3.80 ± 0.2

5.08MAX

(1.37)

0.45 ± 0.10

1.00 ± 0.10

1.778

NOTE: Dimensions are in millimeters.

Figure 15-2. 32-Pin SDIP Package Mechanical Data

0.51MIN

0.3

±

3.30

15-2

S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) MECHANICAL DATA

#40 #21

40-DIP-600B

13.80

± 0.2

#1 #20

52.10

± 0.2

52.42

± 0.2

15.24

4.10

± 0.2

5.08MAX

+ 0.1
– 0.05

0.25

(1.92)

1.27

± 0.1

NOTE: Dimensions are in millimeters.

Figure 15-3. 40-Pin DIP Package Mechanical Data

2.54

0.3 MIN

3.30

± 0.3

15-3

S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) S3P80E5/P80E7 OTP

16 S3P80E5/P80E7 OTP

OVERVIEW

The S3P80E5/P80E7 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the

S3C80E5/C80E7microcontroller. It has an on-chip EPROM instead of a masked ROM.
The S3P80E5/P80E7 is fully compatible with the S3C80E5/C80E7, both in function and in pin configuration.

Because of its simple programming requirements, the S3P80E5/P80E7 is ideal as an evaluation chip for the
S3C80E5/C80E7.

PGM

MEM_REG

A8
A9
A0
A1
A2
A3
A4
A5
A6
A7

NOTES:

1. The bolds indicate an OTP pin name.

2. The address line 14 (A14) be used only for S3P80E7.

(2)

A14

/TEST

MODE

/P2.0/INT5
/P2.1/INT6
/P2.2/INT7
/P2.3/INT8
/P0.0/INT0
/P0.1/INT1
/P0.2/INT2
/P0.3/INT3
/P0.4/INT4
/P0.5/INT4
/P0.6/INT4
/P0.7/INT4

/X

V

X

OUT

SS

1

IN

2
3
4
5
6

S3P80E5

7

S3P80E7

8

32-SOP/SDIP

9

(Top View)

10
11
12
13
14
15
16

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

V

DD

RESET/
P3.1/REM/T0CK/
P3.0/T0PWM/T0CAP/T1CAP/

P2.7/
P2.6/
P2.5/
P2.4/
P1.7/
P1.6/
P1.5/
P1.4/
P1.3/
P1.2/
P1.1/
P1.0/

VPP

CE

A13
A12
A11
A10
D7
D6
D5
D4
D3
D2
D1
D0

OE

Figure 16-1. S3P80E5/P80E7 Pin Assignments of 32SOP/32SDIP

16-1

S3P80E5/P80E7 OTP S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec)

PGM

MEM_REG

A8
A9
A0
A1
A2
A3

A4
A5
A6
A7

A14

/TEST

MODE

/P2.0/INT5
/P2.1/INT6
/P2.2/INT7
/P2.3/INT8
/P0.0/INT0
/P0.1/INT1
/P0.2/INT2
/P0.3/INT3

/P0.4/INT4
/P0.5/INT4
/P0.6/INT4
/P0.7/INT4

NOTES:

/X

V

X

OUT

NC
NC

NC
NC

SS

IN

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

S3P80E5
S3P80E7

40-DIP

(Top View)

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

V

DD

RESET/
P3.1/REM/T0CK/
P3.0/T0PWM/T0CAP/T1CAP/
NC
NC
P2.7/
P2.6/
P2.5/
P2.4/
P1.7/
P1.6/
P1.5/
P1.4/
NC
NC
P1.3/
P1.2/
P1.1/
P1.0/

1. The bolds indicate an OTP pin name.

2. The address line 14 (A14) be used only for S3P80E7.

VPP

CE

OE

A13
A12
A11
A10
D7
D6
D5
D4

D3
D2
D1
D0

16-2

Figure 16-2. S3P80E5/P80E7 Pin Assignments of 40DIP

S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) S3P80E5/P80E7 OTP

Table 16-1. 32 SOP/SDIP Pin Descriptions Used to Read/Write the EPROM

Pin Name Pin No. I/O Function

A0–A14 3, 7– 6, 25–28 O Address lines to read/write EPROM
D0–D7 17–24 I/O 8-bit data input/output lines to read/write EPROM
MODE 4 – Select EPROM mode.

CE
OE
PGM

MEM_REG
V

DD

V

PP

V

SS

X

IN

30 I
29 I Output enable

5 I EPROM Program enable

6 I Select Memory space of EPROM
32 – Supply voltage (normally 5 V)
31 – EPROM Program/Verify voltage (normally 12.5 V)

1 – GROUND

2 – System Clock input pin

Chip enable (Connect to V

, when read/write EPROM)

SS

CHARACTERISTICS OF EPROM OPERATION

When +12.5 V is supplied to V

and MODE pins of the S3P80E5/P80E7, the EPROM programming mode is

PP

entered. The operating mode (read, write) is selected according to the input signals to the pins listed in Table 16­2 as below.

Table 16-2. Operating Mode Selection Criteria

V

5 V

DD

MODE

V

PP

V

PP

PGMPGM MEMMEM OEOE

12.5 V 1 1 0 READ

Mode

0 1 1 PROGRAM
1 1 0 PROGRAM VERIFY

NOTE: "0" means Low level; "1" means High level.

16-3

S3P80E5/P80E7 OTP S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec)

A14−−A0

t

OED

D7−−D0

t

OE

MODE

ACC

t

OEW

t

OEH

12.5V

Figure 16-3. OTP Read Timing

Table 16-3. OTP Read Characteristics

(T

= 25 °C ± 5 °C, V

A

Parameter Symbol Min Typ Max Units

Address to Output Delay

OE to Address Delay
OE Pulse Width

Output hold from OE
whichever occurs first

= 5 V ± 5 %, VPP = 12.5 V ± 0.25V)

DD

t

ACC

t

OED

t

OEW

T

OEH

– – 75 ns
0 – –

75 – –

0 – –

16-4

S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) S3P80E5/P80E7 OTP

PROGRAM VERIFYPROGRAM

A14−−A0

D7−−D0

MODE

PGM

OE

Data In Stable Data Out Valid

t

DS

t

VS

t

PW

Figure 16-4. Program Memory Write Timing

Table 16-4. OTP Program/Program Verify Characteristics

(T

= 25 °C ± 5 °C, V

A

= 5 V ± 5 %, VPP = 12.5 V ± 0.25 V)

DD

Parameter Symbol Min Typ Max Units

VPP Setup Time t
Data Setup Time
Data Hold Time

PGM Pulse Width
Data Valid from OE
OE Pulse Width

Output Enable to Output Float
Delay

VS

t

DS

t

DH

t

PW

t

OE

t

OEW

t

OEH

t

DH

t

OEH

t

OE

t

OEW

– 2 – µs
– 2 –
– 2 –

– 300 500
75 – – ns
75 – –

0 – 130

16-5

S3P80E5/P80E7 OTP S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec)

START

Address= First Location

VDD=5V, VPP=12.5V

x = 0

Program One 1ms Pulse

Increment X

FAIL

Device Failed

Verify Byte

YES

x = 10

NO

FAIL

NO

FAIL

Verify 1 Byte

Last Address

V

= VPP= 5 V

DD

Compare All Byte

PASS

Device Passed

Figure 16-5. OTP Programming Algorithm

Increment Address

16-6

S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) S3P80E5/P80E7 OTP

Table 16-5. D.C. Electrical Characteristics

(T

= – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V)

A

Parameter Symbol Conditions Min Typ Max Unit

Operating Voltage

V

DD

f

OSC

8 MHz

=

2.1 – 5.5 V

(Instruction clock = 1.33 MHz)
f

OSC

4 MHz

=

2.0 – 5.5

(Instruction clock = 0.67 MHz)

Input High
voltage

Input Low voltage

Output High
voltage

Output High
voltage

V

V

V

V

V
V
V

V
V
V

IH1
IH2
IH3

OH1

OH2

OH3

OH4

All input pins except V

RESET

X

IN

All input pins except V

IL1

RESET

IL2

X

IL3

IN

V

= 2.4 V; IOH = – 6 Ma

DD

Port 3.1 only; T
V

= 2.4 V; I

DD

Port 3.0 only; T
V

= 5 V; I

DD

Port 2.7 only; T
V

= 2 V; IOH = – 1 mA

DD

Port 2.7 only; T
V

= 3.0 V; IOH = – 1 mA

DD

A

OH

A

= – 3 mA

OH

A

A

IH2

IL2

= 25 °C

= – 3 mA

= 25 °C

= 25 °C

= 25 °C

and V

and V

IH3

IL3

0.8 V

DD

0.85 V

DD

V

– 0.3 V

DD

0 –

V

– 0.7

DD

V

– 0.7

DD

V

– 0.25

DD

V

– 1

DD

–

V

DD

V

DD
DD

0.2 V

0.4 V

DD
DD

0.3

– – V

– – V

V

V

All output pins except P3 and P2.7

Output Low
voltage

Input High
leakage current

V

V

V

I

I

OL1

OL2

OL3

LIH1

LIH2

port; T
V

DD

Port 3.1 only; T
V

DD

Port 3.0 only; T
I

OL

Port 0, 1, and 2; T
VIN = V

All input pins except X
VIN = VDD, XIN, and X

= 25 °C

A

= 2.4 V; IOL = 15 mA

= 25 °C

A

= 2.4 V; IOL = 5 mA

= 25 °C

A

= 1 mA

= 25 °C

A

DD

IN

OUT

and X

– 0.4 0.5 V

0.4 0.5

0.4 1

– – 1 µA

OUT

20

16-7

S3P80E5/P80E7 OTP S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec)

Table 16-5. D.C. Electrical Characteristics (Continued)

(T

= – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V)

A

Parameter Symbol Conditions Min Typ Max Unit

Input Low
leakage current

I

LIL1

V

= 0 V

IN

All input pins except XIN, X

OUT

– – – 1 µA

, and

RESET

Output High
leakage current

Output Low
leakage current

Pull-up resistors

Supply current

(note)

I

LIL2

I

LOH

I

LOL

R

I

DD1

V

IN

X
V

OUT

All output pins
V

OUT

All output pins
V

L1

IN

T

A

V

DD

Operating mode
V

DD

= 0 V

and X

IN

= 0 V; V

= 25 °C; Ports 0–3

OUT

= V

DD

= 0 V

= 2.4 V

DD

= 5.5 V

= 5 V ± 10 %

– 20

– – 1 µA

– – – 1 µA

44 55 82

15 21 32

– 6 11 mA

kΩ

8 MHz crystal
4 MHz crystal 4.5 9

I

DD2

Idle mode

1.8 3.5

VDD = 5 V ± 10 %
8 MHz crystal

4 MHz crystal 1.6 3

I

DD3

Stop mode;
V

= 6.0 V

DD

V

= 5.5 V

DD

V

= 3.3 V

DD

V

= 0.7 V

DD

20 35

18 25
12 15

1.0 1.5

µA

NOTE: Supply current does not include the current drawn through internal pull-up resistors or external output current loads.

16-8

S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) S3P80E5/P80E7 OTP

(Main oscillation

f

INSTRUCTION

CLOCK

OSC

frequency)

1.33 MHz

1.00 MHz

670 kHz

500 kHz

250 kHz

8.32 kHz

8 MHz

6 MHz

4 MHz

400 kHz

1 2 3 4 5 6 7

2.1 5.5

SUPPLY VOLTAGE (V)

INSTRUCTION CL OCK = 1/6n x oscillator frequency (n = 1, 2, 8, 16)

Figure 16-6. Operating Voltage Range

16-9