Datasheet S3C72F5, S3P72F5 Datasheet (Samsung)

S3C72F5/P72F5 PRODUCT OVERVIEW

1 PRODUCT OVERVIEW

OVERVIEW

The S3C72F5 single-chip CMOS microcontroller has been designed for high performance using Samsung's
newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).

With an up-to-896-dot LCD direct drive capability, 8-bit and 16-bit timer/counter, and serial I/O, the S3C72F5
offers an excellent design solution for a wide variety of applications which require LCD functions.

Up to 39 pins of the 100-pin QFP package can be dedicated to I/O. Eight vectored interrupts provide fast
response to internal and external events. In addition, the S3C72F5's advanced CMOS technology provides for
low power consumption and a wide operating voltage range.

OTP

The S3C72F5 microcontroller is also available in OTP (One Time Programmable) version, S3P72F5. S3P72F5
microcontroller has an on-chip 16K-byte one-time-programable EPROM instead of masked ROM. The S3P72F5
is comparable to S3C72F5, both in function and in pin configuration.

PRODUCT OVERVIEW S3C72F5/P72F5

FEATURES SUMMARY

Memory

• 544 × 4-bit RAM (excluding LCD display RAM)

• 16,384 × 8-bit ROM

39 I/O Pins

• I/O: 35 pins

• Input only: 4 pins

LCD Controller/Driver

• 56 segments and 16 common terminals

• 8 and 16 common selectable

• Internal resistor circuit for LCD bias

• All dot can be switched on/off

8-bit Basic Timer

• 4 interval timer functions

• Watch-dog timer

8-bit Timer/Counter

• Programmable 8-bit timer

• External event counter

• Arbitrary clock frequency output

• External clock signal divider

• Serial I/O interface clock generator

16-Bit Timer/Counter

• Programmable 16-bit timer

• External event counter

• Arbitrary clock frequency output

• External clock signal divider

Watch Timer

• Time interval generation: 0.5 s, 3.9 ms
at 32768 Hz

• 4 frequency outputs to BUZ pin

• Clock source generation for LCD

Interrupts

• Four internal vectored interrupts

• Four external vectored interrupts

• Two quasi-interrupts

Bit Sequential Carrier

• Supports 16-bit serial data transfer in arbitrary
format

Power-Down Modes

• Idle mode (only CPU clock stops)

• Stop mode (main system oscillation stops)

• Subsystem clock stop mode

Oscillation Sources

• Crystal, ceramic, or RC for main system clock

• Crystal oscillator for subsystem clock

• Main system clock frequency: 0.4 – 6 MHz

• Subsystem clock frequency: 32.768 kHz

• CPU clock divider circuit (by 4, 8, or 64)

Instruction Execution Times

• 0.67, 1.33, 10.7 µs at 6 MHz

• 0.95, 1.91, 15.3 µs at 4.19 MHz

• 122 µs at 32.768 kHz

8-bit Serial I/O Interface

• 8-bit transmit/receive mode

• 8-bit receive mode

• LSB-first or MSB-first transmission selectable

• Internal or external clock source

Memory-Mapped I/O Structure

• Data memory bank 15

1–2

Operating Temperature

• – 40 °C to 85 °C

Operating Voltage Range

• 1.8 V to 5.5 V

Package Type

• 100-pin QFP

S3C72F5/P72F5 PRODUCT OVERVIEW

BLOCK DIAGRAM

P1.0-P1.3/

INT0-INT4

P2.0/CLO

P2.1/LCDCK

P2.2/LCDSY

P3.0/TCLO0
P3.1/TCLO1

P3.2/TCL0
P3.3/TCL1

P4.0–P4.3/

COM8-COM11

P5.0–P5.3/

COM12-COM15

P6.0–P6.3/

SEG55-SEG52/

KS4–KS7

P7.0–P7.3/

SEG51-SEG48

P8.0–P8.3/

SEG47-SEG44

P9.0–P9.3/

SEG43-SEG40

INPUT PORT 1

I/O PORT 2

I/O PORT 3

I/O PORT 4

I/O PORT 5

I/O PORT 6

I/O PORT 7

I/O PORT 8

I/O PORT 9

RESET

INTERRUPT

CONTROL

BLOCK

INTERNAL

INTERRUPTS

INSTRUCTION

ARITHMETIC

LOGIC UNIT

544 x 4-BIT

DATA

MEMORY

AND

Xin

XTin

CLOCK

Xout

XTout

BASIC

TIMER

INSTRUCTION

REGISTER

PROGRAM
COUNTER

PROGRAM

STATUS

WORD

STACK

POINTER

16 KBYTE

PROGRAM

MEMORY

WATCH

TIMER

LCD

DRIVER/

CONTROLLER

SERIAL I/O

I/O

PORT 0

8-BIT

TIMER/

COUNTER

16-BIT

TIMER/

COUNTER

VLC1-VLC5
COM0-COM7
P4.0-P5.3/

COM8-COM15
SEG0-SEG39
P9.3-P6.0/

SEG40-SEG55

P0.0/SCK/K0
P0.1/SO/K1
P0.2/SI/K2
P0.3/BUZ/K3

Figure 1-1. S3C72F5 Simplified Block Diagram

PRODUCT OVERVIEW S3C72F5/P72F5

PIN ASSIGNMENTS

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

47

48

49

81

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

50

SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
P9.3/SEG40
P9.2/SEG41
P9.1/SEG42
P9.0/SEG43
P8.3/SEG44
P8.2/SEG45
P8.1/SEG46
P8.0/SEG47
P7.3/SEG48
P7.2/SEG49
P7.1/SEG50
P7.0/SEG51
P6.3/SEG52/K7
P6.2/SEG53/K6
P6.1/SEG54/K5

SEG4
SEG3
SEG2
SEG1
SEG0

VLC5
VLC4
VLC3
VLC2
VLC1

P0.0/

P0.3/BUZ/K3

P2.1/LCDCK
P2.2/LCDSY

P3.0/TCLO0

/K0

SCK

P0.1/SO/K1

P0.2/SI/K2

VDD

VSS
Xout

Xin

TEST

XTin

XTout

RESET

P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT4

P2.0/CLO

100

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

31

32

33

34

S3C72F5

(100-QFP-1420C)

35

36

37

38

39

40

41

42

43

44

45

46

1–4

COM0

COM1

COM2

COM3

COM4

COM5

COM6

COM7

P3.2/TCL0

P3.3/TCL1

P3.1/TCLO1

P4.0/COM8

P4.1/COM9

P4.2/COM10

P4.3/COM11

P5.0/COM12

P5.1/COM13

P5.2/COM14

P5.3/COM15

P6.0/SEG55/K4

Figure 1-2. S3C72F5 100-QFP Pin Assignment Diagram

S3C72F5/P72F5 PRODUCT OVERVIEW

PIN DESCRIPTIONS

Table 1–1. S3C72F5 Pin Descriptions

Pin Name Pin Type Description Number Share Pin

P0.0
P0.1
P0.2
P0.3

P1.0
P1.1
P1.2
P1.3

P2.0
P2.1
P2.2

P3.0
P3.1
P3.2
P3.3

P4.0–P4.3
P5.0–P5.3

P6.0–P6.3

I/O 4-bit I/O port.

1-bit and 4-bit read/write and test are possible.
Individual pins are software configurable as input or
output.
Individual pins are software configurable as open­drain or push-pull output.
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.

I 4-bit input port.

1-bit and 4-bit read and test are possible.
4-bit pull-up resistors are assignable by software.

I/O Same as port 0 except that port 2 is 3-bit I/O port. 27

I/O Same as port 0. 30

I/O 4-bit I/O ports.

1-, 4-bit or 8-bit read/write and test are possible.
Individual pins are software configurable as input or
output.
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.

I/O Same as P4, P5. 50–53

11
12
13
14

23
24
25
26

28
29

31
32
33

42–45
46–49

SCK/K0

SO/K1

SI/K2

BUZ/K3

INT0
INT1
INT2
INT4

CLO
LCDCK
LCDSY

TCLO0
TCLO1

TCL0
TCL1

COM8–
COM11

COM12–

COM15

SEG55/K4–

SEG52/K7

P7.0–P7.3

P8.0–P8.3
P9.0–P9.3

SCK

SO I/O Serial data output. 12 P0.1/K1
SI I/O Serial data input. 13 P0.2/K2
BUZ I/O 2 kHz, 4 kHz, 8 kHz or 16 kHz frequency output for

INT0, INT1 I External interrupts. The triggering edge for INT0 and

I/O Same as P4, P5. 58–61

I/O Serial I/O interface clock signal. 11 P0.0/K0

buzzer signal.

INT1 is selectable.

54–57

62–65

14 P0.3/K3

23, 24 P1.0, P1.1

SEG51–

SEG48

SEG47–

SEG44

SEG43–

SEG40

PRODUCT OVERVIEW S3C72F5/P72F5

Table 1–1. S3C72F5 Pin Descriptions (Continued)

Pin Name Pin Type Description Number Share Pin

INT2 I Quasi-interrupt with detection of rising or

25 P1.2

falling edges.

INT4 I External interrupt with detection of rising or

26 P1.3

falling edges.
CLO I/O Clock output . 27 P2.0
LCDCK I/O LCD clock output for display expansion. 28 P2.1
LCDSY I/O LCD synchronization clock output for display

29 P2.2

expansion.
TCLO0 I/O Timer/counter 0 clock output. 30 P3.0
TCLO1 I/O Timer/counter 1 clock output. 31 P3.1
TCL0 I/O External clock input for timer/counter 0. 32 P3.2
TCL1 I/O External clock input for timer/counter 1. 33 P3.3
COM0–COM7 O LCD common signal output. 34–41 –
COM8–COM11 I/O 42–45 P4.0–P4.3
COM12–COM15 46–49 P5.0–P5.3
SEG0–SEG39 O LCD segment signal output. 5–1,

–

100–66
SEG40–SEG43 I/O 65–62 P9.3–P9.0
SEG44–SEG47 61–58 P8.3–P8.0
SEG48–SEG51 57–54 P7.3–P7.0
SEG52–SEG55 53–50 P6.3/K7–P6.0/K4
K0–K3 I/O External interrupt. The triggering edge is

11–14 P0.0–P0.3

selectable.
K4–K7 50–53 P6.0–P6.3
V

DD

V

SS

RESET

V

LC1–VLC5

X

in, Xout

– Main power supply. 15 –
– Ground. 16 –

I Reset signal. 22 –
– LCD power supply. 10–6 –
– Crystal, Ceramic or RC oscillator pins for

18, 17 –

system clock.

XT

in, XTout

– Crystal oscillator pins for subsystem clock. 20, 21 –

TEST I Test signal input. (must be connected to VSS) 19 –

NOTE: Pull-up resistors for all I/O ports are automatically disabled if they are configured to output mode.

1–6

S3C72F5/P72F5 PRODUCT OVERVIEW

Table 1–2. Overview of S3C72F5 Pin Data

Pin Names Share Pins I/O Type Reset Value Circuit Type

P0.1, P0.3 SO/K1, BUZ/K3 I/O Input E-1
P0.0, P0.2

SCK/K0, SI/K2

I/O Input E-2

P1.0–P1.3 INT0–INT2, INT4 I Input A-3
P2.0–P2.2 CLO, LCDCK, LCDSY I/O Input E
P3.0–P3.1 TCLO0, TCLO1 I/O Input E
P3.2–P3.3 TCL0, TCL1 I/O Input E-1
P4.0–P4.3

P5.0–P5.3
P6.0–P6.3 SEG55/K4–SEG52/K7

COM8–COM11
COM12–COM15

I/O Input H-13

I/O

Input

H-16

P7.0–P7.3 SEG51–SEG48 I/O Input H-13
P8.0–P8.3

P9.0–P9.3

SEG47–SEG44
SEG43–SEG40

I/O

Input

H-13

COM0–COM7 – O High H-3
SEG0–SEG39 – O High H-15
V

DD

V

SS

RESET

V

LC1–VLC5

X

in, Xout

XT

in, XTout

– – – –
– – – –
– I – B
– – – –
– – – –
– – – –

TEST – I – –

PRODUCT OVERVIEW S3C72F5/P72F5

PIN CIRCUIT DIAGRAMS

V

DD

V

DD

IN

Figure 1-3. Pin Circuit Type A

P-CHANNEL

V

DD

PULL-UP
RESISTOR

P-CHANNEL

N-CHANNEL

PULL-UP
RESISTOR
ENABLE

DATA

PULL-UP
RESISTOR

IN

SCHMITT TRIGGER

Figure 1-5. Pin Circuit Type B

V

DD

P-CHANNEL

OUT

1–8

IN

SCHMITT TRIGGER

Figure 1-4. Pin Circuit Type A-3

N-CHANNEL

OUTPUT
DISABLE

Figure 1-6. Pin Circuit Type C

S3C72F5/P72F5 PRODUCT OVERVIEW

VDD

VDD

PULL-UP

PNE

RESISTOR

DATA

OUTPUT

DISABLE

PNE

P-CH

N-CH

CIRCUIT TYPE A

Figure 1-7. Pin Circuit Type E

VDD

VDD

PULL-UP
RESISTOR

RESISTOR
ENABLE

I/O

DATA

OUTPUT
DISABLE

P-CH

N-CH

SCHMITT TRIGGER

RESISTOR
ENABLE

Figure 1-8. Pin Circuit Type E-1

I/O

PRODUCT OVERVIEW S3C72F5/P72F5

VDD

VDD

PULL-UP

PNE

RESISTOR

DATA

OUTPUT

DISABLE

P-CH

N-CH

SCHMITT TRIGGER

Figure 1-9. Pin Circuit Type E-2

RESISTOR
ENABLE

I/O

1–10

S3C72F5/P72F5 PRODUCT OVERVIEW

V

DD

V

LC1

COM DATA

V

LC4

V

LC5

Figure 1-10. Pin Circuit Type H-3

V

DD

V

LC2

OUT

SEG DATA

V

LC3

V

LC5

Figure 1-11. Pin Circuit Type H-15

OUT

PRODUCT OVERVIEW S3C72F5/P72F5

V

DD

PULL-UP

RESISTOR

RESISTOR

ENABLE

COM/SEG

OUTPUT

DISABLE

DATA

Figure 1-12. Pin Circuit Type H-13

TYPE H-3

TYPE C

CIRCUIT TYPE A

PULL-UP

RESISTOR

P-CH

I/O

V

DD

1–12

RESISTOR

ENABLE

SEG

OUTPUT

DISABLE

DATA

P-CH

TYPE H-15

I/OTYPE C

SCHMITT TRIGGER

Figure 1-13. Pin Circuit Type H-16

S3C72F5/P72F5 ELECTRICAL DATA

14 ELECTRICAL DATA

OVERVIEW

In this section, information on S3C72F5 electrical characteristics is presented as tables and graphics. The
information is arranged in the following order:

Standard Electrical Characteristics

— Absolute maximum ratings
— D.C. electrical characteristics
— Main system clock oscillator characteristics
— Subsystem clock oscillator characteristics
— I/O capacitance
— A.C. electrical characteristics
— Operating voltage range

Miscellaneous Timing Waveforms

— A.C timing measurement point
— Clock timing measurement at X

— Clock timing measurement at XT
— TCL timing
— Input timing for RESET

— Input timing for external interrupts
— Serial data transfer timing

Stop Mode Characteristics and Timing Waveforms

— RAM data retention supply voltage in stop mode
— Stop mode release timing when initiated by RESET

— Stop mode release timing when initiated by an interrupt request

in

in

14–1

ELECTRICAL DATA S3C72F5/P72F5

Table 14–1. Absolute Maximum Ratings

(TA = 25 °C)

Parameter Symbol Conditions Rating Units

Supply Voltage
Input Voltage
Output Voltage
Output Current High

V

V

I

OH

DD

V

– – 0.3 to + 6.5 V

Ports 0–9

I

O

–

– 0.3 to V
– 0.3 to VDD + 0.3

DD

+ 0.3

V

V
One I/O pin active – 15 mA
All I/O pins active – 35

Output Current Low

I

OL

One I/O pin active + 30 (Peak value) mA

(note)

+ 15

Total for ports 0, 2–9 + 100 (Peak value)

(note)

+ 60

Operating Temperature
Storage Temperature

T

A

T

stg

– – 40 to + 85
– – 65 to + 150

°

C

°

C

NOTE: The values for Output Current Low ( IOL ) are calculated as Peak Value × Duty .

Table 14–2. D.C. Electrical Characteristics

(T

= – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)

A

Parameter Symbol Conditions Min Typ Max Units

Input High
Voltage

V

IH1

V

IH2

All input pins except those
specified below for V

IH2–VIH3

Ports 0, 1, 6, P3.2, P3.3, and

0.7V

0.8V

DD

DD

–

V

DD

V

DD

RESET

Input Low
Voltage

V

IH3

V

IL1

V

IL2

Xin, X

, and XT

out

in

All input pins except those
specified below for V

IL2–VIL3

Ports 0, 1, 6, P3.2, P3.3, and

V

– 0.1 V

DD

– –

0.3V

0.2V

DD

DD

DD

RESET

Output High
Voltage

V

IL3

V

OH

Xin, X

, and XT

out

in

VDD = 4.5 V to 5.5 V
IOH = – 1 mA

V

DD

– 1.0

0.1

– – V

Ports 0, 2–9

Output Low
Voltage

V

OL

V

= 4.5 V to 5.5 V

DD

IOL = 15 mA

– – 2.0 V

V

V

14–2

Ports 0, 2–9

S3C72F5/P72F5 ELECTRICAL DATA

Table 14–2. D.C. Electrical Characteristics (Continued)

(T

= – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)

A

Parameter Symbol Conditions Min Typ Max Units

Input High
Leakage
Current

Input Low
Leakage

Current

Output High
Leakage

I

LIH1

I

LIH2

I

LIL1

I

LIL2

I

LOH

VI = V

DD

All input pins except those
specified below for I

VI = V

DD

X

in, Xout,

V

= 0 V

I

X

in, Xout,

V

= 0 V

I

Xin, X
VO = V

out,

DD

XT

in,

and XT

and XT

LIH2

and RESET

in

in

All output pins

– – 3 µA

20

– – – 3 µA

– 20

– – 3 µA

Current
Output Low

Leakage

I

LOL

VO = 0 V
All output pins

– – – 3 µA

Current
Pull-Up

Resistor

LCD Voltage

R

R

R

LCD

LI

L2

V

= 0 V; V

I

Port 0–9
V

= 3 V

DD

V

= 0 V; V

I

V

= 3 V

DD

Ta = 25 °C

= 5 V

DD

= 5 V, RESET

DD

25 47 100

50 95 200

100 220 400
200 450 800

25 55 80

kΩ

kΩ
Dividing
Resistor

V

|

DD-COMi|

V

DC

– 15 µA per common pin – – 120 mV

Voltage Drop
(i = 0–15)

V

|

DD-SEGx|

V

DS

– 15 µA per segment pin – – 120

Voltage Drop
(x = 0–55)

V

LC1 Output

V

LC1

LCD clock = 0 Hz, V

= 0 V 0.8VDD-0.2 0.8V

LC5

DD

0.8VDD+0.2

V

Voltage
V

LC2 Output

V

LC2

0.6VDD-0.2 0.6V

DD

0.6VDD+0.2

Voltage
V

LC3 Output

V

LC3

0.4VDD-0.2 0.4V

DD

0.4VDD+0.2

Voltage
V

LC4 Output

V

LC4

0.2VDD-0.2 0.2V

DD

0.2VDD+0.2

Voltage

14–3

ELECTRICAL DATA S3C72F5/P72F5

Table 14–2. D.C. Electrical Characteristics (Concluded)

(T

= – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)

A

Parameter Symbol Conditions Min Typ Max Units

V

Supply
Current

I

DD1

(2)

= 5 V ± 10%

DD

Crystal oscillator

6.0 MHz

4.19 MHz

– 3.9

2.9

8.0

5.5

mA

C1 = C2 = 22 pF
V

I

DD2

DD

(2)

Idle mode;
VDD = 5 V ± 10%

= 3 V ± 10%

6.0 MHz

4.19 MHz

6.0 MHz

4.19 MHz

1.8

1.3

1.3

1.2

4.0

3.0

2.5

1.8

Crystal oscillator
C1 = C2 = 22 pF

V

I

DD3

(3)

= 3 V ± 10%

DD

V

= 3 V ± 10%

DD

6.0 MHz

4.19 MHz

0.5

0.44

1.5

1.0

– 15.3 30 µA

32 kHz crystal oscillator

I

DD4

(3)

Idle mode; V

= 3 V ± 10%

DD

6.4 15

32 kHz crystal oscillator

I

DD5

Stop mode;
VDD = 5 V ± 10%

Stop mode;

SCMOD =
0000B

XT = 0V

2.5 5

0.5 3

VDD = 3 V ± 10%
Stop mode;

VDD = 5 V ± 10%
Stop mode;

SCMOD =
0100B

0.2 3

0.1 2

VDD = 3 V ± 10%

NOTES:

1. Data includes power consumption for subsystem clock oscillation.

2. When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the
subsystem clock is used.

3. Currents in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage dividing resistors,
output port drive currents.

14–4

S3C72F5/P72F5 ELECTRICAL DATA

Table 14–3. Main System Clock Oscillator Characteristics

(TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V)

Oscillator Clock

Configuration

Ceramic

Xin Xout

Oscillator

C1 C2

Crystal

Xin Xout

Oscillator

C1 C2

External

Xin Xout

Clock

Parameter Test Condition Min Typ Max Units

Oscillation frequency

Stabilization time

(2)

Oscillation frequency

Stabilization time

Xin input frequency

(2)

(1)

(1)

Stabilization occurs
when VDD is equal

to the minimum
oscillator voltage
range; VDD = 3.0 V.

(1)

VDD = 3.0 V
VDD = 2.0 V to 5.5 V

– 0.4 – 6.0 MHz

– – 4 ms

– 0.4 – 6.0 MHz

– – 10 ms
– – 30

– 0.4 – 6.0 MHz

Xin input high and low

– 83.3 – 1250 ns

level width (tXH, tXL)

RC
Oscillator

Xin Xout

R

Frequency

R = 20 kΩ,
VDD = 5 V

R = 39 kΩ,

– 2 – MHz

– 1 –

VDD = 3 V

NOTES:

1. Oscillation frequency and X

2. Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is
terminated.

input frequency data are for oscillator characteristics only.

in

14–5

ELECTRICAL DATA S3C72F5/P72F5

Table 14–4. Recommended Oscillator Constants

(TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V)

Manufacturer Series

Number

TDK

FCRM5
FCRMC5

CCRMC3

NOTES:

1. Please specify normal oscillator frequency.

2. On-chip C: 30pF built in.

3. On-chip C: 38pF built in.

Frequency Range Load Cap (pF) Oscillator Voltage

(1)

3.58 MHz–6.0 MHz 33 33 2.0 5.5 Leaded Type

3.58 MHz–6.0 MHz

3.58 MHz–6.0 MHz

Range (V)

C1 C2 MIN MAX

(2) (2)

(3) (3)

2.0 5.5 On-chip C

2.0 5.5 On-chip C

Remarks

Leaded Type

SMD Type

14–6

S3C72F5/P72F5 ELECTRICAL DATA

Table 14–5. Subsystem Clock Oscillator Characteristics

(TA = – 40 °C + 85 °C, V

Oscillator Clock

Configuration

Crystal

XTin XTout

Oscillator

C1 C2

External

XTin XTout

Clock

= 1.8 V to 5.5 V)

DD

Parameter Test Condition Min Typ Max Units

Oscillation
frequency

Stabilization time

XTin input
frequency

XTin input high and
low level width (t
t

)

XTH

(1)

(1)

(2)

XTL

– 32 32.768 35 kHz

VDD = 2.7 V to 5.5 V
VDD = 2.0 V to 5.5 V

– 32 – 100 kHz

– 5 – 15 µs

,

– 1.0 2 s
– – 10

NOTES:

1. Oscillation frequency and XT

2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs.

input frequency data are for oscillator characteristics only.

in

Table 14–6. Input/Output Capacitance

(TA = 25 °C, V

DD

= 0 V )

Parameter Symbol Condition Min Typ Max Units

C

C

IN

OUT

f = 1 MHz; Unmeasured pins

are returned to V

SS

– – 15 pF

– – 15 pF

Input
Capacitance

Output
Capacitance

I/O Capacitance

C

IO

– – 15 pF

14–7

ELECTRICAL DATA S3C72F5/P72F5

Table 14–7. A.C. Electrical Characteristics

(TA = – 40 °C to + 85 °C, V

= 1.8 V to 5.5 V)

DD

Parameter Symbol Conditions Min Typ Max Units

Instruction Cycle

(note)

Time

TCL0, TCL1 Input

t

CY

f

TI0, fTI1

V

= 2.7 V to 5.5 V

DD

VDD = 2.0 V to 5.5 V
V

= 2.7 V to 5.5 V

DD

0.67 – 64 µs

0.95 64
0 – 1.5 MHz

Frequency

TCL0, TCL1 Input
High, Low Width

SCK Cycle Time

SCK High, Low

t

TIH0, tTIL0

t

, t

TIH1

TIL1

t

KCY

tKH, t

KL

VDD = 2.0 V to 5.5 V
V

= 2.7 V to 5.5 V

DD

VDD = 2.0 V to 5.5 V
V

= 2.7 V to 5.5 V; Input

DD

Internal SCK source; Output
VDD = 2.0 V to 5.5 V; Input

Internal SCK source; Output
V

= 2.7 V to 5.5 V; Input

DD

0.48 – – µs

1.8
800 – – ns
650

3200
3800

325 – – ns

1

Width

t

/2 –

Internal SCK source; Output

KCY

50

VDD = 2.0 V to 5.5 V; Input

1600

t

Internal SCK source; Output

KCY

/2 –

150

SI Setup Time to

t

SIK

V

= 2.7 V to 5.5 V; Input

DD

100 – – ns

SCK High

V

SI Hold Time to

t

KSI

= 2.7 V to 5.5 V; Output

DD

V

= 2.0 V to 5.5 V; Input

DD

V

= 2.0 V to 5.5 V; Output

DD

V

= 2.7 V to 5.5 V; Input

DD

150
150
500
400 – – ns

SCK High

V

= 2.7 V to 5.5 V; Output

DD

V

= 2.0 V to 5.5 V; Input

DD

V

= 2.0 V to 5.5 V; Output

DD

NOTE: Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock ( fx ) source.

400
600
500

14–8

S3C72F5/P72F5 ELECTRICAL DATA

Table 14–7. A.C. Electrical Characteristics (Continued)

(TA = – 40 _C to + 85 _C, V

= 1.8 V to 5.5 V)

DD

Parameter Symbol Conditions Min Typ Max Units

Output Delay for

t

KSO

V

= 2.7 V to 5.5 V; Input

DD

– – 300 ns

SCK to SO

V

Interrupt Input
High, Low Width

RESET Input Low

t

INTH

t

INTL

t

RSL

= 2.7 V to 5.5 V; Output

DD

V

= 2.0 V to 5.5 V; Input

DD

V

= 2.0 V to 5.5 V; Output

DD

,

INT0, INT1, INT2, INT4,

10 – – µs

K0–K7
Input 10 – – µs

250
1000
1000

Width

NOTE: Minimum value for INT0 is based on a clock of 2t

CPU CLOCK

1.5 MHz

or 128 / fx as assigned by the IMOD0 register setting.

CY

Main Oscillator Frequency
(Divided by 4)

6 MHz

1.05 MHz

750 kHz

15.6 kHz

4.2 MHz

3 MHz

1 2 3 4 5 6 7

1.8 V
SUPPLY VOLTAGE (V)

CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64)

Figure 14–1. Standard Operating Voltage Range

14–9

ELECTRICAL DATA S3C72F5/P72F5

Table 14–8. RAM Data Retention Supply Voltage in Stop Mode

(TA = – 40 °C to + 85 °C)

Parameter Symbol Conditions Min Typ Max Unit

Data retention supply voltage
Data retention supply current

V

DDDR

I

DDDR

V

DDDR

– 1.8 – 5.5 V

= 1.8 V

– 0.1 10 µA

Release signal set time
Oscillator stabilization wait

(1)

time

NOTES:

1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator
start-up.

2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.

t

SREL

t

WAIT

– 0 – – µs

Released by RESET

Released by interrupt –

–

217 / fx

(2)

– ms

–

14–10

S3C72F5/P72F5 ELECTRICAL DATA

TIMING WAVEFORMS

V

DD

RESET

EXECUTION OF

STOP INSTRUCTION

STOP MODE

DATA RETENTION MODE

V

DDDR

INTERNAL

OPERATION

t

SREL

RESET

IDLE MODE

t

WAIT

Figure 14–2. Stop Mode Release Timing When Initiated by RESETRESET

IDLE MODE

STOP MODE

NORMAL MODE

NORMAL MODE

DATA RETENTION MODE

V

DD

EXECUTION OF

STOP INSTRUCTION

POWER-DOWN MODE TERMINATING SIGNAL

(INTERRUPT REQUEST)

Figure 14–3. Stop Mode Release Timing When Initiated by Interrupt Request

V

DDDR

t

SREL

t

WAIT

14–11

ELECTRICAL DATA S3C72F5/P72F5

0.8 V

0.2 V

DD

DD

MEASUREMENT

POINTS

0.8 V

0.2 V

DD

DD

Figure 14–4. A.C. Timing Measurement Points (Except for Xin and XTin)

1 / f

x

t

XL

X

in

t

XH

VDD -0.1 V

0.1 V

XT

Figure 14–5. Clock Timing Measurement at X

1 / f

xt

t

XTL

in

t

Figure 14–6. Clock Timing Measurement at XT

in

XTH

VDD - 0.1 V

0.1 V

in

14–12

S3C72F5/P72F5 ELECTRICAL DATA

1 / f

TI

TCL0

RESET

t

TIL

Figure 14–7. TCL Timing

t

RSL

t

TIH

0.2 V

DD

0.8 V

0.2 V

DD

DD

INT0, 1, 2, 4 K0 to K7

Figure 14–9. Input Timing for External Interrupts and Quasi-Interrupts

Figure 14–8. Input Timing for RESETRESET Signal

t

INTL

0.8 V

0.2 V

DD

DD

t

INTH

14–13

ELECTRICAL DATA S3C72F5/P72F5

t

KCY

SCK

SI

SO

t

KSO

t

KL

t

SIK

INPUT DATA

OUTPUT DATA

t

KSI

t

Figure 14–10. Serial Data Transfer Timing

KH

0.8 V

0.2 V

DD
DD

0.8 V

0.2 V

DD
DD

14–14

S3C72F5/P72F5 ELECTRICAL DATA

NOTES

14–15

ELECTRICAL DATA S3C72F5/P72F5

CHARACTERISTIC CURVES

NOTE

The characteristic values shown in the following graphs are based on actual test measurements.
They do not, however, represent guaranteed operating values.

(TA = 25 °C, fx = 4.2 MHz)

5.0

4.5
I

, CPU Clock = fx/4

4.0

3.5

3.0

(mA)

DD1

DD2

, I

DD1

I

2.5

2.0

1.5

1.0

0.5

I

, CPU Clock = fx/64

DD1

I

DD2

0

2.7 4.0 4.5 6.0

VDD (V)

Figure 14–11. I

DD1

, I

DD2

VS. V

DD

14–16

S3C72F5/P72F5 ELECTRICAL DATA

(TA = 25 °C, fx = 32.768 kHz)

50

45

40

35

30

(µA)

25

DD3, 4, 5

20

I

15

10

5

0

2.0

2.5

3.0 3.5 4.0

Figure 14–12. I

DD3

VDD (V)

, I

DD4

I

DD3

I

DD4

I

DD5

4.5 5.0 5.5 6.0 6.5

, I

VS. V

DD5

DD

14–17

ELECTRICAL DATA S3C72F5/P72F5

(TA = 25 °C , CPU CLOCK = fx/4)

4.5

4.0

3.5

VDD = 6. 0 V

3.0

2.5

(mA)

1

DD

2.0

I

1.5

1.0

0.5

0

0.5

1.0 1.5 2.0

2.5 3. 0 3.5 4.0 4.5

VDD = 4. 5 V

Main System Clock Freque ncy (MHz)

Figure 14–13. I

VS. Main System Clock Frequency

DD1

(TA = 25 °C )

1.6

1.4

VDD = 6. 0 V

14–18

1.2

1.0

(mA)

2

0.8

DD

I

0.6

0.4

0.2

0

0.5

1.0 1. 5 2.0

2.5 3.0 3.5 4. 0 4.5

VDD = 4. 5 V

Mai n System Clock Frequency (MHz)

Figure 14–14. I

VS. Main System Clock Frequency

DD2

S3C72F5/P72F5 ELECTRICAL DATA

(TA = 25 °C, Ports 0, 2, 3, 4, 5, 6, 7)

–25.0

–22.5

–20.0

–17.5

–15.0

(mA)

–12.5

OH

I

–10.0

–7.5

–5.0

–2.5

VDD = 4.5 V

0

0.5

1.0 1.5 2.0

2.5 3.0 3.5 4.0 4.5 5.0

VDD = 6.0 V

5.5 6.0

VOH (V)

Figure 14–15. IOH VS. VOH (P0, 2, 3, 4, 5, 6, 7)

14–19

ELECTRICAL DATA S3C72F5/P72F5

(TA = 25 °C, Ports 8, 9)

–25.0

–22.5

–20.0

–17.5

–15.0

(mA)

–12.5

OH

I

–10.0

–7.5

–5.0

–2.5

VDD = 4.5 V

0

0.5

1.0 1.5 2.0

2.5 3.0 3.5 4.0 4.5 5.0

VDD = 6.0 V

5.5 6.0

VOH (V)

Figure 14–16. IOH VS. VOH (P8, 9)

14–20

S3C72F5/P72F5 ELECTRICAL DATA

(TA = 25 °C, Ports 0, 2, 3, 4, 5, 6, 7)

55.0

50.0

45.0

40.0

VDD = 6.0 V

35.0

(mA)

30.0

OL

I

25.0

20.0

15.0

10.0

5.0

VDD = 4.5 V

0

0.5

1.0 1.5 2.0

2.5 3.0 3.5 4.0 4.5 5.0

5.5 6.0

VOL (V)

Figure 14–17. IOL VS. VOL (P0, 2, 3, 4, 5, 6, 7)

14–21

ELECTRICAL DATA S3C72F5/P72F5

(TA = 25 °C, Ports 8, 9)

55.0

50.0

45.0

40.0

VDD = 6.0 V

35.0

(mA)

30.0

OL

I

25.0

20.0

15.0

10.0

5.0

VDD = 4.5 V

0

0.5

1.0 1.5 2.0

2.5 3.0 3.5 4.0 4.5 5.0

5.5 6.0

VOL (V)

Figure 14–18. IOL VS. VOL (P8, 9)

14–22

S3C72F5/P72F5 MECHANICAL DATA

15 MECHANICAL DATA

OVERVIEW

This section contains the following information about the device package:
— Package dimensions in millimetersD
— Pad diagram
— Pad/pin coordinate data table

15–1

MECHANICAL DATA S3C72F5/P72F5

14.00 TYP

20.00 TYP

100 QFP

(Top View)

0.65 TYP 0.30 ± 0.1

A

C

D

B

+ 0.1

0.15

– 0.05

E

Package

100-QFP-1420A

100-QFP-1420C

NOTE

Item

: Typical dimensions are in millimeters.

A

25.00 ± 0.3

23.20 ± 0.3

Figure 15–1. 100-QFP Package Dimensions

B C D E

19.00 ± 0.3

17.20 ± 0.3

2.45 MAX

3.00 MAX

+ 0.1

0.15

– 0.05

0.15 ± 0.1

1.20 ± 0.2

0.80 ± 0.2

15-2

S3C72F5/P72F5 S3P72F5 OTP

16 S3P72F5 OTP

OVERVIEW

The S3P72F5 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C72F5

microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data
format.

The S3P72F5 is fully compatible with the S3C72F5, both in function and in pin configuration. Because of its
simple programming requirements, the S3P72F5 is ideal for use as an evaluation chip for the S3C72F5.

16–1

S3P72F5 OTP S3C72F5/P72F5

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

47

48

49

81

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

50

SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
P9.3/SEG40
P9.2/SEG41
P9.1/SEG42
P9.0/SEG43
P8.3/SEG44
P8.2/SEG45
P8.1/SEG46
P8.0/SEG47
P7.3/SEG48
P7.2/SEG49
P7.1/SEG50
P7.0/SEG51
P6.3/SEG52/K7
P6.2/SEG53/K6
P6.1/SEG54/K5

P0.0/

P0.1/SO/K1

/P0.2/SI/K2

SDAT

/P0.3/BUZ/K3

SCLK

RESETRESET /RESET

P2.1/LCDCK
P2.2/LCDSY

P3.0/TCLO0

SEG4
SEG3
SEG2
SEG1
SEG0
VLC5
VLC4
VLC3
VLC2
VLC1

/K0

SCK

/VDD

VDD

/VSS

VSS

Xout

Xin

/TEST

VPP

XTin

XTout

P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT4

P2.0/CLO

100

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

31

32

33

34

S3P72F5

(100-QFP-1420C)

35

36

37

38

39

40

41

42

43

44

45

46

COM0

COM1

COM2

COM3

COM4

P3.2/TCL0

P3.3/TCL1

P3.1/TCLO1

The bolds indicate an OTP pin name.

NOTE:

Figure 16–1. S3P72F5 Pin Assignments (100-QFP Package)

16–2

COM5

COM6

COM7

P4.0/COM8

P4.1/COM9

P4.2/COM10

P4.3/COM11

P5.0/COM12

P5.1/COM13

P5.2/COM14

P5.3/COM15

P6.0/SEG55/K4

S3C72F5/P72F5 S3P72F5 OTP

Table 16–1. Descriptions of Pins Used to Read/Write the EPROM

Main Chip During Programming

Pin Name Pin Name Pin No. I/O Function

P0.2 SDAT 13 I/O Serial data pin. Output port when reading and

input port when writing. Can be assigned as a
Input / push-pull output port.

P0.3 SCLK 14 I/O Serial clock pin. Input only pin.

TEST

VPP(TEST)

19 I Power supply pin for EPROM cell writing

(indicates that OTP enters into the writing
mode). When 12.5 V is applied, OTP is in
writing mode and when 5 V is applied, OTP is in
reading mode. (Option)

RESET RESET

VDD / V

SS

VDD / V

SS

22 I Chip initialization

15/16 I Logic power supply pin. VDD should be tied to

+5 V during programming.

Table 16–2. Comparison of S3P72F5 and S3C72F5 Features

Characteristic S3P72F5 S3C72F5

Program Memory 16 Kbyte EPROM 16 Kbyte mask ROM
Operating Voltage (VDD)

OTP Programming Mode

1.8 V to 5.5 V 1.8 V to 5.5 V
VDD = 5 V, VPP(TEST)=12.5V

Pin Configuration 100 QFP 100 QFP
EPROM Programmability User Program 1 time Programmed at the factory

OPERATING MODE CHARACTERISTICS

When 12.5 V is supplied to the VPP(TEST) pin of the S3P72F5, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in

Table 16–3 below.

Table 16–3. Operating Mode Selection Criteria

V

DD

Vpp

(TEST)

REG/MEM Address

(A15-A0)

R/W Mode

5 V 5 V 0 0000H 1 EPROM read

12.5 V 0 0000H 0 EPROM program

12.5 V 0 0000H 1 EPROM verify

12.5 V 1 0E3FH 0 EPROM read protection

NOTE: "0" means Low level; "1" means High level.

16–3

S3P72F5 OTP S3C72F5/P72F5

Table 16–4. D.C. Electrical Characteristics

(T

= – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)

A

Parameter Symbol Conditions Min Typ Max Units

(2)

V

Supply
Current

I

DD1

= 5 V ± 10%

DD

Crystal oscillator

6.0 MHz

4.19 MHz

– 3.9

2.9

8.0

5.5

mA

C1 = C2 = 22 pF
V

I

DD2

DD

(2)

Idle mode;
VDD = 5 V ± 10%

= 3 V ± 10%

6.0 MHz

4.19 MHz

6.0 MHz

4.19 MHz

1.8

1.3

1.3

1.2

4.0

3.0

2.5

1.8

Crystal oscillator
C1 = C2 = 22 pF

V

I

DD3

(3)

= 3 V ± 10%

DD

V

= 3 V ± 10%

DD

6.0 MHz

4.19 MHz

0.5

0.44

1.5

1.0

– 15.3 30 µA

32 kHz crystal oscillator

(3)

I

DD4

Idle mode; V

= 3 V ± 10%

DD

6.4 15

32 kHz crystal oscillator

I

DD5

Stop mode;
VDD = 5 V ± 10%

Stop mode;

SCMOD =
0000B

XT = 0V

2.5 5

0.5 3

VDD = 3 V ± 10%
Stop mode;

VDD = 5 V ± 10%
Stop mode;

SCMOD =
0100B

0.2 3

0.1 2

VDD = 3 V ± 10%

NOTES:

1. Data includes power consumption for subsystem clock oscillation.

2. When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the
subsystem clock is used.

3. Currents in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage dividing resistors,
output port drive currents.

16–4

S3C72F5/P72F5 S3P72F5 OTP

Main Oscillator Frequency

CPU CLOCK

1.5 MHz

1.05 MHz 4.2 MHz

(Divided by 4)
6 MHz

750 kHz

15.6 kHz

3 MHz

1 2 3 4 5 6 7

1.8 V
SUPPLY VOLTAGE (V)

CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64)

Figure 16–2. Standard Operating Voltage Range

16–5