Datasheet S3C72C8, S3P72C8 Datasheet (Samsung)

S3C72C8/P72C8 PRODUCT OVERVIEW

1 PRODUCT OVERVIEW

OVERVIEW

The S3C72C8 single-chip CMOS microcontroller has been designed for high performance using Samsung's
newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).

With an up-to-96-dot LCD direct drive capability flexible 16-bit timer/counter, and 4-chanel comparator, the
S3C72C8 offers an excellent design solution for a low CDP and a card reader.

Up to 28 pins of the 44-pin QFP or up to 26 pins of the 42-pin SDIP package can be dedicated to I/O. Eight
vectored interrupts provide fast response to internal and external events. In addition, the S3C72C8's advanced
CMOS technology provides for low power consumption.

OTP

The S3C72C8 microcontroller is also available in OTP (One Time Programmable) version, S3P72C8. S3P72C8
microcontroller has an on-chip 8K-byte one-time-programable EPROM instead of masked ROM.
The S3P72C8 is comparable to S3C72C8, both in function and in pin configuration.

1-1

PRODUCT OVERVIEW S3C72C8/P72C8

FEATURES

Memory

• 512 × 4-bit RAM (including LCD display RAM)

• 8,192 × 8-bit ROM

28 I/O Pins

• I/O: 26 pins (44-pin QFP, 42-pin SDIP)

• Output only: 2 pins (44-pin QFP)

LCD Controller/Driver

• 12 segments and 8 common terminals
(3, 4, and 8 common selectable)

• Internal resistor circuit for LCD bias

• All dot can be switched on/off

8-bit Basic Timer

• 4 interval timer functions

• Watch-dog timer

16-bit Timer/Counter 1

• Programmable 16-bit timer/counter

• Arbitrary clock output

• External event counter

• External clock signal divider

• Configurable as two 8-bit timer/counters

• Serial I/O interface clock generator

Watch Timer

• Time interval generation: 0.5 s, 3.9 ms
at 32768 Hz

• Four frequency outputs to BUZ pin

• Clock source generation for LCD

8-bit Serial I/O Interface

• 8-bit transmit/receive mode

• 8-bit receive mode

• LSB-first or MSB-first transmission selectable

• Internal or external clock source

Interrupts

• Four internal vectored interrupts

• Five external vectored interrupts

• Two quasi-interrupts

Bit Sequential Carrier

• Supports 16-bit serial data transfer in arbitrary
format

Memory-Mapped I/O Structure

• Data memory bank 15

Power-Down Modes

• Idle mode (only CPU clock stops)

• Stop mode (main system oscillation stops)

• Sub system clock stop mode

Oscillation Sources

• Crystal, ceramic, or RC for main system clock

• Crystal oscillator for subsystem clock

• Main system clock frequency: 0.4 MHz-6 MHz

• Subsystem clock frequency: 32.768 kHz

• CPU clock divider circuit (by 4, 8, or 64)

Instruction Execution Times

• 0.67, 1.33, 10.7 µs at 6 MHz (main)

• 0.95, 1.91, 15.3 µs at 4.19 MHz (main)

• 122 µs at 32.768 kHz (subsystem)

Operating Temperature

• – 40 °C to 85 °C

Operating Voltage Range

• 1.8 V to 5.5 V

Package Type

• 44-pin QFP, 42-pin SDIP

Comparator

• 4 channel mode: internal reference (4-bit
resolution)

• 3 channel mode: external reference

1-2

S3C72C8/P72C8 PRODUCT OVERVIEW

BLOCK DIAGRAM

Watch Dog

8-Bit Timer/

Counter1A

8-Bit Timer/

Counter1B

P2.0/CIN0/K0
P2.1/CIN1/K1
P2.2/CIN2/K2
P2.3/CIN3/K3

P3.0/INTP30
P3.1/INTP31

P5.0-P5.3/

SEG0-SEG3

P6.0-P6.3/

SEG4-SEG7

P7.0-P7.3/

SEG8-SEG11

16-Bit

Timer/

Counter

I/O Port 2

I/O Port 3

I/O Port 5

I/O Port 6

I/O Port 7

RESET XTOUTXTIN

Interrupt

Control

Block

Internal

Interrupts

Instruction Decoder

Arithmetic

and

Logic Unit

Clock

XOUTXIN

Instruction

Register

Program

Counter

Program

Status Word

Stack

Pointer

Timer

Basic Timer

Watch Timer

LCD

Driver/

Controller

SIO

I/O Port 0

I/O Port 1

COM0-COM3
COM4-COM7/

SEG15-SEG12
SEG0-SEG3/

P5.0-P5.3
SEG4-SEG7/

P6.0-P6.3
SEG8-SEG11/

P7.0-P7.3

SCK

P0.0/
P0.1/SO
P0.2/SI
P0.3/BTCO

P1.0/TCLO1/INT0
P1.1/TCL1/INT1
P1.2/CLO/INT2
P1.3/BUZ/INT4

P4.0
P4.1

Output Port 4

44 QFP Only

512 x 4-Bit

Data

Memory

8 K Byte
Program

Memory

Figure 1-1. S3C72C8 Simplified Block Diagram

Comparator

1-3

PRODUCT OVERVIEW S3C72C8/P72C8

PIN ASSIGNMENTS

P4.0

P4.1

P1.3/BUZ/INT4

P1.2/CLO/INT2

P1.1/TCL1/INT1

P1.0/TCLO1/INT0

COM0

COM1

COM2

COM3

COM4/SEG15

4443424140393837363534

P2.0/CIN0/K0
P2.1/CIN1/K1
P2.2/CIN2/K2
P2.3/CIN3/K3

VDD

VSS

XOUT

XIN

TEST

XTIN

XTOUT

1
2
3
4
5
6
7
8
9
10
11

S3C72C8

(44-QFP-1010B)

1213141516171819202122

RESET

P0.2/SI

P0.1/SO

P0.3/BTCO

P0.0/SCK

P3.1/INTP31

P3.0/INTP30

SEG0/P5.0

33
32
31
30
29
28
27
26
25
24
23

SEG1/P5.1

SEG2/P5.2

SEG3/P5.3

Figure 1-2. S3C72C8 44-QFP Pin Assignment Diagram

COM5/SEG14
COM6/SEG13
COM7/SEG12
SEG11/P7.3
SEG10/P7.2
SEG9/P7.1
SEG8/P7.0
SEG7/P6.3
SEG6/P6.2
SEG5/P6.1
SEG4/P6.0

1-4

S3C72C8/P72C8 PRODUCT OVERVIEW

COM1
COM0

P1.0/TCLO1/INT0

P1.1/TCL1/INT1

P1.2/CLO/INT2

P1.3/BUZ/INT4

P2.0/CIN0/K0
P2.1/CIN1/K1
P2.2/CIN2/K2
P2.3/CIN3/K3

VDD

VSS

XOUT

XIN

TEST

XTIN

XTOUT

RESET

P0.3/BTCO

P0.2/SI

P0.1/SO

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

(42-SDIP-600)

S3C72C8

Figure 1-3. S3C72C8 42-SDIP Pin Assignment Diagram

42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22

COM2
COM3
COM4/SEG15
COM5/SEG14
COM6/SEG13
COM7/SEG12
SEG11/P7.3
SEG10/P7.2
SEG9/P7.1
SEG8/P7.0
SEG7/P6.3
SEG6/P6.2
SEG5/P6.1
SEG4/P6.0
SEG3/P5.3
SEG2/P5.2
SEG1/P5.1
SEG0/P5.0
P3.0/INTP30
P3.1/INTP31
P0.0/SCK

1-5

PRODUCT OVERVIEW S3C72C8/P72C8

Table 1-1. S3C72C8 Pin Descriptions

Pin Name Pin

Type

P0.0

I/O 4-bit I/O port.

P0.1
P0.2
P0.3

1-bit and 4-bit read/write and test are possible.
Individual pins are software configurable as
input or output; Individual pins are software

Description Circuit

Type

E–1 16 (22)

Number Share Pin

15 (21)
14 (20)

13 (19)
configurable as open-drain or push-pull output;
Individual pull-up resistors are software
assignable; pull-up resistors are automatically
disabled for output pins.

P1.0
P1.1
P1.2
P1.3

P2.0
P2.1
P2.2
P2.3

P3.0
P3.1

I/O Same as port 0. E–1 39 (3)

40 (4)
41 (5)
42 (6)

I/O Same as port 0 except that port 2 is not

configurable as n-channel open drain and is
configurable as analog input pin.

F–8 1 (7)

2 (8)
3 (9)

4 (10)

I/O 2-bit I/O port

1-bit and 4-bit read/write and test is possible.

E–3 18 (24)

17 (23)
Individual pins are software configurable as
input or output; Individual pins are software
configurable as open-drain or push-pull output;
2-bit pull-up resistors are software assignable;
pull-up resistors are automatically disabled for
output pins.

P4.0
P4.1

O 2-bit output port.

1-bit and 4-bit read/write and test is possible.

E-2 44

43
Individual pins are software configurable as
open-drain or push-pull output.

P5.0-P5.3 I/O 4-bit I/O port.

1-bit and 4-bit read/write and test is possible.

H-13 19-22

(25-28)
Individual pins are software configurable as
input or output; Individual pins are software
configurable as open-drain or push-pull output;
4-bit pull-up resistors are software assignable;
pull-up resistors are automatically disabled for
output pins.

P6.0-P6.3 I/O Same as port5 H-13 23-26

(29-32)

P7.0-P7.3 I/O Same as port5 H-13 27-30

(33-36)

SCK

SO

SI

BTCO

TCLO1/INT0

TCL1/INT1

CLO/INT2
BUZ/INT4

K0/CIN0
K1/CIN1
K2/CIN2
K3/CIN3

INTP30
INTP31

SEG0-SEG3

SEG4-SEG7

SEG8-SEG11

1-6

S3C72C8/P72C8 PRODUCT OVERVIEW

Table 1-1. S3C72C8 Pin Descriptions (Continued)

Pin Name Pin

Type

SEG0-SEG3 I/O LCD segment display signal output pins H–13 19-22

Description Circuit

Type

Number Share Pin

P5.0-P5.3

(25-28)

SEG4-SEG7 23-26

P6.0-P6.3

(29-32)

SEG8-SEG11 27-30

P7.0-P7.3

(33-36)

SEG12-SEG15 O LCD segment display output pins H–6 31-34

COM7-COM4

(37-40)

COM0-COM3 O LCD common signal output pins H–4 38-35

(2-1,

42-41)

COM4-COM7 I/O LCD common signal output pins H–6 34-31

(40-37)

SCK

I/O Serial interface clock signal E–1 16 (22) P0.0

SO I/O Serial data output E–1 15 (21) P0.1

SI I/O Serial data input E–1 14 (20) P0.2

BTCO I/O Basic timer overflow signal E–1 13 (19) P0.3

TCLO1 I/O Timer/counter external clock output E–1 39 (3) P1.0/INT0

TCL1 I/O Timer/counter external clock input E–1 40 (4) P1.1/INT1

CLO I/O Clock output E–1 41 (5) P1.2/INT2
BUZ I/O Frequency output to buzzer E–1 42 (6) P1.3/INT4

RESET

X

in, Xout

XT

in, XTout

I

System RESET pin

– Clock input and output pins for main system

clock

– Clock input and output pins for subsystem

clock

B 12 (18) –

– 8-7

(14-13)

– 10-11

(16-17)

CIN0–CIN3 I Analog input port for Comparator F–8 1-4

(7-10)

K0–K3 I/O External interrupts. The triggering edge is

selectable.

INT0
INT1

I External interrupts. The triggering edge for

INT0 and INT1 is selectable.

F–8 1-4

(7-10)

E–1 39 (3)

40 (4)

P2.0/CIN0

-P2.3/CIN3

P1.0/TCLO1

-P1.1/TCL1

–

SEG12–

SEG15

–

–

P2.0/K0

-P2.3/K3

1-7

PRODUCT OVERVIEW S3C72C8/P72C8

Table 1-1. S3C72C8 Pin Descriptions (Continued)

Pin Name Pin

Type

INT2 I Quasi-interrupt with detection of rising or

Description Circuit

Type

E-1 41 (5) P1.2/CLO

Number Share Pin

falling edges.

INT4 I External interrupt with detection of rising or

E-1 42 (6) P1.3/BUZ

falling edges.

INTP30
INTP31

I Key scan interrupts inputs. E-3 18-17

(24-23)

TEST I System test pin – 9 (15) –

V

DD

V

SS

NOTES:

1. Parentheses indicate pin number for 42-SDIP package.

2. Pull-up resistors for all I/O ports are automatically disabled if they are configured to output mode.

– Power supply pin – 5 (11) –
– Ground pin – 6 (12) –

P3.0, P3.1

1-8

S3C72C8/P72C8 PRODUCT OVERVIEW

PIN CIRCUIT DIAGRAMS

VDD

Pull-Up
Resistor

In

Schmitt Trigger Input

Figure 1-4. Pin Circuit Type B

Pull-Up

Resistor

Enable

PNE

Data

Output

DIsable

VDD

Pull-up

Resistor

P-CH

VDD

I/O

Figure 1-5. Pin Circuit Type E-1

1-9

PRODUCT OVERVIEW S3C72C8/P72C8

VDD

PNE

Data

Pull-Up

Resistor

Enable

PNE

Ouput

Disable

Data

Figure 1-6. Pin Circuit Type E-2

VDD

Pull-Up

Resistor

Circuit

Type E-4

Out

P-CH

I/O

LCON.1

1-10

Figure 1-7. Pin Circuit Type E-3

S3C72C8/P72C8 PRODUCT OVERVIEW

VDD

PNE

VDD

Data

VLC1

Out

Figure 1-8. Pin Circuit Type E-4

COM Data

VLC4

VSS

Out

LPOT.3

Figure 1-9. Pin Circuit Type H-4

1-11

PRODUCT OVERVIEW S3C72C8/P72C8

VDD

VLC1

VLC2

SEG/COM Data

Out

VSS

VLC4

VLC3

Figure 1-10. Pin Circuit Type H-6

LPOT.3

1-12

S3C72C8/P72C8 PRODUCT OVERVIEW

VDD

VLC2

SEG Data

Output Disable

Out

VLC3

VSS

Figure 1-11. Pin Circuit Type H-7

1-13

PRODUCT OVERVIEW S3C72C8/P72C8

VDD

Pull-Up

Resistor

Enable

SEG

Output

DIsable

Data
PNE

P-CH

Circuit

Type H-7

Circuit

Type E-4

Figure 1-12. Pin Circuit Type H-13

1-14

S3C72C8/P72C8 PRODUCT OVERVIEW

VDD

Pull-up

Resistor

Pull-Up

Resistor

Enable

VDD

Data

Output

DIsable

P-CH

I/O

(Digital)

(Analog)

INTK

External REF

(P2.3 only)

+

-

Comparator

REF

Digital or Analog can be seleted
by software.

Figure 1-13. Pin Circuit Type F-8

1-15

S3C72C8/P72C8 ELECTRICAL DATA

15 ELECTRICAL DATA

OVERVIEW

In this section, information on S3C72C8 electrical characteristics is presented as tables and graphics. The
information is arranged in the following order:

Standard Electrical Characteristics

— Absolute maximum ratings
— D.C. electrical characteristics
— Main system clock oscillator characteristics
— Subsystem clock oscillator characteristics
— I/O capacitance
— Comparator electrical characteristics
— A.C. electrical characteristics
— Operating voltage range

Stop Mode Characteristics and Timing Waveforms

— RAM data retention supply voltage in stop mode
— Stop mode release timing when initiated by RESET

— Stop mode release timing when initiated by an interrupt request

Miscellaneous Timing Waveforms

— A.C timing measurement points
— Clock timing measurement at X

— Clock timing measurement at XT
— TCL1 timing
— Input timing for RESET signal

— Input timing for external interrupts and quasi-interrupts
— Serial data transfer timing

in

in

15-1

ELECTRICAL DATA S3C72C8/P72C8

Table 15-1. Absolute Maximum Ratings

(TA = 25 °C)

Parameter Symbol Conditions Rating Units

Supply Voltage V
Input Voltage V
Output Voltage V
Output Current High I

DD

OH

All I/O pins active – 0.3 to V

I

O

One I/O pin active – 15 mA

– – 0.3 to + 6.5 V

+ 0.3 V

DD

– – 0.3 to VDD + 0.3 V

All I/O pins active – 35

Output Current Low I

OL

One I/O pin active + 30 (Peak value) mA

+ 15 *

Total for ports 0, 2–9 + 100 (Peak value)

+ 60 *

Operating Temperature T
Storage Temperature T

A

stg

– – 40 to + 85 °
– – 65 to + 150 °

C
C

* The values for Output Current Low ( I

) are calculated as Peak Value × Duty .

OL

Table 15-2. D.C. Electrical Characteristics

(T

= – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)

A

Parameter Symbol Conditions Min Typ Max Units

Input High V
Voltage V
Input Low V
Voltage V
Output High

Voltage

IH1
IH2

IL1
IL2

V

OH

Ports 0, 1, 2, 3, 5, 6, 7, RESET
Xin, X

, XTin, and XT

out

out

Ports 0, 1, 2, 3, 5, 6, 7, RESET
Xin, X

, XTin, and XT

out

out

VDD = 4.5 V to 5.5 V
IOH = – 1 mA

0.8 V

DD

V

– 0.1 V

DD

– – 0.2 V

– V

DD
DD

DD

0.1

V

– 1.0 – – V

DD

Ports 0, 1, 2, 3, 4, 5, 6, 7

Output Low
Voltage

V

OL

V

= 4.5 V to 5.5 V

DD

– – 2.0 V

IOL = 15 mA
Ports 0, 1, 2, 3, 4, 5, 6, 7

V

= 1.8 V to 5.5 V

DD

0.4

IOL = 1.6 mA

V

V

15-2

S3C72C8/P72C8 ELECTRICAL DATA

Table 15-2. D.C. Electrical Characteristics (Continued)

(T

= – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)

A

Parameter Symbol Conditions Min Typ Max Units

Input High
Leakage
Current

Input Low
Leakage
Current

Output High
Leakage

I

LIH1

I

LIH2

I

LIL1

I

LIL2

I

LOH

VI = V

DD

All input pins except those
specified below for I

VI = V

DD

Xin, X

out, XTin

V

= 0 V

I

, and XT

LIH2

out

All input pins except RESET, X
X

out, XTin

V

= 0 V

I

Xin, X
V

O

, and XT

, XTin, and XT

out

= V

DD

out

out

All output pins

– – 3 µA

20

– – – 3 µA

,

in

– 20

– – 3 µA

Current
Output Low

Leakage

I

LOL

V

= 0 V

O

All output pins

– – – 3 µA

Current
Pull-Up

Resistor

R

LI

V

= 0 V; V

I

DD

= 5 V

25 47 100

kΩ

Ports 0-3, 5-7 expect

RESET

V

= 3 V 50 95 200

DD

LCD Voltage

R

R

LCD

L2

V

= 0 V; V

I

V

= 3 V 200 450 800

DD

= 5 V, RESET

DD

Ta = 25 °C

100 220 400

60 80 100

kΩ
Dividing
Resistor

V

|

-COMi|

LC1

V

DC

– 15 µA per common pin – – 120 mV

Voltage Drop
(i = 0–7

|

V

LC1

-SEGx|

V

DS

– 15 µA per segment pin – – 120

Voltage Drop
(x = 0–15)

V

Output

LC1

Voltage
V

Output

LC2

Voltage
V

Output

LC3

Voltage
V

Output

LC4

Voltage

V

V

V

V

LC1

LC2

LC3

LC4

V

= 1.8 V to 5.5 V, 1/5 bias

DD

LCD clock = 0 Hz, V

LCD

0.8 V

=

V

DD

0.6 V

0.4 V

0.2 V

0.2

0.2

0.2

0.2

DD

DD

DD

DD

–

0.8 V

DD

0.8 V

DD

+

V

0.2

–

0.6 V

DD

0.6 V

DD

+

0.2

–

0.4 V

DD

0.4 V

DD

+

0.2

–

0.2 V

DD

0.2 V

DD

+

0.2

15-3

ELECTRICAL DATA S3C72C8/P72C8

Table 15-2. D.C. Electrical Characteristics (Concluded)

(T

= – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)

A

Parameter Symbol Conditions Min Typ Max Units

Supply
Current

(1)

I

DD1

(2)

V

DD

Crystal oscillator

= 5 V ± 10%

6.0 MHz

4.19 MHz

– 3.0

2.3

8.0

5.5

mA

C1 = C2 = 22 pF
V

I

DD2

DD

(2)

Idle mode
VDD = 5 V ± 10%

= 3 V ± 10% 6.0 MHz

4.19 MHz

6.0 MHz

4.19 MHz

1.5

1.0

1.3

1.2

4.0

3.0

2.5

1.8

Crystal oscillator
C1 = C2 = 22 pF

V

I

DD3

(3)

= 3 V ± 10% 6.0 MHz

DD

V

= 3 V ± 10%

DD

4.19 MHz
– 15.0 30 µA

0.5

0.44

1.5

1.0

32 kHz crystal oscillator

(3)

I

DD4

Idle mode; V

= 3 V ± 10%

DD

5.0 15

32 kHz crystal oscillator

I

DD5

Stop mode;
VDD = 5 V ± 10%

SCMOD =
0000B

2.5 5

XTin = 0V

Stop mode;

0.5 3

VDD = 3 V ± 10%
VDD = 5 V ± 10% SCMOD =

0.2 3

0100B

VDD = 3 V ± 10% 0.1 2

NOTES:

1. Currents in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage dividing resistors,
comparator, output port drive currents.

2. Data includes power consumption for subsystem clock oscillation.

3. When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the
subsystem clock is used.

4. Every values in this table is measured when the power control register (PCON) is set to "0011B".

15-4

S3C72C8/P72C8 ELECTRICAL DATA

Table 15-3. Main System Clock Oscillator Characteristics

(TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V)

Oscillator Clock

Configuration

Ceramic

Xin Xout

Oscillator

C1 C2

Crystal

Xin Xout

Oscillator

C1 C2

External

Xin Xout

Clock

Parameter Test Condition Min Typ Max Units

Oscillation frequency

Stabilization time

(2)

(1)

Stabilization occurs

– 0.4 – 6.0 MHz

– – 4 ms

when VDD is equal to
the minimum

oscillator voltage
range; VDD = 3.0 V.

Oscillation frequency

Stabilization time

(2)

(1)

VDD = 2.7 V to 5.5 V – – 10 ms

– 0.4 – 6.0 MHz

VDD = 1.8 V to 5.5 V – – 30

Xin input frequency

(1)

– 0.4 – 6.0 MHz

Xin input high and low

– 83.3 – 1250 ns

level width (tXH, tXL)

RC

Oscillator

Xin Xout

R

Frequency

R = 25 kΩ,
VDD = 5 V

R = 40 kΩ,

– 2 – MHz

– 1 –

VDD = 3 V

NOTES:

1. Oscillation frequency and X

2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is
terminated.

input frequency data are for oscillator characteristics only.

in

15-5

ELECTRICAL DATA S3C72C8/P72C8

Table 15-4. Recommended Oscillator Constants

(TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V)

Manufacturer Series

Number

TDK

FCRM5
FCRMC5

CCRMC3

NOTES:

1. Please specify normal oscillator frequency.

2. On-chip C: 30pF built in.

3. On-chip C: 38pF built in.

Frequency Range Load Cap (pF) Oscillator Voltage

(1)

3.58 MHz–6.0 MHz 33 33 2.0 5.5

3.58 MHz–6.0 MHz

3.58 MHz–6.0 MHz

Table 15-5. Subsystem Clock Oscillator Characteristics

(TA = – 40 °C + 85 °C, V

Oscillator Clock

= 1.8 V to 5.5 V)

DD

Parameter Test Condition Min Typ Max Units

Configuration

Crystal

Oscillator

XTin XTout

Oscillation frequency

(1)

Range (V)

C1 C2 MIN MAX

(2) (2)

(3) (3)

2.0 5.5

2.0 5.5

– 32 32.768 35 kHz

Remarks

Leaded Type
On-chip C

Leaded Type
On-chip C

SMD Type

C1 C2

Stabilization time

(2)

VDD = 2.7 V to 5.5 V – 1.0 2 s
VDD = 1.8 V to 5.5 V – – 10

External

Clock

NOTES:

1. Oscillation frequency and XT

2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs.

XTin XTout

XTin input frequency

(1)

XTin input high and
low level width (t
t

)

XTH

input frequency data are for oscillator characteristics only.

in

XTL

,

– 32 – 100 kHz

– 5 – 15 µs

15-6

S3C72C8/P72C8 ELECTRICAL DATA

Table 15-6. Input/Output Capacitance

(TA = 25 °C, V

DD

= 0 V )

Parameter Symbol Condition Min Typ Max Units

Input
Capacitance

Output

C

C

OUT

IN

f = 1 MHz; Unmeasured

pins are returned to V

SS

– – 15 pF

– – 15 pF

Capacitance
I/O Capacitance C

IO

– – 15 pF

Table 15-7. Comparator Electrical Characteristics

(T

= – 40 °C + 85 °C, V

A

= 4.0 V to 5.5 V, V

DD

SS

= 0 V)

Parameter Symbol Condition Min Typ Max Units

Input Voltage Range – – 0 – V
Reference Voltage Range VREF – 0 – V

Input Voltage
Accuracy

Internal VCIN1 – – –
External VCIN2 – – –

Input Leakage Current ICIN, IREF – – 3 – 3

DD
DD

± 150
± 150

V

V
mV
mV

µA

15-7

ELECTRICAL DATA S3C72C8/P72C8

Table 15-8. A.C. Electrical Characteristics

(T

= – 40 °C to + 85 °C, V

A

= 1.8 V to 5.5 V)

DD

Parameter Symbol Conditions Min Typ Max Units

Instruction Cycle

(note)

Time

t

CY

V

= 2.7 V to 5.5 V 0.67 – 64 µs

DD

VDD = 1.8 V to 5.5 V 1.33 64

TCL1 Input
Frequency

TCL1 Input High,
Low Width

SCK Cycle Time

SCK High, Low

Width

SI Setup Time to
SCK High

SI Hold Time to
SCK High

t

TIH1

tKH, t

f

TI1

, t

TIL1VDD

t

KCY

KL

t

SIK

t

KSI

V

= 2.7 V to 5.5 V 0 – 1.5 MHz

DD

VDD = 1.8 V to 5.5 V 1

= 2.7 V to 5.5 V 0.48 – – µs

VDD = 1.8 V to 5.5 V 1.8
V

= 2.7 V to 5.5 V; Input 800 – – ns

DD

Output 650
V

= 1.8 V to 5.5 V; Input 3200

DD

Output 3800
V

= 2.7 V to 5.5 V; Input 325 – – ns

DD

Output t

KCY

/2 – 50
VDD = 1.8 V to 5.5 V; Input 1600
Output

V

= 2.7 V to 5.5 V; Input 100 – – ns

DD

V

= 2.7 V to 5.5 V; Output 150

DD

V

= 1.8 V to 5.5 V; Input 150

DD

V

= 1.8 V to 5.5 V; Output 500

DD

V

= 2.7 V to 5.5 V; Input 400 – – ns

DD

V

= 2.7 V to 5.5 V; Output 400

DD

V

= 1.8 V to 5.5 V; Input 600

DD

V

= 1.8 V to 5.5 V; Output 500

DD

t

KCY

/2 – 150

NOTE: Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock ( fx ) source.

15-8

S3C72C8/P72C8 ELECTRICAL DATA

Table 15-8. A.C. Electrical Characteristics (Continued)

(T

= – 40 °C to + 85 °C, V

A

= 1.8 V to 5.5 V)

DD

Parameter Symbol Conditions Min Typ Max Units

Output Delay for

t

KSO

V

= 2.7 V to 5.5 V; Input – – 300 ns

DD

SCK to SO

V

= 2.7 V to 5.5 V; Output 250

DD

V

= 1.8 V to 5.5 V; Input 1000

DD

V

= 1.8 V to 5.5 V; Output 1000

DD

Interrupt Input
High, Low Width

RESET Input Low

t

INTH

t

RSL

, t

INT0, INT1, INT2, INT4,

INTL

10 – – µs

K0– K3, INTP30, INTP31
Input 10 – – µs

Width

NOTE: Minimum value for INT0 is based on a clock of 2t

CPU CLOCK

1.5 MHz

1.05 MHz 4.2 MHz

0.75 MHz

15.6 kHz

1 2 3 4 5 6 7

1.8
SUPPLY VOLTAGE (V)

CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, or 64)

or 128 / fx as assigned by the IMOD0 register setting.

CY

Main Oscillator Frequency
(Divided by 4)

6 MHz

3.0 MHz

Figure 15-1. Standard Operating Voltage Range

15-9

ELECTRICAL DATA S3C72C8/P72C8

Table 15-9. RAM Data Retention Supply Voltage in Stop Mode

(TA = – 40 °C to + 85 °C)

Parameter Symbol Conditions Min Typ Max Unit

Data retention supply voltage V
Data retention supply current I

DDDR

DDDR

V

DDDR

– 1.8 – 5.5 V

= 1.8 V – 0.1 10 µA

Release signal set time t
Oscillator stabilization wait

(1)

time

SREL

t

WAIT

Released by RESET

Released by interrupt –

NOTES:

1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator
start-up.

2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.

– 0 – – µs

–

17

2

/ fx

(2)

– ms

–

15-10

S3C72C8/P72C8 ELECTRICAL DATA

TIMING WAVEFORMS

Internal Reset

Operation

~

~

Stop Mode

Idle Mode

VDD

RESET

VDD

~

~

Execution of

STOP Instruction

Data Retention Mode

VDDDR

tWAIT

tSREL

Figure 15-2. Stop Mode Release Timing When Initiated By RESETRESET

Idle Mode

~

~

~

~

Execution of

STOP Instruction

Stop Mode

Data Retention Mode

VDDDR

tSREL

Operating Mode

Normal
Operating
Mode

tWAIT

Power-down Mode Terminating Signal
(Interrupt Request)

Figure 15-3. Stop Mode Release Timing When Initiated By Interrupt Request

15-11

ELECTRICAL DATA S3C72C8/P72C8

0.8 VDD

0.8 VDD

Measurement

Points

0.2 VDD

0.2 VDD

Figure 15-4. A.C. Timing Measurement Points (Except for XIN and XTIN)

1/fx

tXHtXL

XIN

VDD - 0.1 V

0.1 V

XTIN

Figure 15-5. Clock Timing Measurement at X

1/fxt

tXTHtXTL

Figure 15-6. Clock Timing Measurement at XT

IN

VDD - 0.1 V

0.1 V

IN

15-12

S3C72C8/P72C8 ELECTRICAL DATA

1/fTI

tTIHtTIL

TCL1

0.7 VDD

0.3 VDD

Figure 15-7. TCL1 Timing

tRSL

RESET

0.2 VDD

Figure 15-8. Input Timing for RESETRESET Signal

INT0, 1, 2, 4
K0 to K3
INTP30, INTP31

Figure 15-9. Input Timing for External Interrupts and Quasi-Interrupts

tINTHtINTL

0.8 VDD

0.2 VDD

15-13

ELECTRICAL DATA S3C72C8/P72C8

tKCY

SCK

SI

SO

tKSO

tKL

tSIK tKSI

Input Data

Output Data

tKH

Figure 15-10. Serial Data Transfer Timing

0.8 VDD

0.2 VDD

0.8 VDD

0.2 VDD

15-14

S3C72C8/P72C8 MECHANICAL DATA

16 MECHANICAL DATA

OVERVIEW

This section contains the following information about the device package:
— Package dimensions in millimeters

— Pad diagram

(1.77)

#42 #22

42-SDIP-600

14.00 ± 0.2

39.50 MAX

39.10 ± 0.2

0.50 ± 0.1

1.00 ± 0.1

1.78

0-15

15.24

#21#1

3.50 ± 0.2

5.08 MAX

3.30 ± 0.3

0.51 MIN

+ 0.1

0.25

- 0.05

NOTE: Dimensions are in millimeters.

Figure 16-1. 42-SDIP-600 Package Dimensions

16-1

MECHANICAL DATA S3C72C8/P72C8

13.20 ± 0.3
0-8

10.00 ± 0.2

0.15

+ 0.10

- 0.05

13.20 ± 0.3

44-QFP-1010B

10.00 ± 0.2

#44

#1

0.80

NOTE: Dimensions are in millimeters.

Figure 16-1. 44-QFP-1010B Package Dimensions

0.35

+ 0.10

- 0.05

0.10 MAX

0.80 ± 0.20

0.05 MIN

(1.00)

2.05 ± 0.10

2.30 MAX

16-2

S3C72C8/P72C8 S3P72C8 OTP

17 S3P72C8 OTP

OVERVIEW

The S3P72C8 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C72C8

microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data
format.

The S3P72C8 is fully compatible with the S3C72C8, both in function and in pin configuration. Because of its
simple programming requirements, the S3P72C8 is ideal for use as an evaluation chip for the S3C72C8.

P2.0/CIN0/K0
P2.1/CIN1/K1

SDAT/P2.2/CIN2/K2
SCLK/P2.3/CIN3/K3

VDD/VDD

VSS/VSS

XOUT

XIN

VPP/TEST

XTIN

XTOUT

Figure 17-1. S3P72C8 44-QFP Pin Assignments

P4.0

P4.1

P1.3/BUZ/INT4

P1.2/CLO/INT2

P1.1/TCL1/INT1

P1.0/TCLO1/INT0

COM0

4443424140393837363534

1
2
3
4
5
6
7
8
9
10
11

S3P72C8

1213141516171819202122

SI/P0.2

SO/P0.1

BTCO/P0.3

RESET

RESET/RESET

SCK/P0.0

INTP31/P3.1

INTP30/P3.0

COM1

COM2

COM3

SEG15/COM4

P5.0/SEG0

P5.1/SEG1

P5.2/SEG2

P5.3/SEG3

33
32
31
30
29
28
27
26
25
24
23

COM5/SEG14
COM6/SEG13
COM7/SEG12
SEG11/P7.3
SEG10/P7.2
SEG9/P7.1
SEG8/P7.0
SEG7/P6.3
SEG6/P6.2
SEG5/P6.1
SEG4/P6.0

17-1

S3P72C8 OTP S3C72C8/P72C8

COM1
COM2

P1.0/TCLO1/INT0

P1.1/TCL1/INT1

P1.2/CLO/INT2
P1.3/BUZ/INT4

P2.0/CIN0/K0
P2.1/CIN1/K1

SDAT/P2.2/CIN2/K2
SCLK/P2.3/CIN3/K3

VDD/VDD

VSS/VSS

XOUT

XIN

VPP/TEST

XTIN

XTOUT

RESETRESET/RESET

P0.3/BTCO

P0.2/SI

P0.1/SO

Figure 17-2. S3P72C8 42-SDIP Pin Assignments

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

S3P72C8

42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22

COM2
COM3
COM4/SEG15
COM5/SEG14
COM6/SEG13
COM7/SEG12
SEG11/P7.3
SEG10/P7.2
SEG9/P7.1
SEG8/P7.0
SEG7/P6.3
SEG6/P6.2
SEG5/P6.1
SEG4/P6.0
SEG3/P5.3
SEG2/P5.2
SEG1/P5.1
SEG0/P5.1
P3.0/INTP30
P3.1/INTP31
P0.0/SCK

17-2

S3C72C8/P72C8 S3P72C8 OTP

Table 17-1. Descriptions of Pins Used to Read/Write the EPROM

Main Chip During Programming

Pin Name Pin Name Pin No. I/O Function

P2.2 SDAT 3 (9) I/O Serial data pin. Output port when reading and

input port when writing. Can be assigned as a
Input/push-pull output port.

P2.3 SCLK 4 (10) I/O Serial clock pin. Input only pin.

TEST

VPP(TEST)

9 (15) I Power supply pin for EPROM cell writing

(indicates that OTP enters into the writing
mode). When 12.5 V is applied, OTP is in
writing mode and when 5 V is applied, OTP is in
reading mode. (Option)

RESET RESET

VDD/V

SS

VDD/V

SS

12 (18) I Chip initialization

5/6 (11/12) I

Logic power supply pin. VDD should be tied to
+ 5 V during programming.

NOTE: Parentheses indicate pin number for 42-SDIP package.

Table 17-2. Comparison of S3P72C8 and S3C72C8 Features

Characteristic S3P72C8 S3C72C8

Program Memory 8 Kbyte EPROM 8 Kbyte mask ROM
Operating Voltage (VDD)

OTP Programming Mode

1.8 V to 5.5 V 1.8 V to 5.5 V
VDD = 5 V, VPP(TEST)=12.5V

Pin Configuration 44-QFP, 42-SDIP 44-QFP, 42-SDIP
EPROM Programmability User Program 1 time Programmed at the factory

OPERATING MODE CHARACTERISTICS

When 12.5 V is supplied to the VPP(TEST) pin of the S3P72C8, the EPROM programming mode is entered.
The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in

Table 17-3 below.

Table 17-3. Operating Mode Selection Criteria

V

DD

V

(TEST) REG/MEM Address

PP

R/W Mode

(A15-A0)

5 V 5 V 0 0000H 1 EPROM read

12.5 V 0 0000H 0 EPROM program

12.5 V 0 0000H 1 EPROM verify

12.5 V 1 0E3FH 0 EPROM read protection

NOTE: "0" means Low level; "1" means High level.

17-3

S3P72C8 OTP S3C72C8/P72C8

Table 17-4. D.C. Electrical Characteristics

(T

= - 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)

A

Parameter Symbol Conditions Min Typ Max Units

(2)

V

Supply
Current

(1)

I

DD1

= 5 V ± 10%

DD

Crystal oscillator

6.0 MHz

4.19 MHz

– 3.0

2.3

8.0

5.5

mA

C1 = C2 = 22 pF
V

I

DD2

DD

(2)

Idle mode
VDD = 5 V ± 10%

= 3 V ± 10%

6.0 MHz

4.19 MHz

6.0 MHz

4.19 MHz

1.5

1.0

1.3

1.2

4.0

3.0

2.5

1.8

Crystal oscillator
C1 = C2 = 22 pF

V

I

DD3

(3)

= 3 V ± 10%

DD

V

= 3 V ± 10%

DD

6.0 MHz

4.19 MHz

0.5

0.44

1.5

1.0

– 15.0 30

µA

32 kHz crystal oscillator

(3)

I

DD4

Idle mode; V

= 3 V ± 10%

DD

5.0 15

32 kHz crystal oscillator

I

DD5

Stop mode;
VDD = 5 V ± 10%

SCMOD =
0000B

2.5 5

XTIN = 0V

Stop mode;

0.5 3

VDD = 3 V ± 10%
VDD = 5 V ± 10%

SCMOD =

0.2 3

0100B

VDD = 3 V ± 10%

NOTES:

1. Currents in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage dividing resistors,
comparator, output port drive currents.

2. Data includes power consumption for subsystem clock oscillation.

3. When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the
subsystem clock is used.

4. Every values in this table is measured when the power control register (PCON) is set to "0011B".

0.1 2

17-4

S3C72C8/P72C8 S3P72C8 OTP

Main Oscillator Frequency

CPU CLOCK

1.5 MHz

1.05 MHz 4.2 MHz

0.75 MHz

15.6 kHz

(Divided by 4)
6 MHz

3.0 MHz

1 2 3 4 5 6 7

1.8
SUPPLY VOLTAGE (V)

CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, or 64)

Figure 17-3 Standard Operating Voltage Range

17-5

S3P72C8 OTP S3C72C8/P72C8

NOTES

17-6