Samsung's SAM87 family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide
range of integrated peripherals, and various mask-programmable ROM sizes. Important CPU features include:
— Efficient register-oriented architecture
— Selectable CPU clock sources
— Release by interrupt of Idle and Stop power-down modes
— Built-in basic timer circuit with watchdog function
A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more
interrupt sources and vectors. Fast interrupt processing (within a minimum six CPU clocks) can be assigned to
specific interrupt levels.
S3C8835/C8837/P8837
The S3C8835 microcontroller has 16 K bytes of on-chip program memory and the S3C8837 has 24 K bytes. Both
chips have a 272-byte general-purpose internal register file. The interrupt structure has seven interrupt sources
with six interrupt vectors. The CPU recognizes six interrupt priority levels.
Using a modular design approach, the following peripherals were integrated with the SAM87 core to make the
S3C8835/C8837/P8837 suitable for use in color television and other types of screen display applications:
— Four programmable I/O ports (26 pins total: 16 general-purpose I/O pins; 8 n-channel, open-drain output pins)
— 2 channel A/D converter (4-bit resolution)
— 14-bit PWM output (one channels: push-pull type)
— Basic timer (BT) with watchdog timer function
— One 8-bit timer/counter (T0) with interval timer
— One 8-bit general-purpose timer/counter (TA) with prescalers
— On-screen display (OSD) with a wide range of programmable features including halftone control signal output
The S3C8835/C8837 are available in a versatile 42-pin SDIP package.
OTP
The S3C8835/C8837 microcontroller is also available in OTP (One Time Programmable) version, S3P8837.
S3P8837 microcontroller has an on-chip 24K-byte one-time-programmable EPROM instead of masked ROM.
The S3P8837 is comparable to S3C8835/C8837, both in function and in pin configuration.
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Page 2
PRODUCT OVERVIEWS3C8835/C8837/P8837
FEATURES
CPU
•SAM87 CPU core
Memory
•16-K byte (S3C8835) or 24K- byte (S3C8837)
internal program memory
•272-byte general-purpose register area
Instruction Set
•78 instructions
•IDLE and STOP instructions added for powerdown modes
Instruction Execution Time
•750 ns (minimum) with an 8-MHz CPU clock
Interrupts
•7 interrupt sources with 6 vectors
•6 interrupt levels
•Fast interrupt processing for select levels
General I/O
Pulse Width Modulation Module
•14-bit PWM with one-channel output (push-pull
type)
•PWM counter and data capture input pin
•Frequency: 5.859 kHz to 23.437 kHz with a
6-MHz CPU clock
P0.0–P0.7I/OGeneral I/O port (8-bit), configurable for
digital input or push-pull output.
P1.0–P1.1I/OGeneral I/O port (2-bit), configurable for
digital input or n-channel open-drain output.
P1.0–P1.1 can withstand up to 6-volt loads.
Multiplexed for alternative use as external
interrupt inputs INT0–INT1.
P1.2–P1.5General I/O port (4-bit), configurable for
digital input or n-channel open-drain output.
P1.2–P1.5 can withstand up to 6-volt loads.
High current port (10mA).
P1.6–P1.7General I/O port (2-bit), configurable for
digital input or push-pull output.
P2.0–P2.4,
P2.6
I/OGeneral I/O port (6-bit). I/O mode or
n-channel open-drain, push-pull output
mode is software configurable. Pins can
withstand up to 5-volt loads.
P2.2: OTP serial clock pin
P2.3: OTP serial data pin
P2.5, P2.7General I/O port (2-bit). I/O mode or
n-channel open-drain, push-pull output
mode is software configurable. Pins can
withstand up to 5-volt loads.
Each pin has an alternative function.
P2.5: PWM0 (14-bit PWM output)
P2.7: OSDHT (Halftone signal output)
NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.
15-3
Page 12
ELECTRICAL DATAS3C8835/C8837/P8837
Table 15-3. Input/Output Capacitance
(T
= – 20°C to + 85°C, V
A
DD
=0 V)
ParameterSymbolConditionsMinTypMaxUnit
C
C
OUT
IN
f = 1 MHz; unmeasured pins
are connected to V
SS
––10pF
Input
capacitance
Output
capacitance
I/O capacitance
C
IO
Table 15-4. A.C. Electrical Characteristics
(T
= – 20°C to + 85°C, V
A
= 4.5 V to 5.5 V)
DD
ParameterSymbolConditionsMinTypMaxUnit
V-sync Pulse
t
VW
–4––µs
Width
H-sync Pulse
t
HW
–3––µs
Width
Noise Filter
t
NF1
t
NF2
t
NF3
t
NF4
t
NF5
P1.0–P1.1, V-sync–350–ns
RESET
–1000
Glitch filter (oscillator block)–15
CAPA–5–
t
CAPA
H-sync–650–ns
NOTE: t
CAPA
= f
/128.
OSC
1t
CPU
t
NF1L
t
NF2
0.8 V
0.2 V
Figure 15-1. Input Timing Measurement Points for t
DD
DD
t
NF1H
NF1
and t
NF2
15-4
Page 13
S3C8835/C8837/P8837ELECTRICAL DATA
Table 15-5. Data Retention Supply Voltage in Stop Mode
(TA = – 20 °C to + 85 °C)
ParameterSymbolConditionsMinTypMaxUnit
Data Retention
V
DDDR
Stop mode2–6V
Supply Voltage
Data Retention
I
DDDR
Stop mode, V
DDDR
= 2.0 V
––5µA
Supply Current
NOTES:
1.Supply current does not include current drawn through internal pull-up resistors or external output current loads.
2.During the oscillator stabilization wait time (t
~
~
~
~
V
DD
EXECUTION OF
STOP INSTRUCTION
RESET
), all CPU operations must be stopped.
WAIT
STOP MODE
DATA RETENTION MODE
V
DDDR
t
SREL
OSCILLATION
STABILIZATION
TIME
NORMAL
OPERATING
MODE
NOTE:
t
is the same as 4096 x 16 x 1 / f
WAIT
OSC
t
WAIT
Figure 15-2. Stop Mode Release Timing When Initiated by a Reset
15-5
Page 14
ELECTRICAL DATAS3C8835/C8837/P8837
Table 15-6. Main Oscillator and L-C Oscillator Frequency
(TA = – 20°C to + 85°C, VDD = 4.5 V to 5.5 V)
OscillatorClock CircuitConditionsMinTypMaxUnit
Crystal
C1
C2
X
X
IN
OSD block active568MHz
OUT
OSD block inactive0.568
Ceramic
C1
C2
X
X
IN
OSD block active568MHz
OUT
OSD block inactive0.568
External Clock
X
IN
OSD block active568MHz
X
OUT
OSD block inactive0.568
L-C Oscillator
C1
C2
OSC
OSC
Recommend value:
IN
C1 = C2 = 20 pF
OUT
56.58MHz
CPU Clock Frequency–0.0326.08MHz
1 / f
OSC
t
XL
X
IN
t
XH
2.7 V
1.0 V
15-6
Figure 15-3. Clock Timing Measurement Points for X
IN
Page 15
S3C8835/C8837/P8837ELECTRICAL DATA
Table 15-7. Main Oscillator Clock Stabilization Time
(TA = – 20°C to + 85°C, VDD = 4.5 V to 5.5 V)
OscillatorSymbolTest ConditionMinTypMaxUnit
Crystal–
VDD = 4.5 V to 6.0 V
––20ms
Ceramic(Oscillation stabilization occurs when
10
VDD is equal to the minimum oscillator
voltage range.)
External Clock
Release Signal
t
SREL
XIN input High and Low level width
(t
XH, tXL
)
65–100ns
Normal operation–1000–ns
Setup Time
Oscillation
Stabilization
Wait Time
(1)
t
WAIT
CPU clock = 8 MHz; Stop mode
released by RESET
CPU clock = 8 MHz; Stop mode
–8.3–ms
(2)
released by an interrupt
NOTES:
1.Oscillation stabilization time is the time required for the CPU clock to return to its normal oscillation frequency after a
power-on occurs, or when Stop mode is released.
2.The oscillation stabilization interval is determined by the basic timer (BT) input clock setting.
= – 20°C to + 85°C, VDD = 4.5 V to 5.5 V, VSS = 0 V)
A
ParameterSymbolConditionsMinTypMaxUnit
Absolute
Accuracy
(1)
Conversion
(2)
Time
Analog Input
–CPU clock = 8 MHz––
t
CON
V
IAN
–
t
CPU
(3)
V
SS
× 25
± 0.5
LSB
–µs
–
V
DD
V
Voltage
Analog Input
R
AN
–2–
MΩ
Impedance
NOTES:
1.Excluding quantization error, absolute accuracy values are within ± 1/2 LSB.
2.'Conversion time' is the time required from the moment a conversion operation starts until it ends.
3.The unit t
means one CPU clock period.
CPU
15-7
Page 16
S3C8835/C8837/P8837MECHANICAL DATA
16MECHANICAL DATA
OVERVIEW
The S3C8835/C8837 microcontrollers are available in a 42-pin SIP package (42-SDIP-600).
14.00 ± 0.2
(1.77)
0.50 ± 0.1
4222
42-SDIP-600
#121
39.10 ± 0.2
1.00 ± 0.1
1.778
15.24
0.51MIN3.50 ± 0.2
3.30 ± 0.35.08MAX
+0.1
– 0.05
0.25
0 ~ 15 °
: Package dimensions are in millimeters.
NOTE
Figure 16-1. 42-Pin SDIP Package Mechanical Data (42-SDIP-600)
16-1
Page 17
S3C8835/C8837/P8837S3P8837 OTP
17S3P8837 OTP
OVERVIEW
The S3P8837 single-chip CMOS microcontroller is the OTP (One Time Programmable)version of the
S3C8835/C8837 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed
by serial data format.
The S3P8837 is fully compatible with the S3C8835/C8837, both in function and in pin configuration. Because of
its simple programming requirements, the S3P8837 is ideal for use as an evaluation chip for the
S3C8835/C8837.