Datasheet S24022PAT, S24022PB, S24022PBT, S24023P2.7, S24023P2.7T Datasheet (SUMMIT)

SUMMIT MICROELECTRONICS, Inc. • 300 Orchard City Drive, Suite 131 • Campbell, CA 95008 • Telephone [phone] • Fax [phone] • www.summitmicro.com

1

© SUMMIT MICROELECTRONICS, Inc. 2000
2011 2.0 5/2/00

Characteristics subject to change without notice

SUMMIT

MICROELECTRONICS, Inc.

FEATURES

• Precision Supply Voltage Monitor
— Dual reset outputs for complex

microcontroller systems

— Integrated memory write lockout

• Guaranteed RESET (RESET#) assertion
to VCC=1V

• Power-Fail Accuracy Guaranteed

• No External Components

• 3 and 5 Volt system versions

• Low Power CMOS
— Active current less than 3mA

— Standby current less than 25µA

• Memory Internally Organized 512 X 8
— Two Wire Serial Interface (I2C™)

– Bidirectional data transfer protocol
– Standard 100KHz and Fast 400KHz

Precision RESET Controller and 4K I2C Memory
With Both RESET and

RESETRESET

RESETRESET

RESET Outputs

S24042/S24043

• High Reliability
— Endurance: 100,000 erase/write cycles

— Data retention: 100 years

• 8-Pin PDIP or SOIC Packages

OVERVIEW

The S24042 and S24043 are power supervisory devices
with 4,096 bits of serial E

2

PROM. They are fabricated
using SUMMIT’s advanced CMOS E2PROM technology
and are suitable for both 3 and 5 volt systems.

The memory is internally organized as 512 x 8. It features
the I2C serial interface and software protocol allowing
operation on a simple two-wire bus.

The S24042 provides a precision VCC sense circuit and
two open drain outputs: one (RESET) drives high and the

other (RESET#) drives low whenever VCC falls below
V

TRIP

. The S24043 is identical to the S24042 with the

exception being RESET is not bonded out on pin 7.

BLOCK DIAGRAM

3 and 5 Volt Systems

+

–

GND

V

CC

RESET#

V

TRIP

RESET
PULSE

GENERATOR

5kHz

OSCILLATOR

RESET

CONTROL

MODE

DECODE

ADDRESS
DECODER

WRITE

CONTROL

DATA I/O

E2PROM

MEMORY

ARRAY

RESET

1.26V

SCL

6

SDA

5

2

7

22

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4

2

S24042/S24043

2011 2.0 5/2/00 SUMMIT MICROELECTRONICS, Inc.

RESET #- RESET# is an active low open drain output.
It is driven low whenever VCC is below V

TRIP

. It is also
an input and can be used to debounce a switch input or
perform signal conditioning. The pin has an internal pull­up and should be left unconnected if the signal is not used
in the system. However, when the pin is tied to a system
RESET# line an external pull-up resistor should be
employed.

RESET - RESET is an active high open drain output. It is
driven high whenever VCC is below V

TRIP

. RESET is also
an input and can be used to debounce a switch input or
perform signal conditioning. The RESET pin does have
an internal pull-down and should be left unconnected if
the signal is not used in the system. However, when the
pin is tied to a system reset line an external pull-down
resistor should be employed.

ENDURANCE AND DATA RETENTION

The S24042/43 is designed for applications requiring
100,000 erase/write cycles and unlimited read cycles. It
provides 100 years of secure data retention, with or
without power applied, after the execution of 100,000

erase/write cycles.

APPLICATIONS

Reset Controller Description

The S24042/43 provides a precision RESET controller
that ensures correct system operation during brown-out
and power-up/-down conditions. It is configured with two
open drain RESET outputs; pin 7 is an active high output
and pin 2 is an active low output.

During power-up, the RESET outputs remain active until
VCC reaches the V

TRIP

threshold and will continue driving
the outputs for approximately 200ms after reaching
V

TRIP

. The RESET outputs will be valid so long as VCC is
> 1.0V. During power-down, the RESET outputs will
begin driving active when VCC falls below V

TRIP

.

The RESET pins are I/Os; therefore, the S24042/43 can
act as a signal conditioning circuit for an externally
applied reset. The inputs are edge triggered; that is, the
RESET input will initiate a reset timeout after detecting a

low to high transition and the RESET# input will initiate a
reset timeout after detecting a high to low transition. Refer

to the applications Information section for more details on
device operation as a reset conditioning circuit.

PIN DESCRIPTIONS
Serial Clock (SCL) - The SCL input is used to clock data

into and out of the device. In the WRITE mode, data must
remain stable while SCL is HIGH. In the READ mode, data
is clocked out on the falling edge of SCL.

Serial Data (SDA) - The SDA pin is a bidirectional pin
used to transfer data into and out of the device. Data may
change only when SCL is LOW, except START and STOP
conditions. It is an open-drain output and may be wire­ORed with any number of open-drain or open-collector
outputs.

No Connects (NC) the no connect pins may be left
floating or tied to ground. They cannot be tied high.

PIN NAMES

SD A Serial Data I/O

S C L Serial Clock Input

RESET & RESET# Reset Output

V

SS

Ground

V

CC

Supply Voltage

N C No Connect

PIN CONFIGURATIONS

8

7
6
5

1

2
3
4

NC

RESET#

NC

V

SS

V

CC

NC
SCL
SDA

NC

RESET#

NC

V

SS

V

CC

RESET
SCL
SDA

8

7
6
5

1

2
3
4

S24043

S24042

2011 PCon 2.0

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SUMMIT MICROELECTRONICS, Inc.

FIGURE 1. TYPICAL SYSTEM CONFIGURATION FOR DUAL RESET

FIGURE 2. START AND STOP CONDITIONS

SCL

SDA In

START

Condition

STOP

Condition

2011 ILL5 1.0

RESET

SCL

SDA

SCL

Vss

VCC = 3.0 0r 5.0

8051 Type MCU

S24042

I C
Peripheral

2

2

1

3

4

7

8

6

5

2011 T fig01 2.0

Vcc

RESET

SDA

SCL

SDA

RESET#

RESET#

4

S24042/S24043

2011 2.0 5/2/00 SUMMIT MICROELECTRONICS, Inc.

FIGURE 3. ACKNOWLEDGE RESPONSE FROM RECEIVER

CHARACTERISTICS OF THE I2C BUS

General Description

The I2C bus was designed for two-way, two-line serial
communication between different integrated circuits. The
two lines are: a serial data line (SDA), and a serial clock
line (SCL). The SDA line must be connected to a positive
supply by a pull-up resistor, located somewhere on the
bus (See Figure 1). Data transfer between devices may
be initiated with a START condition only when SCL and
SDA are HIGH (bus is not busy).

Input Data Protocol

One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable during clock
HIGH time, because changes on the data line while SCL
is HIGH will be interpreted as start or stop condition, refer
to Figure 10.

START and STOP Conditions

When both the data and clock lines are HIGH, the bus is
said to be not busy. A HIGH-to-LOW transition on the data
line, while the clock is HIGH, is defined as the “START”
condition. A LOW-to-HIGH transition on the data line,
while the clock is HIGH, is defined as the “STOP” condi­tion (See Figure 2).

DEVICE OPERATION

The S24042/43 is a 4,096-bit serial E2PROM. The device
supports the I2C bidirectional data transmission protocol.
The protocol defines any device that sends data onto the
bus as a “transmitter” and any device which receives data
as a “receiver.” The device controlling data transmission
is called the “master” and the controlled device is called
the “slave.” In all cases, the S24042/43 will be a “slave”
device, since it never initiates any data transfers.

FIGURE 4. SLAVE ADDRESS BYTE

Acknowledge (ACK)

Acknowledge is a software convention used to indicate
successful data transfers. The transmitting device, either
the master or the slave, will release the bus after transmit­ting eight bits. During the ninth clock cycle, the receiver
will pull the SDA line LOW to ACKnowledge that it re­ceived the eight bits of data (See Figure 3).

The S24042/43 will respond with an ACKnowledge after
recognition of a START condition and its slave address
byte. If both the device and a write operation are selected,
the S24042/43 will respond with an ACKnowledge after
the receipt of each subsequent 8-bit word.

In the READ mode, the S24042/43 transmits eight bits of
data, then releases the SDA line, and monitors the line for
an ACKnowledge signal. If an ACKnowledge is detected,
and no STOP condition is generated by the master, the
S24042/43 will continue to transmit data. If an
ACKnowledge is not detected, the S24042/43 will termi­nate further data transmissions and awaits a STOP condi­tion before returning to the standby power mode.

Device Addressing

Following a start condition the master must output the
address of the slave it is accessing. The most significant
four bits of the slave address are the device type identifier
(see figure 4). For the S24042/43 this is fixed as 1010[B].

The next two bits are don’t care. The next bit is the high
order address bit A8.

SCL from

Master

Data Output

from

Transmitter

Data Output

from

Receiver

Start
Condition

ACKnowledge

t

AA

t

AA

1

8

9

2011 ILL6 1.0

1 0 1 0

X X R/W

DEVICE

IDENTIFIER

DON’T CARE

2011 ILL7 1.1

A
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SUMMIT MICROELECTRONICS, Inc.

FIGURE 5. PAGE/BYTE WRITE MODE

WRITE OPERATIONS

The S24042/43 allows two types of write operations: byte
write and page write. The byte write operation writes a
single byte during the nonvolatile write period (tWR). The
page write operation allows up to 16 bytes in the same
page to be written during tWR.

Byte WRITE

Upon receipt of the slave address and word address, the
S24042/43 responds with an ACKnowledge. After receiv­ing the next byte of data, it again responds with an
ACKnowledge. The master then terminates the transfer
by generating a STOP condition, at which time the
S24042/43 begins the internal write cycle.

While the internal write cycle is in progress, the S24042/
43 inputs are disabled, and the device will not respond to
any requests from the master. Refer to Figure 5 for the
address, ACKnowledge and data transfer sequence.

Page WRITE

The S24042/43 is capable of a 16-byte page write opera­tion. It is initiated in the same manner as the byte-write
operation, but instead of terminating the write cycle after
the first data word, the master can transmit up to 15 more
bytes of data. After the receipt of each byte, the S24042/
43 will respond with an ACKnowledge.

The S24042/43 automatically increments the address for
subsequent data words. After the receipt of each word,
the low order address bits are internally incremented by
one. The high order five bits of the address byte remain
constant. Should the master transmit more than 16 bytes,
prior to generating the STOP condition, the address
counter will “roll over,” and the previously written data will
be overwritten. As with the byte-write operation, all inputs
are disabled during the internal write cycle. Refer to
Figure 5 for the address, ACKnowledge and data transfer
sequence.

Read/Write Bit

The last bit of the data stream defines the operation to be
performed. When set to “1,” a read operation is selected;
when set to “0,” a write operation is selected.

D7D6D5D4D3D2D1D

0

D7D6D5D4D3D2D1D

0

A
7

A
8

A
8

A6A5A4A3A2A1A0D7D5D6D

4

D
0

D3D2D

1

S
T
A
R
T

Word Address Data Byte n Data Byte n+15

S
T
O
P

A

C

K

Acknowledges Transmitted from

24042/43 to Master Receiver

Slave Address

Device

Type

Address

Read/Write

0= Write

SDA
Bus
Activity

A
C
K

A
C
K

Master Sends Read
Request to Slave

Master Writes Word
Address to Slave

1 0 1 0

0

Data Byte n+1

A
C
K

Master Writes
Data to Slave

Master Transmitter

to

Slave Receiver

Slave Transmitter

to

Master Receiver

Slave Transmitter

to

Master Receiver

Master Transmitter

to

Slave Receiver

Master Transmitter

to

Slave Receiver

Shading Denotes

24042/43

SDA Output Active

Master Transmitter

to

Slave Receiver

Slave Transmitter

to

Master Receiver

Slave Transmitter

to

Master Receiver

Master Transmitter

to

Slave Receiver

Slave Transmitter

to

Master Receiver

Master Writes
Data to Slave

Master Writes
Data to Slave

Acknowledges Transmitted from

24042/43 to Master Receiver

If single byte-write only,

Stop bit issued here.

XX

R

W

A
C
K

2011 ILL8 1.0

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2011 2.0 5/2/00 SUMMIT MICROELECTRONICS, Inc.

FIGURE 7. CURRENT ADDRESS BYTE READ MODE

FIGURE 6. ACKNOWLEDGE POLLING

Acknowledge Polling

When the S24042/43 is performing an internal WRITE
operation, it will ignore any new START conditions. Since
the device will only return an acknowledge after it accepts
the START, the part can be continuously queried until an
acknowledge is issued, indicating that the internal WRITE
cycle is complete.

To poll the device, give it a START condition, followed by
a slave address for a WRITE operation (See Figure 6).

READ OPERATIONS

Read operations are initiated with the R/W bit of the
identification field set to “1.” There are four different read
options:

1. Current Address Byte Read

2. Random Address Byte Read

3. Current Address Sequential Read

4. Random Address Sequential Read

Current Address Byte Read

The S24042/43 contains an internal address counter
which maintains the address of the last word accessed,
incremented by one. If the last address accessed (either
a read or write) was to address location n, the next read
operation would access data from address location n+1
and increment the current address pointer. When the
S24042/43 receives the slave address field with the R/W
bit set to “1,” it issues an acknowledge and transmits the
8-bit word stored at address location n+1.

The current address byte read operation only accesses a
single byte of data. The master does not acknowledge the
transfer, but does generate a stop condition. At this point,
the S24042/43 discontinues data transmission. See Fig­ure 7 for the address acknowledge and data transfer
sequence.

Issue Start

Internal WRITE Cycle

In Progress;

Begin ACK Polling

Issue Slave

Address and

R/W = 0

ACK

Returned?

Next

operation a

WRITE?

Issue Byte

Address

Proceed with

WRITE

Issue Stop

Await Next

Command

Issue Stop

No

No

Yes (Internal WRITE Cycle is completed)

Yes

2011 ILL9 1.0

S
T
A
R
T

S
T

O

P

Slave Address

Device

Type

Address

Read/Write

1= Read

SDA Bus Activity

D7D6D5D4D3D2D1D

0

Master sends Read
request to Slave

Slave sends
Data to Master

Master Transmitter

to

Slave Receiver

Slave Transmitter

to

Master Receiver

11100 1

Lack of ACK (low)
from Master
determines last
data byte to be read

1

Shading Denotes

24042/43

SDA Output Active

XX

R
W

A
C
K

X

Data Byte

2011 ILL 10 1.0

S24042/S24043

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2011 2.0 5/2/00

SUMMIT MICROELECTRONICS, Inc.

FIGURE 8. RANDOM ADDRESS BYTE READ MODE

Random Address Byte Read

Random address read operations allow the master to
access any memory location in a random fashion. This
operation involves a two-step process. First, the master
issues a write command which includes the start condi­tion and the slave address field (with the R/W bit set to
WRITE) followed by the address of the word it is to read.
This procedure sets the internal address counter of the
S24042/43 to the desired address.

After the word address acknowledge is received by the
master, the master immediately reissues a start condition
followed by another slave address field with the R/W bit
set to READ. The S24042/43 will respond with an ac­knowledge and then transmit the 8-data bits stored at the
addressed location. At this point, the master does not
acknowledge the transmission but does generate the stop
condition. The S24042/43 discontinues data transmis­sion and reverts to its standby power mode. See Figure 8
for the address, acknowledge and data transfer se­quence.

D7D6D5D4D3D2D1D

0

A

7

A
8

A
8

A6A5A4A3A2A1A

0

S
T
A
R
T

Word Address

S
T
O
P

A
C
K

Slave Address

Slave Address

Device

Type

Address

Read/Write

0= Write

Device

Type

Address

SDA Bus
Activity

S
T
A
R
T

Read/Write

1= Read

A

C

K

A
C
K

Master sends Read
request to Slave

Master Writes Word
Address to Slave

Master Requests
Data from Slave

Slave sends
Data to Master

1010 1010 10

XX

R
W

X

R

W

XX

Lack of ACK (low)
from Master
determines last
data byte to be read

1

Slave Transmitter

to

Master Receiver

Slave Transmitter

to

Master Receiver

Shading Denotes

24042/43

SDA Output Active

Slave Transmitter

to

Master Receiver

Master Transmitter

to

Slave Receiver

Master Transmitter

to

Slave Receiver

Master Transmitter

to

Slave Receiver

Slave Transmitter

to

Master Receiver

Data Byte

2011 ILL11 1.0

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S24042/S24043

2011 2.0 5/2/00 SUMMIT MICROELECTRONICS, Inc.

Sequential READ

Sequential READs can be initiated as either a current
address READ or random access READ. The first word is
transmitted as with the other byte read modes (current
address byte READ or random address byte READ);
however, the master now responds with an ACKnowledge,
indicating that it requires additional data from the
S24042/43. The S24042/43 continues to output data for
each ACKnowledge received. The master terminates the
sequential READ operation by not responding with an
ACKnowledge, and issues a STOP conditions.

During a sequential read operation, the internal address
counter is automatically incremented with each acknowl­edge signal. For read operations, all address bits are
incremented, allowing the entire array to be read using a
single read command. After a count of the last memory
address, the address counter will ‘roll-over’ and the
memory will continue to output data. See Figure 9 for the
address, acknowledge and data transfer sequence.

FIGURE 9. SEQUENTIAL READ OPERATION (starting with a Random Address READ)

D7D6D5D4D3D2D1D

0

D7D6D5D4D3D2D1D

0

A
7

A
8

A
8

A6A5A4A3A2A1A

0

Shading Denotes

24042/43

SDA Output Active

S
T
A
R
T

Word Address

S
T
O
P

A
C
K

Acknowledges from 24042/43

Slave AddressSlave Address

Device

Type

Address

Read/Write

0= Write

Device

Type

Address

SDA Bus
Activity

S
T
A
R
T

Read/Write

1= Read

X

R
W

X

Acknowledge from

Master Receiver

A
C
K

A
C
K

A
C
K

Master sends Read
request to Slave

Master Writes Word
Address to Slave

Master Requests
Data from Slave

Slave sends
Data to Master

Slave Transmitter

to

Master Receiver

Slave Transmitter

to

Master Receiver

Master Transmitter

to

Slave Receiver

1010 1010 10

Slave sends
Data to Master

XX

R
W

Lack of ACK (low)
determines last
data byte to be read

1

Lack of

Acknowledge from

Master Receiver

Slave Transmitter

to

Master Receiver

Master Transmitter

to

Slave Receiver

Master Transmitter

to

Slave Receiver

Master Transmitter

to

Slave Receiver

Slave Transmitter

to

Master Receiver

Slave Transmitter

to

Master Receiver

Last Data Byte

First Data Byte

2011 T fig09 2.0

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8

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2011 2.0 5/2/00

SUMMIT MICROELECTRONICS, Inc.

ABSOLUTE MAXIMUM RATINGS

Temperature Under Bias ............................................................................................................................... -40°C to +85°C

Storage Temperature ..................................................................................................................................... -65°C to +125°C

Soldering Temperature (less than 10 seconds) ...................................................................................................................300°C

Supply Voltage ............................................................................................................................................................. 0 to 6.5V

Voltage on Any Pin ....................................................................................................................................... -0.3V to V

CC

+0.3V

ESD Voltage (JEDEC method) .......................................................................................................................................... 2,000V

NOTE: These are STRESS ratings only. Appropriate conditions for operating these devices are given elsewhere in this specification. Stresses
beyond those listed here may permanently damage the part. Prolonged exposure to maximum ratings may affect device reliability.

2.7V to 4.5V 4.5V to 5.5V

Symbol Parameter Conditions Min Max Min Max Units

fSCL SCL Clock Frequency 0 100 400 KHz
tLOW Clock Low Period 4.7 1.3 µs
tHIGH Clock High Period 4.0 0.6 µs
tBUF Bus Free Time Before New Transmission 4.7 1.3 µs
tSU:STA Start Condition Setup Time 4.7 0.6 µs
tHD:STA Start Condition Hold Time 4.0 0.6 µs
tSU:STO Stop Condition Setup Time 4.7 0.6 µs
tAA Clock to Output SCL Low to SDA Data Out Valid 0.3 3.5 0.2 0.9 µs
tDH Data Out Hold Time SCL Low to SDA Data Out Change 0.3 0.2 µs
tR SCL and SDA Rise Time 1000 300 ns
tF SCL and SDA Fall Time 300 300 ns
tSU:DAT Data In Setup Time 250 100 ns
tHD:DAT Data In Hold Time 0 0 ns

TI Noise Spike Width Noise Suppression Time Constant 100 100 ns

@ SCL, SDA Inputs

tWR Write Cycle Time 10 10 ms

AC ELECTRICAL CHARACTERISTICS
(over recommended operating conditions unless otherwise specified)

2011 PGM T2 1.0

2011 PGM T1 1.0

DC ELECTRICAL CHARACTERISTICS (over recommended operating conditions unless otherwise specified)

Symbol Parameter Conditions Min Max Units

SCL = CMOS Levels @ 100KHz V

CC

=5.5V 3 mA

I

CC

Supply Current (CMOS) SDA = Open

All other inputs = GND or V

CC

V

CC

=3.3V 2 mA

I

SB

Standby Current (CMOS) SCL = SDA = V

CC

V

CC

=5.5V 50 µA

All other inputs = GND

I

LI

Input Leakage VIN = 0 To V

CC

10 µA

I

LO

Output Leakage V

OUT

= 0 To V

CC

10 µA

V

IL

Input Low Voltage SCL, SDA, RESET 0.3xV

CC

V

V

IH

Input High Voltage SCL, SDA 0.7xV

CC

V

V

OL

Output Low Voltage IOL = 3mA SDA 0.4 V

V

CC

=3.3V 25 µA

Characteristic Min Max

V

CC

2.7V 5.5V

Operating Temperature Range –40°C85°C

RECOMMENDED OPERATING CONDITIONS

2011 PGM T6 1.0

10

S24042/S24043

2011 2.0 5/2/00 SUMMIT MICROELECTRONICS, Inc.

FIGURE 10. BUS TIMING

CAPACITANCE

TA = 25°C, f = 100KHz

Symbol Parameter Max Units

C

IN

Input Capacitance 5 pF

C

OUT

Output Capacitance 8 pF

2011 PGM T3 1.0

SCL

SDA In

SDA Out

t

AA

t

R

t

H IGHtLOW

t

SU:STO

t

BUF

t

SU:DAT

t

HD:DAT

t

HD:SDA

t

SU:SDA

t

DH

2011 ILL 13 1.0

t

F

S24042/S24043

11

2011 2.0 5/2/00

SUMMIT MICROELECTRONICS, Inc.

FIGURE 11. RESET OUTPUT TIMING

S24042/43-2.7 S24042/43–A S24042/43–B

Symbol Parameter Min Max Min Max Min Max Unit

V

TRIP

Reset Trip Point 2.55 2.7 4.25 4.5 4.5 4.75 V

t

PURST

Power-Up Reset Timeout 130 270 130 270 130 270 ms

t

RPD

V

TRIP

to RESET Output Delay 5 5 5 µs

V

RVALID

RESET# Output Valid 1 1 1 V

t

GLITCH

Glitch Reject Pulse Width 30 30 30 ns

V

OLRS

RESET# Output Low Voltage IOL= 1mA 0.4 0.4 0.4 V

V

OHRS

RESET Output High Voltage IOH = 800 µA VCC-.75 VCC-.75 VCC-.75 V

RESET CIRCUIT AC and DC ELECTRICAL CHARACTERISTICS

TA = -40°C to +85°C

2011 PGM T6 1.1

V

CC

V

RVALID

V

TRIP

t

PURST

RESET#

RESET

2011 T fig11 2.0

t

GLITCH

t

RPD

t

PURST

t

RPD

S24042 only

12

S24042/S24043

2011 2.0 5/2/00 SUMMIT MICROELECTRONICS, Inc.

Frequently the reset controller will be deployed on a PC board that provides a peripheral function to a system.
Examples might be modem or network cards in a PC or a PCMCIA card in a laptop. In instances like this the peripheral
card may have a requirement for a clean reset function to insure proper operation. The system may or may not provide
a reset pulse of sufficient duration to clear the peripheral or to protect data stored in a nonvolatile memory.

The I/O capability of the RESET pins can provide a solution. The system’s reset signal to the peripheral can be fed
into the S24042/43 and it in turn can clean up the signal and provide a known entity to the peripheral’s circuits. The
figure below shows the basic timing characteristics under the assumption the reset input is shorter in duration than
t

PURST

. The same reset output affect can be attained by using the active high reset input.

When planning your resistor pull-up and pull-down values, use the following chart to help determine min. resistances.

Condition Min Typ Max Units

VCC = 1.0V, IOL=100µA 0.3 V
VCC = 1.2V, IOL=100µA 0.3 V
VCC = 3.0V, IOL=500µA 0.3 V
VCC = 3.6V, IOL=500µA 0.3 V
VCC = 4.5V, IOL=750µA 0.3 V
VCC = 1.0V, IOL=100µA 0.4 V
VCC = 1.2V, IOL=150µA 0.4 V
VCC = 3.0V, IOL=750µA 0.4 V
VCC = 3.6V, IOL=1mA 0.4 V
VCC = 4.5V, IOL=1mA 0.4 V
VCC = 1.0V, IOH=400µA VCC-0.75 V
VCC = 1.2V, IOH=800µA VCC-0.75 V
VCC = 3.0V, IOH=800µA VCC-0.5 V
VCC = 3.6V, IOH=800µA VCC-0.5 V
VCC = 4.5V, IOH=800µA VCC-0.5 V

Worst Case RESET Sink/Source Capabilities at Various VCC Levels

Parameter Symbol

RESET# Output V

OL

Voltage

RESET# Output V

OL

Voltage

RESET Output V

OH

Voltage

2011 PGM T5 1.0

RESET#

Input

RESET#

Output

RESET

Output

2011 T fig12 2.0

t

PURST

S24042/S24043

13

2011 2.0 5/2/00

SUMMIT MICROELECTRONICS, Inc.

.228 (5.80)

.244 (6.20)

.016 (.40)

.035 (.90)

.020 (.50)
.010 (.25)

x45°

.0192 (.49)
.0138 (.35)

.061 (1.75)
.053 (1.35)

.0098 (.25)
.004 (.127)

.05 (1.27) TYP.

.275 (6.99) TYP.

.030 (.762) TYP.
8 Places

.050 (1.27) TYP.

.050 (1.270) TYP.
8 Places

.157 (4.00)
.150 (3.80)

.196 (5.00)

1

.189 (4.80)

FOOTPRINT

8pn JEDEC SOIC ILL.2

8 Pin SOIC (Type S) Package JEDEC (150 mil body width)

8 Pin PDIP (Type P) Package

.375

(9.525)

PIN 1 INDICATOR

.015 (.381) Min.

.130 (3.302)

.100 (2.54)

TYP.

.018 (.457)

TYP.

.060 ± .005

(1.524) ± .127

TYP.

.130 (3.302)

SEATING PLANE

.070 (1.778)

.0375 (0.952)

.300 (7.620)

5°-7°TYP.

(4 PLCS)

.350 (8.89)

.009 ± .002

(.229 ± .051)

0°-15°

.250

(6.350)

8pn PDIP/P ILL.3

14

S24042/S24043

2011 2.0 5/2/00 SUMMIT MICROELECTRONICS, Inc.

ORDERING INFORMATION

NOTICE

SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve
design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described
herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent
infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon
a user’s specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc.
shall not be liable for any damages arising as a result of any error or omission.

SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety
or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written
assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and
(c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances.

I2C is a trademark of Philips Corporation.
© Copyright 2000 SUMMIT Microelectronics, Inc.

S24022

P

A

T

Base Part Number

Tape & Reel Option

Operating V oltage Range

Package

P = 8 Lead PDIP
S = 8 Lead 150mil SOIC

Blank = Tube
T = Tape & Reel

A = 4.5V to 5.5V V

TRIP

min. @ 4.25V

B = 4.5V to 5.5V V

TRIP

min. @ 4.50V

2.7 = 2.7V to 5.5V V

TRIP

min. @ 2.55V

S24022 = Reset Active High & Low
S24023 = Reset Active Low

2011 Tree 2.0