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1 CHIP CLP SUBSYSTEM IC S1T8527C
INTRODUCTION
48−QFP−1010E
S1T8527C is a monolithic circuit which can be used in high
performance 60MHz MCA type CLP System. The S1T8527C is a
subsystem IC for FM / FSK receiving systems and a complete one chip
FM / FSK receiver IC for 60MHz system. It’s feature includes receiving
functions for FM / FSK systems, a compander to remove external
noise, and PLL ( Phase Lock Loop ) of channel selection which blocks
surrounding frequency interference.
The S1T8527C can be used with a wide range of FM / FSK VHF
bandwidth systems, including cordless phone, and the narrow band
voice and data sending / receiving systems.
To make applications easily and simply, peripheral parts are minimized.
FEATURES
• Operating voltage range: 2.0V — 5.5V
• Typical supply current: 13.5mA at 3.6V
• Built−in low battery detection function ( selectable 3.45V, 3.3V, 3.0V, 2.2V, 2.1V )
• Built−in speaker amplifier
• Built−in splatter filter
• Built−in dual conversion receiver, compander and universal PLL
• FM Receiver
— Complete dual conversion circuit
— Excellent input sensitivity (0.7µVrms at 12dB SINAD)
• Compader
— Easy gain control to use external component
— Included ALC (Automatic Level Control) circuit
— Included Mute logic
• Universal PLL
— RX (TX) divided counter range: 1/16 — 1/16383
— Reference frequency divided counter range: 1/16 — 1/4095
— Lock detector signal output
— Serial interface with MCU for controlling each block
ORDERING INFORMATION
Device Package Operating Temperature
S1T8527C01-Q0R0 48−QFP−1010E −20°C — + 70°C
1
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S1T8527C 1 CHIP CLP SUBSYSTEM IC
BLOCK DIAGRAM
2MI
1MO
1LOI
1LOI
VCO
RX
1MI
1MI
GND
(PLL)
PDR
V
REF
(PLL)
V
(PLL)
TIF
LD
(RX)
GND
30
Meter
Driver
Carrier
Detector
Low
Battery
Detector
29
QCI
RAO
28 27
Limiter
Gain Cell
Rectifier
DSCI
FSK
COMP
DSCO
26
Rectifier
Gain Cell
25
SUM
AMP
MDO
Regulator
(1V)
PRI
+
-
SUM
AMP
SPK
AMP
SPK
AMP
+
-
PRI
ALC
VREF
V
REF
24
(COMP)
23
ALC
22
EPI
21
ERC
EO
20
SAI
19
SAO1
18
SAO2
17
VCC
16
(COMP)
GND
15
(COMP)
CPI+
14
13
CPI -
(RX)
37
2LOI
36
X-tal
OSC
2nd
MIX
35
2LOI
2MO
34 33
IF AMP
(455KHz)
VCC
LI
32 31
Limiting
IF AMP
38
39
40
RX
VCO
Quad
Detector
AMP
41
42
1st
MIX
IF AMP
(10.7MHz)
Regulator
43
44
( 2.15 V )
Buffer
Programmable Counter
45
46
CC
47
48
( RX )
Programmable Counter
( TX )
Programmable Counter
( REF )
4_25 CNT
Splatter
SFI
Filter
SFO
fMCU
CDO/LDT
CONTROL
6
(PLL)
GND
CLK
DATA
EN
LBD
AGIC
Compandor
mute
121110 9 8 754 3 1 2
CRC
RX Phase
Detector
TX Phase
Detector
CO
PDT
2
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1 CHIP CLP SUBSYSTEM IC S1T8527C
CDO/LDT
GND
PIN CONFIGURATION
VCO
GND
V
REF(PLL)
V
CC(PLL)
2MI
1MO
1LOI
1LOI
RX
1MI
1MI
(PLL)
PDR
37
38
39
40
41
42
43
44
45
46
47
36
2LOI
35
2LOI
34 33
(RX)
VCC
2MO
LI
LD
32 31
S1T8527C
KB8527B
GND
30
(RX)
29
QCI
RAO
28
27
DSCI
26
DSCO
MDO
25
24
23
22
21
20
19
18
17
16
15
14
V
REF(COMP)
ALC
EPI
ERC
EO
SAI
SAO1
SAO2
VCC
(COMP)
GND
(COMP)
CPI+
TIF
48
1
PDT
2
CO
3
SFI
4
SFO
5 6
(PLL)
7
CLK
8
DATA
9
EN
10
11
LBD
12
AGIC
13
CRC
CPI -
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S1T8527C 1 CHIP CLP SUBSYSTEM IC
PIN DESCRIPTION
Pin No Symbol Description
1 PDT3 Phase detector output terminal of the transmitter at PLL.
If fTX > f
If fTX < f
if fTX = f
2 CO Compressor output terminal of compander; connected to the splatter filter amp input
terminal.
3 SFI Input terminal of Splatter filter amp.
4 SFO3 Output terminal of Splatter filter amp.
5 LDT/CDO LDT: Output terminal of transmitter lock detector in PLL block. The output is low if PLL
is in lock state and the output is high if PLL is in unlock state.
CDO: As an output terminal of the carrier detector buffer, connected to (RSSI )
terminal of MCU. This pin outputs the contents of Meter Driver buffer which is
turned on / off, according to the signal level detected by Meter Driver.
or fTX is leading → the output is negative pulse
REF
or fTX is lagging → the output is positive Pulse
REF
and the same phase → the output is High Impedance
REF
6 GND
PLL
Ground.
Ground of logic section at PLL.
7
8
9
CLK
DATA
EN
These pins are serial interface terminals for programming reference counter, auxiliary
reference counter, TX channel counter, RX channel counter and control block that
controls internal each block with test mode and power saving mode.
10 LBD Low Battery Detecting output. ( Selectable 3.45V, 3.3V, 3.0V, 2.2V, 2.0V ). During
the normal operation, output level is low, but it is high at low battery detection. As this
pin is an open collector type, it requires a pull - up resistor.
11 AGIC This pin bypasses AC elements at the feedback loop which come from the SUM amp
block of COMPRESSOR. A capacitor should be connected between this terminal and
GND. ( C = 2.2uF )
12 CRC Converts waveform from the full wave rectifier to DC element at the rectifier block of
Compressor. ( RC = 33msec )
13 CPI - Pre-amp inverting input terminal of Compressor.
Adjusts the negative feedback loop gain. ( in application, gain is 5 )
14 CPI + Pre-amp non-inverting input terminal of Compressor.
Used as an input terminal for voice signals.
15 GND
16 Vcc
(COMP)
(COMP)
Ground of Compander block.
Supply voltage.
Power supply terminal of Compander.
17 SAO 2 Output terminal of speaker amp 2.
This signal is the same as SAO1 output, but phase difference is180° for SAO1.
DC voltage level is ( Vcc — 0.7V ) / 2.
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1 CHIP CLP SUBSYSTEM IC S1T8527C
PIN DESCRIPTION (Continued)
Pin No Symbol Description
18 SAO 1 Output terminal of Speaker amp 1.
DC voltage level is ( Vcc — 0.7V ) / 2.
19 SAI Speaker Amp 1 input terminal.
Between this terminal and Expander output terminal, uses a AC coupled.
20 EO Output terminal of Expander, from which a regenerated voice signals are emitted.
21 ERC Converts waveform from the full wave rectifier to DC element at the rectifier block of
Expander. ( RC = 33 msec )
22 EPI − Pre-amp inverting input terminal of Expander.
Adjusts the negative feedback loop gain. ( in application, gain is 5 ).
23 ALC Reference current input terminal of Automatic Level Control ( ALC); Adjusts THD of
compressor output voltage to less than 3% or limits the frequency deviation of TX if the
input is higher than a certain level. The ALC circuit may be turned off depending on the
ALC reference current or the magnitude of output voltage may be limited if it is higher
than a certain level.
24 V
REF(COMP)
Reference voltage ( V
= 1V ). Supplies a regulator voltage to the Compressor and
REF
Expander of COMPANDER.
25 MDO Output terminal of the Meter Driver.
Amplitude of RF input signal for useful frequency is detected by Meter Driver circuit.
The Meter Driver circuit has perfect linear characteristic of 60dB range for input signal
level. ( 0.1µA / dB ).
26 DSCO Output terminal of Data Slicing comparator.
Separates Frequency Shift Keying ( FSK ) serial data and executes data shaping and
limiting.
27 DSCI Input terminal of Data slicing comparator.
Non-inverting type with the negative input terminal biased to 1/2 Vcc.
28 RAO Recovered Audio Output terminal. Voice signals detected by the Quadrature Detector
are amplified and then output through this terminal.
29 QCI3 Quadrature coil input terminal.
The 455kHz oscillator circuit is an Lp = 680uH, Cp = 180pF valued LC tank circuit.
Voice signals are detected by mixture of 455kHz ( by phase difference ) which is
converted from mixer 2.
30 GND
RX
Ground .
Ground for Receiver.
31
32
LD
LI
Limiter input and decoupling terminal.
Removes amplitude modulation elements caused by fading or FM signal noise. Limiting
IF amplifies and limits the second intermediate frequency, 455kHz.The input
impedance of the limiting IF amplifier is set to 1.5kΩ. While FM waves are transmitted
with constant magnitude, their magnitudes are slightly modulated due to reflection from
obstacles, fading phenomenon, noise wave, and mixing with AM wave elements before
entering the receiver’s antenna.The limiter makes amplitude uniform by removing these
AM wave elements.
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S1T8527C 1 CHIP CLP SUBSYSTEM IC
PIN DESCRIPTION (Continued)
Pin No Symbol Description
33 V
CC(RX)
Supply voltage.
Supplies power to the Receiver.
34 2MO3 Output terminal of Mixer 2. Second intermediate frequency ( 455kHz ), generated by
mixing first intermediate frequency ( 10.7MHz ) and Second Local Oscillator is output.
35
36
2LOI
2LOI
Input terminal of second local oscillator. Generates second local oscillator frequency to
convert output from mixer 1 ( 10.7MHz ) into second intermediate frequency. It is an
oscillator with crystal of 10.24MHz and 10.245MHz.
37 2MI Input terminal of mixer 2. Output from mixer 1 is entered to mixer 2 input terminal via
10.7MHz ceramic filter. Second mixer converts frequency to second intermediate
frequency ( 455kHz: AM IF ).
38 1MO3 Output terminal of mixer 1.
The signal from mixer 1 and the frequency of the first local oscillator are mixed to
produce the first intermediate frequency, which is the output through this terminal. The
output terminal is an emitter follower with an output impedance of 330Ω to match the
330Ω input/output impedance of the 10.7MHz ceramic filter.
39
40
1LOI
1LOI
Input terminal of the first local oscillator.
The local oscillator is a voltage controlled oscillator. local oscillation frequency and
received frequency are mixed at mixer 1 and then converted to the first intermediate
frequency of 10.7MHz or 10.695MHz.
41 VCO
RX
The terminal which variable capacitor is included in the chip. Used as an input terminal
where 1st local oscillation frequency is changed by varying the capacitor connected
between 1st local oscillator terminals.The internal variable capacitor has the value of
18.73 ~ 15.86pF depending on the applied voltage. ( 1.0 ~ 2.0 V ).
42
43
44 GND
1MI
1MI
(PLL)
Input terminal of Mixer 1. This mixer is made of double balanced multiplier.
The received signal amplified at RF AMP is input to this terminal.
Ground.
Ground for analog at PLL
45 PDR Phase detector output terminal of the receiver at PLL.
46 V
REF(PLL)
If fRX > f
If fRX < f
If fRX = f
PLL voltage reference output pin.
or fRX is Leading → The output is negative pulse
REF
or fRX is Lagging → The output is positive pulse
REF
and the same phase → The output is high impedance
REF
An internal voltage regulator provides a stable power supply voltage for the RX and TX
PLLs.
47 V
CC(PLL)
Power supply terminal of PLL.
48 TIF Input terminal of TX channel counter.
AC coupling with TX VCO.
Minimum input level is 300mVp-p ( at 60MHz ).
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1 CHIP CLP SUBSYSTEM IC S1T8527C
ABSOLUTE MAXIMUM RATINGS
Characteristic Symbol Value Unit
Maximum Supply Voltage V
Power Dissipation P
Operating Temperature T
Storage Temperature T
CC
D
OPR
STG
5.5 V
600 mW
−20 — + 70 °C
− 55 — + 150 °C
CURRENT CONSUMPTION AT EACH MODE ( VCC = 3.6V )
MODES Min. Typ. Max.
Inactive mode − 350uA 600uA
RX mode − 6.6mA −
Communication mode ( Active mode ) − 13.5mA
CURRENT CONSUMPTION IN EACH BLOCK ( VCC = 3.6V )
MODES Min. Typ. Max.
Receiver part − 5.0mA 7.5mA
Expander part − 1.4mA 2.1mA
Speaker part − 1.7mA 2.5mA
compressor part − 3.0mA 4.5mA
PLL RX part − 1.6mA 2.4mA
TX part − 0.8mA 1.2mA
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S1T8527C 1 CHIP CLP SUBSYSTEM IC
ELECTRICAL CHARACTERISTICS
Characteristic Symbol Test Conditions Min. Typ.
Max. Unit
Operating Voltage Vcc − 2.0 − 5.5 V
RECEIVER
( VCC = 3.6V, fC = 49.7MHz, f
Input for −3dB Sensitivity V
Input for 20dB Sensitivity V
S/N Ratio S/N Modulation Input
= ± 3kHz, f
DEV
LIM
I(SEN)
= 1kHz,Ta = 25°C, unless otherwise specified )
MOD
−3dB Point − 0.7 2.0 µVrms
Modulation Input − 0.7 2.0 µVrms
48 55 − dB
No Modulation Input
Recovered Audio Output V
Noise Output Level V
Recovered Audio Output
V
O(RAD)
Voltage Drop
Detect Output Voltage V
Carrier Detector Threshold V
Comparator Threshold
O(DET)
TH(DET)
∆V
Voltage Difference
Comparator Output Voltage 1 V
O(RA)
NO
TH
OH
RFin = 1mVrms 145 185 225 mVrms
RFin = No Input − 130 205 mVrms
Vcc = 5V → 2V
−8 −3.3 − dB
RFin = 1mVrms
RFin = 1mVrms 1.0 1.5 2.0 V
RFin = No Input 0.49 0.60 0.73 V
V
= 150mVp-p
COMP
70 110 150 mV
RL = 180kΩ
V
= 150mVp-p
COMP
2.7 3.0 − V
RL = 180kΩ
Comparator Output Voltage 2 V
OL
V
COMP
= 150mVp-p
− 0.25 0.5 V
RL = 180kΩ
First Mixer Conversion
Voltage Gain
Second Mixer Conversion
Voltage Gain
Detector Output Distortion THD
Detector Output Resistance R
Detector Output DC Voltage
∆G
∆G
∆V
V(1M)
V(2M)
DET
O(DET)
O(DET)
V
R
V
R
I(43)
L(38)
I(37)
L(34)
= 1mVrms
= 330Ω
= 1mVrms
= 1.5kΩ
14 18 22 dB
17 21 25 dB
RFin = 1mVrms − 1.5 2.5 %
RFin = 1mVrms − 1.2 − kΩ
RFin = 1mVrms − 0.15 0.23 V/kHz
Change Ratio
Meter Drive Slope MDS 70 100 135 nA/dB
First Mixer Input Resistance R
First Mixer Input Capacitance C
Limiter Input Sensitivity V
Second Mixer Input
S
I(1M)
I(1M)
I(LIM)
V(2M)
fc = 50MHz 500 690 − Ω
fc = 50MHz − 7.2 10 pF
fc = 455kHz, 20dB SINAD − 100 250 µVrms
fc = 10.7MHz, 20dB SINAD − 10 25 µVrms
Sensitivity
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1 CHIP CLP SUBSYSTEM IC S1T8527C
ELECTRICAL CHARACTERISTICS (Continued)
Characteristic Symbol Test Conditions Min. Typ.
First Mixer 3rd Order
3RD − − -22 − dBm
Sensitivity
Low Battery Detector LBD3 LBD0—LBD3 = 0 ( Default )
Only LBD2 = 0
Only LBD1 = 0
Only LBD3 = 0
LBD0 — LBD3 = 1
AM Rejection Ratio AMRR RFin = 1mVrms — 10mVrms
AM MOD = 30%
Compressor
( Vcc = 3.6V, fc = 1kHz, Ta = 25°C, unless otherwise specified )
Reference Voltage V
REF
No Signal 0.9 1.0 1.1 V
Standard Output Voltage Vo(com) Vinc = 13mVrms ( 0dB ),
Ralc = GND
Compressor Gain Difference ∆GV1
(COM)
Vinc=1.3mVrms (−20dB),
∆Gv1 (COM) = 20 × log
(Voc1/Voc) + 10K
∆GV2
(COM)
Vinc = 0.13mVrms (−40dB)
∆Gv2 (COM) = 20 × log
(Voc2/Voc) + 20K
Max. Unit
−0.15 3.45
0.1 V
3.3
3.0
−0.1 2.2
0.075
2.1
25 25 − dB
255 300 345 mVrms
−1.0 −0.5 − dB
−2.0 −1.0 − dB
Compressor Output Distortion THD
Mute Attenuation Ratio ATT
Compressor Limiting
V
LIM(COM)
COM
MUTE
Vinc = 0dB − 0.5 1.0 %
Vinc = 0dB 60 80 − dB
Vinc = Variable 1.41 1.65 1.83 Vp-p
Voltaget
ALC V
ALC
I
= 8uA ( R
ALC
= 120kΩ ) 280 330 380 mVrms
ALC
Splatter filter Vo(SF) VINC = 13mVrms = 0dB 255 300 345 mVrms
Expander
(Vcc = 3.6V, fc = 1kHz, Ta = 25°C, unless otherwise specified)
Standard Output Voltage V
O(EXP)
Vine=30mVrms ( 0dB ) 104 130 156 mVrms
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S1T8527C 1 CHIP CLP SUBSYSTEM IC
ELECTRICAL CHARACTERISTICS (Continued)
Characteristic Symbol Test Conditions Min. Typ.
Expander Gain Difference ∆G
V1(EXP)
Vine = 9.5mVrms (−10dB)
0 0.5 1.0 dB
Max. Unit
∆Gv1(EXP) = 20 × log (Voe1/
Voe) + 20
∆G
V2(EXP)
Vine = 3mVrms (−20dB)
0 1.0 2.0 dB
∆Gv2 (EXP) = 20 × log
(Voe2/Voe) + 40T
∆G
V3(EXP)
Vine = 0.95mVrms (−30dB)
0 1.5 3.0 dB
∆Gv3 (EXP) = 20 × log
(Voe3/Voe) + 60K
Expander Output Distortion THDEXP VinE = 0dB − 0.5 1.0 %
Mute Attenuation Ratio ATTMUTE VinE = 0dB 60 80 − dB
Expander Maximum Output
Voltage
V
OEXP(MAX)
VinE = Variable
THD = 10%l
500 600 − mVrms
Speaker amp output 1 Vo( SA1) VINE = 30mVrms = 0 dB 104 130 156 mVrms
Speaker amp output 2 Vo( SA1) VINE = 30mVrms = 0 dB 104 130 156 mVrms
PLL
( Vcc = 3.6V, Ta = 25°C, unless otherwise specified )
Operating Current I
CCPLL
Input Current I
Input Voltage V
Output Current I
Output Voltage V
IH
I
IL
IH
V
OH
I
OL
OH1
IL
Vcc = 3.6V − 2.0 3.5 mA
Vin = Vcc − − 5 µA
Vin = 0V −5 − − µA
− Vcc-0.3 − − V
− − − 0.3 V
Vout = Vcc 0.3 − − mA
Vout = 0V 0.3 − − mA
PDT, PDR: Io = −0.3mA
Vcc-0.4 − − V
( Sourcing )
PLL regulator voltage V
10
V
OL1
V
OH2
V
OL2
PLLREG
PDT, PDR: Io = 0.3mA
( Sinking )
LD, fMCU: Io = −0.1mA
( Sourcing )
LD, fMCU: Io = 0.1mA
( Sinking )
− − 0.4 V
Vcc-0.5 − − V
− − 0.5 V
1.95 2.15 2.25 V
Page 11
1 CHIP CLP SUBSYSTEM IC S1T8527C
PLL PROGRAM SUMMARY
MCU ( MICOM ) SERIAL INTERFACE ( MSB : 1ST INPUT )
Use CLK (Pin 7 ), DATA (Pin 8 ) , EN (Pin 9 ) terminals for program. DATA and CLK terminals are used for loading
data to internal Shift - Register. When EN terminal is ‘Low’ It is possible to program TX-Channel Counter, RX Channel Counter and various control functions of PLL. When EN terminal is ‘High’ Program 1st Local Oscillator
Capacitor Selection in receiver for U.S.A - 25 CH function.
— TX - Register, RX-Register, Control Register
MSB LSB
DATA
PMC0 PMC1 14 Bit DATA
EN
CLK
— Reference - Register
MSB LSB
PMC0 PMC1 UK_S1 UK_S0 12 Bit DATADATA
EN
CLK
— RECEIVER -1st local oscillator internal capacitor selection register & low battery detector voltage register
[ CLO_LBD-Register ]
DATA
EN
CLK
MSB
PMC LBD3 LBD2 LBD1 LBD0 CLO5 CLO4 CLO3 CLO2 CLO1 CLO0
LSB
<1>
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S1T8527C 1 CHIP CLP SUBSYSTEM IC
• Programmable Counter
— RX - counter: Setting frequency for RX.VCO ( 14 Bits --> 1/16 — 1/16383 )
[ Default_CH. = USA_#21 ( REMOTE ): 36.075MHz ( Div._NO = 7215 )]c
< RX. Register (16bits) >
Bit Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Name PMC0 PMC1 D13 D12 D11 D10 D9 D8
Default
* 0 1 1 1 0 0
value
7215
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name D7 D6 D5 D4 D3 D2 D1 D0
Default
0 0 1 0 1 1 1 1
value
7215
— TX - counter: Setting frequency for TX.VCO ( 14 Bits --> 1/16 — 1/16383 )
[ Default_CH. = USA_#21 ( REMOTE ): 49.830MHz ( Div._NO = 9966 )]'
< TX. Register (16 bits) >
Bit Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Name PMC0 PMC1 D13 D12 D11 D10 D9 D8
Default
* 0 1 1 1 0 0
value
9966
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name D7 D6 D5 D4 D3 D2 D1 D0
Default
1 1 1 0 1 1 1 0
value
9966
* Program mode control
PMC0 PMC1 Program mode PMC0 PMC1 Program mode
0 0 Control Block 0 1 UPLL_RX. Block
1 0 UPLL_Ref. Block 1 1 UPLL_TX. Block
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1 CHIP CLP SUBSYSTEM IC S1T8527C
— Ref - counter: Setting reference frequency for phase detector ( 12 Bits --> 1/16 ~ 1/4095 )
[ Default_Divider = 2048, X-tal_OSC = 10.240 MHz --> Fref = 5kHz ]
< Ref. Register (16bits) >
Bit Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Name PMC0 PMC1 UK_S1 UK_S0 D11 D10 D9 D8
Default
value
* Ref.freq. selection
for United KingdomD
1 0 0 0
2048
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name D7 D6 D5 D4 D3 D2 D1 D0
Default
0 0 0 0 0 0 0 0
value
2048
— UK_Selection
UK_S0 UK_S1 FR1 FR2 FrefTX FrefRX
0 0 fREF (A) − fREF (A) fREF (A)
1 0 fREF (A) fREF/4 (B) fREF/4 (B) fREF/4 (B)
0 1 fREF/4 (B) fREF/25 (C) fREF/4 (B) fREF/25 (C)
1 1 fREF/4 (B) fREF/25 (C) fREF/25 (C) fREF/4 (B)
12 Bits Reference
program divider.
Figure 1. < Reference frequency selection >
÷ 4
÷ 25
fREF
(A)
fREF ÷ 4
(B)
fREF ÷ 25
(C)
FR1
FR2
LD
PD_TX
PDT
PDR
PD_RX
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S1T8527C 1 CHIP CLP SUBSYSTEM IC
• Control program
— Control register (16 Bits)
Bit Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Name PMC0 PMC0 - PLLTX-BS CO_M CO_BS CO_BS EX_BS
Description Program
Mode
Control_0
Function *
Program Latch Assign
Program
Mode
Control_1
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name LDT_
CDO
Description LDT or
CDO
Select
Function LDT or
CDO
Select
LBD-BS Rx-Bs
Low
Battery
Detector
Battery
Save
0:Normal
(LBD-ON)
1:LBD-Part
Power-Off
*** TEST Mode & LDT-CDO Mode
Don’t
Care
Don’t
Care
RX Battery
Save
0:Normal
(RX-ON)
1:RX-Part
Power-Offf
PLL_Tx
Battery
Save
0:Normal
(PLL_TX-On)
1:PLL_TX
Power-Off
Compress
or Mute
Selection
0:Normal
1:Mute
− − −
Don’t
care
Don’t
care
−
Compress
or Battery
Save
0: CO-On
1: Normal
( CO-part
Power-Off )
Don’t
care
Expander
Mute
Selection
0:Normal
1:Mute
TEST2 TEST1
TEST
Mode 2
Function Test On
each block of UPLL
Expander
Battery
Save
0: EX-On
1: Normal
( EX-part
Power-Off )
TEST
Mode 1
* * *
LDT/CDO TEST1 TEST2 LDT / CDO Remark
0 0 0 Rx block CDO Default
1 0 Rx block CDO
0 1 4_25cnt block FR2
1 1 4_25cnt block FR2
1 0 0 PLL block LDT
1 0 PLL block LDT
0 1 PLL block LDT
1 1 Test PLL_TX
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1 CHIP CLP SUBSYSTEM IC S1T8527C
• Operating internal circuit blocks in each mode
Mode ( state ) Operating circuit blocks
Active state
( Communication mode )
PLL regulator/MICOM I/F ( Data, CLK, EN ) / 2nd local oscillator / Receiver /
1st local oscillator / RX PLL / Carrier detector / FSK comparator / Low battery
detector / TX PLL / Expander & speaker amp / Compressor / Splatter filter
amp
Receiving mode PLL regulator / MICOM I/F ( Data, CLK, EN )/ 2nd local oscillator / Receiver /
1st local oscillator / RX PLL / Carrier detector / FSK comparator / Low battery
detector.
Inactive state PLL regulator / MICOM I/F( Data, CLK, EN )
• CLO_LBD - Register Program
[ Rx - 1’st local oscillation internal cap. for U.S.A - 25CH & Alarm sensor detect voltage ]
— CLO register ( 6 bits ) : Receiver 1’st local oscillator internal capacitor selection
Bit Bit10 (MSB) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name PMC CLO5 CLO4 CLO3 CLO2 CLO1 CLO0
Default
Value 0
Function − 0:Normal
1
* * * * *
0 0 0 0 0 0
1:Internal
Cap. for
USA 25
Channel =
4.4pF
0:Normal
1:Internal
Cap. for
USA 25
Channel =
1.0pF
0:Normal
1:Internal
Cap. for
USA 25
Channel =
3.6pF
0:Normal
1:Internal
Cap. for
USA 25
Channel =
2.4pF
0:Normal
1:Internal
Cap. for
USA 25
Channel =
1.2pF
0:Normal
1:Internal
Cap. for
USA 25
Channel =
0.6pF
*****PMC ( Program Mode Control )
PMC = ‘HIGH’ & EN = ‘HIGH’ ---> CLO_LBD Register Program Modeap
— Rx - Low Battery Detect Voltage
Bit Bit 10(MSB) Bit 9 Bit 8 Bit 7 Bit 6 Low Battery
Name PMC LBD3 LBD2 LBD1 LBD0
Default
1* * * * * 0 0 0 0 − Default
Detector Voltagef
Value
Function 1 0 0 0 0 3.45V −
1 0 1 1 3.3V −
1 1 0 1 3.0V −
0 1 1 1 2.2V −
1 1 1 1 2.1V −
Remark
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S1T8527C 1 CHIP CLP SUBSYSTEM IC
***** PMC ( Program Mode Control )
PMC = ‘HIGH’ & EN = ‘HIGH’ ---> CLO - LBD Register Program Mode
• Example 1 >
Low battery detector voltage : 2.1V
U.S.A _CH-#1 ( REMOTE ) ---> 1st local osc. varicap value = 15.86pF, Internal cap = 7.0pF
( Ext_L = 0.45uH, EXT_C = 30pF )
— 12 bit data format
MSB LSB
DATA
Dummy
PMC LBD3 LBD2 LBD1 LBD0 CLO5 CLO4 CLO3 CLO2 CLO1 CLO0
bit
1 1 1 1 1 0 1 1 1 0 01( 0 )
EN
CLK
In case the 12 bits programming, insert 1 don’t care bit ( Dummy bit ) between PMC and LBD3.
— In case of setting 16 bit data format
DATA
MSB LSB
PMC LBD3 LBD2 LBD1 LBD0 CLO5 CLO4 CLO3 CLO2 CLO1 CLO0
1 1 1 1 1 0 1 1 1 0 0
1( 0 )
Dummy
bit
1( 0 ) 1( 0 ) 1( 0 ) 1( 0 )
EN
CLK
In case of 16 bits programming, insert 5 don’t care bits between the PMC and LBD3
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1 CHIP CLP SUBSYSTEM IC S1T8527C
EXAMPLE DATA FOR U.S.A 25_CHANNEL SELECTION
1’st Local Osc. Internal Capacitor Select Base
Channels
Bit5
(CLO5)
Bit4
(CLO4
Bit3
(CLO3)
Bit2
(CLO2)
Bit1
(CLO1)
Bit0
(CLO0)
1 —
25CH.
0 0 0 0 0 0 16 —
25CH.
0 0 0 0 0 1 16 —
0 1 0 0 0 1 01 —
04CH.
0 0 0 0 1 0 05 —
10CH.
0 0 0 0 0 1 11 —
15CH
0 1 1 1 0 0 01 —
0 1 1 0 1 0 07 —
• Phase detector / Lock Detector Output Waveforms
Hand
Channels
1 —
25CH.
25CH.
06CH.
15CH.
Varicap
Value
1.0V—2.0V
TYP 1.5Vo
18.73
—15.86pF
18.73
— 15.86pF
18.73
—15.86pF
18.73
— 15.86pF
18.73
— 15.86pF
18.73
— 15.86pF
18.73
— 15.86pF
ExternalCExternalLInternal
C
27pF
0.45uH pF
( 30pF )
27pF 0.45uH -
30pF 0.45uH 0.6
27pF 0.45uH 1.6
27pF 0.45uH 1.2
27pF 0.45uH 0.6
30pF 0.45uH 7.0
30pF 0.45uH 5.8
2LOI
TIF
12 Bits Reference
program divider.
14 Bits TX.
program divider.
÷ 4
÷ 25
fREF
(A)
fREF ÷ 4
(B)
fREF ÷ 25
(C)
FR1
FR2
REF.Freq
TIF ÷ N
LD
PD_TX
PDT
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S1T8527C 1 CHIP CLP SUBSYSTEM IC
REF.Freq.
TIF ÷ N
PDT
LD
Figure 2. ( Phase Detector / Lock Detector Output Waveform )
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1 CHIP CLP SUBSYSTEM IC S1T8527C
DATA FROM MICOM (MCU)
to MICOM (MCU)
APPLICATION CIRCUIT (BASE SET)
COMPRESSOR INPUT
MAIN POWER
RX OUT
RX DATA OUT
L5
C38
VR1
22uH
220uF
50K
Y1
R28
R29
C40
R33
T5
10.24MHz
C45
CVI
20P
10K
10K
20P
C37
10N
22K
FLT3
10N
C39
10N
R30
27K
R31
R34
455kHz
C42
27K
C30
R24
R22
1.0N
33K
R2
50K
R25
100N
3.3uF
C33
C32
51K
100N
C35
4.7uF
R26
C34
120K
2423222120191817161514
EO
EPI
VREF
ALC
(COMP)
CDO
R32
470K
DSCO
ERC
SAI
SAO1
SAO2
DSCI
C41
33N
51K
RAO
QCI
GND(RX)
10N
C43
LD
LI
(RX)
VCC
S1T8527C
68N
2MO
2LOI
C44
33P
2LDI
36 35 34 33 32 31 30 29 28 27 26 25
2MI
1MO
1LOI
1LOI
VCORX1MI
1MI
GND(PLL)
3738394041424344454647
T2
R36
(AW)
C49
10N
56K
100N
C50
T3
C51
(AY)
2P
(AY)
10N
R40
R39
C52
FET2
10.7MHz
C46
R35
C47
10N
22
30P
T4
C48
10
C29
10N
CC(COMP)
V
PDR
C57
47N
10K
3.9K
0.47uF
C28
CPI+
GND (COMP)
VREF(PLL)
VCC(PLL)
C58
10N
C53
10uF
C56
R41
R14
100N
R19
10
560
13
CPI-
(PLL)
TIF
48
10N
C26
1.0uF
68K
CRC
AGIC
LBD
EN
DATA
CLK
GND
CDO/LDT
SFO
SFI
CO
PDT
to MICOM (MCU)
C25
3.3uF
C24
2.2uF
C17
12N
R44
10K
10K
R11
10K
R10
1 2 3 4 5 6 7 8 9 10 11 12
TX VCO
ANT
FET1
25K544
L1
1.8uH
R37
100
TX
RX
ANT
DUPLEX
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S1T8527C 1 CHIP CLP SUBSYSTEM IC
DATA FROM MICOM (MCU)
to MICOM (MCU)
APPLICATION CIRCUIT (HAND SET)
COMPRESSOR INPUT
MAIN POWER
RX DATA OUT
C38
L5
VR1
22uH
220uF
50K
Y1
R28
R29
R31
C40
R33
T5
10.24MHz
C45
CVI
20P
C37
10K
10K
FLT3
20P
10N
C39
R30
27K
10N
22K
455kHz
10N
27K
R34
C42
10
R22
R2
50K
C34
100N
C35
4.7uF
3.3uF
R26
120K
C36
2423222120191817161514
68N
EPI
VREF
ALC
(COMP)
CDO
R32
470K
DSCO
DSCI
C41
33N
51K
RAO
QCI
GND(RX)
10N
C43
LD
LI
68N
VCC(RX)
2MO
2LOI
C44
33P
2LDI
36 35 34 33 32 31 30 29 28 27 26 25
2MI
1MO
1LOI
3738394041424344454647
47P
C47
T4
FET2
C46
10N
10.7MHz
22
R35
C48
SPK
1
C30
1.0N
R25
51K
C33
C32
ERC
C31
R24
33K
100N
EO
SAI
SAO1
S1T8527C
1LOI
VCORX
1MI
1MI
T2
(AY)
R36
120K
(AW)
100N
C49
2P
C50
T3
(AY)
C51
10N
10N
2
10P
SAO2
GND(PLL)
C52
R40
R39
1.0uF
C28
C29
10N
VCC(COMP)
GND (COMP)
PDR
VREF(PLL)
C57
47N
C58
1.0K
C53
4.3K
R41
CPI+
VCC(PLL)
10N
10uF
C56
100N
R19
10N
10
C26
20K
13
CPI-
TIF
48
1N
CRC
AGIC
LBD
EN
DATA
CLK
GND(PLL)
CDO/LDT
SFO
SFI
CO
PDT
1 2 3 4 5 6 7 8 9 10 11 12
C25
3.3uF
C17
to MICOM (MCU)
C24
2.2uF
12N
10K
R11
22K
R10
R44
10K
TX VCO
20
ANT
FET1
25K544
L1
C21
1.8uH
R37
100
6P
TX
RX
ANT
DUPLEX
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