CD-ROM 48X RF AMP Chip is RF pre signal processor and processes signals from optical pick-up. This chip
processes main signal through summing amp, AGC block, EQ block, and generates SERVO error signals for
SERVO control. It can playback CD-ROM and CD-RW disc.
MAIN FEATURES (FEATURES, CHARACTERISTICS)
•CD-ROM 48X
— 1, 4, 8: CLV mode
— Maximum Speed of 48X: CAV mode
•Support CD-R/RW disc
•RF Amp & Equalizer
•Focus Error Amp
•Tracking Error Amp (3-Beam)
•Mirror (RFCT, RFRP) Signal Detection
•Defect Signal Detection
•Built-in AGC Function
•ALPC (Automatic Laser Power Control) Block
•Built-in RF Envelop Detector
•SBAD Signal Generation
•Signal Generation for Center Position Servo
•Built-in Serial Interface Port
•Power Down Mode
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S1L9251XCD-ROM 48X RF AMP
BLOCK DIAGRAM
Internal Block Diagram
LDO
PD
SUM
VCC
VR
CLPF
4443424140393837363534
1
+
-
Peak
Bottom
Peak
AGCLPF
DVCC
Vbg
2
3
4
A
B
5
6
C
7
D
8
9
+
VCC
+
+
-
+
-
+
-
+
-
Peak
Bottom
+
-
+
offset
+
-
+
DVC
+
+
-
Peak
+
-
RFRPICP_ENVRFEQOAGCINCAGCPLLFLPFADJRFOCM8CM4
33
RFRP
32
CP2
31
CB2
30
RFCT
CDFCT
29
28
+
-
DVCC
+
CC2
CC1
27
26
DFCT
25
VDD
-
E
10
11
F
1213141516171819202122
GNDDVCCDVCSBADFETERFCLK
+
+
+
VSS
+
CSERVOCSERC
SERIAL
I/F
SEROUT
24
RFEN
23
RFDATA
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CD-ROM 48X RF AMPS1L9251X
External Application
RF Output
LD
PD
SUM
A
B
C
D
E
F
LASER PICK UP
2.5V Analog Voltage
Output
VCC
VR
4443424140393837363534
RFO
CM8
CM4
1
LDO
2
PD
3
SUM
4
A
5
B
6
C
7
D
8
VCC
9
VR
10
E
11
F
GND
DVCC
DVC
1213141516171819202122
LPFADJ
FE
PLLF
SBAD
CLPF
TE
VCCDSP
CAGC
VSS
AGCIN
CSERC
RFEQO
CSERVO
CP_ENV
SEROUT
RFRPI
RFRP
CP2
CB2
RFCT
CDFCT
CC2
CC1
DFCT
VDD
RFEN
RFDATA
RFCLK
33
32
31
30
29
28
27
26
25
24
23
RFRP Output
VR
VR
RFCT Output
DFCT Output
VDD
Enable Signal Input
Serial Data Input
GND
DVCC
1.65V
SBAD Output
FE Output
TE Output
Center Servo
Output
Clock Input
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S1L9251XCD-ROM 48X RF AMP
PIN DESCRIPTION
NoNameI/ODescriptionRelated Block
1LDOOOutput of ALPC block ALPC
2PDIInput for ALPC block ALPC
3SUMIInput for ABCD signalRFSUM
4AIInput for A signalRFSUM
5BIInput for B signalRFSUM
6CIInput for C signalRFSUM
7DIInput for D signalRFSUM
8VCCP
9VRO2.5V Reference voltage outputBias
10EIInput for E signalTE Amp
11FIInput for F signalTE Amp
12GNDPGround for Analog BlockAnalog
13DVCCPPower input for Digital BlockDSP
14DVCO1.65V Reference Voltage outputBias
15FEOFocus Error signal output FE Amp
16SBADOSub Beam ADD output SBAD
17TEOTracking Error signal output TE Amp
18VSSPDigital GNDDigital
19CSERCITime constant setting for center position servoSERVO
20CSERVOOTime constant setting for center position servoSERVO
21SEROUTOError signal output for center position servoSERVO
22RFCLKIClock input for serial interfaceS I/F
23RFDATAIData input for serial interfaceS I/F
24RFENIData Enable input for serial interfaceS I/F
Power input for Analog Block
Analog
25VDDPDigital VDDDigital
26DFCTODefect Detection Comparator output DFCT
27CC1OBottom Hold output of Defect detection AmpDFCT
28CC2IDFCT Bottom HoldDFCT
29CDFCTICapacitor for DFCT Bottom HoldDFCT
30RFCTORFCT output , ENV output Mirror
31CB2OCapacitor for RFRP, RFCT Mirror
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CD-ROM 48X RF AMPS1L9251X
PIN DESCRIPTION (Continued)
NoNameI/ODescriptionRelated Block
32CP2OCapacitor for RFRP, RFCT Mirror
33RFRPORFRP output Mirror
34RFRPIIInput for MIRR MIRR
35CP_ENVICapacitor for Envelope HoldENV
36RFEQOOSumming and EQ signa of A,B,C,DlRFSUM
37AGCINIInput for AGCAGC
38CAGCIHold Capacitor for AGCAGC
39CLPFILPF output buffer REF connecting pinAGC
40PLLFIRF Frequency control for wide band PLL EQ
41LPFADJOLPF Frequency select for wide band PLL EQ
42RFOORF Signal Output RFSUM
43CM8OEQ Boost frequency for 8X speed EQ
44CM4OEQ Boost frequency for 4X speedEQ
SERIAL INTERFACE
Serial Interface Timing Graph
— The Serial Interface controls the Disc type, Speed, AGC, and Laser Diode On/Off.
— The Timing Diagram of the Serial Interface is shown below:
RFEN
RFDATA
RFCLK
— RFCLK : Clock synchronized with data from MICOM
— RFDATA : Address and Data from MICOM
— RFEN : Indicates Data is Enabled
Address, 8-bitData, 8-Bit
A7A0D7D0
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S1L9251XCD-ROM 48X RF AMP
Control signals generated from each Address are as below:
* When 1Vpp, 7% modulation, 10kHz carrier input, output Vpp change amount.
SBAD_ATT (D2-D0): SBAD Output Gain Select
D2D1D0MODE
000− 6 dB
001− 2.5 dB
0100 dB
0111.5 dB
1002.5 dB
1013.5 dB
1105 dB
1116 dB
•Address : 0AH
DATAD7D6D5D4D3D2D1D0
FunctionRSVLD_ON
Initial Value00000001
LD_ON (D0): LD On/Off Select
0 : LD OFF
1 : LD ON
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CD-ROM 48X RF AMPS1L9251X
•Address : 0BH
DATAD7D6D5D4D3D2D1D0
FunctionRSVRFRP_SEL
Initial Value00000000
RFRP_SET (D0): RFRP Block Output Select
D0OUTPUT
0RFRP, RFCT
1ENVELOPE
•Address : 0FH
DATAD7D6D5D4D3D2D1D0
FunctionRSVMODE_SELRSVPDmode
Initial Value00010001
MLDE_SEL (D4): CD-ROM, CD-RW Select
0 : CD-RW
1 : CD-ROM
PDmode (D0): Power Down Mode On/Off Select
0 : Power Down Mode
1 : Normal Mode
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S1L9251XCD-ROM 48X RF AMP
BLOCK DESCRIPTION
Tracking Error Amp
F
.TBAL
VR
E
-
+
+
-
-
+
.MODE_SEL
.TE_ATT
VR
-
+
VR
+
-
.TE_LPF
VOFST
— The Gain of the E, F signals are controlled by the Tracking Balance signal(TBAL).
— The output of TE AMP is expressed by -K(E-F).
— CD-ROM or CD-RW operation is selected by CDRW signal.
— Output stage is compatible to 3.3 V Servo operation.
Focus Error Amp
A
C
B
D
+
-
.Mode
.FE_ATT
-
+
VR
VR
+
-
.FE_LPF
VOFST
TE
FE
— The Gain of the input signals A, C and B, D can be adjusted by the Focus Balance signal.
— FE signal is expressed by − K {(PAC) − (PBD)}.
— CD-ROM or CD-RW operation is selected by CDRW signal.
— Output stage is compatible to 3.3 V Servo operation.
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CD-ROM 48X RF AMPS1L9251X
AGC & EQ
.RFEQ_SEL
CM4
CM8
.EQG_CEN
.CAV_SEL
SUM
a
b
c
d
Pick-UP
.PUP_SEL
AGCIN
+
.AGCON/OFF
.AGC-LVL
.AGCIN_Z
AGC
CAGC
.Mode_SEL
.GAIN_PLLF
.RFEQ_SEL
+
.ABCD-ATT
LPF
PLLF
LPFADJ
CLPFiCLPF
+
-
RFO
RFEQO
— Input level of RF AMP signal is convert to ouput level selected by AGC block.
— It is discreminated that CD-ROM or CD-RW.
— AGC Amp is designed to work with the Wide Range PLL.
— Boost Control of the Summing Amp is possible using the EQ Control Switc
RFRP & RFCT Block & Envelope Detector
RFRPI
PEAK
-HOLD2
BOTTOM
dvc
AGCIN
-HOLD2
+
-
A2
Peak
cp_env
Voffset
PEAK
vr
vofst
+
-
-HOLD1
BOTTOM
-HOLD1
+
-
dvc
1
1
vcc
+
-
RFCT
A1
vcc
+
-
RFRP
A3
+
-
— This circuit generates RF’s amplitude signals by detecting the upper envelope, using Servo Control signals
for Focus Error signal balance adjustment.
— Capacitance connected to CE that decides the time-constant value.
— RFRP is a block for detecting signals crossing the Track.
— Using the AC-coupled ABCD signals, carries out Peak and Bottom hold operation.
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S1L9251XCD-ROM 48X RF AMP
Defect Detector Block
CC1
A
B
C
D
VR
.Mode_sel
VR
+
-
+
-
.RFRP_FREQ
Peak-
Hold
VR
+
-
.DFT_TH
+
-
DVCC
+
— Block for detecting defects such as disc scratch or finger prints.
— External capacitor decides the time constant value.
— It detects ABCD signals through high speed peak hold and low speed bottom hold.
— After add DC to high speed peak hold, .then compares it to low-speed peak hold output.
CC2
DFCT
CDFCT
ALPC
CD-ON
AVSS
AVDD
.LD_OFF
+
-
LDO
P-sub
LD
vdc125
+
-
+
-
— Circuit for controlling the light power of the Laser Diode.
— Laser Power fluctuation caused by voltage and temperature changes are detected by Monitor Photo
Diode’s output current, then it is able to control the stable output power of Laser Diode.
— ALPC on/off is controlled by LDON switch.
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CD-ROM 48X RF AMPS1L9251X
SBAD
E
F
.TBAL
-
+
-
+
VR
VR
-
+
.Mode
.SBAD_ATT
VR
-
+
VR
+
-
VOFST
— E, F signal are excuted tracking balance adjust and added, and passed LPF.
— It is expressed by K (E + F)
Reference Block
DVCC
+
−
1.65V
2.5V
SBAD
AVCC
+
−
DVC
VR
— This block generates Reference voltage.
— The Output voltages are 1.65V (from RF part supply input) and 2.5V (from SERVO part supply input) .
Vdc Offset Block
DVC
VR
-
+
VR
VOFST
— It shifts the output stage to match the Servo and DSP block.
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S1L9251XCD-ROM 48X RF AMP
Center Servo Block
vofst
a
d
b
c
Pick-UP
DAC
+
Offset
Control
From
Micom
— This block controls level shift in seek mode.
— Output signal is expressed by - K ((B + C) - (A + D))