Datasheet RX5000 Datasheet (RFM)

®

· Designed for Short-Range Wireless Control and Data Communications

· Supports RF Data Transmission Rates Up to 115.2 kbps

· 3 V, Low Current Operation plus Sleep Mode

· Stable, Easy to Use, Low External Parts Count

The RX5000 hybrid receiver is ideal for short-range wireless control and data applications where
robust operation, small size, low power consumption and low cost are required. The RX5000
employs RFM’s amplifier-sequenced hybrid (ASH) architecture to achieve this unique blend of
characteristics. All critical RF functions are contained in the hybrid, simplifying and speeding de
sign-in. The RX5000 is sensitive and stable. A wide dynamic range log detector, in combination
with digital AGC and a compound data slicer, provide robust performance in the presence of
on-channel interference or noise. Two stages of SAW filtering provide excellent receiver out­of-band rejection. The RX5000 generates virtually no RF emissions, facilitating compliance with
ETSI I-ETS 300 220 and similar regulations.

Absolute Maximum Ratings

Rating Value Units

Power Supply and All Input/Output Pins -0.3 to +4.0 V

Non-Operating Case Temperature -50 to +100

Soldering Temperature (10 seconds) 250

-

o

C

o

C

RX5000

433.92 MHz
Hybrid

Receiver

Electrical Characteristics (typical values given for 3.0 Vdc power supply, 25oC)

Characteristic Sym Notes Minimum Typical Maximum Units

Operating Frequency f

Modulation Type OOK/ASK

Data Rate 115.2 kbps

Receiver Performance, High Sensitivity Mode

Sensitivity, 2.4 kbps, 10-3 BER, AM Test Method 1 -109 dBm

Sensitivity, 2.4 kbps, 10-3 BER, Pulse Test Method 1 -103 dBm

Current, 2.4 kbps (R

Sensitivity, 19.2 kbps, 10-3 BER, AM Test Method 1 -105 dBm

Sensitivity, 19.2 kbps, 10-3 BER, Pulse Test Method 1 -99 dBm

Current, 19.2 kbps (R

Sensitivity, 115.2 kbps, 10-3 BER, AM Test Method 1 -101 dBm

Sensitivity, 115.2 kbps, 10-3 BER, Pulse Test Method 1 -95 dBm

Current, 115.2 kbps 3.8 mA

Receiver Performance, Low Current Mode

Sensitivity, 2.4 kbps, 10-3 BER, AM Test Method 1 -104 dBm

Sensitivity, 2.4 kbps, 10-3 BER, Pulse Test Method 1 -98 dBm

Current, 2.4 kbps (R

= 330 K) 2 3.0 mA

PR

= 330 K) 2 3.1 mA

PR

= 1100 K) 2 1.8 mA

PR

O

433.72 434.12 MHz

1

Electrical Characteristics (typical values given for 3.0 Vdc power supply, 25oC)

Characteristic Sym Notes Minimum Typical Maximum Units

Receiver Out-of-Band Rejection, ±5% f

O

Receiver Ultimate Rejection R

Sleep Mode Current I

Power Supply Voltage Range V

R

±5%

ULT

S

CC

Power Supply Voltage Ripple 10 mV

Ambient Operating Temperature T

A

380dB

3 100 dB

0.7 µA

2.2 3.7 Vdc

P-P

-40 85

o

C

Notes:

1. Typical sensitivity data is based on a 10
measure OOK/ASK receiver sensitivity, the “100% AM” test method and the “Pulse” test method. Sensitivity data is given for both test meth

-3

bit error rate (BER), using DC-balanced data. There are two test methods commonly used to

-

ods. See Appendix 3.8 in the ASH Transceiver Designer’s Guide for the details of each test method, and for sensitivity curves for a 2.2 to

3.7 V supply voltage range at five operating temperatures. The application/test circuit and component values are shown on the next page and
in the Designer’s Guide.

2. At low data rates it is possible to adjust the ASH pulse generator to trade-off some receiver sensitivity for lower operating current. Sensitiv
ity data and receiver current are given at 2.4 kbps for both high sensitivity operation (R

= 330 K) and low current operation (RPR= 1100 K).

PR

3. Data is given with the ASH radio matched to a 50 ohm load. Matching component values are given on the next page.

4. See Table 1 on Page 8 for additional information on ASH radio event timing.

-

0.43"
(10.9)

SM -20L Package D raw ing

0.38"
(9.65)

0.08"

(2.03)

0.13"
(3.30)

0.125"
(3 .20 )

0.02"
(0 .51 )

0.04"
(1 .02 )

0.075"
(1 .90 )

A S H Transceiver Pin O ut

19

18

17

16

15

14

13

12

RFIO

GND3

CNTRL0

CNTRL1

VCC2

PW IDTH

PRATE

THLD2

RREF

GND1

201

2

VCC1

AGCCAP

RXDATA

3

4

PKDET

5

BBOUT

6

CMPIN

7

8

TXM O D THLD1

LPFA D J

9

10

11

GND2

2

ASH Receiver Application C ircuit

O O K C onfiguration

+ 3

VDC

C

DCB

+

R/S

GND3CNT

CNT

L

AT

RFIO

20

L

ESD

GND1

1

VCC

1

23456789

+ 3

VDC

Receiver Set-Up, 3.0 Vdc, -40 to +85

Item Symbol OOK OOK ASK Units Notes

Nominal NRZ Data Rate

Minimum Signal Pulse SP

Maximum Signal Pulse SP

AGCCAP Capacitor C

PKDET Capacitor C

BBOUT Capacitor C

BBOUT Resistor R

LPFAUX Capacitor C

LPFADJ Resistor

RREF Resistor

THLD2 Resistor

THLD1 Resistor

PRATE Resistor

PWIDTH Resistor

DC Bypass Capacitor C

RF Bypass Capacitor 1 C

Antenna Tuning Inductor L

Shunt Tuning/ESD Inductor L

VCC

RL0

RL1PWIDTHPRATE

TOP VIEW

PK

RF

DET

A1

R

BBO

C

RFB1

C

LPF

2

CMP

INBBOUT

C

BBO

DR

RPWR

AGC

PKD

BBO

BBO

R

R

REF

R

R

R

R

DCB

RFB1

ESD

DATA

0

NOM

MIN

MAX

LPF

LPF

TH2

TH1

PR

PW

AT

R

TH1

PR

1213141516171819

THLD1NC

RREF

11

R

GND2

RX

LPF

NC

ADJ

R

REF

10

LPF

D a ta O u tp u t

C

2.4 19.2 115.2 kbps see pages1&2

416.67 52.08 8.68 µs single bit

1666.68 208.32 34.72 µs 4 bits of same value

- - 2200 pF ±10% ceramic

- - 0.001 µF ±10% ceramic

0.1 0.015 0.0027 µF ±10% ceramic

12 0 0 K ±5%

0.0047 - - µF ±5%

300 100 15

100 100 100

- - 100

0010

330 330 160

270 to GND 270 to GND 1000 to Vcc

4.7 4.7 4.7 µF tantalum

100 100 100 pF ±5% NPO

56 56 56 nH 50 ohm antenna

220 220 220 nH 50 ohm antenna

ASH Receiver Application C ircuit

ASK Configuration

+ 3

VDC

C

DCB

+

VCC

TOP VIEW

PKD

RPWR

2

RX

CMP

DATA

INBBOUT

C

BBO

±1%, for 6 dB below peak

R/S

GND3CNT

L

AT

20

L

ESD

1

C

RFB1

CNT

RL0

RL1PWIDTHPRATE

RFIO

GND1
VCC

VDC

PK

AGC

DET

CAP

1

23456789

+ 3

C

C

AGC

K

K

K

K

K

K

R

TH1

PR

R

1213141516171819

THLD1THLD

RREF

GND2

LPF

NC

ADJ

TH2

2

11

R

10

R

LPF

D a ta O u tp u t

±5%

±1%

±1%, typical values

±5%

±5%

REF

CAUTION: Electrostatic Sensitive Device. Observe precautions when handling.

3

ASH Receiver Theory of Operation

Introduction

RFM’s RX5000 series amplifier-sequenced hybrid (ASH) receivers
are specifically designed for short-range wireless control and data
communication applications. The receivers provide robust operation,
very small size, low power consumption and low implementation
cost. All critical RF functions are contained in the hybrid, simplifying
and speeding design-in. The ASH receiver can be readily configured
to support a wide range of data rates and protocol requirements.
The receiver features virtually no RF emissions, making it easy to
certify to short-range (unlicensed) radio regulations.

Amplifier-Sequenced Receiver Operation

The ASH receiver’s unique feature set is made possible by its sys
tem architecture. The heart of the receiver is the amplifier­sequenced receiver section, which provides more than 100 dB of
stable RF and detector gain without any special shielding or de
coupling provisions. Stability is achieved by distributing the total RF
gain over time. This is in contrast to a superheterodyne receiver,
which achieves stability by distributing total RF gain over multiple
frequencies.

Figure 1 shows the basic block diagram and timing cycle for an am
plifier-sequenced receiver. Note that the bias to RF amplifiers RFA1
and RFA2 are independently controlled by a pulse generator, and

-

-

that the two amplifiers are coupled by a surface acoustic wave
(SAW) delay line, which has a typical delay of 0.5 µs.

An incoming RF signal is first filtered by a narrow-band SAW filter,
and is then applied to RFA1. The pulse generator turns RFA1 ON
for 0.5 µs. The amplified signal from RFA1 emerges from the SAW
delay line at the input to RFA2. RFA1 is now switched OFF and
RFA2 is switched ON for 0.55 µs, amplifying the RF signal further.
The ON time for RFA2 is usually set at 1.1 times the ON time for
RFA1, as the filtering effect of the SAW delay line stretches the sig
nal pulse from RFA1 somewhat. As shown in the timing diagram,
RFA1 and RFA2 are never on at the same time, assuring excellent
receiver stability. Note that the narrow-band SAW filter eliminates
sampling sideband responses outside of the receiver passband, and
the SAW filter and delay line act together to provide very high re
ceiver ultimate rejection.

Amplifier-sequenced receiver operation has several interesting char
acteristics that can be exploited in system design. The RF amplifiers
in an amplifier-sequenced receiver can be turned on and off almost
instantly, allowing for very quick power-down (sleep) and wake-up
times. Also, both RF amplifiers can be off between ON sequences
to trade-off receiver noise figure for lower average current consump
tion. The effect on noise figure can be modeled as if RFA1 is on
continuously, with an attenuator placed in front of it with a loss

-

equivalent to 10*log

(RFA1 duty factor), where the duty factor is the

10

average amount of time RFA1 is ON (up to 50%). Since an
amplifier-sequenced receiver is inherently a sampling receiver, the
overall cycle time between the start of one RFA1 ON sequence and

-

-

-

-

Antenna

R F Input

P1

RFA1 Out

D elay Line
Out

A S H R e c e iv e r B lo c k D ia g r a m & T im in g C y c le

S A W F ilte r R F A 1 R F A 2

P1 P2

t

PW 1

t

PW 2

t

PRI

t

PRC

D elay Line

G enerator

RF Data Pulse

SAW

Pulse

D e te c to r &

Low -P ass

F ilte r

Data
Out

P2

Figure 1

4

Antenna

RFIO

ESD
C hoke

20

SAW

CR Filter

R X5000 S eries A S H R eceiver B lock D iagram

CNTRL1 CNTRL0

18

17

Bias C ontrol

PRATE

SAW

D elay Line

AGC Set

G ain S elect

Pulse G enerator

& R F A m p B ia s

15

14

R

PR

PW IDTH

R

PW

RFA1 RFA2

Power
Down
C ontrol

Log

AGC CAP

V C C 1 : P in 2
V C C 2 : P in 1 6
G N D 1 : P in 1
G N D 2 : P in 1 0
G N D 3 : P in 1 9
N C : P in 8
R R EF : Pin 11
CMPIN: Pin 6

Detector

AGC

C ontrol

3

LPF AD J

C

AGC

Figure 2

Low -P ass

F ilte r

9

R

AGC Reset

BBOU T

DS2

Ref

BB

56

LPF

Peak

Detector

C

BBO

PKDET

4

AGC

C

PKD

dB Below
Peak T hld

DS1

Ref Thld

Threshold

C ontrol

11 12

13

R

TH1

R

AND

THLD 2THLD 1

R

TH2

REF

RXDATA

7

the start of the next RFA1 ON sequence should be set to sample
the narrowest RF data pulse at least 10 times. Otherwise, significant
edge jitter will be added to the detected data pulse.

RX5000 Series ASH Receiver Block Diagram

Figure 2 is the general block diagram of the RX5000 series ASH
receiver. Please refer to Figure 2 for the following discussions.

Antenna Port

The only external RF components needed for the receiver are the
antenna and its matching components. Antennas presenting an im
pedance in the range of 35 to 72 ohms resistive can be satisfactorily
matched to the RFIO pin with a series matching coil and a shunt
matching/ESD protection coil. Other antenna impedances can be
matched using two or three components. For some impedances,
two inductors and a capacitor will be required. A DC path from RFIO
to ground is required for ESD protection.

Receiver Chain

The output of the SAW filter drives amplifier RFA1. This amplifier in
cludes provisions for detecting the onset of saturation (AGC Set),
and for switching between 35 dB of gain and 5 dB of gain (Gain Se
lect). AGC Set is an input to the AGC Control function, and Gain Se
lect is the AGC Control function output. ON/OFF control to RFA1
(and RFA2) is generated by the Pulse Generator & RF Amp Bias
function. The output of RFA1 drives the SAW delay line, which has
a nominal delay of 0.5 µs.

The second amplifier, RFA2, provides 51 dB of gain below satura

­tion. The output of RFA2 drives a full-wave detector with 19 dB of
threshold gain. The onset of saturation in each section of RFA2 is
detected and summed to provide a logarithmic response. This is
added to the output of the full-wave detector to produce an overall
detector response that is square law for low signal levels, and tran
sitions into a log response for high signal levels. This combination
provides excellent threshold sensitivity and more than 70 dB of
detector dynamic range. In combination with the 30 dB of AGC

range in RFA1, more than 100 dB of receiver dynamic range is
achieved.

The detector output drives a gyrator filter. The filter provides a
three-pole, 0.05 degree equiripple low-pass response with excellent
group delay flatness and minimal pulse ringing. The 3 dB bandwidth
of the filter can be set from 4.5 kHz to 1.8 MHz with an external re­sistor.

The filter is followed by a base-band amplifier which boosts the de­tected signal to the BBOUT pin. When the receiver RF amplifiers

-

are operating at a 50%-50% duty cycle, the BBOUT signal changes
about 10 mV/dB, with a peak-to-peak signal level of up to 685 mV.
For lower duty cycles, the mV/dB slope and peak-to-peak signal
level are proportionately less. The detected signal is riding on a

1.1 Vdc level that varies somewhat with supply voltage, tempera
ture, etc. BBOUT is coupled to the CMPIN pin or to an external data
recovery process (DSP, etc.) by a series capacitor. The correct
value of the series capacitor depends on data rate, data run length,
and other factors as discussed in the ASH Transceiver Designer’s

-

Guide.

When an external data recovery process is used with AGC, BBOUT

­must be coupled to the external data recovery process and CMPIN

­by separate series coupling capacitors. The AGC reset function is

driven by the signal applied to CMPIN.

When the receiver is placed in the power-down (sleep) mode, the
output impedance of BBOUT becomes very high. This feature helps
preserve the charge on the coupling capacitor to minimize data
slicer stabilization time when the receiver switches out of the sleep
mode.

Data Slicers

The CMPIN pin drives two data slicers, which convert the analog

­signal from BBOUT back into a digital stream. The best data slicer

choice depends on the system operating parameters. Data slicer
DS1 is a capacitively-coupled comparator with provisions for an ad
justable threshold. DS1 provides the best performance at low

-

-

5

signal-to-noise conditions. The threshold, or squelch, offsets the
comparator’s slicing level from 0 to 90 mV, and is set with a resistor
between the RREF and THLD1 pins. This threshold allows a trade­off between receiver sensitivity and output noise density in the
no-signal condition. For best sensitivity, the threshold is set to 0. In
this case, noise is output continuously when no signal is present.
This, in turn, requires the circuit being driven by the RXDATA pin to
be able to process noise (and signals) continuously.

This can be a problem if RXDATA is driving a circuit that must
“sleep” when data is not present to conserve power, or when it its
necessary to minimize false interrupts to a multitasking processor.
In this case, noise can be greatly reduced by increasing the thresh
old level, but at the expense of sensitivity. The best 3 dB bandwidth
for the low-pass filter is also affected by the threshold level setting of
DS1. The bandwidth must be increased as the threshold is in
creased to minimize data pulse-width variations with signal ampli

-

-

tude.

Data slicer DS2 can overcome this compromise once the signal
level is high enough to enable its operation. DS2 is a “dB-below­peak” slicer. The peak detector charges rapidly to the peak value of
each data pulse, and decays slowly in between data pulses (1:1000
ratio). The slicer trip point can be set from 0 to 120 mV below this
peak value with a resistor between RREF and THLD2. A threshold
of 60 mV is the most common setting, which equates to “6 dB below
peak” when RFA1 and RFA2 are running a 50%-50% duty cycle.
Slicing at the “6 dB-below-peak” point reduces the signal amplitude
to data pulse-width variation, allowing a lower 3 dB filter bandwidth
to be used for improved sensitivity.

DS2 is best for ASK modulation where the transmitted waveform
has been shaped to minimize signal bandwidth. However, DS2 is
subject to being temporarily “blinded” by strong noise pulses, which
can cause burst data errors. Note that DS1 is active when DS2 is
used, as RXDATA is the logical AND of the DS1 and DS2 outputs.
DS2 can be disabled by leaving THLD2 disconnected. A non-zero
DS1 threshold is required for proper AGC operation.

AGC Control

The output of the Peak Detector also provides an AGC Reset signal
to the AGC Control function through the AGC comparator. The pur
pose of the AGC function is to extend the dynamic range of the re

­ceiver, so that the receiver can operate close to its transmitter when
running ASK and/or high data rate modulation. The onset of satura
tion in the output stage of RFA1 is detected and generates the AGC
Set signal to the AGC Control function. The AGC Control function
then selects the 5 dB gain mode for RFA1. The AGC Comparator
will send a reset signal when the Peak Detector output (multiplied by

0.8) falls below the threshold voltage for DS1.

A capacitor at the AGCCAP pin avoids AGC “chattering” during the
time it takes for the signal to propagate through the low-pass filter
and charge the peak detector. The AGC capacitor also allows the
hold-in time to be set longer than the peak detector decay time to
avoid AGC chattering during runs of “0” bits in the received data
stream. Note that AGC operation requires the peak detector to be
functioning, even if DS2 is not being used. AGC operation can be
defeated by connecting the AGCCAP pin to Vcc. The AGC can be
latched on once engaged by connecting a 150 kilohm resistor be

-

tween the AGCCAP pin and ground in lieu of a capacitor.

Receiver Pulse Generator and RF Amplifier Bias

The receiver amplifier-sequence operation is controlled by the Pulse
Generator & RF Amplifier Bias module, which in turn is controlled by

the PRATE and PWIDTH input pins, and the Power Down (sleep)
Control Signal from the Bias Control function.

In the low data rate mode, the interval between the falling edge of
one RFA1 ON pulse to the rising edge of the next RFA1 ON pulse

is set by a resistor between the PRATE pin and ground. The in

t

PRI

terval can be adjusted between 0.1 and 5 µs. In the high data rate
mode (selected at the PWIDTH pin) the receiver RF amplifiers oper
ate at a nominal 50%-50% duty cycle. In this case, the start-to-start
period t

for ON pulses to RFA1 are controlled by the PRATE re

PRC

sistor over a range of 0.1 to 1.1 µs.

In the low data rate mode, the PWIDTH pin sets the width of the ON

­pulse t

t

PW2

data rate mode). The ON pulse width t

to RFA1 with a resistor to ground (the ON pulse width

PW1

to RFA2 is set at 1.1 times the pulse width to RFA1 in the low

can be adjusted between

PW1

0.55 and 1 µs. However, when the PWIDTH pin is connected to Vcc
througha1Mresistor, the RF amplifiers operate at a nominal
50%-50% duty cycle, facilitating high data rate operation. In this
case, the RF amplifiers are controlled by the PRATE resistor as de
scribed above.

Both receiver RF amplifiers are turned off by the Power Down Con
trol Signal, which is invoked in the sleep mode.

Receiver Mode Control

The receiver operating modes – receive and power-down (sleep),
are controlled by the Bias Control function, and are selected with the
CNTRL1 and CNTRL0 control pins. Setting CNTRL1 and CNTRL0
both high place the unit in the receive mode. Setting CNTRL1 and
CNTRL0 both low place the unit in the power-down (sleep) mode.
CNTRL1 and CNTRL0 are CMOS compatible inputs. These inputs
must be held at a logic level; they cannot be left unconnected.

Receiver Event Timing

Receiver event timing is summarized in Table 1. Please refer to this
table for the following discussions.

Turn-On Timing

The maximum time t

required for the receive function to become

PR

operational at turn on is influenced by two factors. All receiver cir
cuitry will be operational 5 ms after the supply voltage reaches

-

2.2 Vdc. The BBOUT-CMPIN coupling-capacitor is then DC stabi
lized in 3 time constants (3*t
ceiver operation for a 10 ms power supply rise time is:

-

=15ms+3*t

t

PR

BBC

). The total turn-on time to stable re

BBC

Sleep and Wake-Up Timing

The maximum transition time from the receive mode to the
power-down (sleep) mode t

is 10 µs after CNTRL1 and CNTRL0

RS

are both low (1 µs fall time).

The maximum transition time t
mode is 3*t

, where t

BBC

BBC

from the sleep mode to the receive

SR

is the BBOUT-CMPIN coupling-capacitor
time constant. When the operating temperature is limited to 60
the time required to switch from sleep to receive is dramatically less
for short sleep times, as less charge leaks away from the BBOUT­CMPIN coupling capacitor.

AGC Timing

The maximum AGC engage time t

is 5 µs after the reception of a

AGC

-30 dBm RF signal witha1µsenvelope rise time.

The minimum AGC hold-in time is set by the value of the capacitor
at the AGCCAP pin. The hold-in time t
in µs and C

AGC

is in pF.

AGH=CAGC

/19.1, where t

o

AGH

-

-

-

-

-

-

-

-

C,

is

6

Peak Detector Timing

The Peak Detector attack time constant is set by the value of the ca
pacitor at the PKDET pin. The attack time t

is in µs and C

t

PKA

stant t

PKD

= 1000*t

is in pF. The Peak Detector decay time con

PKD

.

PKA

PKA=CPKD

/4167, where

-

Pulse Generator Timing

In the low data rate mode, the interval t

between the falling edge

PRI

of an ON pulse to the first RF amplifier and the rising edge of the
next ON pulse to the first RF amplifier is set by a resistor R

be

-

PR

tween the PRATE pin and ground. The interval can be adjusted be
tween 0.1 and 5 µs with a resistor in the range of 51 K to 2000 K.
The value of the R

= 404* t

R

PR

PRI

In the high data rate mode (selected at the PWIDTH pin) the re

is given by:

PR

+ 10.5, where t

is in µs, and RPRis in kilohms

PRI

­ceiver RF amplifiers operate at a nominal 50%-50% duty cycle. In
this case, the period t

from the start of an ON pulse to the first

PRC

RF amplifier to the start of the next ON pulse to the first RF amplifier
is controlled by the PRATE resistor over a range of 0.1 to 1.1 µs us
ing a resistor of 11 K to 220 K. In this case R

R

= 198* t

PR

- 8.51, where t

PRC

is in µs and RPRis in kilohms

PRC

is given by:

PR

In the low data rate mode, the PWIDTH pin sets the width of the ON
pulse to the first RF amplifier t

­ON pulse width to the second RF amplifier t

with a resistor RPWto ground (the

PW1

is set at 1.1 times

PW2

the pulse width to the first RF amplifier in the low data rate mode).
The ON pulse width t

can be adjusted between 0.55 and 1 µs

PW1

with a resistor value in the range of 200 K to 390 K. The value of

is given by:

R

PW

R

PW

= 404* t

- 18.6, where t

PW1

is in µs and RPWis in kilohms

PW1

However, when the PWIDTH pin is connected to Vcc througha1M
resistor, the RF amplifiers operate at a nominal 50%-50% duty cy

­cle, facilitating high data rate operation. In this case, the RF amplifi

ers are controlled by the PRATE resistor as described above.

LPF Group Delay

The low-pass filter group delay is a function of the filter 3 dB band
width, which is set by a resistor R
The minimum 3 dB bandwidth f
and R

The maximum group delay t

­is in µs, f

is in kilohms.

LPF

in kHz, and R

LPF

FGD

LPF

to ground at the LPFADJ pin.

LPF

= 1445/R

LPF

= 1750/f

LPF

, where f

LPF

= 1.21*R

in kilohms.

LPF

, where t

LPF

-

-

-

is in kHz,

FGD

7

PKD

in µs user selected; longer than t

AGH

in µs user selected

in µs slaved to attack time

PKA

PKA

and t

in pF, t

PKD

PKD

in kHz user selected

in kilohms user selected

LPF

LPF

in µs, f

in kHz, R

FGD

LPF

in pF user selected

BBO

in µs, C

BBC

Table 1

19.1 min CAGC in pF, t

AGC/

C

AGH

/4167 min C

PKD

C

PKA

min t

PKA

1000*t

0.1 to 5 µs range low data rate mode user selected mode

PRI

PKD

0.55 to 1 µs range low data rate mode user selected mode

PW1

range low data rate mode user selected mode

PW1

1.1*t

PW2

0.1 to 1.1 µs range high data rate mode user selected mode

PRC

max 1µs CNTRL0/CNTROL1 rise times time until receiver operational

BBC

+ 15 ms max 10 ms supply voltage rise time time until receiver operational

BBC

3*t

10 µs max 1µs CNTRL0/CNTROL1 fall times time until receiver is in power-down mode

5 µs max 1 µs rise time, -30 dBm signal RFA1 switches from 35 to 5 dB gain

3*t

C

0

PR

SR

RS

AGC

0.05 to 0.55 µs range high data rate mode user selected mode

PWH

min f

max t

LPF

LPF

1750/f

1445/R

LPF

FGD

min t

BBO

0.064*C

BBC

Event Symbol Time Min/Max Test Conditions Notes

Receiver Event Timing, 3.0 Vdc, -40 to +85

PKDET Decay Time Constant t

PRATE Interval t

Turn On to Receive t

RX to Sleep t

Sleep to RX t

AGC Hold-In t

PKDET Attack Time Constant t

AGC Engage t

PWIDTH RFA1 t

PWIDTH High (RFA1 & RFA2) t

PRATE Cycle t

PWIDTH RFA2 t

BBOUT-CMPIN Time Constant t

LPF 3 dB Bandwidth f

LPF Group Delay t

Pin Descriptions

Pin Name Description

1 GND1 GND1 is the RF ground pin. GND2 and GND3 should be connected to GND1 by short, low-inductance traces.

2 VCC1

3 AGCCAP

4 PKDET

VCC1 is the positive supply voltage pin for the receiver base-band circuitry. VCC1 must be bypassed by an RF
capacitor, which may be shared with VCC2. See the description of VCC2 (Pin 16) for additional information.

This pin controls the AGC reset operation. A capacitor between this pin and ground sets the minimum time the
AGC will hold-in once it is engaged. The hold-in time is set to avoid AGC chattering. For a given hold-in time t
the capacitor value C

C

= 19.1* t

AGC

A ±10% ceramic capacitor should be used at this pin. The value of C
tween t

and 2.65* t

AGH

is:

AGC

, where t

AGH

, depending on operating voltage, temperature, etc. The hold-in time is chosen to allow

AGH

is in µs and C

AGH

AGC

is in pF

given above provides a hold-in time be

AGC

AGH

-

the AGC to ride through the longest run of zero bits that can occur in a received data stream. The AGC hold-in
time can be greater than the peak detector decay time, as discussed below. However, the AGC hold-in time
should not be set too long, or the receiver will be slow in returning to full sensitivity once the AGC is engaged by
noise or interference. The use of AGC is optional when using OOK modulation with data pulses of at least 30 µs.
AGC operation can be defeated by connecting this pin to Vcc. Active or latched AGC operation is required for
ASK modulation and/or for data pulses of less than 30 µs. The AGC can be latched on once engaged by connect
ing a 150 K resistor between this pin and ground, instead of a capacitor. AGC operation depends on a functioning
peak detector, as discussed below. The AGC capacitor is discharged in the receiver power-down (sleep) mode.

This pin controls the peak detector operation. A capacitor between this pin and ground sets the peak detector at
tack and decay times, which have a fixed 1:1000 ratio. For most applications, these time constants should be co
ordinated with the base-band time constant. For a given base-band capacitor C

C

PKD

= 0.33* C

BBO

, where C

BBO

and C

PKD

are in pF

A ±10% ceramic capacitor should be used at this pin. This time constant will vary between t

, the capacitor value C

BBO

and 1.5* t

PKA

PKD

PKA

is:

with
variations in supply voltage, temperature, etc. The capacitor is driven from a 200 ohm “attack” source, and decays
through a 200 K load. The peak detector is used to drive the “dB-below-peak” data slicer and the AGC release
function. The AGC hold-in time can be extended beyond the peak detector decay time with the AGC capacitor, as
discussed above. Where low data rates and OOK modulation are used, the “dB-below-peak” data slicer and the
AGC are optional. In this case, the PKDET pin and the THLD2 pin can be left unconnected, and the AGC pin can
be connected to Vcc to reduce the number of external components needed. The peak detector capacitor is dis­charged in the receiver power-down (sleep) mode.

,

-

-

-

BBOUT is the receiver base-band output pin. This pin drives the CMPIN pin through a coupling capacitor C
internal data slicer operation. The time constant t

t

= 0.064*C

BBC

BBO

, where t

is in µs and C

BBC

BBC

A ±10% ceramic capacitor should be used between BBOUT and CMPIN. The time constant can vary between t
and 1.8*t

with variations in supply voltage, temperature, etc. The optimum time constant in a given circum

BBC

stance will depend on the data rate, data run length, and other factors as discussed in the ASH Transceiver De
signer’s Guide. A common criteria is to set the time constant for no more than a 20% voltage droop during SP
For this case:

5 BBOUT

= 70*SP

BBO

The output from this pin can also be used to drive an external data recovery process (DSP, etc.). The nominal out

, where SP

MAX

is the maximum signal pulse width in µs and C

MAX

C

put impedance of this pin is 1 K. When the receiver RF amplifiers are operating at a 50%-50% duty cycle, the
BBOUT signal changes about 10 mV/dB, with a peak-to-peak signal level of up to 685 mV. For lower duty cycles,
the mV/dB slope and peak-to-peak signal level are proportionately less. The signal at BBOUT is riding on a

1.1 Vdc value that varies somewhat with supply voltage and temperature, so it should be coupled through a ca
pacitor to an external load. A load impedance of 50 K to 500 K in parallel with no more than 10 pF is recom
mended. When an external data recovery process is used with AGC, BBOUT must be coupled to the external
data recovery process and CMPIN by separate series coupling capacitors. The AGC reset function is driven by
the signal applied to CMPIN. When the receiver is in power-down (sleep) mode, the output impedance of this pin
becomes very high, preserving the charge on the coupling capacitor.

6 CMPIN

This pin is the input to the internal data slicers. It is driven from BBOUT through a coupling capacitor. The input
impedance of this pin is 70 K to 100 K.

RXDATA is the receiver data output pin. This pin will drive a 10 pF, 500 K parallel load. The peak current available
from this pin increases with the receiver low-pass filter cutoff frequency. In the power-down (sleep) mode, this pin

7 RXDATA

becomes high impedance. If required, a 1000 K pull-up or pull-down resistor can be used to establish a definite
logic state when this pin is high impedance. If a pull-up resistor is used, the positive supply end should be con
nected to a voltage no greater than Vcc + 200 mV.

8 NC This pin may be left unconnected or may be grounded.

for this connection is:

is in pF

BBO

BBO

is in pF

BBO

-

-

MAX

-

for

BBC

-

.

-

-

9

Pin Name Description

This pin is the receiver low-pass filter bandwidth adjust. The filter bandwidth is set by a resistor R
pin and ground. The resistor value can range from 330 K to 820 ohms, providing a filter 3 dB bandwidth f

4.5 kHz to 1.8 MHz. The resistor value is determined by:

9 LPFADJ

= 1445/ f

LPF

A ±5% resistor should be used to set the filter bandwidth. This will providea3dBfilter bandwidth between f
and 1.3* f

with variations in supply voltage, temperature, etc. The filter provides a three-pole, 0.05 degree

LPF

, where R

LPF

is in kilohms, and f

LPF

LPF

is in kHz

R

equiripple phase response. The peak drive current available from RXDATA increases in proportion to the filter
bandwidth setting.

10 GND2 GND2 is an IC ground pin. It should be connected to GND1 by a short, low inductance trace.

RREF is the external reference resistor pin. A 100 K reference resistor is connected between this pin and ground.
A ±1% resistor tolerance is recommended. It is important to keep the total capacitance between ground, Vcc and

11 RREF

this node to less than 5 pF to maintain current source stability. If THLD1 and/or THDL2 are connected to RREF
through resistor values less that 1.5 K, their node capacitance must be added to the RREF node capacitance and
the total should not exceed 5 pF.

THLD2 is the “dB-below-peak” data slicer (DS2) threshold adjust pin. The threshold is set bya0to200Kresistor

between this pin and RREF. Increasing the value of the resistor decreases the threshold below the peak de

R

TH2

tector value (increases difference) from 0 to 120 mV. For most applications, this threshold should be set at 6 dB

12 THLD2

below peak, or 60 mV for a 50%-50% RF amplifier duty cycle. The value of the THLD2 resistor is given by:

R

= 1.67*V, where R

TH2

is in kilohms and the threshold V is in mV

TH2

A ±1% resistor tolerance is recommended for the THLD2 resistor. Leaving the THLD2 pin open disables the
dB-below-peak data slicer operation.

The THLD1 pin sets the threshold for the standard data slicer (DS1) through a resistor R

TH1

old is increased by increasing the resistor value. Connecting this pin directly to RREF provides zero threshold.
The value of the resistor depends on whether THLD2 is used. For the case that THLD2 is not used, the accept
able range for the resistor is 0 to 100 K, providing a THLD1 range of 0 to 90 mV. The resistor value is given by:

13 THLD1

= 1.11*V, where R

TH1

For the case that THLD2 is used, the acceptable range for the THLD1 resistor is 0 to 200 K, again providing a

is in kilohms and the threshold V is in mV

TH1

R

THLD1 range of 0 to 90 mV. The resistor value is given by:

R

= 2.22*V, where R

TH1

is in kilohms and the threshold V is in mV

TH1

A ±1% resistor tolerance is recommended for the THLD1 resistor. Note that a non-zero DS1 threshold is required
for proper AGC operation.

between this

LPF

LPF

from

LPF

to RREF. The thresh

-

-

-

14 PRATE

15 PWIDTH

16 VCC2

The interval between the falling edge of an ON pulse to the first RF amplifier and the rising edge of the next ON
pulse to the first RF amplifier t
justed between 0.1 and 5 µs with a resistor in the range of 51 K to 2000 K. The value of R

R

= 404* t

PR

+ 10.5, where t

PRI

is set by a resistor RPRbetween this pin and ground. The interval t

PRI

is in µs, and RPRis in kilohms

PRI

PR

PRI

is given by:

can be ad

A ±5% resistor value is recommended. When the PWIDTH pin is connected to Vcc througha1Mresistor, the RF
amplifiers operate at a nominal 50%-50% duty cycle, facilitating high data rate operation. In this case, the period
t

from start-to-start of ON pulses to the first RF amplifier is controlled by the PRATE resistor over a range of 0.1

PRC

to 1.1 µs using a resistor of 11 K to 220 K. In this case the value of R

R

= 198* t

PR

- 8.51, where t

PRC

is in µs and RPRis in kilohms

PRC

is given by:

PR

A ±5% resistor value should also be used in this case. Please refer to the ASH Transceiver Designer’s Guide for
additional amplifier duty cycle information. It is important to keep the total capacitance between ground, Vcc and
this pin to less than 5 pF to maintain stability.

The PWIDTH pin sets the width of the ON pulse to the first RF amplifier t
pulse width to the second RF amplifier t
pulse width t
value of R

can be adjusted between 0.55 and 1 µs with a resistor value in the range of 200 K to 390 K. The

PW1

is given by:

PW

R

PW

= 404* t

- 18.6, where t

PW1

is set at 1.1 times the pulse width to the first RF amplifier). The ON

PW2

is in µs and RPWis in kilohms

PW1

A ±5% resistor value is recommended. When this pin is connected to Vcc througha1Mresistor, the RF amplifi

with a resistor RPWto ground (the ON

PW1

­ers operate at a nominal 50%-50% duty cycle, facilitating high data rate operation. In this case, the RF amplifier
ON times are controlled by the PRATE resistor as described above. It is important to keep the total capacitance
between ground, Vcc and this node to less than 5 pF to maintain stability. When using the high data rate operation
with the sleep mode, connect the 1 M resistor between this pin and CNTRL1 (Pin 17), so this pin is low in the
sleep mode.

VCC2 is the positive supply voltage pin for the receiver RF section. This pin must be bypassed with an RF capaci
tor, which may be shared with VCC1. VCC2 must also be bypassed witha1to10µFtantalum or electrolytic ca

-

pacitor.

-

-

10

Pin Name Description

CNTRL1 and CNTRL0 select the receiver modes. CNTRL1 and CNTRL0 both high place the unit in the receive
mode. CNTRL1 and CNTRL0 both low place the unit in the power-down (sleep) mode. CNTRL1 is a

17 CNTRL1

high-impedance input (CMOS compatible). An input voltage of 0 to 300 mV is interpreted as a logic low. An input
voltage of Vcc - 300 mV or greater is interpreted as a logic high. An input voltage greater than Vcc + 200 mV
should not be applied to this pin. A logic high requires a maximum source current of 40 µA. Sleep mode requires a
maximum sink current of 1 µA. This pin must be held at a logic level; it cannot be left unconnected.

CNTRL0 is used with CNTRL1 to control the receiver modes. CNTRL0 is a high-impedance input (CMOS compat
ible). An input voltage of 0 to 300 mV is interpreted as a logic low. An input voltage of Vcc - 300 mV or greater is

18 CNTRL0

interpreted as a logic high. An input voltage greater than Vcc + 200 mV should not be applied to this pin. A logic
high requires a maximum source current of 40 µA. Sleep mode requires a maximum sink current of 1 µA. This pin
must be held at a logic level; it cannot be left unconnected.

19 GND3 GND3 is an IC ground pin. It should be connected to GND1 by a short, low inductance trace.

RFIO is the receiver RF input pin. This pin is connected directly to the SAW filter transducer. Antennas presenting
an impedance in the range of 35 to 72 ohms resistive can be satisfactorily matched to this pin with a series match

20 RFIO

ing coil and a shunt matching/ESD protection coil. Other antenna impedances can be matched using two or three
components. For some impedances, two inductors and a capacitor will be required. A DC path from RFIO to
ground is required for ESD protection.

-

-

Note: Specifications subject to change without notice.

S M -2 0 L P C B P a d L a y o u t

.1 9 7 5

.1 7 2 5

.4 6 0 0

0.000

.1 4 0

0.000

D im ensions in inches

.2 1 2 5

.2 3 7 5

.3 8 2 5

.3 5 7 5

.3 1 7 5

.2 7 7 5

.2 3 7 5

.1 9 7 5

.1 5 7 5

.1 1 7 5
.1 0 2 5

.0 7 7 5

.2 7 0

.4 1 0

file: rx5000v.vp, 2003.07.17 rev

11