Datasheet RV4141A Datasheet (Fairchild Semiconductor)

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RV4141A

Low Power Ground Fault Interrupter

Features

• Powered from the AC line

• Built-in rectifier

• Direct interface to SCR

• 500 µA quiescent current

• Precision sense amplifier

• Adjustable time delay

• Minimum external components

• Meets UL 943 requirements

• For use with 110V or 220V systems

• Available in 8 pin DIP or SOIC package

Description

The RV4141A is a low power controller for AC receptacle
ground fault circuit interrupters. These devices detect
hazardous current paths to ground and ground to neutral
faults. The circuit interrupter then disconnects the load from
the line before a harmful or lethal shock occurs.

Internally, the RV4141A contains a diode rectifier, shunt
regulator, precision sense amplifier, current reference, time
delay circuit, and SCR driver.

Two sense transformers, SCR, solenoid, three resistors and
four capacitors complete the design of the basic circuit inter­rupter. The simple layout and minimum component count
insure ease of application and long term reliability.

Features not found in other GFCI controllers include a low
offset voltage sense amplifier eliminating the need for a
coupling capacitor between the sense transformer and sense
amplifier, and an internal rectifier to eliminate high voltage
rectifying diodes.

The RV4141A is powered only during the positive half
period of the line voltage, but can sense current faults inde­pendent of its phase relative to the line voltage. The gate of
the SCR is driven only during the positive half cycle of the
line voltage.

Block Diagram

Amp Out

V

FB

V

REF

Gnd

RV4141A

Cap

–

+

+

–

+

+

–

Delay

–

4.7K

65-4141-01

SCR

+V

S

Line

REV. 1.0.1 7/8/03

PRODUCT SPECIFICATION RV4141A

Pin Assignments

Amp Out

V

FB

V

REF

GND

1

2

3

4

65-4141A-02

8

7

6

5

Delay Cap

SCR Trigger

+V

S

Line

Absolute Maximum Ratings

(beyond which the device may be damaged)

Parameter Min Typ Max Units

Supply Current 10 mA

Internal Power Dissipation 500 mW

Storage Temperature Range -65 +150 °C

Operating Temperature Range -35 +80 °C

Junction Temperature 125 °C

Lead Soldering Temperature 60 Sec, DIP 300 °C

Notes:

1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if
Operating Conditions are not exceeded.

1

10 Sec, SOIC 260 °C

Thermal Characteristics

Parameter Min Typ Max Units

θ

JA

Thermal resistance SOIC 240 °C/W

PDIP 160 °C/W

2

REV. 1.0.1 7/8/03

RV4141A PRODUCT SPECIFICATION

Electrical Characteristics

(I

= 1.5mA and T

LINE

= +25°C, R

A

= 650k Ω )

SET

Parameters Test Conditions Min Typ Max Units

Shunt Regulator (Pins 5 to 4)

Regulated Voltage I

Regulated Voltage I

Quiescent Current V

= 11µA 25.0 27.0 29.0 V

2-3

= 750 µA, I

LINE

= 24V — 500 — µA

5-4

= 9µA 25.0 27.0 29.0 V

2-3

Sense Amplifier (Pins 2 to 3)

Offset Voltage -200 0 200 µV

Gain Bandwidth (Design Value) — 1.5 — MHz

Input Bias Current (Design Value) 30 100 nA

SCR Trigger (Pins 7 to 4)

Output Resistance V

Output Voltage I

Output Voltage I

Output Current V

= Open, I

7-4

= 9µA 0 0.1 10 mV

2-3

= 11µA 2.4 3.0 3.6 V

2-3

= 0V, I

7-4

= µA 3.8 4.7 5.6 k Ω

2-3

= 11µA 400 600 µA

2-3

Reference Voltage (Pins 3 to 4)

Reference Voltage I

= 750 µA 12.0 13.0 14.0 V

LINE

Delay Timer (Pins 8 to 4)

Delay Time (Note 1) C

Delay Current I

Note:

1. Delay time is defined as starting when the instantaneous sense current (I
trigger voltage V

goes high.

7-6

= 12nF — 2.0 — ms

8-4

= 11µA 30 40 50 µA

2-3

) exceeds 6.5 V/R

2-3

and ending when the SCR

SET

REV. 1.0.1 7/8/03

3

PRODUCT SPECIFICATION RV4141A

Circuit Operation

(Refer to Block Diagram and Figure 1)

The precision op amp connected to Pins 1 through 3 senses
the fault current flowing in the secondary of the sense trans­former, converting it to a voltage at Pin 1. The ratio of sec­ondary current to output voltage is directly proportional to
feedback resistor, R

R

converts the sense transformer secondary current to a

SET

voltage at Pin 1. Due to the virtual ground created at the
sense amplifier input by its negative feedback loop, the sense
transformer's burden is equal to the value of R
transformer's point of view, the ideal value for R
This will cause it to operate as a true current transformer
with minimal error. However, making R
ates a large offset voltage at Pin 1 due to the sense amplifier's
very high DC gain. R
ble consistent with preserving the transformer's operation as
a true current mode transformer. A typical value for R
between 200 and 1000 Ω .

As seen by the equation below, maximizing R
the DC offset error at the sense amplifiers output. The DC
offset voltage at Pin 1 contributes directly to the trip current
error. The offset voltage at Pin 1 is:

V

x R

OS

SET

Where:
V

= Input offset voltage of sense amplifier

OS

R

= Feedback resistor

SET

R

= Input resistor

IN

R

= Transformer secondary winding resistance

SEC

The sense amplifier has a specified maximum offset voltage
of 200 µV to minimize trip current errors.

Two comparators connected to the sense amplifier output are
configured as a window detector, whose references are -6.5
volts and +6.5 volts referred to Pin 3. When the sense trans­former secondary RMS current exceeds 4.6/R
of the window detector starts the delay circuit. If the second­ary current exceeds the predetermined trip current for longer
than the delay time a current pulse appears at Pin 7, trigger­ing the SCR.

The SCR anode is directly connected to a solenoid or relay
coil. The SCR can be tripped only when its anode is more
positive than its cathode.

Supply Current Requirements

The RV4141A is powered directly from the line through a
series limiting resistor called R
24 k Ω and 91 k Ω . The controller IC has a built-in diode
rectifier eliminating the need for external power diodes.

.

SET

equal to zero cre-

IN

should be selected as high as possi-

IN

/(R

IN

+ R

SEC

)

, its value is between

LINE

. From the

IN

IN

minimizes

IN

SET

is 0 Ω .

is

IN

the output

The recommended value for R

is 24 k Ω to 47 k Ω for

LINE

110V systems and 47 k Ω to 91 k Ω for 220V systems. When
R

is 47 k Ω the shunt regulator current is limited to

LINE

3.6 mA. The recommended maximum peak line current
through R

GFCI Application

LINE

is 10 mA.

(Refer to Figure 1)

The GFCI detects a ground fault by sensing a difference cur­rent in the line and neutral wires. The difference current is
assumed to be a fault current creating a potentially hazardous
path from iine to ground. Since the line and neutral wires
pass through the center of the sense transformer, only the dif­ferential primary current is transferred to the secondary.
Assuming the turns ratio is 1:1000 the secondary current is
1/1000th the fault current. The RV4141A’s sense amplifier
converts the secondary current to a voltage which is com­pared with either of the two window detector reference volt­ages. If the fault current exceeds the design value for the
duration of the programmed time delay, the RV4141A will
send a current pulse to the gate of the SCR.

Detecting ground to neutral faults is more difficult. R
sents a normal ground fault resistance, R

is the wire resis-

N

repre-

B

tance of the electrical circuit between load/ neutral and earth
ground. R
According to UL 943, the GFCI must trip when R
R

= 1.6 Ω and the normal ground fault is 6 mA.

G

represents the ground to neutral fault condition.

G

= 0.4 Ω ,

N

Assuming the ground fault to be 5 mA, 1 mA and 4 mA will
go through R

and R

G

, respectively, causing an effective 1

N

mA fault current. This current is detected by the sense trans­former and amplified by the sense amplifier. The ground/
neutral and sense transformers are now mutually coupled by
R

, R

and the neutral wire ground loop, producing a posi-

G

N

tive feedback loop around the sense amplifier. The newly
created feedback loop causes the sense amplifier to oscillate
at a frequency determined by ground/neutral transformer
secondary inductance and C4. Typically it occurs at 8 KHz.

C2 is used to program the time required for the fault to be
present before the SCR is triggered. Refer to the equation
below for calculating the value of C2. Its typical value is
12 nF for a 2 ms delay.

R

is used to set the fault current at which the GFCI trips.

SET

When used with a 1:1000 sense transformer, its typical value
is 1 M Ω for a GFCI designed to trip at 5 mA.

R

should be the highest value possible which insures a

IN

predictable secondary current from the sense transformer.
If R

is set too high, normal production variations in the

IN

transformer permeability will cause unit to unit variations in
the secondary current. If it is too low, a large offset voltage
error at Pin 1 will be present. This error voltage in turn cre­ates a trip current error proportional to the input offset volt­age of the sense amplifier. As an example, if R

is 500 Ω ,

IN

4

REV. 1.0.1 7/8/03

5

RV4141A PRODUCT SPECIFICATION

R

is 1 M Ω , R

SET

fier is its maximum of 200 µV, the trip current error is
±5.6%.

The SCR anode is directly connected to a solenoid or relay
coil. It can be tripped only when its anode is more positive
than its cathode. It must have a high dV/dt rating to ensure
that line noise (generated by electrically noisy appliances)
does not falsely trigger it. Also the SCR must have a gate
drive requirement less than 200 µA. C3 is a noise filter that
prevents high frequency line pulses from triggering the SCR.

The relay solenoid used should have a response time of 3 ms
or less to meet the UL 943 timing requirement.

Sense Transformers and Cores

The sense and ground/neutral transformer cores are usually
fabricated using high permeability laminated steel rings.
Their single turn primary is created by passing the line and
neutral wires through the center of its core. The secondary is
usually from 200 to 1500 turns.

is 45 Ω and the V

SEC

of the sense ampli-

OS

Calculating The Values Of R

SET

and C2

Determine the nominal ground fault trip current requirement.
This will be typically 5 mA in North America (117V AC)
and 22 mA in the UK and Europe (220V AC). Determine the
minimum delay time required to prevent nuisance tripping.
This will typically be 1 to 2 ms. The value of C2 required to
provide the desired delay time is:

C2 = 6 x T

where:
C2 is in nF
T is the desired delay time in ms.

The value of R

to meet the nominal ground fault trip cur-

SET

rent specification is:

R

SET

---------------------------------------------------------------=
I

FAULT

4.6 N×
COS 180× TP⁄()

where:
R

is in k Ω

SET

T is the time delay in ms
Magnetic Metals Corporation
1900 Hayes Ave.
Camden, NJ 08105

P is the period of the line frequency in ms

I

is the desired ground fault trip current in mA RMS

FAULT

N is the number of sense transformer secondary turns.
[phone]

This formula assumes an ideal sense transformer is used.
Is a full-line suppliers of ring cores and transformers
designed specifically for GFCI and related applications.

The calculated value of R

may have to be changed up to

SET

30% to when using a non-ideal transformer.

R

TEST

Mov

Sense Transformer

1:1000

5 Ring Steel Core

Line

R

IN

470

R

1.1 Meg

GFCI

Note:

1. Portions of this schematic are subject to U.S. patents 3,878,435 and Re. 30,678.

Phase

Neutral

C1

10 nF

SET

1

2

3

4

15K

Grounded Neutral

1:200

1000 pF

RV4141A

Figure 1. GFI Application Circuit

C4

Press to

8

7

6

1µF 35V

5

Test

12 nF

+

C2

C

Normally Closed

Latching Contacts

Load

Solenoid

Q1

TAG

X0103DA

C3

F

10 nF

1N4004

R

24K

LINE

1W

R

N

0.4

65-4141A-03

R

B

20K

R

G

1.6

Fault

Resistance

Not Part of

Application

REV. 1.0.1 7/8/03

PRODUCT SPECIFICATION RV4141A

Mechanical Dimensions

8-Lead Plastic DIP Package

Symbol

A — .210 — 5.33

A1 .015 — .38 —

A2 .115 .195 2.93 4.95
B .014 .36

B1 .045 .070 1.14 1.78
C .008 .015 .20 .38

D .348 .430 8.84 10.92

D1
E
E1
e

eB
L

N

E1

Inches

Min. Max. Min. Max.

.022 .56

.005 — .13 —
.300 .325 7.62 8.26
.240 .280 6.10 7.11

.100 BSC 2.54 BSC

— .430 — 10.92

.115 .160 2.92 4.06

°

8

D

4

1

Millimeters

°

8

Notes

4

2

2

5

Notes:

1.

Dimensioning and tolerancing per ANSI Y14.5M-1982.

2.

"D" and "E1" do not include mold flashing. Mold flash or protrusions
shall not exceed .010 inch (0.25mm).

3.

Terminal numbers are for reference only.

4.

"C" dimension does not include solder finish thickness.

5.

Symbol "N" is the maximum number of terminals.

5

D1

A

A1

B1

8

e

A2

L

B

E

C

eB

6 REV. 1.0.1 7/8/03

RV4141A PRODUCT SPECIFICATION

Mechanical Dimensions (continued)

8-Lead SOIC Package

Symbol

A .053 .069 1.35 1.75

A1 .004 .010 0.10 0.25

B .013 0.33

C .008 .010 0.20 0.25
D .189 .197 4.80 5.00

E .150 .158 3.81 4.01

e

H

h

L .016 .050 0.40 1.27

N8 8

α

ccc .004 0.10——

85

14

Inches

Min. Max. Min. Max.

.020 0.51

.050 BSC 1.27 BSC

.228 .244 5.79 6.20

.010 .020 0.25 0.50

°

0

°

8

EH

Millimeters

°

0

Notes

°

8

Notes:

1.

Dimensioning and tolerancing per ANSI Y14.5M-1982.

2.

"D" and "E" do not include mold flash. Mold flash or
protrusions shall not exceed .010 inch (0.25mm).

3.

"L" is the length of terminal for soldering to a substrate.

4.

5
2

2

3
6

Terminal numbers are shown for reference only.

5.

"C" dimension does not include solder finish thickness.

6.

Symbol "N" is the maximum number of terminals.

°

D

A

e

B

A1

SEATING
PLANE

– C –

LEAD COPLANARITY

ccc C

α

h x 45

C

L

REV. 1.0.1 7/8/03 7

PRODUCT SPECIFICATION RV4141A

Ordering Information

Part Number Package Operating Temperature Range

RV4141AN 8-Lead Plastic DIP -35°C to +80°C

RV4141AM 8-Lead Plastic SOIC -35°C to +80°C

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.

2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.

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7/8/03 0.0m 001

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