Datasheet rt9607 Datasheets

Page 1

RT9607/A

Dual Channel Synchronous-Rectified Buck MOSFET Driver

General Description

The RT9607/A is a dual power channel MOSFET driver specifically designed to drive four power N-MOSFET s in a synchronous-rectified buck converter topology. These drivers combined with RichTek’s series of Multi-Phase Buck PWM controllers provide a complete core voltage regulator solution for adva nced microprocessors.

The RT9607/A can

provide flexible gate driving for both high side and low side drivers. This gives more flexibility of MOSFET selection.

The output drivers of the part are capble to driver a 3nF load in 30/40ns rising/falling time with fast propagation delay from input transition to the gate of the power MOSFET. This device implements bootstrapping on the upper gates with only a single external cap acitor required for each power channel. This reduces implementation complexity and allows the use of higher performa nce, cost effective, N-MOSFET s. Ada ptive shoot-through protect-ion is integrated to prevent both MOSFETs from conducting simultaneously.

The RT9607/A can detect high side MOSFET drain-to-

source electrical short at power on and pull the 12V power by low side MOS and cause power supply to go into over current shutdown to prevent damage of CPU.

RT9607 ha s longer UGA TE/LGA TE dead time which ca n drive the MOSFETs with large gate RC value, avoiding the shoot-through phenomenon. RT9607A is targeted to drive small gate RC value MOSFET s a nd performs better efficiency.

Marking Information

Features

Drives Four N-MOSFET s

z Adaptive Shoot-Through Protection

z Propagation Delay 40ns

z Support High Switching Frequency

z Fast Output Rise T ime

z 5V to 12V Gate-Drive V oltages for Optimal Efficiency

z Tri-State Input for Bridge Shutdown

z Supply Under-Voltage Protection

z RoHS Compliant and 100% Lead (Pb)-Free

Applications

z Core Voltage Supplies for motherboard/desktop PC

microprocessor core power

z High Frequency Low Profile DC-DC Converters z High Current Low V oltage DC-DC Converters

Ordering Information

RT9607/A

Package Type QV : V QFN-1 6 L 3 x 3 (V-Type ) S : SOP-14

Operating Temperature Range P : Pb F re e with Commercia l Standard G : Green (Halogen Free with Commer cial Sta n d a rd)

Short Dead Time Long Dead Time

Note :

Richtek Pb-free and Green products are :

`RoHS compliant and compatible with the current require ments of IPC/JEDEC J-STD-020.

`Suitable for use in SnPb or Pb-free soldering processes. `100%matte tin (Sn) plating.

For marking information, contact our sales re presentative directly or through a Richtek distributor located in your area, otherwise visit our website for detail.

DS9607/A-06 August 2007

www.richtek.com

Page 2

RT9607/A

Pin Configurations

(TOP VIEW)

PWM1

GND

LGATE2

VCC

13141516

PHASE2

PHASE1

12 11 10

8765

UGATE1 BOOT1 BOOT2 UGATE2

GND

LGATE1

PGND

PWM2

1 2 3 4

PVCC

VQFN-16L 3x3

Typical Application Circuit

12V

Optional

BOOT1

UGATE1

PHASE1

RT9607/A

VCC

PVCC

PWM1

PWM1 PWM2

GND

LGATE1

PVCC

PGND

LGATE2

14 2 3 4 5 6 7

9 8

SOP-14

From Controller

PWM1

VCC PHASE1

UGATE1 BOOT1 BOOT2 UGATE2 PHASE2

12V

CORE

LGATE1

UGATE2

PHASE2

LGATE2

PWM2

BOOT2 10

Optional

GND

PGND

From Controller

PWM2

www.richtek.com

DS9607/A-06 August 2007

Page 3

Timing Diagram

RT9607/A

PWM

LGATE

UGATE

pdlLGATE

90%

pdhUGATE

Functional Pin Description

Pin No.

RT9607/A□S RT9607/A□QV

1 15 2 16 3 1 4 2

Pin Name Pin Function

PWM1 Channel 1 PW M Input. PWM2 Channel 2 PW M Input. GND Ground Pin. LGATE1 Lower Gate Drive of Channel 1.

pdlUGATE

90%

pdhLGATE

5 5 6 4 7 6

PVCC Upper and Lower Gate Driver Power Rail. PGND Lower Gate Driver Ground Pin. LGATE2 Lower Gate Drive of Channel 2.

Connect this pin to phase point of Channel 2.

8 7 PHASE2

9 9 10 10 11 11 12 12

UGATE2 Upper Gate Drive of Channel 2. BOOT2 Floating Bootstrap Supply Pin of Channel 2. BOOT1 Floating Bootstrap Supply Pin of Channel 1. UGATE1 Upper Gate Drive of Channel 1.

Phase point is the connection point of high side MOSFET source

Connect this pin to phase point of Channel 1.

13 13 PHASE1

14 14

VCC Control Logic Power Supply.

Phase point is the connection point of high side MOSFET source

-- 3, 8 NC No Connection.

-- Exposed Pad (17) GND

The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation.

DS9607/A-06 August 2007

www.richtek.com

Page 4

RT9607/A

Function Block Diagram

PWM1

PWM2

Internal

VCC

Control

Logic

Shoot-Through

Protection

Power-On OVP

Shoot-Through

Protection

PVCC

Shoot-Through

Protection

Power-On OVP

Shoot-Through

Protection

PVCC

PGND

BOOT1

UGATE1

PHASE1

PVCC

LGATE1

PGND BOOT2

UGATE2

PHASE2

PVCC

LGATE2

GND

PGND

www.richtek.com

DS9607/A-06 August 2007

Page 5

Absolute Maximum Ratings (Note 1)

RT9607/A

z Supply Voltage, V z Supply Voltage, PV z BOOT V oltage, V z Input V oltage, V z PHASE to GND

------------------------------------------------------------------------------------- 15V

----------------------------------------------------------------------------------- VCC + 0.3V

BOOT-VPHASE

-------------------------------------------------------------------------------------- GND - 0.3V to 7V

PWM

------------------------------------------------------------------------- 15V

DC------------------------------------------------------------------------------------------------------------ −5V to 15V < 200ns ----------------------------------------------------------------------------------------------------- −10V to 30V

z BOOT to GND

DC------------------------------------------------------------------------------------------------------------ −0.3V to V

+ 15V

< 200ns ----------------------------------------------------------------------------------------------------- −0.3V to 42V

z UGATE------------------------------------------------------------------------------------------------------ V z LGATE ------------------------------------------------------------------------------------------------------ GND - 0.3V to V

PHASE

- 0.3V to V

< 200ns ----------------------------------------------------------------------------------------------------- −2V to VCC + 0.3V

z Power Dissipation, P

@ T

= 25°C

VQF N−1 6L 3x3-------------------------------------------------------------------------------------------- 1.471W SOP-14 ----------------------------------------------------------------------------------------------------- 0.909W

z Package Thermal Resistance (Note 4)

VQFN−16L 3x3, θJA-------------------------------------------------------------------------------------- 68°C/W SOP-14, θJA----------------------------------------------------------------------------------------------- 110°C /W

z Storage T emperature Range --------------------------------------------------------------------------- −40°C to 150°C z Lead T e mperature (Soldering, 10 sec.)-------------------------------------------------------------- 26 0°C z ESD Susceptibility (Note 2)

HBM (Human Body Mode) ----------------------------------------------------------------------------- 2kV MM (Ma chine Mode)------------------------------------------------------------------------------------- 200V

BOOT

PVCC

+ 0.3V

Recommended Operating Conditions (Note 3)

z Supply Voltage, V z Junction T emperature Range--------------------------------------------------------------------------- 0°C to 125°C

z Ambient T emperature Range--------------------------------------------------------------------------- 0°C to 70°C

------------------------------------------------------------------------------------- 12V ±10%

Electrical Characteristics

(Recommended Operating Conditions, TA = 25°C unless otherwise specified)

Parameter Symbol Test Conditions Min Typ Max Units

VCC Supply Current

= 250kHz, V

Bias Supply Current

Power Supply Current

VCC

PVCC

PWM

f C

= 0.1μF, R

BOOT

= 250kHz, V

PWM

= 0.1μF, R

BOOT

Power-On Reset VCC Rising Threshold

-- 8.0 -- V

Hysteresis -- 1.0 -- V

PVCC

PHASE PVCC

PHASE

= 12V,

= 20Ω

= 12V,

= 20Ω

-- 5.5 8.0 mA

-- 5.5 10.0 mA

To be continued

DS9607/A-06 August 2007

www.richtek.com

Page 6

RT9607/A

Parameter Symbol Test Conditions Min Typ Max Units

PWM Input

Maximum Input Current PWM Floating Voltage

= 0 or 5V

PWM

cc = 12V

-- 500 --

μA

-- 2.5 -- V

PWM Rising Threshold 3.3 3.7 4.3 V PWM Falling Threshold 1.0 1.26 1.5 V Output UGATE Rise Ti me UGATE Fall Time LGATE Rise Time LGATE Fall Time

rUGATE

fUGATE

rLGATE

fLGATE

PVCC

= V = V = V = V

= 12V, 3nF load

VCC

= 12V, 3nF load

VCC

= 12V, 3nF load

VCC

= 12V, 3nF load

VCC

-- 30 -- ns

-- 40 -- ns

-- 30 -- ns

RT9607 -- 75 --

BOOT

= V

PHASE

See Timing Diagram

= 12V

-- 25 --

-- 40 --

-- 20 --

-- 35 --

Propagation Delay

RT9607A

RT9607/A

pdhUGATE

pdlUGATE

pdhLGATE

pdlLGATE

Shutdown Window 1.0 -- 4.3 V

UGATE Drive Source R

UGATE Drive Sink R

LGATE Drive Source R

LGATE Drive Sink R

Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for

stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability.

Note 2. Devices are ESD sensitive. Handling precaution recommended. Note 3. The device is not guaranteed to function outside its operating conditions. Note 4. θ

is measured in the n atural convection at TA = 25°C on a high effective thermal conductivity test board (2S2P,4-layers)

of JEDEC 51-7 thermal measurement standard.

UGATEsr UGATEsk VBOOT LGATEsr LGATEsk

BOOT

– V – V

= 12V -- 1.8 -- Ω

PHASE

= 12V -- 1.7 -- Ω

PHASE

VCC = 12V -- 1.5 -- Ω

VCC = 12V -- 1.4 -- Ω

www.richtek.com

DS9607/A-06 August 2007

Page 7

Typical Operating Characteristics

For RT9607

Dead Time at LGATE Falling

RT9607/A

Dead Time at LGATE Falling

(5V/Div)

Full Load (60A), PHASE1

Time (25ns/Div)

Dead Time at LGATE Rising

Full Load (60A), PHASE1

UGATE

PHASE

LGATE

(5V/Div)

Full Load (60A), PHASE2

UGATE

PHASE

LGATE

Time (25ns/Div)

Dead Time at LGATE Rising

Full Load (60A), PHASE2

UGATE

(5V/Div)

PHASE

LGATE

Time (25ns/Div)

Dead Time at LGATE Falling

No Load, PHASE1

UGATE

PHASE

LGATE

(5V/Div)

PHASE

LGATE

Time (25ns/Div)

Dead Time at LGATE Falling

No Load, PHASE2

UGATE

PHASE

LGATE

DS9607/A-06 August 2007

Time (50ns/Div)

www.richtek.com

Page 8

RT9607/A

(5V/Div)

Dead Time at LGATE Rising

No Load, PHASE1

UGATE

PHASE

LGATE

Time (50ns/Div)

(5V/Div)

Dead Time at LGATE Rising

No Load, PHASE2

UGATE

PHASE

LGATE

Time (50ns/Div)

www.richtek.com

DS9607/A-06 August 2007

Page 9

For RT9607A

RT9607/A

(5V/Div)

Dead Time at LGATE Falling

Full Load (60A), PHASE1

Time (25ns/Div)

Dead Time at LGATE Rising

Full Load (60A), PHASE1

UGATE

PHASE

UGATE

PHASE

LGATE - PHASE

LGATE

(5V/Div)

Dead Time at LGATE Falling

Full Load (60A), PHASE2

Time (25ns/Div)

Dead Time at LGATE Rising

Full Load (60A), PHASE2

UGATE

PHASE

UGATE

PHASE

LGATE - PHASE

LGATE

(5V/Div)

LGATE - PHASE

LGATE

Time (25ns/Div)

Dead Time at LGATE Falling

No Load , PHASE1

UGATE

PHASE

LGATE - PHASE

LGATE

(5V/Div)

LGATE - PHASE

LGATE

Time (25ns/Div)

Dead Time at LGATE Falling

No Load , PHASE2

UGATE

PHASE

LGATE - PHASE

LGATE

DS9607/A-06 August 2007

Time (25ns/Div)

www.richtek.com

Page 10

RT9607/A

(5V/Div)

Dead Time at LGATE Rising

No Load, PHASE1

UGATE

PHASE

LGATE - PHASE

LGATE

Time (25ns/Div)

(5V/Div)

Dead Time at LGATE Rising

No Load, PHASE2

UGATE

PHASE

LGATE - PHASE

LGATE

Time (25ns/Div)

www.richtek.com

DS9607/A-06 August 2007

Page 11

RT9607/A

Application Information

The RT9607/A ha s power on protection function which held

UGATE and LGATE low before VCC up cross the rising threshold voltage. After the initi alization, the PWM signal takes the control. The rising PWM signal first forces the LGA TE signal turns low then UGA TE sign al is allowed to go high just after a non-overlapping ti me to avoid shootthrough current. The falling of PWM signal first forces UGA TE to go low. When UGA TE a nd PHASE signal reach a predetermined low level, LGATE signal is allowed to turn high. The non-overla pping function is also presented between UGA TE and LGA TE signal tra nsient.

The PWM signal is recognized as high if above rising threshold and a s low if below falling threshold. Any signal level in this window is considered as tri-state, which cause s turn-off of both high side and low-side MOSFET. When PWM input is floating (not connected), internal divider will pull the PWM to 1.9V to give the controller a recognizable level. The maximum sink/source capability of internal PWM reference is 60μA.

The PVCC pin provides flexibility of both high side and low side MOSFET gate drive voltages. If 8V , f or example, is applied to PVCC, then high side MOSFET gate drive is 8V to 1.5V (approximately, internal diode plus series resistance voltage drop). The low side gate drive voltage is exactly 8V.

The RT9607/A implements a power on over-voltage

protection function. If the PHASE voltage exceeds 1.5V at power on, the LGATE would be turn on to pull the PHASE low until the PHASE voltage goes below 1.5V. Such function can protect the CPU from da mage by some short condition happened before power on, which is sometimes encountered in the M/B ma nufacturing line.

Non-overlap Control

if the PHASE pin had not gone high after LGATE turns low, the LGATE has to wait for 200ns before turn high only under short pulse (tON<60ns) condition. By waiting for the voltages of the PHASE pin and high side gate drive to fall below 1.2V, the non-overlap protection circuit ensures that UGA TE is low before LGA TE turns high. Also to prevent the overlap of the gate drives during LGATE turn low and UGATE turn high, the non-overlap circuit monitors the LGA TE voltage. When LGATE go below 1.2V, UGA TE is allowed to go high.

Driving power MOSFET s

The DC input impedance of the power MOSFET is extremely high. When V

at 12V (or 5V), the gate draws

the current only few nanoamperes. Thus once the gate ha s been driven up to “ON”ON level, the current could be negligible.

However, the capacitance at the gate to source terminal should be considered. It requires relatively large currents to drive the gate up and down 12V (or 5V) rapidly. It also required to switch drain current on and off with the required speed. The required gate drive currents are calculated a s follows.

Vg1

gd1

Vphase

gd1

+12V

gs1

gd2

gs2

GND

T o prevent the overla p of the gate drives during the UGA TE turn low and the LGA TE turn high, the non-overla p circuit monitors the voltages at the PHASE node and high side gate drive (UGA TE-PHASE). When the PWM input signal goes low, UGATE begins to turn low (after propagation delay). Before LGATE can turn high, the non-overlap protection circuit ensures that the monitored voltages have gone below 1.2V . Once the monitored voltages fall below

1.2V , LGA TE begins to turn high. For short pulse condtion,

DS9607/A-06 August 2007

Vg2

+12V

Figure1. The gate driver must supply Igs to Cgs and I

www.richtek.com

Page 12

RT9607/A

In Figure 1, the current Ig1 and Ig2 are required to move the gate up to 12V.The operation consists of charging C and Cgs. C

gs1

and C

are the capacitances from gate to

gs2

source of the high side and the low side power MOSFET s, respectively . In general data sheets, the Cgs is referred as

“C

” which is the input capacitance. C

iss

gd1

and C

gd2

are the cap acitances from gate to drain of the high side and the low side power MOSFETs, respectively and referred to the data sheets as "C cap acita nce. For example, t

," the reverse transfer

rss

and tr2 are the rising time of

the high side and the low side power MOSFETs respectively , the required current I

gs1

and I

are showed

gs2

below

C I

gs1gs1

C I

gs2gs2

12 x C

gs1g1

12 x C

gs2g2

(1)

(2)

According to the design of RT9607/A, before driving the gate of the high side MOSFET up to 12V (or 5V), the low side MOSFET ha s to be of f; and the high side MOSFET is turned off before the low side is turned on. From Figure 1, the body diode "D2" had been turned on before high side MOSFET s turned on

C I ==

12V

gd1g1gd1

(3)

from equation. (3) and (4)

-12

gs1

gs2

12 x 10 x 380

10 x 14

12-

10 x 30

0.326A

12) (12 x 10 x 500

0.4A

(7)

(8)

the total current required from the gate driving source is Ig1 = Igs + Igd1 = (1.428 + 0.326) = 1.745A (9) Ig2 = Igs2 + Igd2 = (0.88 + 0.4) = 1.28A (10) By a similar calculation, we can also get the sink current

required from the turned off MOSFET .

Layout Consider

Figure 2. shows the schematic circuit of a two-phase synchronous-buck converter to implement the

RT9607/A. The converter operates for the input ra ng from

5V to 12V. When layout the PC board, it should be very careful. The

power-circuit section is the most critical one. If not configured properly , it will generate a large amount of EMI. The junction of Q1, Q2, L2 and Q3, Q4, L4 should be very close. The connection from Q1, and Q3 drain to positive sides of C1, C2, C3, and C4; the connection from Q2, a nd Q4 source to the negative sides of C1, C2, C3, and C4 should be as short as possible.

Before the low side MOSFET is turned on, the C been charged to Vi. Thus, as C and g

is charged up to 12V, the required current is

C I

gd2gd2gd2

12V V

reverses its polarity

gd2

have

(4)

It is helpful to calculate these currents in a typical case. Assume a synchronous rectified BUCK converter, input voltage V

= 12V , Vg1 = V

is PHB83N03LT whose C

= 12V . The high side MOSFET

= 1660pF , C

iss

= 380pF ,and t

rss

= 14nS. The low side MOSFET is PHB95N03LT whose C

= 2200pF, C

iss

= 500pF, and t

rss

= 30nS, from the

equation (1) and (2) we can obtain

-12

gs1

gs2

12 x 10 x 1660

10 x 14

12-

10 x 30

1.428A

12 x 10 x 2200

0.88A

(5)

(6)

Next, the trace from Ugate1, Ugate2, Lgate1, a nd Lgate2 should also be short to decrease the noise of the driver output signals. Phase1 and phase2 signals from the junction of the power MOSFET, carrying the large gate drive current pulses, should be a s heavy as the gate drive trace. The bypass capacitor C7 should be connected to PGND directly . Furthermore, the bootstra p ca pacitors (Cb1, Cb2) should always be placed as close to the pins of the IC as possible.

Select the Bootstrap Capacitor

Figure 3. shows part of the bootstrap circuit of R T9607/A.

The V

(the voltage difference between BOOT1 and

PHASE1 on RT9607/A) provides a voltage to the gate of

the high side power MOSFET. This supply needs to be ensured that the MOSFET can be driven. For this, the capacitance CB has to be selected properly. It is

www.richtek.com

DS9607/A-06 August 2007

Page 13

RT9607/A

determined by following constraints. In practice, a low value ca pa citor CB will lead the overcharging that could da mage the IC. Therefore to mini mize the risk

of overcharging and reducing the ripple on VCB, the bootstrap ca pa citor should not be smaller than 0.1μF, and the larger the better. In general design, using 1μF can provide better performa nce. At lea st one low-ESR ca pa citor should be used to provide good local de-coupling. Here, to adopt either a cera mic or ta ntalum capacitor is suitable.

12V

CORE

1.2uH

C5 1500uF

1500uF

1000uF

2uH

C3 1000uF

2uH

PHB83N03LT

1uF

PHB95N03LT

1uF

PHB95N03LT

Cb2

1uF

Cb1 1uF

11 14

BOOT1

UGATE1

PHASE1

LGATE1

UGATE2

PHASE2

LGATE2

PWM1

RT9607/A

PWM2

PGND

BOOT2 10

VCC

PVCC

GND

C7 1uF

PWM1

PWM2

R1 10

12V

Figure 2. T wo- Phase Synchronous-Buck Converter Circuit

PVCC

BOOT1

UGATE1 PHASE1

PVCC

LGATE1 PGND

Vin

Figure 3. Part of Bootstrap Circuit of R T9607/A

DS9607/A-06 August 2007

www.richtek.com

Page 14

RT9607/A

Outline Dimension

SEE DETAIL A

1 2

DETAIL A

Pin #1 ID a nd T ie Bar Mark Option s

Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated.

Dimensions In Millimeters Dimen sions In Inches

Symbol

Min Max Min Max

A 0.800 1.000 0.031 0.039 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010

b 0.180 0.300 0.007 0.012

D 2.950 3.050 0.116 0.120 D2 1.300 1.750 0.051 0.069

E 2.950 3.050 0.116 0.120 E2 1.300 1.750 0.051 0.069

e 0.500 0.020 L 0.350 0.450

0.014 0.018

V-Type 16L QFN 3x3 Package

www.richtek.com

DS9607/A-06 August 2007

Page 15

RT9607/A

Dimensions In Millimeters Dimensions In Inches

Symbol

Min Max Min Max

A 8.534 8.738 0.336 0.344 B 3.810 3.988 0.150 0.157

C 1.346 1.753 0.053 0.069 D 0.330 0.508 0.013 0.020

F 1.194 1.346 0.047 0.053

H 0.178 0.254 0.007 0.010

I 0.102 0.254 0.004 0.010

J 5.791 6.198 0.228 0.244 M 0.406 1.270 0.016 0.050

Richtek Technology Corporation

Headquarter 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611

14–Lead SOP Plastic Package

Richtek Technology Corporation

Taipei Office (Marketing) 8F, No. 137, Lane 235, Paochiao Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862)89191466 Fax: (8862)89191465 Email: marketing@richtek.com

DS9607/A-06 August 2007 www.richtek.com