Datasheet RT9603 Datasheet

Page 1

Preliminary

RT9603

Synchronous-Rectified Buck MOSFET Drivers

General Description

The RT9603 is a high frequency, dual MOSFET drivers specifically designed to drive two power N-Channel MOSFETs in a synchronous-rectified buck converter topology. The device combined with the RT924x series of multi-phase PWM controllers and MOSFETs form a complete core voltage regulator solution for advanced microprocessors.

The output drivers in the RT9603 can efficiently switch power MOSFETs at frequencies up to 500kHz. It shall be taken into account the thermal consideration when the switching frequency above 500kHz. Each driver is capable of driving a 3nF load in 30/40ns rise/fall time with fast propagation delay from input transition to the gate of the power MOSFET. The device implements bootstrapping on the upper gate with only an external capacitor and a diode required. This reduces implementation complexity and allows the use of higher performance, cost effective N-Channel MOSFETs.

Both drivers incorporate adaptive shoot-through protection to prevent upper and lower MOSFETs from conducting simultaneously and shorting the input supply.

Features

l Drives Two N-Channel MOSFETs l Adaptive Shoot-Through Protection l Supports High Switching Frequency

- Fast Output Rise Time

- Propagation Delay 40ns

l Tri-State Input for Bridge Shutdown l Supply Over-Voltage Protection above Maximum

Voltage Rating

l Supply Under-Voltage Protection l Upper MOSFET Direct Shorted Protection l Small SOP-8 Package

Applications

l Core Voltage Supplies for Intel Pentium



4, AMD

AthlonTM Microprocessors

l High Frequency Low Profile DC-DC Converters l High Current Low Voltage DC-DC Converters l IA Equipments



Pin Configurations

An unique feature of the RT9603 driver is the addition of over-voltage protection in the event of upper MOSFET direct shorted before power-on. The RT9603 detects the fault condition during initial start-up, the internal poweron OVP sense circuitry will rapidly drive the output lower MOSFET on before the multi-phase PWM controller takes control. As a result, the input supply will latch into the shutdown state, thereby prevent the processor from damaged.

Ordering Information

RT9603

Package Type S : SOP-8

Operating Temperature Range C : Commercial Standard

BST

VCC

(TOP VIEW)

2 3 4

SOP-8

DRVH

PGND

DRVL

DS9603-00 November 2003 www.richtek.com

Page 2

RT9603

Typical Application Circuit

+12V

Preliminary

1uF

+12V

Q1 PHB83N03LT

1000uF/16V

2uH

2.4K R3

2.4K

VCORE

C5 x1500uFC6x1500uF

ISPx

ISNx

1uF

PWM

INPUT

1N4148

VCC

BST

RT9603

PGND

DRVH

DRVL

8 7

PHB95N03LT

Note: The traces that run from the controller ISPx and ISNx pins, should be run together next to each other and Kelvin connected

to the Q2. Place both R2 and R3 as close to the PWM Controller as possible.

Functional Pin Description

Pin No. Pin Name

Pin Function

Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor

1 BST

between this pin and the SW pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET.

Accepts a logic control signal. Connect this pin to the PWM output of the controller.

2 IN

If the PWM signal enters and remains within the shutdown window, the output drivers are

disabled and both MOSFET gates are pulled and held low. 3 NC No Internal Connection. 4 VCC Supply Input. Connect to +12V supply. Place a bypass capacitor from this pin to PGND.

5 DRVL Lower gate drive output. Should be connected to the lower MOSFET gate. 6 PGND Common Ground.

7 SW

Upper driver return. Should be connected to the common node of upper and lower

MOSFETs. The SW voltage is monitored for adaptive shoot-through protection. 8 DRVH Upper gate drive output. Should be connected to the upper MOSFET gate.

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Page 3

Function Block Diagram

VCC

Preliminary

RT9603

Timing Diagram

Internal

Control

Logic

Shoot-Through

Protection

Power-On OVP

VCC

Shoot-Through

Protection

BST

DRVH

DRVL

PGND

DRVH

DRVL

TPDDRVL

TFDRVL

TRDRVH

TPDDRVH

TFDRVH

TRDRVL

DS9603-00 November 2003 www.richtek.com

Page 4

RT9603

Preliminary

Absolute Maximum Ratings (Note 1)

l Supply Voltage (V l BST to SW------------------------------------------------------------------------------------------------15V l SW to GND----------------------------------------------------------------------------------------------- −4V to 15V l PWM Input Voltage-------------------------------------------------------------------------------------GND - 0.3V to 7V l DRVH------------------------------------------------------------------------------------------------------ V l DRVL-------------------------------------------------------------------------------------------------------GND - 0.3V to V l Package Thermal Resistance

SOP-8, θJA------------------------------------------------------------------------------------------------67° C/W

l Lead Temperature (Soldering, 10 sec.)------------------------------------------------------------260°C l Storage Temperature Range------------------------------------------------------------------------- −40° C to 150° C l ESD Susceptibility (Note 2)

HBM--------------------------------------------------------------------------------------------------------2kV

)------------------------------------------------------------------------------------15V

- 0.3V to V

BST

VCC

+ 0.3V

Recommended Operating Conditions (Note 3)

l Supply Voltage, V l Ambient Temperature Range-------------------------------------------------------------------------------------0° C to 70°C l Junction Temperature Range------------------------------------------------------------------------------------0° C to 125°C

-------------------------------------------------------------------------------------------------12V ±10%

Electrical Characteristics

(Recommended Operating Conditions, T

Parameter Symbol

VCC Supply Current

Power Supply Current I

Power-On Reset

POR Threshold V

Hysteresis V

PWM Input

Input Current I Floating Voltage V

PWM_IN Threshold

DRVH Rise Time T DRVH Fall Time T DRVL Rise Time T DRVL Fall Time T DRVH Turn-Off Propagation Delay T DRVL Turn-Off Propagation Delay T Shutdown Window

= 25°C unless otherwise specified)

Test Conditions Min Typ Max Units

VCC

VCC Rising

VCCRTH

VCCHYS

PWM_IN

VCC = 12V

PWMFL

V V

RDRVH

FDRVH

RDRVL

FDRVL

PDDRVH

PDDRVL

PWM_IN Rising

PWMRTH

PWM_IN Falling

PWMFTH

V V V

V V

= 12V, V

BST

= 0V or 5V

PWM_IN

= 12V, 3nF load

VCC

= 12V, 3nF load

VCC

= 12V, 3nF load

VCC

= 12V, 3nF load

VCC

= 12V, 3nF load

VCC

= 12V, 3nF load

VCC

= 0V -- 5 7 mA

PWM_IN

8.6 9.9 10.7

-- 1.35 --

80 127 150

1.1 2.1 3.7

3.3 3.7 4.3

1.0 1.26 1.5

-- 30 --

-- 40 --

-- 30 --

-- 40 --

-- 35 --

1.0 -- 4.3

V V

µA

V ns ns ns ns ns ns

To be continued

DS9603-00 November 2003www.richtek.com

Page 5

Preliminary

RT9603

Parameter Symbol

Output

Upper Drive Source R Upper Drive Sink R Lower Drive Source R Lower Drive Sink R

DRVH

DRVL

Test Conditions Min Typ Max Units

= 12V -- 2 --

VCC

= 12V = 12V = 12V

-- 2.8 --

-- 1.9 --

-- 1.6 --

Ω Ω Ω Ω

Note 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are

stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Note 2. Devices are ESD sensitive. Handling precaution recommended. The human body model is a 100pF capacitor discharged

through a 1.5kΩ resistor into each pin.

Note 3. The device is not guaranteed to function outside its operating conditions.

DS9603-00 November 2003 www.richtek.com

Page 6

RT9603

Applications Information

Preliminary

The RT9603 is designed to drive both high side and low side N-Channel MOSFET through externally input PWM control signal. It has power-on protection function which held DRVH and DRVL low before VCC up across the rising threshold voltage. After the initialization, the PWM signal takes the control. The rising PWM signal first forces the DRVL signal turns low then DRVH signal is allowed to go high just after a non-overlapping time to avoid shootthrough current. The falling of PWM signal first forces DRVH to go low. When DRVH and SW signal reach a predetermined low level, DRVL signal is allowed to turn high. The non-overlapping function is also presented between DRVH and DRVL signal transient.

The PWM signal is acted as "High" if above the rising threshold and acted as "Low" if below the falling threshold. Any signal level enters and remains within the shutdown window is considered as "tri-state", the output drivers are disabled and both MOSFET gates are pulled and held low. If left the PWM signal (IN) floating, the pin will be kept at 2.1V by the internal divider and provide the PWM controller with a recognizable level.

The RT9603 typically operates at frequency of 200kHz to 250kHz. It shall be noted that to place a 1N4148 or schottky diode between the VCC and BST pin as shown in the typical application circuit.

Driving Power MOSFETs

The DC input impedance of the power MOSFET is extremely high. When Vgs at 12V (or 5V), the gate draws the current only few nano-amperes. Thus once the gate has been driven up to "ON" level, the current could be negligible.

However, the capacitance at the gate to source terminal should be considered. It requires relatively large currents to drive the gate up and down 12V (or 5V) rapidly. It also required to switch drain current on and off with the required speed. The required gate drive currents are calculated as follows.

VIN

Cgd1

Vg1

Vg2

Igs1

Igd1

Ig1

VSW +12V

Cgs1

12V

Ig2

Cgd2

Igd2

Igs2

Cgs2

VOUT

GND

Figure 1. Equivalent Circuit and Associated Waveforms

In Figure 1, the current Ig1 and Ig2 are required to move the gate up to 12V. The operation consists of charging C

and Cgs. C

and C

gs1

are the capacitances from

gs2

gate to source of the high side and the low side power MOSFETs, respectively. In general data sheets, the C is referred as "C and C

are the capacitances from gate to drain of the

gd2

" which is the input capacitance. C

rss

gd1

high side and the low side power MOSFETs, respectively and referred to the data sheets as "C transfer capacitance. For example, t

and t

rss

" the reverse

are the rising time of the high side and the low side power MOSFETs respectively, the required current I

gs1

and I

are showed

gs2

below:

dVg1

gs1gs1

dVg2

gs2gs2

gs1

gs2

12C

(1)

(2)

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Page 7

Preliminary

lCC(4)

lCC (3)

dtt

RT9603

Before driving the gate of the high side MOSFET up to 12V (or 5V), the low side MOSFET has to be off; and the high side MOSFET is turned off before the low side is turned on. From Figure 1, the body diode "D2" had been turned on before high side MOSFETs turned on.

dV12V

==gd1g1gd1

Before the low side MOSFET is turned on, the C been charged to VIN. Thus, as C and g

is charged up to 12V, the required current is

gd2gd2gd2

dVVi12V

dtt

have

gd2

reverses its polarity

gd2

It is helpful to calculate these currents in a typical case. Assume a synchronous rectified buck converter, input voltage V is PHB83N03LT whose C t

= 14ns. The low side MOSFET is PHB95N03LT whose

iss

= 12V, Vg1 = Vg2 = 12V. The high side MOSFET

= 1660pF, C

= 2200pF, C

iss

= 500pF and t

rss

= 30ns, from the

= 380pF, and

equation (1) and (2) we can obtain

−

12101660

gs1 =

gs2 =

××

−

1014

−

12102200

××

−

1030

(5)(A) 1.428

(6)(A) 0.88

Layout Consideration

Figure 2 shows the schematic circuit of a two-phase synchronous buck converter to implement the RT9603. The converter operates from 5V to 12V of VIN.

BST

VCC

DRVH

RT9603

DRVL

PGND

C4 1uF

PWM

12V

VIN 12V

VCORE

1.2uH C1

1000uF

1500uF

2uH

1uF

PHB83N03LT

PHB95N03LT

Figure 2. Two-Phase Synch. Buck Converter Circuit

When layout the PC board, it should be very careful. The power-circuit section is the most critical one. If not configured properly, it will generate a large amount of EMI. The junction of Q1, Q2, L2 should be very close.

Next, the trace from DRVH, and DRVL should also be short to decrease the noise of the driver output signals. SW signals from the junction of the power MOSFET, carrying the large gate drive current pulses, should be as heavy as the gate drive trace. The bypass capacitor C4 should be connected to PGND directly. Furthermore, the bootstrap capacitors (CB) should always be placed as close to the pins of the IC as possible.

from equation. (3) and (4)

Select the Bootstrap Capacitor

Figure 3 shows part of the bootstrap circuit of RT9603.

−

1210 380

gs1 =

××

−

1014

(7)(A) 0.326

The V

(the voltage difference between BST and SW on

RT9603) provides a voltage to the gate of the high side power MOSFET. This supply needs to be ensured that

-12

gd2 =

1030

12)(1210500

+××

−

(8)0.4(A)

the total current required from the gate driving source is

the MOSFET can be driven. For this, the capacitance C has to be selected properly. It is determined by following constraints.

(9)1.745(A)0.326)(1.428III gd1gs1g1 =+=+=

(10)1.28(A)0.4)(0.88III gd2gs2g2 =+=+=

By a similar calculation, we can also get the sink current required from the turned off MOSFET.

DS9603-00 November 2003 www.richtek.com

Page 8

RT9603

Preliminary

VCC

1N4148

BST

DRVH SW

VCC

DRVL PGND

VIN

VCB

Figure 3. Part of Bootstrap Circuit of RT9603

In practice, a low value capacitor CB will lead the overcharging that could damage the IC. Therefore to minimize the risk of overcharging and reducing the ripple on VCB, the bootstrap capacitor should not be smaller than 0.1µF, and the larger the better. In general design, using 1µF can provide better performance. At least one low-ESR capacitor should be used to provide good local decoupling. Here, to adopt either a ceramic or tantalum capacitor is suitable.

Power Dissipation

For not exceeding the maximum allowable power dissipation to drive the IC beyond the maximum recommended operating junction temperature of 125°C, it is necessary to calculate power dissipation appropriately. This dissipation is a function of switching frequency and total gate charge of the selected MOSFET. Figure 4 shows the power dissipation test circuit. C

and CU are the DRVH and DRVL load capacitors, respectively. The bootstrap capacitor value is 0.01µF.

BST

PGND

CBST

DRVH

DRVL

1uF

2N7002

3nF

+12V

2N7002

C 3nF

+12V

1uF

PWM

1N4148

VCC

RT9603

Figure 5 shows the power dissipation of the RT9603 as a function of frequency and load capacitance. The value of the CU and CL are the same and the frequency is varied from 100kHz to 1MHz.

Power Dissipation vs. Frequency

1000

900 800 700 600 500 400 300 200

Power Dissipation (mW)

100

02004006008001000

CU=CL=3nF

CU=CL=2nF

CU=CL=1nF

Frequency (kHz)

Figure 5. Power Dissipation vs. Frequency

The operating junction temperature can be calculated from the power dissipation curves (Figure 5). Assume VCC=12V, operating frequency is 200kHz and the CU=CL=1nF which emulate the input capacitances of the high side and low side power MOSFETs. From Figure 5, the power dissipation is 100mW. For RT9603, the package thermal resistance θ

is 67° C/W, the operating

junction temperature is calculated as: T

= (67°C/W x 100mW) + 25°C = 31.7°C (11)

where the ambient temperature is 25°C. The method to improve the thermal transfer is to increase

the PC board copper area around the RT9603 firstly. Then, adding a ground pad under IC to transfer the heat to the peripheral of the board.

Figure 4. Test Circuit

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Page 9

Preliminary

Over-Voltage Protection Function at Power-On

Figure 6 shows the measured waveforms with the high side MOSFET directly shorted to 12V.

VCC

RT9603

DRVL

CORE

Figure 6. Waveforms at High Side MOSFET Shorted

Please note that the VCC trigger point to RT9603 is at 3V, and the clamped level on SW pin is at about 2.4V. Obviously since the SW pin voltage increases during initial start-up, the V

increases correspondingly, but

CORE

it would quickly drop-off followed by DRVL and VCC decreased.

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Page 10

RT9603

Outline Dimension

Preliminary

J B

Dimensions In Millimeters

Symbol

Min Max Min Max

A 4.801 5.004 0.189 0.197 B 3.810 3.988 0.150 0.157

Dimensions In Inches

C 1.346 1.753 0.053 0.069 D 0.330 0.508 0.013 0.020 F 1.194 1.346 0.047 0.053 H 0.178 0.254 0.007 0.010

I 0.102 0.254 0.004 0.010

J 5.791 6.198 0.228 0.244

M 0.406 1.270 0.016 0.050

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Headquarter 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611

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