Datasheet rt9259a Datasheets

RT9259A

12V Synchronous Buck PWM DC-DC and Linear Power
Controller

General Description

The RT9259A is a dual-channel DC/DC controller
specifically designed to deliver high quality power where
12V power source is available. This part consists of a
synchronous buck controller and a n LDO controller. The
synchronous buck controller integrates MOSFET drivers
that support 12V+12V bootstrapped voltage for high
efficiency power conversion. The bootstra p diode is built­in to simplify the circuit design and mini mize external part
count. The LDO controller drives an external N-MOSFET
for lower power requirement.

Other features include adjustable operation frequency,
internal soft start, under voltage protection, over current
protection and shut down function. With the above
functions, this part provides customers a compact, high
efficiency , well-protected a nd cost-effective solution. This
part comes to SOP-14 package.

Ordering Information

RT9259A

Package Type

S : SOP-14

Operating Temperature Range

P : Pb Free with Commercial Standard
G : Green (Halogen Free with Commer­ cial Standard)

Note :
RichTek Pb-free and Green products are :

`RoHS compliant and compatible with the current require­ ments of IPC/JEDEC J-STD-020.

`Suitable for use in SnPb or Pb-free soldering processes.
`100% matte tin (Sn) plating.

Features

zz

Single 12V Bias Supply

z

zz

zz

z Support Dual Channel Power Conversion

zz

`One Synchronous Rectified Buck PWM Controller
`One Linear Controller

zz

z Both Controllers Drive Low Cost N-Channel

zz

MOSFET s

zz

z Adjustable Frequency from 150kHz to 1MHz

zz

and Free-Run Frequency at 230kHz

zz

z Small External Component Count

zz

zz

z Output Voltage Regulation

zz

`PWM Controller :
`LDO Controller :

zz

z Two Internal V

zz

zz

z Adjustable External Compensation

zz

zz

z Linear Controller Drives N-Channel MOSFET Pass

zz

±±

±1% Accuracy

±±

±±

±2% Accuracy

±±

Power Support Lower to 0.8V

REF

Transistor

zz

z Fully-Adjustable Outputs

zz

zz

z Under V oltage Prote ction for Both Outputs

zz

zz

z Adjustable Over Current Protection

zz

zz

z RoHS Compliant and 100% Lead (Pb)-Free

zz

Applications

z Graphic Card GPU, Memory Core Power
z Graphic Card Interfa ce Power
z Motherboard, Des ktop and Servers Chipset a nd Memory

Core Power

z IA Equipments
z T elecomm Equipments
z High Power DC-DC Regulators

Pin Configurations

(TOP VIEW)

SOP-14

14
13
12
11
10

UGATE
PHASE
PGND
LGATE
OCSET

9

VREF
VCC12

8

BOOT

FB

2
3
4

5
6
7

RT_DIS

COMP

DRV

FBL

GND

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1

RT9259A

Typical Application Circuit

V

C

C

+

2

V

1

V

N

2

+

I

5

o

V

t

2

+

V

1

Q3

V

O

2

U

T

C

O

U

2

T

1
8
5

6

2
7

9

10

RT9259A

BOOT
VCC12

DRV

FBL

RT_DIS
GND

VREF
OCSET

R

UGATE

PHASE

LGATE

OCSET

PGND

FB

COMP

14

13

11

12

V

N

1

I

+

3

V

+

/

3

Q1

Q2

.

C

IN

L

O

U

T

1

+

V

/

1

5

V

2

V

O

U

T

1

C

O

U

T

4
3

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2

Functional Pin Description

RT9259A

BOOT (Pin 1)

Bootstrap supply for the upper gate driver. Connect the
bootstrap capacitor between BOOT pin and the PHASE
pin. The bootstra p capa citor provides the charge to turn on
the upper MOSFET .

RT_DIS (Pin 2)

Connect a resistor from RT_DIS to GND to set frequency .
In addition, if this pin is pulled down towards GND, it will
disable both regulator outputs until relea sed.

COMP (Pin 3)

Buck converter external compensation. This pin is used
to compensate the control loop of the buck converter.

FB (Pin 4)

Buck converter feedback voltage. This pin is the inverting
input of the PWM error a mplifier. FB senses the switcher
output through an external resistor divider network.

VREF (Pin 9)

0.8V reference voltage output.

OCSET (Pin 10)

Connecting a resistor (R

) from this pin to the source

OCSET

of the upper MOSFET and the drain of the lower MOSFET
sets the over-current trip point. R

, an internal 40μA

OCSET

current source, and the lower MOSFET on resistance,
R

, set the converter over-current trip point (I

DS(ON)

OCSET

according to the following Equation :

I

OCSET

=

R

DS(ON)

OCSET

0.4VR40uA

−×

MOSFET lower the of

LGA TE (Pin 11)

Lower gate driver output. Connect to the gate of the low­side power N-Cha nnel MOSFET . This pin is monitored by
the ada ptive shoot-through protection circuitry to determine
when the lower MOSFET ha s turn off.

)

DRV (Pin 5)

Connect this pin to the gate of an external MOSFET. This
pin provides the drive for the linear regulator’ s pass
MOSFET.

FBL (Pin 6)

Linear regulator feedback voltage. This pin is the inverting
input of the LDO error amplifier and protection monitor.
Connect this pin to an external resistor divider network of
the linear regulator.

GND (Pin 7)

Signal ground for the IC. All voltages levels are mea sured
with respect to this pin.

VCC12 (Pin 8)

Connect this pin to a well-decoupled 12V bia s supply . It is
also the positive supply for the lower gate driver , LGA TE.

PGND (Pin 12)

Power ground return for the lower gate driver .

PHASE (Pin 13)

Connect this pin to the source of the upper MOSFET and
the drain of the lower MOSFET. This pin is monitored by
the ada ptive shoot-through protection circuitry to determine
when the upper MOSFET ha s turned off.

UGA TE (Pin 14)

Upper gate driver output. Connect to gate of the high-side
power N-Cha nnel MOSFET. This pin is monitored by the
adaptive shoot-through protection circuitry to determine
when the upper MOSFET ha s turned off.

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RT9259A

Function Block Diagram

VCC12

VREF

FBL

DRV

RT_DIS

GND

REF_OUT

VCC12

Inhibit

0.8V

V

REF1

­+
+

Shutdown

Oscillator

Voltage

Reference

V

REF2

0.4V

FB

­+

­+

SSE

Bias

+
+

EA

-

COMP

On Reset

+

­PWM

Power

POR

Soft-Start

&

Fault Logic

SSE

Inhibit

Regulator

OC

Driver

Logic

5V

PH_M

5VDD

40uA

0.4V

+

-

-

1.5V

+

OCSET

BOOT
UGATE

PHASE

LGATE

PGND

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Absolute Maximum Ratings (Note 1)

RT9259A

z Supply Voltage, V
z PHASE to GND

-------------------------------------------------------------------------------------- 15V

CC

DC------------------------------------------------------------------------------------------------------------- −5V to 15V
< 200ns------------------------------------------------------------------------------------------------------ −10V to 30V

z BOOT to PHASE ------------------------------------------------------------------------------------------ 15V
z BOOT to GND

DC------------------------------------------------------------------------------------------------------------- −0.3V to VCC+15V
< 200ns------------------------------------------------------------------------------------------------------ −0.3V to 42V

z UGATE------------------------------------------------------------------------------------------------------- V
z LGATE ------------------------------------------------------------------------------------------------------- GND − 0.3V to V
z DRV ---------------------------------------------------------------------------------------------------------- GND − 0.3V to V
z Input, Output or I/O Voltage ----------------------------------------------------------------------------- GND − 0.3V to 7V
z Power Dissipation, P

@ T

D

= 25°C

A

PHASE

− 0.3V to V

SOP-14 ------------------------------------------------------------------------------------------------------ 1.000W

z Package Thermal Resistance (Note 4)

SOP-14, θJA------------------------------------------------------------------------------------------------- 100°C/W

z Junction T emperature------------------------------------------------------------------------------------- 150°C
z Lead T e mperature (Soldering, 10 sec.)--------------------------------------------------------------- 26 0°C
z Storage T emperature Range ---------------------------------------------------------------------------- −40°C to 150°C
z ESD Susceptibility (Note 2)

HBM (Human Body Mode) ------------------------------------------------------------------------------ 2kV
MM (Ma chine Mode)-------------------------------------------------------------------------------------- 200V

BOOT

+ 0.3V

CC

+ 0.3V

CC

+ 0.3V

Recommended Operating Conditions (Note 3)

z Supply Voltage, V
z Junction T emperature Range---------------------------------------------------------------------------- −40°C to 125°C
z Ambient T emperature Range---------------------------------------------------------------------------- −40°C to 85°C

-------------------------------------------------------------------------------------- 12V ± 10%

CC

Electrical Characteristics

(VCC = 12V, T

Supply Input
Power Supply Voltage VCC -- 12 15 V
Power On Reset V

Power On Reset Hysteresis V
Power Supply Current I
Oscillator

Free Running Frequency f
Ramp Amplitude -- 1.6 -- V

= 25°C unless otherwise specified)

A

Parameter Symbol Test Conditions Min Typ Max Units

VCCRTH
VCCHYS

VCC

OSC

VCC Rising 8.8 9.6 10.4 V

0.4 0.78 1.2 V

UGATE, LGATE Open -- 3 -- mA

R

= 110kΩ 250 300 350 kHz

RT

To be continued

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RT9259A

Parameter Symbol Test Conditions Min Typ Max Units

Reference Voltage

PWM Error Amplifier Reference V
Linear Driver Reference V
V

Buffer Source Current 5 -- -- mA

REF

0.792 0.8 0.808 V

REF1

0.784 0.8 0.816 V

REF2

Error Amplifier

DC Gain 70 88 -- dB
Gain-Bandwidth Product GBW
Slew Rate SR

C

LOAD

= 5pF

6 15 -- MHz
3 6 -- V/us

Gate Driver

Upper Drive Source R

Upper Drive Sink R
Lower Drive Source R
Lower Drive Sink R

UGATE

UGATE
LGATE
LGATE

V

BOOT

V

BOOT

V

UGATE

VCC – V
V

LGATE

− V

− V
= 1V -- 4 8 Ω

LGATE

= 1V -- 2 4 Ω

= 12V,

PHASE
UGATE

= 1V

-- 4 8 Ω

= 1V -- 4 6 Ω

Protection
Under Voltage Protection
Soft-Start Time Interval

V
T

UVP

SS

Over Current Threshold
RT_DIS Shutdown Threshold 0.35

0.36 0.4 0.45 V
2 3 4 ms
R

OCSET

= 20kΩ

--

−400

0.4

-- mV

-- V
Linear Regulator
Output High Voltage
Output Low Voltage
Source Current
Sink Current

Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for

stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.

Note 2. The device is not guaranteed to function outside its operating conditions.
Note 3. θ

Note 4. θ

is measured in the natural convection at TA = 25°C on a low effective thermal conductivity test board of

JA

JEDEC 51-3 thermal measurement standard.

is measured in the natural convection at TA = 25°C on a high effective 4-layers 2S2P thermal conductivity test board

JA

of JEDEC 51-7 thermal measurement standard.

V

DRV

V

DRV

I

DRVSR

I

DRVSC

9.5 10.3 -- V

-- 0.1 1 V
2 -- -- mA

0.5 -- -- mA

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Typical Operating Characteristics

RT9259A

(5V/Div)

(2V/Div)

No Load, Falling

V

OUT1

I

L

Dead Time

V

IN1

PHASE

Time (25ns/Div)

OCP

UGATE

LGATE

(5V/Div)

(10V/Div)

(10V/Div)

No Load, Rising

UGATE

PHASE

LGATE

Dead Time

V

IN1

Time (25ns/Div)

Power Off

No Load

UGATE

V

REF

LGATE

(10A/Div)

(20V/Div)

(10V/Div)

(500mV/Div)

(1V/Div)

Full Load

Time (2.5ms/Div)

Shut Down

Time (5μs/Div)

UGATE

LGATE

V

OUT1

RT_Dis

(0.5A/Div)

(200mV/Div)

(5V/Div)

(500mV/Div)

(10V/Div)

(500mV/Div)

No Load
V

IN1

RT_Dis

PHASE
V

OUT1

Time (5μs/Div)

Start Up

Time (1ms/Div)

I

L

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RT9259A

(2.5A/Div)

(500mV/Div)

(20V/Div)

I

LOAD

V

OUT1

UGATE

Start Up

Time (1ms/Div)

Transient Response

No Load

(500mV/Div)

(500mV/Div)

(100mV/Div)

I

= 20A

Load

RT_Dis

V

OUT1

Start Up

Time (1ms/Div)

Transient Response

V

OUT

(100mV/Div)

(10A/Div)

(2mV/Div)

(0.5A/Div)

V

OUT1

I

L

LDO

V

I

L

OUT2

V

= 12V, V

IN1

I

= 1A to 20A

LOAD1

Time (2.5μs/Div)

Transient Response

V

= 12V , V

IN2

I

= 1A to 100mA

LOAD

OUT1

OUT2

= 2V

= 2.5V

(20V/Div)

(10A/Div)

(10V/Div)
(20V/Div)

(500mV/Div)

(1V/Div)

V

IN1

I

LOAD1

= 12V, V

= 20A to 1A

OUT1

= 2V

Time (10μs/Div)

Under Voltage Protection

LDO

LGATE

UGATE

COMP

V

OUT2

UGATE

V

IN2

= 0V

I

L

Time (100μs/Div)

Time (10ms/Div)

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Application Information

RT9259A

Introduction

The RT9259A is a dual-channel DC/DC controller
specifically designed to deliver high quality power where
12V power source is available. This part consists of a
synchronous buck controller and a n LDO controller. The
synchronous buck controller integrates internal MOSFET
drivers that support 12V+12V bootstra pped voltage for high
efficiency power conversion. The bootstra p diode is built­in to simplify the circuit design and mini mize external part
count. The LDO controller drives an external N-MOSFET
for lower power requirement.

Internal 5VDD Regulator

It is highly recommended to power the RT9259A with well­decoupled 12V to VCC12 pin. VCC12 powers the RT9259A
control circuit, low side gate driver and bootstra p circuit for
high side gate driver. A bootstrap diode is embedded to
facilitates PCB design a nd reduce the total BOM cost. N o
external Schottky diode is required. The RT9259A
integrates MOSFET gate drives that are powered from the
VCC12 pin and support 12V + 12V driving capability.
Converters that consist of RT9259A feature high efficiency
without special consideration on the selection of
MOSFETs.

When let open, the free running frequency is 230kHz
typically . Figure 1 shows the operation frequency vs. R

RT

for quick reference.

1400

1200

1000

800

(kHz)

600

SW

f

400

200

0

10 100 1000

(kΩ)

RRT (kohm)

Figure 1. RT vs. fsw at Low Frequency

Shorting the RT_DIS pin to G ND with an external signal­level MOSFET shuts down the device. This allows flexible
power sequence control for specified application. The
RT_DIS pin threshold voltage is 0.4V typically.

An internal linear regulator regulates VCC12 input to a
5V DD voltage for internal control logic circuit. No external
bypass ca pa citor is required for filtering the 5V DD voltage.
This further facilitates PCB design and reduces the total
BOM cost.

Power On Reset

The RT9259A automatically initializes upon applying of

input power (at the VCC12) pin. The power on reset function

(POR) continually monitors the input bias supply voltage
at the VCC12 pin. The VCC12V POR level is typically

9.6V at VCC12V rising.

Frequency Setting and Shut Down

Connecting a resistor RRT from the RT_DIS pin to GND
sets the operation frequency . The relation can be roughly
expressed in the equation.

7700

OSC

kHz302f

+≅

(kHz)

R

RT

VIN1 Detection

The RT9259A continuously generates a 10kHz pulse train
with 1μs pulse width to turn on the upper MOSFET for
detecting the existence of VIN1 after VCC12V POR and
RT_DIS enabled a s shown in Figure 2. PHASE pin voltage
is monitored during the detection duration.

If the PHASE voltage crosses 1.5V four times, VIN1
existence is recognized and the RT9259A initiates its soft
start cycle as described in next section.

V

POR_H

IN1

PHASE_M

+

-

1.5V

PHASE

UGATE

1st 2nd 3rd4th

Internal Counter will count (V
four times (rising & falling) to recognize

V

is ready.

IN1

PHASE
waveform

PHASE

> 1.5V)

Figure 2

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9

RT9259A

μ

Soft Start for Synchronous Buck Converter

A built-in soft-start is used to prevent surge current from
power supply input during power on (referring to the
Functional Block Di agram). The error a mplifier EA is a three­input device. SSE or V

whichever is smaller dominates

REF1

the behavior non-inverting input. The internal soft start

voltage SSE linearly ramps up to about 4V after VIN1
existence is recognized with about 2ms delay . According,

the output voltage ramps up smoothly to its target level.
The rise time of output voltage is about 2ms as shown in
Figure 3. V
V

.

REF1

takes over the behavior EA when SSE >

REF1

SSE is also used for LDO soft start. LDO input voltage
VIN2 MUST be ready before SSE starts to ramp up.
Otherwise UVP function of LDO may be triggered and shut
down the RT9259A.

UGATE

(20V/Div)

FB

(500mV/Div)

V

OUT

(20V/Div)

LGATE

(10V/Div)

UGATE

(20V/Div)

V

Time (10ms/Div)

Figure 4. UVP triggered by FB

= 12V to 0V

IN1

V

IN2

= 0V

RT_DIS

(500mV/Div)

UGATE

(20V/Div)
V

OUT1

(500mV/Div)

LGATE

(10V/Div)

Time (1ms/Div)

Figure 3 : Start up by RT_DIS

Under Voltage Protection

The voltages at FB and FBL pin are monitored for under
voltage protection (UVP) after the soft start is completed.
UVP is triggered if one of the feedback voltages is under
(50% x V

) with a 30us delay. As shown in Figure 4,

REFX

the RT9259A PWM controller is shut down when VFB drops
lower than the UVP threshold. In Figure 5, the RT9259A
shuts down after 4 time UVP hiccups triggered by FBL.

COMP

(500mV/Div)

V

OUT1

(1V/Div)

Time (10ms/Div)

Figure 5. UVP hiccups triggered by FBL

Over Current Protection

The RT9259A senses the current flowing through lower
MOSFET for over current protection (OCP) by sensing the
PHASE pin voltage as shown in the Functional Block
Diagra m. A 40uA current source flows through the extern al
resistor R

to PHASE pin causes 0.8V voltage drop

OCSET

across the resistor. OCP is triggered if the voltage at
PHASE pin (drop of lower MOSFET VDS) is lower than −

0.4V when low side MOSFET conducting. Accordingly
inductor current threshold for OCP is a function of
conducting resistance of lower MOSFET R

DS(ON)

as :

0.4V-RA40

DS9259A-02 March 2007www.richtek.com

10

I

OCSET

×

=

OCSET

R

DS(ON)

RT9259A

If MOSFET with R

= 16mΩ is used, the OCP

DS(ON)

threshold current is about 25A. Once OCP is triggered,
the RT9259A enters hiccup mode and re-soft starts again.
The RT9259A shuts down after 4 time OCP hiccups.

Inductor Current

(20A/Div)

Time (2.5ms/Div)

Figure 6. Shorted then Start Up

I

L

(20A/Div)

A well-designed compensator regulates the output voltage
to the reference voltage V

with fast tra nsient response

REF

and good stability.
In order to achieve fast transient response and accurate

output regulation, an adequate compensator design is
necessary. The goal of the compensation network is to
provide adequate pha se margin (greater than 45 degrees)
and the highest 0dB crossing frequency. It is also
recommended to manipulate loop frequency response that
its gain crosses over 0dB at a slope of −20dB/dec.

V

IN

ΔV

OSC

OSC

Comparator

PWM

­+

COMP

Z

FB

EA

Driver

L

Driver

­+

REF

PHASE

C

Z

IN

OUT

ESR

V

OUT

LGATE

(5V/Div)

UGATE

(5V/Div)

Time (5μs/Div)

Figure 7. Shorted then Start Up (Extended Figure 3)

Feedback Compensation

The RT9259A is a voltage mode controller. The control
loop is a single voltage feedback path including a
compensator and modulator as shown Figure 8. The
modulator consists of the PWM comparator and power
stage. The PWM comparator compares error a mplifier EA
output (COMP) with oscillator (OSC) sawtooth wave to
provide a pulse-width modulated (PWM) with an a mplitude
of VIN at the PHASE node. The PWM wave is smoothed
by the output filter L

OUT

and C

. The output voltage (V

OUT

OUT

is sensed and fed to the inverting input of the error a mplifier .

C1

COMP

EA

C2

­+

R2

REF

FB

Z

FB

C3

R1

Z

IN

R3

V

OUT

Figure 8. Closed Loop

1) Modulator Frequency Equations

The modulator trans fer function is the small-signal transfer
function of V

OUT/VCOMP

(output voltage over the error
amplifier output. This transfer function is dominated by a
DC gain, a double pole, and a zero a s shown in Figure 10.
The DC gain of the modulator is the input voltage (VIN)
divided by the peak to peak oscillator voltage V
output LC filter introduces a double pole, 40dB/decade
gain slope above its corner resonant frequency , a nd a total
phase lag of 180 degrees. The resona nt frequency of the

)

LC filter expressed a s :

OSC

. The

f

=

LC

π

1

CL2

×

OUTOUT

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11

RT9259A

The ESR zero is contributed by the ESR associ ated with
the output capacitance. Note that this requires that the
output capa citor should have enough ESR to satisfy stability
requirements. The ESR zero of the output capacitor
expressed as f ollows :

f

=

ESR

2) Compensation Frequency Equations

The compensation network consists of the error a mplifier
and the impedance networks ZC and ZF as shown in
Figure 9.

f

=

Z1

π

f

=

P1

π

Figure 10 shows the DC-DC converter's gain vs. frequency .
The compensation gain uses external impeda nce networks
ZC and ZF to provide a stable, high bandwidth loop. High
crossover frequency is desirable for fa st transient respon se,
but often jeopardize the system stability . In order to cancel
one of the LC filter poles, place the zero before the LC
filter resona nt frequency. In the experience, pla ce the zero
at 75% LC filter resona nt frequency. Crossover frequency
should be higher than the ESR zero but less than 1/5 of
the switching frequency . The second pole is placed at hal f
the switching frequency .

1

ESRC2

OUT

R2

C1

EA

××

Z

F

Z

C2

FB

­+

V

REF

R1

R

F

π

COMP

Figure 9. Compensation Loop

1

C2 x R2 x 2

1

x R2 x 2

C2 x C1
C2C1

+

C

V

OUT

80

80

Gain

Loop Gain

Frequency

Frequency (Hz)

Compensation

Gain

60

40

40

20

0

0

Modulator

Gain (d B)

-20

-40

-40

-60

-60

10Hz 100Hz 1.0KHz 10KHz 100KHz 1.0MHz

10 100 1k 10k 100k 1M

vdb(vo) vdb(comp2) vdb(lo)

Figure 10. Bode Plot

Thermal Considerations

For continuous operation, do not exceed absolute
maximum operation junction temperature 125°C. The
maximum power dissipation depends on the thermal
resistance of IC package, PCB layout, the rate of
surroundings airflow and temperature difference between
junction to ambient. The maximum power dissipation ca n
be calculated by following formula :

P
Where T

temperature 125°C, T

θ

= ( T

D(MAX)

J(MAX)

is the junction to ambient thermal resistance.

JA

− TA ) / θ

J(MAX)

JA

is the maximum operation junction

is the ambient temperature a nd the

A

The junction to ambient thermal resistance θJA is layout
dependent. For SOP-14 packages, the thermal re sistance

θ

is 100°C/W on the standard JEDEC 51-7 four-layers

JA

thermal test board.
The maximum power dissipation at TA = 25°C can be

calculated by following formula :
P

= ( 125°C − 25°C) / 100°C/W = 1.000 W for

D(MAX)

SOP-14 packages
The maximum power dissipation depends on operating

a mbient temperature for fixed T

θ

. For RT9259A packages, the Figure 11 of derating

JA

and thermal resistance

J(MAX)

curves allows the designer to see the effect of rising
a mbient temperature on the maximum power allowed.

12

DS9259A-02 March 2007www.richtek.com

RT9259A

1.2

1

0.8

0.6

0.4

0.2

Maximum Power Dissipation (W)

0

0 25 50 75 100 125

SOP-14

Ambient Temperat ure

4-Layers PCB

(°C)

Figure 11. Derating Curves for R T9259A Pa ckages

PCB Layout Considerations

MOSFET s switch very fa st and ef ficiently . The speed with
which the current transitions from one device to another
causes voltage spikes across the interconnecting
impedances and parasitic circuit elements. The voltage
spikes can degrade eff iciency and radiate noise, that results
in over-voltage stress on devices. Careful component
placement layout a nd printed circuit design ca n minimize
the voltage spikes induced in the converter. Con sider , a s
an example, the turn-off transition of the upper MOSFET
prior to turn-off, the upper MOSFET was carrying the full
load current. During turn-off, current stops flowing in the
upper MOSFET and is picked up by the low side MOSFET
or schottky diode. Any inducta nce in the switched current
path generates a large voltage spike during the switching
interval. Careful component selections, layout of the critical
components, and use shorter a nd wider PCB tra ces help
in minimizing the magnitude of voltage spikes.

There are two sets of critical components in a DC-DC
converter using the RT9259A. The switching power
components are most critical because they switch large
amounts of energy, and as such, they tend to generate
equally large amounts of noise. The critical small signal
components are those connected to sensitive nodes or
those supplying critical bypass current.

The power components and the PWM controller should
be placed firstly . Pla ce the input ca pacitors, especi ally the
high-frequency ceramic de coupling capa citors, close to the
power switches. Place the output inductor and output
capa citors between the MOSFET s and the loa d. Also locate
the PWM controller near by MOSFET s. A multi-layer printed
circuit board is recommended. Figure 12 shows the
connections of the critical components in the converter.
Note that the capacitors CIN and C

each of them

OUT

represents numerous physical ca pa citors.
Use a dedicated grounding plane a nd use vias to ground

all critical components to this layer. Apply another solid
layer as a power pla ne and cut this plane into smaller isla nds
of common voltage levels. The power plane should support
the input power and output power nodes. Use copper filled
polygons on the top and bottom circuit layers for the PHASE
node, but it is not necessary to oversize this particular
island. Since the PHASE node is subjected to very high
dV/dt voltages, the stray capacitance formed between
these islands a nd the surrounding circuitry will tend to couple
switching noise. Use the remaining printed circuit layers
for small signal routing. The PCB tra ces between the PWM
controller and the gate of MOSFET and also the traces
connecting source of MOSFETs should be sized to carry
2A pea k currents.

5V/12V

GND

IQ1

Q1

+

Q2

LGATE

UGATE

IQ2

VCC

IL

GND

RT9259A

FB

V

OUT

+

+

LOAD

Figure 12. The connections of the critical components in

the converter

DS9259A-02 March 2007 www.richtek.com

13

RT9259A

Outline Dimension

A

J

I

Dimensions In Millimeters Dimensions In Inches

Symbol

Min Max Min Max

A 8.534 8.738 0.336 0.344
B 3.810 3.988 0.150 0.157

B

F

C

D

H

M

C 1.346 1.753 0.053 0.069
D 0.330 0.508 0.013 0.020

F 1.194 1.346 0.047 0.053

H 0.178 0.254 0.007 0.010

I 0.102 0.254 0.004 0.010

J 5.791 6.198 0.228 0.244

M 0.406 1.270 0.016 0.050

Richtek Technology Corporation

Headquarter
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: [phone] Fax: [phone]

14–Lead SOP Plastic Package

Richtek Technology Corporation

Ta ipei Office (Marketing)
8F, No. 137, Lane 235, Paochiao Road, Hsintien City
Taipei County, Taiwan, R.O.C.
Tel: [phone] Fax: [phone]
Email: [e-mail]

14

DS9259A-02 March 2007www.richtek.com