Page 1
RT9245
Multi-Phase PWM Controller for CPU Core Power Supply
General Description
RT9245 is a multi-pha se buck DC/DC controller integrated
with all control functions for Intel
VRD10.X-complia nt. The RT9245 could be operated with
2, 3 or 4 buck switching stages operating in interleaved
phase set automatically. The multiphase architecture
provides high output current while maintaining low power
dissipation on power devices and low stress on in put and
output cap acitors. The high equivalent operating frequency
also reduces the component dimension and the output
voltage ripple in load tra nsient.
RT9245 implements both voltage and current loops to
achieve good regulation, response and power stage
thermal balance.
RT9245 a pplies the DCR sensing technology newly . The
RT9245 extracts the ESR of output inductor as sense
component to deliver a precise load line regulation and
good thermal balance for next generation processor
a pplication.
®
GHz CPU which is
Features
zz
Multi-Phase Power Conversion with Automatic
z
zz
Phase Selection
zz
z 6-bits VRD10.x DAC Output with Active Droop
zz
Compensation for Fast Load Transient
zz
z Smooth V
zz
zz
z Power Stage Thermal Balance by DCR Current
zz
Transition at VID Jump
CORE
Sense
zz
z Hiccup Mode Over-Current Protection
zz
zz
z Programmable Switching Frequency (50kHz to
zz
400kHz per Phase), Under-V oltage Lockout a nd SoftStart
zz
z High Ripple Frequency Times Channel Number
zz
zz
z 28-TSSOP Package
zz
zz
z RoHS Compliant and 100% Lead (Pb)-Free
zz
Applications
®
z Intel
z Low Output V oltage, High Current DC-DC Converters
z V oltage Regulator Modules
Processors V oltage Regulator : VR D10.x
Current sense setting, droop tuning, V
initial offset
CORE
and over current protection are independent on
compensation circuit of voltage loop. The feature greatly
facilitates the flexibility of CPU power supply design a nd
tuning. The DAC output of R T9245 supports VRD10.x with
6-bit VID input, precise offset value & smooth V
transient at VID jump. The IC monitors the V
CORE
CORE
voltage
for PGOOD and over-voltage protection. Soft-start, overcurrent protection and progra mmable under-voltage lockout
are also provided to assure the safety of microprocessor
and power system. The R T9245 comes to a small footprint
package TSSOP-28.
Ordering Information
RT9245
Package Type
C : TSSOP-28
Operating Temperature Range
P : Pb Free with Commercial Standard
G : Green (Halogen Free with Commer cial Standard)
Pin Configurations
(TOP VIEW)
VID4
VID3
VID2
VID1
VID0
VID125
SGND
FB
COMP
PGOOD
DVD
SS
RT
VOSS
2
3
4
524
6
7
821
9
10
11 18
12
13
14
TSSOP-28
Note :
RichTek Pb-free and Green products are :
`RoHS compliant and compatible with the current require ments of IPC/JEDEC J-STD-020.
`Suitable for use in SnPb or Pb-free soldering processes.
`100% matte tin (Sn) plating.
28
27
26
25
23
22
20
19
17
16
15
VCC
PWM1
PWM2
PWM3
PWM4
CSP4
CSP2
CSP3
CSP1
GND
ADJ
NC
CSN
IMAX
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Page 2
RT9245
Typical Application Circuit
F
u
0
5
0
1
0
1
C
+
F
u
0
4
+
0
1
0
C
1
N
I
V
2
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H
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C
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T
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2
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3
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4
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6
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6
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7
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1
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1
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k
6
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k
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9
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C
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C
5
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0
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9
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R
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7
6
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4
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4
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W
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4
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4
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6
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4
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2
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1
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k
5
1
3
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R
1
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9
5
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k
C
2
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C
5
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C
N
0
2
R
6
7
1
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S
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D
2
3
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1
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V
T
2
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A
k
1
8
2
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R
6
5
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R
k
6
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R
DS9245-06 March 2007www.richtek.com
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Page 3
Functional Pin Description
RT9245
VID4 (Pin 1), VID3 (Pin 2), VID2 (Pin 3), VID1 (Pin 4),
VID0 (Pin 5) & VID125 (Pin 6)
DAC voltage identification inputs for VRD10.x. These pins
are internally pulled to 1.2V if left open.
SGND (Pin 7)
V
differential sense negative input.
CORE
FB (Pin 8)
Inverting input of the internal error a mplifier.
COMP (Pin 9)
Output of the error amplifier and input of the PWM
comparator.
PGOOD (Pin 10)
Power good open-drain output.
D V D (Pin 1 1)
Programma ble power UVLO detection input. Tri p threshold
= 1.2V at V
SS (Pin 12)
Connect this SS pin to GND with a capacitor to set the
soft-start time interval. Pulling this pin below 1V (ramp
valley of sawtooth wave in pulse width modulator) would
make all PWMs low , turn on low side MOSFET s, a nd turn
off high side MOSFETs.
RT (Pin 13)
Switching frequency setting. Connect this pin to GN D with
a resistor to set the frequency.
DVD
rising.
IMAX (Pin 15)
Program mable over currert setting.
CSN (Pin 16)
Current sense negative input of all channels.
NC (Pin 17)
No Connection.
ADJ (Pin 18)
Current sense output for a ctive droop a djust. Conne ct a
resistor from this pin to GND to set the load droop.
GND (Pin 19)
Ground for the IC.
CSP1 (Pin 20), CSP2 (Pin 22), CSP3 (Pin 21) & CSP4
(Pin 23)
Current sense positive inputs for individual converter
channel current sense.
PWM1 (Pin 27), PWM2 (Pin 26), PWM3 (Pin 25) &
PWM4 (Pin 24)
PWM outputs for ea ch driven channel. Connect these pins
to the PWM input of the MOSFET driver. For systems
which use 3 channels, connect PWM4 high. T wo cha nnel
systems connect PWM3 high.
VCC (Pin 28)
IC power supply . Conne ct this pin to a 5V supply.
VOSS (Pin 14)
V
initial value offset. Connect this pin to GND with a
CORE
resistor to set the negative offset value. Connect this pin
to VCC to set positive offset value.
DS9245-06 March 2007 www.richtek.com
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Page 4
RT9245
Function Block Diagram
PWM1
& Driver
PWM Logic
INH
-
+
Oscillator&Sawtooth
PGOOD VCC DVD RT
+
+
Power On Reset
PWM2
PWM Logic
INH
+
PWMCP
INH
& Driver
-
PWM3
& Driver
PWM Logic
INH
+
PWMCP
+
+
PWM4
& Driver
PWM Logic
INH
-
+
+
-
+
PWMCP
PWMCP
+
+
Phase Control
CSP1
CSP2
MUX
Current
Correction
+
+
-
CSN
CSP3
CSP4
+
-
MUX
SUM/M
+
+
-
-
+
GAP
Amplifier
-
GND
ADJSSCOMPFB
-
IMAX
OCP
VID3
VID4
Setting
DAC
VID2
VID1
VID0
VID125
-
+
Point
OVP Trip
-
+
SS
Control
Point
PG Trip
DAC + Droop
-
Error
+
Amplifier
Offset Currrent
Source/Sink
VOSS
DS9245-06 March 2007www.richtek.com
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Page 5
Table 1. Output Voltage Program
RT9245
Pin Name
VID4 VID3 VID2 VID1 VID0 VID125
1 1 1 1 1 X No CPU
0 1 0 1 0 0 0.8375V
0 1 0 0 1 1 0.850V
0 1 0 0 1 0 0.8625V
0 1 0 0 0 1 0.875V
0 1 0 0 0 0 0.8875V
0 0 1 1 1 1 0.900V
0 0 1 1 1 0 0.9125V
0 0 1 1 0 1 0.925V
0 0 1 1 0 0 0.9375V
0 0 1 0 1 1 0.950V
0 0 1 0 1 0 0.9625V
0 0 1 0 0 1 0.975V
0 0 1 0 0 0 0.9875V
Nominal Output Voltage DACOUT
0 0 0 1 1 1 1.000V
0 0 0 1 1 0 1.0125V
0 0 0 1 0 1 1.025V
0 0 0 1 0 0 1.0375V
0 0 0 0 1 1 1.050V
0 0 0 0 1 0 1.0625V
0 0 0 0 0 1 1.075V
0 0 0 0 0 0 1.0875V
1 1 1 1 0 1 1.100V
1 1 1 1 0 0 1.1125V
1 1 1 0 1 1 1.125V
1 1 1 0 1 0 1.1375V
1 1 1 0 0 1 1.150V
1 1 1 0 0 0 1.1625V
1 1 0 1 1 1 1.175V
1 1 0 1 1 0 1.1875V
1 1 0 1 0 1 1.200V
1 1 0 1 0 0 1.2125V
To be continued
DS9245-06 March 2007 www.richtek.com
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Page 6
RT9245
Table 1. Output Voltage Program
Pin Name
VID4 VID3 VID2 VID1 VID0 VID125
1 1 0 0 1 1 1.225V
1 1 0 0 1 0 1.2375V
1 1 0 0 0 1 1.250V
1 1 0 0 0 0 1.2625V
1 0 1 1 1 1 1.275V
1 0 1 1 1 0 1.2875V
1 0 1 1 0 1 1.300V
1 0 1 1 0 0 1.3125V
1 0 1 0 1 1 1.325V
1 0 1 0 1 0 1.3375V
1 0 1 0 0 1 1.350V
1 0 1 0 0 0 1.3625V
1 0 0 1 1 1 1.375V
1 0 0 1 1 0 1.3875V
Nominal Output Voltage DACOUT
1 0 0 1 0 1 1.400V
1 0 0 1 0 0 1.4125V
1 0 0 0 1 1 1.425V
1 0 0 0 1 0 1.4375V
1 0 0 0 0 1 1.450V
1 0 0 0 0 0 1.4625V
0 1 1 1 1 1 1.475V
0 1 1 1 1 0 1.4875V
0 1 1 1 0 1 1.500V
0 1 1 1 0 0 1.5125V
0 1 1 0 1 1 1.525V
0 1 1 0 1 0 1.5375V
0 1 1 0 0 1 1.550V
0 1 1 0 0 0 1.5625V
0 1 0 1 1 1 1.575V
0 1 0 1 1 0 1.5875V
0 1 0 1 0 1 1.600V
Note: (1) 0 : Connected to GND
(2) 1 : Open
(3) X : Don
6
't Care
DS9245-06 March 2007www.richtek.com
Page 7
Absolute Maximum Ratings (Note 1)
RT9245
z Supply Voltage, V
z Input, Output or I/O V oltage---------------------------------------------------------------------------------- GND − 0.3V to V
z Package Thermal Resista nce
------------------------------------------------------------------------------------------- 7V
CC
TSSOP-28, θJA-------------------------------------------------------------------------------------------------- 100°C/W
z Junction T emperature------------------------------------------------------------------------------------------ 150°C
z Lead T e mperature (Soldering, 10 sec.)-------------------------------------------------------------------- 260°C
z Storage T emperature Range --------------------------------------------------------------------------------- −65°C to 150°C
z ESD Susceptibility (Note 2)
HBM (Human Body Mode) ----------------------------------------------------------------------------------- 2kV
MM (Ma chine Mode)------------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions (Note 3)
z Supply Voltage, V
z Ambient T emperature Range--------------------------------------------------------------------------------- 0°C to 70°C
z Junction T emperature Range--------------------------------------------------------------------------------- 0°C to 125°C
------------------------------------------------------------------------------------------- 5V ± 10%
CC
Electrical Characteristics
(V
= 5V , TA = 25°C, unless otherwise specified)
CC
Parameter Symbol Test Conditions Min Typ Max Units
V
Supply Current
CC
Nominal Supply Current
Power-On Reset
I
CC
PWM 1,2,3,4 Open
--
12 16 mA
CC
+ 0.3V
POR Threshold
Hysteresis
V
Threshold
DVD
Trip (Low to High)
Hysteresis
V
CCRTH
V
CCHYS
V
DVDTP
V
DVDHYS
VCC Rising
0.2 0.5 -- V
Enable 1.1 1.2 1.3 V
-- 50 -- mV
4.0 4.2 4.5 V
Oscillator
Free Running Frequency
Frequency Adjustable Range
Ramp Amplitude
Ramp Valley
f
R
OSC
f
OSC_ADJ
ΔV
V
RV
RRT = 32kΩ
OSC
= 32kΩ
RT
50 -- 400 kHz
0.7 1.0 -- V
170 200 230 kHz
-- 1.9 -- V
Maximum On-Time of Each Channel 62 66 75 %
RT Pin Voltage
V
R
RT
= 32kΩ
RT
1.4 1.60 1.8 V
Reference and DAC
DACOUT Vol ta g e Accuracy
DAC (VID0-VID125) Input Low
DAC (VID0-VID125) Input High
DAC (VID0-VID125) Bias Current
VOSS Pin Voltage
ΔV
DAC
V
ILDAC
V
IHDAC
I
BIAS_DAC
R
V
VOSS
V
≥ 1V
DAC
< 1V
V
DAC
-- -- 0.4 V
0.8 -- -- V
25 50 75
= 100kΩ
VOSS
−1
−10
1.5 1.65 1.8 V
-- +1 %
-- +10 mV
μA
To be continued
DS9245-06 March 2007 www.richtek.com
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Page 8
RT9245
Parameter Symbol Test Conditions Min Typ Max Units
Error Amplifier
DC Gain -- 85 -- dB
Gain-Bandwidth Product GBW -- 10 -- MHz
Slew Rate SR COMP = 10pF -- 3 --
V/μs
Current Sense GM Amplifier
CSN Full Scale Source Current
I
ISPFSS
CSN Current for OCP 150 -- --
100 -- --
μA
μA
Protection
SS Current
Over-Voltage Trip (VSEN/DACOUT)
IMAX Voltage
V
I
SS
Δ
OVT
R
V
IMAX
SS
IMAX
= 1V
130 140 150 %
= 32k
8 13 18
μA
1.4 1.60 1.8 V
Power Good
Output Low Voltage
Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are
for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may remain possibility to affect device reliability.
Note 2. Devices are ESD sensitive. Handling precaution recommended.
Note 3. The device is not guaranteed to function outside its operating conditions.
V
PGOODL
IPG = 4mA
-- -- 0.2 V
DS9245-06 March 2007www.richtek.com
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Page 9
Typical Operating Characteristics
RT9245
300
250
200
150
Voltage (mV)
100
50
0
0 25 50 75 100 125 150
Vx ( mV)
GM3
300
250
200
GM1
300
V
ADJ
250
200
V
P
V
N
150
Voltage (mV)
100
50
0
0 25 50 75 100 125 150
Vx ( mV)
V
ADJ
V
P
V
N
GM4
GM2
V
ADJ
300
250
200
V
ADJ
150
Voltage (mV)
100
50
0
0 25 50 75 100 125 150
Vx ( m V)
Adjustable Frequency
450
400
350
300
250
(kHz)
200
OSC
F
150
100
50
0
0 25 50 75 100 125 150 175
RRT (k⎠)
(kΩ)
V
P
V
N
150
Voltage (mV)
100
50
0
0 25 50 75 100 125 150
V
P
V
N
Vx ( m V)
Linearity of each PWM
3
2.8
2.6
2.4
2.2
(V)
2
COMP
1.8
V
1.6
1.4
1.2
1
0 500 1000 1500 2000 2500 3000 3500
Pul se Width (ns)
f
OSC
PWM2
PWM3
PWM1
PWM4
= 200k
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Page 10
RT9245
V
CORE
Phase
I
OUT
V
ADJ
PWM
V
SS
V
ADJ
I
L
Load Transient Response
CH1: (500mV/Div)
CH2: (10V/Div)
CH3: (50A/Div)
CH4: (100mV/Div)
Time (5μs/Div)
Relationship Between Inductor
Current and V
CH1:(5V/Div)
CH2:(5V/Div)
ADJ
CH3:(50mV/Div)
CH4:(20A/Div)
V
CORE
Phase1
Phase2
Phase3
PWM
UGATE
LGATE
V
COMP
Load Transient Response
CH1: (500mV/Div), CH2: (10V/Div)
CH3: (10V/Div), CH4: (10V/Div)
Time (5μs/Div)
Power-Off @ I
= 60A
OUT
CH1:(5V/Div)
CH2:(20V/Div)
CH3:(10V/Div)
CH4:(1V/Div)
10
V
SS
PWM
UGATE
LGATE
Power-On @ I
CH1:(5V/Div)
CH2:(5V/Div)
CH3:(20V/Div)
CH4:(10V/Div)
Time (25ms/Div)
= 60A
OUT
Time (10ms/Div)
Time (10μs/Div)
DS9245-06 March 2007www.richtek.com
Page 11
Application Information
RT9245 is a multi-pha se DC/DC controller that precisely
regulates CPU core voltage and bala nces the current of
different power channels. The converter consisting of
RT9245 and its companion MOSFET driver RT9603/
RT9603A provides high quality CPUpower and all
protection functions to meet the requirement of modern
VRM.
RT9245
Load Droop
The sensed power channel current signals regulate the
reference of DAC to form an output voltage droop
proportional to the load current. The droop or so call “active
voltage positioning” can reduce the output voltage ripple
at load tran sient and the LC filter size.
Fault Detection
Voltage Control
RT9245 senses the CPU VCORE by SGND pin to sense
the return of CPU to minimize the voltage drop on PCB
trace at heavy load. OVP is sensed at FB pin. The internal
high accura cy VID DAC provides the reference voltage fo r
VRD10.X compliance. Control loop consists of error
amplifier, multi-phase pulse width modulator, driver and
power components. As conventional voltage mode PWM
controller, the output voltage is locked at the VREF of
error amplif ier a nd the error sign al is used as the control
signal of pulse width modulator. The PWM signals of
different channels are generated by comparison of EA
output and split-phase sawtooth wave. Power stage
trans forms VIN to output by PWM signal on-time ratio.
Current Balance
RT9245 senses the inductor current via inductor's DCR
for channel current balance and droop tuning. The
differential sensing GM a mplif ier converts the voltage on
the sense component (can be a sense resistor or the
DCR of the inductor) to current signal into internal balance
circuit.
The current balance circuit sums a nd averages the current
signals and then produces the bala ncing signals injected
to pulse width modulator. If the current of some power
channel is larger than average, the balancing signal
reduces that channels pulse width to keep current bala nce.
The use of single GM a mplifier vi a time sharing technique
to sense all inductor currents can reduce the of fset errors
and linearity variation between GMs. Thus it can greatly
improve signal processing especially when dealing with
such small signal a s voltage drop a cross DCR.
The chip detects FB for over voltage and power good
detection. The “hiccup mode” operation of over current
protection is adopted to reduce the short circuit current.
The in-rush current at the start up is suppressed by the
soft start circuit through clamping the pulse width and
output voltage.
Phase Setting and Converter Start Up
RT9245 interfac es with companion MOSFET drivers (like
RT9603, RT9602 series) for correct converter initialization.
The tri-state PWM output (high, low and high impeda nce)
senses its interface voltage when IC POR a cts (both VCC
and D V D trip). The channel is ena bled if the pin voltage is
1.2V less than VCC. Tie the PWM to VCC and the
corresponding current sense pins to GND or left float if
the channel is unused. For example, for 3-Channel
a pplication, connect PWM4 high.
Current Sensing Setting
RT9245 senses the current flowing through inductor via
its DCR for cha nnel current balance a nd droop tuning. The
differential sensing GM a mplifier converts the voltage on
the sense component (can be a sense resistor or the
DCR of the inductor) to current signal into internal circuit
(see Figure 1).
L
DCR
GMx
L
R
+
-
R
CSN
V
I IDCR VCR
XLC
C
=×=×=
R
CSN
DCR
C
I
x
Figure 1. Current Sense Circuit
DS9245-06 March 2007 www.richtek.com
11
Page 12
RT9245
Figure 2 is the test circuit for GM. We apply test signal at
GM inputs and observe its signal process output at ADJ
pin. Figure 3 shows the variation of signal processing of
all channels. We observe zero offsets and good linearity
between phases.
GMx
I
x
L
V
+
V
-
ESR
CSP
CSN
R
CSN
1k
DCR
V
X
Figure 2. The T est Circuit of G M
GM
300
250
200
(mV)
150
ADJ
V
100
50
0
0 25 50 75 100 125 150
Vx ( m V)
Figure 3. The Linearity of GMx
Figure 4 shows the time sharing technique of GM amplifier .
W e apply test signal at pha se 4 a nd observe the waveforms
at both pins of GM amplifier. The waveforms show time
sharing mechanism and the perfomance of GM to hold
both input pins equal when the shared time is on.
Time Sharing of GM
CH1:(2V/Div)
CH2:(50mV/Div)
CH3:(50mV/Div)
PWM3
V
CSP4
V
CSP4
V
CSN
and
V
CSN
Time (1μs/Div)
Figure 4
Over Current Protection
RT9245 uses an external resistor R
to set a
IMAX
programmable over current trip point. OCP comparator
compares each inductor current with this reference current.
RT9245 uses hiccup mode to eliminate fault detection of
OCP or reduce output current when output is shorted to
ground.
L
×⇔×
R
+
-
DCRI
COMMON
1/3 I
1/2 I
X
IMAX
V
1 ×
IMAX
R
2
IMAX
1
3
OCP Comparator
Figure 5. Over Current Comparator
Over Current Protection
CH1:(5V/Div)
CH2:(5V/Div)
PWM
12
V
SS
Time (25ms/Div)
Figure 6. The Over Current Protection in the soft start
interval
DS9245-06 March 2007www.richtek.com
Page 13
RT9245
Over Current Protection
CH1:(5V/Div)
CH2:(5V/Div)
PWM
V
SS
Time (25ms/Div)
Figure 7. Over Current Protection at steady state
Current Ratio Setting
Thus if
Then
V ××
C
L
DCR
=
R2
+
R2R1
C(R1//R2)
×=
IDCR
L
With internal current balance function, this phase would
share (R1+R2)/R2 times current than other phases.
Figure 9 &10 show different settings for the power stages.
Figure 1 1 shows the performance of current ratio compared
with conventional current balance function in Figure 12.
Figure 9. GM4 Setting for current ratio function
Figure 8. Application circuit f or current ratio setting
For some case with preferable current ratio instead of
current balance, the corresponding technique is provided.
Due to different physical environment of ea ch channel, it
is necessary to slightly adjust current loading between
channels. Figure 8 shows the a pplication circuit of GM f or
current ratio requirement. Applying KVL along L+DCR
branch a nd R1+C//R2 branch :
dI
L
L
dt
dV
CR
1
VFor
+=
dt
R2
=
C
+
V
(RIDCR
1L
R
RR
+
21C
V
R
2
RR
21
dV
C
2
C
×
C
dt
V)
++=×+
C
C
IDCR
L
Look for its corresponding conditions :
dI
L
L
dt
L
Let
DCR
L
C(R1//R2)
×=
dI
DCRC(R1//R2)IDCR
L
dt
IDCR
×+×××=×+
L
Figure 10. GM1~3 Setting f or current ratio function
35
30
25
20
(A)
L
I
15
10
5
0
0 153045607590
Current R atio Function
I
(A)
OUT
I
L4
I
L3
I
L2
I
L1
Figure 1 1
DS9245-06 March 2007 www.richtek.com
13
Page 14
RT9245
30
I
L3
I
25
20
15
(A)
L
I
10
5
0
0 20406080100
I
(A)
OUT
L4
I
L2
Figure 12
Current Balance Function
GMx
Ix
L
ESR
V
CSP
+
V
CSN
-
R
CSN2
R
DCR
C
CSN1
Assume the negative inductor valley current is −5A at no
load, then for
R
= 330Ω, R
CSN1
I
L1
1.3V 5A 1m
R330
CSN2
R
CSN2
Choose R
−×Ω
≥
≤ 85.8kΩ
CSN2
= 160Ω, V
ADJ
Ω
= 82kΩ
OUT
= 1.300
Load Line without dead zone at light loads
1.31
1.3
1.29
1.28
(V)
1.27
CORE
V
1.26
1.25
1.24
1.23
0 5 10 15 20 25
I
(A)
OUT
R
R
CSN2
CSN2
open
= 82k
Figure 14
Figure13. Application circuit of GM
For load line design, with a pplication circuit in Figure 13,
it can eliminate the dead zone of load line at light loads.
V
CSP
= V
+IL x DCR
OUT
if GM holds input voltages equal, then
V
For the lack of sinking capability of GM, R
= V
CSP
I
X
=+
=+ +
CSN
V
=+
RR
CSN2 CSN1
VIDCR
OUT L
V
OUT
RR R
CSN2 CSN2 CSN1
IDCR
CSN
+×
RR
CSN2 CSN1
×
L
IDCR
×
L
IDCRIDCR
××
LL
should be
CSN2
small enough to compensate the negative inductor valley
current especially at light loads.
V
RR
I DCR
CSN
CSN2 CSN1
×
L
≥
VID on the Fly
With external pull up resistors tied to VID pins, RT9245
converters different VID codes from CPU into output
voltage. Figure 12 and Figure 13 show the waveforms of
VID on the fly function.
VID on the Fly (Falling)
PWM
V
CORE
V
FB
CH3:(500mV/Div)
CH4:(1V/Div)
VID125
CH1:(5V/Div)
CH2:(500mV/Div)
V
= 1.500, I
DAC
OUT
= 5A
Time (25μs/Div)
Figure 15
14
DS9245-06 March 2007www.richtek.com
Page 15
RT9245
PWM
V
CORE
V
FB
VID125
VID on the Fly (Rising)
CH3:(500mV/Div)
CH4:(1V/Div)
V
= 1.500, I
DAC
RB1
= 5A
OUT
Time (25μs/Div)
Figure 16
1/4 I
VOSS
-
EA
+
CH1:(5V/Div)
CH2:(500mV/Div)
Voltage Offset Function
1.284
1.282
1.28
1.278
(V)
1.276
CORE
V
1.274
1.272
1.27
1.268
50 60 70 80 90 100 110
R
(kٛ)
(kΩ)
OSS
Figure 18
PGOOD Waveform
CH1:(500mV/Div)
CH2:(5V/Div)
CH3:(5V/Div)
V
DAC-VADJ
Figure 17
Output V oltage Offset Function
To meet Intel's requirement of initial offset of load line,
RT9245 provides progra mmable initial offset function. With
an external resistor R
to set offset current I
and voltage source at V
VOSS
. One quart of I
VOSS
flows through
VOSS
OSS
pin
RB1. Error amplif ier would hold the inverting pin equal to
V
DAC-VADJ
V
DAL
. Thus output voltage is subtracted from
− V
for a consta nt offset voltage.
ADJ
PGOOD Function
T o indicate the condition of multipha se converter , RT9245
provides PGOOD sign al through an open drain connection.
The waveforms of PGOOD function are shown in Figure
15.
V
CORE
PGOOD
V
SS
Time (10ms/Div)
Figure 19
VDD
R
PGOOD
V
PGOOD
Figure 20. PGOOD Test Circuit
DS9245-06 March 2007 www.richtek.com
15
Page 16
RT9245
Error Amplifier Characteristic
For fast response of converter to meet stringent output
current transient response, R T9245 provides large slew
rate capa bility and high gain-bandwidth perf ormance.
EA Falling Slew Rate
V
FB
V
COMP
CH1:(500mV/Div)
CH2:(2V/Div)
Time (250ns/Div)
Figure 21. EA Rising T ra nsient with 10pF Loa ding; Slew
Rate=10V/us
EA Rising Slew Rate
V
FB
V
COMP
Time (250ns/Div)
CH1:(500mV/Div)
CH2:(2V/Div)
Figure 22. EA Falling T ra nsient with 10pF Loading;
Slew Rate=8V/us
4.7k
4.7k
B
-
EA
+
V
REF
A
0dB
180°
Figure 23. Gain-Ba ndwidth Mea surement by signal A
divided by signal B
Figure 24. EA Frequency Response with closed loop gain set at 0db to observe gain-ba ndwidth product; -3dB at
10.86MHz
DS9245-06 March 2007www.richtek.com
16
Page 17
RT9245
Design Procedure Suggestion
a.Output filter pole and zero (Inductor, output capacitor
value & ESR).
b.Error amplifier compensation & sawtooth wave amp-
litude (compensation network).
c.Kelvin sense for VCORE.
Current Loop Setting
a.GM amplifier S/H current (current sense component
DCR, CSN pin external resistor value).
b.Over-current protection trip point (R
IMAX
resistor).
VRM Load Line Setting
a.Droop amplitude (ADJ pin resistor).
b.No load offset (R
CSN2
)
c.DAC offset voltage setting (VOSS pin & compen- sation
network resistor RB1).
Power Sequence & SS
D VD pin external resistor and SS pin ca p a citor .
1. Compensation Setting
a. Modulator Gain, Pole a nd Zero:
From the following formula:
Modulator Gain =VIN/V
where V
: ramp a mplitude of saw-tooth wave
RAMP
=12/2.4=5 (i.e 14dB)
RAMP
LC Filter Pole = = 1.45kHz and
ESR Zero =3.98kHz
b. EA Compensation Network:
Select R1 = 4.7k, R2 = 15k, C1 = 12nF, C2 = 68pF and
use the Type 2 compensation scheme shown in Figure
25. By calculation, the FZ = 0.88kHz, FP = 322kHz and
Middle Band Gain is 3.19 (i.e 10.07dB).
C2 68pF
C1
RB2
15k
RB1
4.7k
12nF
-
EA
+
PCB Layout
a.Kelvin sense for current sense GM a mplifier input.
b.Refer to layout guide for other items.
Voltage Loop Setting
Design Example
Given:
Apply for four pha se converter
VIN = 12V
V
= 1.5V
CORE
I
LOAD (MAX)
V
DROOP
= 100A
= 100mV at full load (1mΩ Load Line)
OCP trip point set at 40A for ea ch cha nnel (S/H)
DCR = 1mΩ of inductor at 25°C
L = 1.5μH
C
= 8000μF with 5mΩ equivalent ESR.
OUT
Figure 25. T ype 2 compensation network of EA
The bode plot of EA compensation is shown as Figure 26.
The bode plot of power stage is shown as Figure 27. The
total loop gain is in Figure 28.
3. Over-Current Protection Setting
Consider the temperature coefficient of copper
3900ppm/°C,
×
1
2
1
2
Let R
V
IMAX
R
IMAX
1.690V
R
IMAX
= 14kΩ
IMAX
1
3
3
×⇔×
R
1
×⇔×
DCRI
L
COMMON
1.39m40A
330
Ω×
Ω
4. Soft-Start Capacitor Selection
For most application cases, 0.1μF is a good engineering
value.
DS9245-06 March 2007 www.richtek.com
17
Page 18
RT9245
0dB
-180°
0dB
-180°
Figure 26. The Frequency Response of the Compensator Network
18
Figure 27. The Frequency Response of Power Stage
DS9245-06 March 2007www.richtek.com
Page 19
0dB
-180°
RT9245
Figure 28. The Loop Gain of Converter
Layout Guide
Place the high-power switching components first, a nd separate them from sensitive nodes.
1. Most critical path: the current sense circuit is the most sensitive part of the converter. The current sense
resistors tied to CSP1,2,3,4 and CSN should be located not more than 0.5 inch from the IC and away from
the noise switching nodes. The PCB trace of sense nodes should be parallel and as short as possible.
Kelvin connection of the sense component (additional sense resistor or Inductor DCR) ensures the accurate
stable current sensing.
Keep well Kelvin sense to ensure the stable operation!
2. Switching ripple current path:
a. Input ca pa citor to high side MOSFET.
b. Low side MOSFET to output ca pa citor.
c. The return path of input and output ca p a citor .
d. Separate the power and signal GND.
e. The switching nodes (the connection node of high/low side MOSFET a nd inductor) is the most noisy points.
Keep them away from sensitive small-signal node.
f. Reduce parasitic R, L by minimum length, enough copper thickness a nd avoiding of vi a.
3. MOSFET driver should be closed to MOSFET .
4. The compensation, bypass a nd other function setting components should be ne ar the IC and away from the noisy
power path.
DS9245-06 March 2007 www.richtek.com
19
Page 20
RT9245
L2
L1
V
OUT
C
OUT
R
L
SW1
V
IN
R
IN
C
V
IN
SW2
Figure 29. Power Stage Ripple Current Path
+12V
0.1uF
VCC
PVCC
IN
BST
DRVH
SW
RT9603
DRVL
GND
Locate near MOSFETs
Next to IC
C
BOOT
C
IN
+12V or +5V
L
O1
V
CORE
C
OUT
Kelvin
Sense
For Thermal Couple
Figure 30. Layout Consideration
R
CSN
PWM
RT
VOSS
SGND
CSN
CSPx
ADJ
COMP
RT9245
GND
VCC
FB
R
R
C
BP
C
C
C
FB
+5V
IN
Next to IC
Locate next
to FB Pin
20
DS9245-06 March 2007www.richtek.com
Page 21
η
Test Conditions :
V
: 12V
IN
RT9245
Figure 31. Layout of power stage
V
: 1.300V
OUT
F
: 200kHz
SW
I
: 80A
OUT
Phase Number : 4 Pha ses
U-MOSFET : IR3707 x 1 (9.5mΩ x 9.6nC)
L-MOSFET : IR81 13 x 2 (6.0mΩ x 22nC)
L : 1.5uH
DCR : 1m
C
: 1000uF x 8
IN
C
: 1000uF x 8
OUT
Snubber : 2R2+3.3nF
Air Speed : Using MAGIC MGA8012HS FAN with 5V DC drive.
P1 P1 P1 P1 P2 P2 P2 P2
Driver M1 M2 M3 Driver M4 M5 M6
55°C 58°C 58°C 56°C 56°C 60°C 60°C 60°C
P3 P3 P3 P3 P4 P4 P4 P4
Driver M7 M8 M9 Driver M10 M11 M12
55°C 64°C 64°C 65°C 59°C 69°C 66°C 61°C
Note: VIN= 10.835V; I
DS9245-06 March 2007 www.richtek.com
= 10.6A; V
IN
= 1.2127V; I
OUT
= 80A; =84.47%
OUT
21
Page 22
RT9245
Outline Dimension
D
L
E
A
b
E1
e
A2
A1
Dimensions In M illimeters Dimensio ns In Inches
Symbol
Min Max Min Max
A 0.850 1.200 0.033 0.047
A1 0.050 0.152 0.002 0.006
A2 0.800 1.050 0.031 0.041
b 0.178 0.305 0.007 0.012
D 9.601 9.804 0.378 0.386
e 0.650 0.026
E 6.300 6.500 0.248 0.256
E1 4.293 4.496 0.169 0.177
L 0.450 0.762 0.018 0.030
Richtek Technology Corporation
Headquarter
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
28-Lead TSSOP Plastic Package
Richtek Technology Corporation
Taipei Office (Marketing)
8F, No. 137, Lane 235, Paochiao Road, Hsintien City
Taipei County, Taiwan, R.O.C.
Tel: (8862)89191466 Fax: (8862)89191465
Email: [email protected]
22
DS9245-06 March 2007www.richtek.com
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