Datasheet rt9232b Datasheets

RT9232B

Programmable Frequency Synchronous Buck PWM Controller

General Description

The RT9232B is a single-phase synchronous buck PWM
DC-DC converter controller designed to drive two
N- MOSFET s. It provides a highly accurate, progra mmable
output voltage precisely regulated to low voltage
requirement with an internal 0.8V ± 1% reference.

The

RT9232B uses an external compensated, single

feedback loop voltage mode PWM control for fa st tran sient
response. An oscillator with Programmable frequency
(50kHz to 800kHz) reduces the external inductor and
cap acitor component size f or saving PCB board area.

The RT9232B provides fast tra n sient response to satisfy
high current output applications (up to 25A) while
minimizing external components. It is suitable for high­performance gra phic processors, DDR a nd VTT power .

The RT9232B integrates complete protect functions such

a s Soft Start, Output Enable, UVLO(under-voltage lockout)
and OCP into a small 14-pin pa ckage.

Applications

 System (Graphic, MB) with 12V Power.
 Graphic Cards (AGP 8X, 4X, PCI Express*16) :

`High-Current f or High-Performance Gra phic Processors
(GPU, VPU)
`Middle Current for High-Perf ormance Graphic Memory
Power (DDR, D DR II)
`Low Current with Sink Ca pacity for High-Perf ormance
Gra phic Memory Power (DDR/VTT)

 3.3V to 12V Input DC-DC Regulators
 Low V oltage Distributed Power Supplies

Pin Configurations

(TOP VIEW)

RT

OCSET

SS

COMP

FB
EN

GND

2
3
4
5
6
7

14
13
12
11
10

VCC
PVCC
LGATE
PGND
BOOT

9

UGATE

8

PHASE

Features



Single IC Supply Voltage : 12V







 Single phase DC/DC Buck Converter with



`High Output Current (up to 25A )
`Low Output Voltage (down to 0.8V )
`High Input Voltage (up to 12V )



 Operate from 12V, 5V or 3.3V Input



 0.8V ± 1% Internal Reference



 Adaptive Non-Overlapping Gate Drivers





 Integrated High-Current, HV Gate Drivers





 External Programmable Soft Start





 External Programmable Frequency



(Range : 50kHz to 800kHz, 200kHz Free Run )



 Provide Over Current Protection by Sensing



MOSFET R



 On/Off Control by Enable Pin





 Drives T wo N-MOSFET





 Full 0 to 100% Duty Cycle





 Fast T ran sient Respon se





 Voltage Mode PWM Control with External



DS(ON)

Feedback Loop Compensation



 RoHS Compliant and 100% Lead (Pb)-Free



Ordering Information

RT9232B

Package Type
S : SOP-14

Operating Temperature Range
P : Pb Free with Commercial Standard
G : Green (Halogen Free with Commer­ cial Standard)

Note :
RichTek Pb-free and Green products are :

`RoHS compliant and compatible with the current require­ ments of IPC/JEDEC J-STD-020.

`Suitable for use in SnPb or Pb-free soldering processes.
`100% matte tin (Sn) plating.

SOP-14

DS9232B-03 March 2007 www.richtek.com

1

RT9232B

Typical Application Circuit

V

CC

R1

C1

C2

C

SS

2.2

0.22uF

0.1uF

R2

51k

14

13

3
1

6
7
4

VCC

PVCC

SS
RT

EN
GND
COMP

RT9232B

C11

BOOT

OCSET

UGATE

PHASE

LGATE

PGND

33pF

0.22uF

V

CC

R3

10k

1N4148

10
2

9

8

12
11

5

FB

D1

R4

3.01k

C3

1nF

R5

0

C4

0.1uF

R6

0

IPD06N03LA

R9

Q1
IPD09N03LA

Q2

1k

R7

2.2
1nF

2.2uH

C7

L2

C5

0.1uF

+

CE3

2200uF

1uH

+

C6

10uF

+

CE4

510uF

V

IN

3.3V - 12V

L1

22uF

CE0

+

C8

470uF

+

CE1
1000uF

10uF

C9

C10

0.1uF

+

CE2

1000uF

V

OUT

C12

10nF

R8

15k

R10
562

C13

10nF

R11

1k

Functional Pin Description

Pin No. Pin Name Pin Function

1 RT Oscillator Frequency Setting
2 OCSET Set Over Current Protection Triggering Level
3 SS Soft Start Time Interval Setting
4 COMP Feedback Compensation
5 FB Voltage Feedback
6 EN Chip Enable (Active High)
7 GND IC Signal Reference Ground
8 PHASE Return Path for Upper MOSFET

9 UGATE Upper MOSFET Gate Drive
10 BOOT Input Supply for Upper Gate Drive
11 PGND Power Ground
12 LGATE Lower MOSFET Gate Drive
13 PVCC Input Supply for Lower Gate Drive
14 VCC Internal IC Supply (12V Bias)

2

DS9232B-03 March 2007www.richtek.com

Function Block Diagram

VCC

RT9232B

EN

10uA

SS

+

-

UV

Oscillator

RT

+
+

-

FB

COMP

0.8V

Reference

0.6V

+

EA

­+

Operation

Startup

RT9232B initializes automatically after receiving both V
and VIN power. Special power-on sequence is not
necessary. The Power-On Reset (POR) function

continually monitors input supply voltages and enable
voltage. POR function monitors IC power via VCC pin a nd
external MOSFET power via OCSET pin. Voltage on
OCSET pin is a fixed voltage drop less than VIN. When
voltages on VCC, OCSET, and EN pins exceed their
thresholds, POR function initializes soft-start operation.

POR inhibits driver operation while EN pin pulls low.
Tra nsitioning EN pin high after in put supply voltages ready
initializes soft-start operation.

Soft-Start

After POR function relea ses soft-start operation, an internal
10uA current source charges a n external ca pacitor on SS
pin (Css) to 5V . Soft-start function clamps both COMP &
FB pins to SS pin voltage & a fixed voltage drop less tha n
SS pin voltage respectively. Thus upper MOSFET turns
on at a limited duty and output current overshoot ca n be
reduced. This method provides a rapid and controlled
output voltage rise.

CC

Power-On

Reset (POR)

POR

Soft Start

and

Fault Logic

PWM

­+

200uA

INHIBIT

Driver Logic

OCSET

BOOT
UGATE

PHASE

PVCC
LGATE
PGND
GND

OCP

The OCP function monitors output current by using upper
MOSFET R

. The OCP function cycles soft-start

DS(ON)

function in a hiccup mode. Overcurrent triggering level
can be arbitrarily set by adjusting R

. An Internal 200μA

OCSET

current sink makes a voltage drop across R
VIN. When V

is lower than V

PHASE

, OCP function

OCSET

initializes soft-start cycles. The soft-start function
discharges CSS with 10μA current sink a nd disable PWM
function. Then soft-start function recharges Css and PWM
operation resumes. The soft-start hiccup restarts after
SS voltage fully charges to 4V if the output short event
still remains. The converter is shutdown permanently after
3 times hiccup and only restarting supply voltages can
enable the converter. The OCP funcion will be triggered
a s inductor current rea ch :

I=

L(MAX)

IR

×

OCSET OCSET

R

DS(ON)

OCSET

from

DS9232B-03 March 2007 www.richtek.com

3

RT9232B

T o prevent OC f orm tripping in normal operation, R

OCSET

must be carefully chosen with :

1. Maximum R

2. MInimum I

3. I

L(MAX)

> I

OUT(MAX)

OCSET

at highest junction temperature

DS(ON)

from specification table

+ ΔIL /2

ΔIL = inductor ripple current

Under Voltage Protection

The under voltage protection function protects the converter
from an shorted output by detecting the voltage on FB pin
to monitor the output voltage. The UVP function cycles
soft-start function in a hiccup mode. When output voltage
lower than 75% of designated voltage, UVP function
initializes soft-start cycles. The soft-start function
discharges Css with 10μA current sink a nd disable PWM
operation. Then soft-start function recharges Css and
PWM operation resumes. The soft-start hiccup restarts
after SS voltage fully charges to 4V if the output short
event still remains. The converter is shutdown permanently
after 3 times hiccup and only restarting supply voltages
can ena ble the converter.

DS9232B-03 March 2007www.richtek.com

4

Absolute Maximum Ratings (Note 1)

RT9232B

 Supply Input Voltage, V
 PHASE to GND

, PVCC--------------------------------------------------------------------------- 15V

CC

DC------------------------------------------------------------------------------------------------------------------- −5V to 15V
< 200ns------------------------------------------------------------------------------------------------------------ −10V to 30V

 BOOT to PHASE ------------------------------------------------------------------------------------------------ 15V
 BOOT to GND

DC------------------------------------------------------------------------------------------------------------------- −0.3V to VCC+15V
< 200ns------------------------------------------------------------------------------------------------------------ −0.3V to 42V

 SS, FB, COMP, RT --------------------------------------------------------------------------------------------- 6V
 Input, Output or I/O Voltage----------------------------------------------------------------------------------- GND−0.3V to V
 Pack age Thermal Resista nce (Note 4)

CC

SOP-14, θJA----------------------------------------------------------------------------------------------------- 100°C/W

 Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------- 260°C
 Junction T e mperature ------------------------------------------------------------------------------------------ 150°C
 Storage Temperature Range---------------------------------------------------------------------------------- −65°C to 150°C
 ESD Susceptibility (Note 2)
HBM (Huma n Body Mode) ----------------------------------------------------------------------------------- 2kV
MM (Machine Mode)------------------------------------------------------------------------------------------- 150V

Recommended Operating Conditions (Note 3)

+ 0.3V

 Supply Input Voltage, V
 Supply Voltage to Drain of Upper MOSFETs, V
 Ambient Temperature Range --------------------------------------------------------------------------------- −40°C to 85°C
 Junction Temperature Range --------------------------------------------------------------------------------- −40°C to 125°C

------------------------------------------------------------------------------------ 12V ±10%

CC

------------------------------------------------------- 3.3V, 5V to 12V ±10%

IN

Electrical Characteristics

(V

= 12V, T

CC

VCC Supply Current

Nominal Supply Current

Power-On Reset (POR)

VCC Rising Threshold
Power On Reset Hysteresis

OCSET Rising Threshold for start up
Enable Input Threshold (ON)
Enable Input Threshold (OFF)

Oscillator

Free Running Frequency

= 25°C, Unless otherwise specified.)

A

Parameter Symbol

EN = VCC, UGATE, LGATE open

I

CC

RT9232B

V

V

OCSET_ON

V
V

f

OSC

CC_ON

EN_ON
EN,_OFF

V

V

-- 1.5 2 V

V

V

170 200 230 kHz

Test Conditions

= 4.5V

OCSET

= 4.5V

OCSET

= 4.5V

OCSET

= 4.5V

OCSET

Variation 6k < (RT to GND) < 200k

Min Typ. Max Units

-- 3 -- mA

8.4 -- 10.4 V

0.3 0.7 --

-- -- 2 V

0.8 -- -- V

−20

-- 20 %

V

Ramp Amplitude

ΔV

OSC

-- 1.5 --

V

P-P

To be continued

DS9232B-03 March 2007 www.richtek.com

5

RT9232B

Parameter Symbol Test Conditions Min Typ Max Units

Reference

Error Amplifier Reference Vo ltage

V

REF

Error Amplifier

DC gain -- 88 -- dB
Gain-Bandwidth product GBW -- 15 -- MHz
Slew Rate SR COMP=10pF -- 6 -- V/μs

Soft Start

External SS Source Current ISS 7 10 -- μA

PWM Controller Gate Driver

0.792 0.8 0.808 V

Upper Drive Source R

Upper Drive Sink R
Lower Drive Source R
Lower Drive Sink R

UG_SC

UG_SK
LG_SC
LG_SK

V

BOOT − PHASE

V

BOOT − UGATE

V

BOOT − PHASE

V

PVCC − LGATE

V

LGATE

= 1V -- 1.7 -- Ω

= 12V
= 1V

-- 5.2 -- Ω

= 1V -- 2.7 -- Ω

= 1V -- 3.5 -- Ω

Driving Capability

Upper Drive Source I
Upper Drive Sink I
Lower Drive Source I
Lower Drive Sink I

UG_SC
UG_SK
LG_SC
LG_SK

V

BOOT − UGATE

V

UGATE − PHASE

V

PVCC − LGATE

V

LGATE − GND

= 12V -- 1.0 -- A

= 12V -- 2.0 -- A

= 12V -- 1.6 -- A

= 12V -- 3.2 -- A

Protection

OCSET Current Source I

OCSET

V

OCSET

= 11.5V 170 200 230 μA
Under-Voltage Protection FB Falling 0.5 0.6 0.7 V
Under-Voltage Protection Delay -- 30 -- μs

Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for

stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.

Note 2. Devices are ESD sensitive. Handling precaution recommended.
Note 3. The device is not guaranteed to function outside its operating conditions.
Note 4. θ

JEDEC 51-3 thermal measurement standard.

is measured in the natural convection at T

JA

= 25°C on a low effective thermal conductivity test board of

A

DS9232B-03 March 2007www.richtek.com

6

Typical Operating Characteristics

RT9232B

100

Eff iciency (%)

SS

(2V/Div)

V

OUT

(2V/Div)

Efficiency vs. Output Current

V

= 1.6V

OUT

f = 300kHz

90

80

70

60

50

VIN = 3.3V

VIN = 5V

V

= 12V

IN

0 5 10 15 20 25

Output Cu rrent (A)

Power On

10000

1000

(kΩ)

RT

100

R

SS

(2V/Div)

V

OUT

(2V/Div)

RRT vs. Oscillator Frequency

Pull high to VCC 12

Pull down to GND

10

1

0 100 200 300 400 500 600 700

Frequ ency (kHz )

Power On

EN

(10V/Div)

COMP

(500mV/Div)

SS

(2V/Div)

V

OUT

(2V/Div)

EN

(10V/Div)

I

L

(1A/Div)

Time (10ms/Div)

Power On

Time (25ms/Div)

EN

(10V/Div)

I

L

(1A/Div)

UGATE

(20V/Div)

LGATE

(10V/Div)

V

OUT

(500mV/Div)

I

L

(10A/Div)

Time (10ms/Div)

Power Off

Time (10μs/Div)

DS9232B-03 March 2007 www.richtek.com

7

RT9232B

UGATE

(20V/Div)

LGATE

(10V/Div)

V

OUT

(100mV/Div)

I

L

(10A/Div)

UGATE

(20V/Div)

V

OUT

(500mV/Div)

LGATE

(10V/Div)

Load Transient Response

Time (25μs/Div)

Load Transient Response

Falling

UGATE

(20V/Div)

LGATE

(10V/Div)

V

OUT

(100mV/Div)

I

L

(10A/Div)

UGATE

(5V/Div)

V

OUT

(500mV/Div)

SS

(5V/Div)

Load Transient Response

Rising

Time (5μs/Div)

OCP

I

L

(20A/Div)

(5/Div)

Falling

UGATE

UGATE−PHASE

LGATE

Time (1ms/Div)

Dead Time

PHASE

Time (25ns/Div)

I

L

(10A/Div)

(5/Div)

Time (25ms/Div)

Dead Time

Rising

UGATE

PHASE

UGATE−PHASE

LGATE

Time (25ns/Div)

DS9232B-03 March 2007www.richtek.com

8

FSW vs. Temperature

230
220
210
200

(kHz)

190

SW

180

F

170
160
150

-40 -20 0 20 40 60 80 100 120 140

Temperature

(°C)

(V)

REF

V

RT9232B

V

vs. Temperature

0.804

0.803

0.802

0.801

0.800

0.799

0.798

0.797

0.796

0.795

0.794

-40 -20 0 20 40 60 80 100 120 140

REF

Temperature

(°C)

DS9232B-03 March 2007 www.richtek.com

9

RT9232B

Application Information

The RT9232B is a single-pha se synchronous buck PWM
DC-DC controller designed to drive two N-MOSFETs. It
provides a highly accurate, progra mmable output voltage
precisely regulated to low voltage requirement with an
internal 0.8V ±1% reference.

whichever is smaller dominates the behavior of the devices.
During T0~T1, since SS is smaller than the sawtooth valley ,
the PWM comparator outputs low no matter what the
COMP voltage is.

T1~T2

Initialization

The RT9232B automatically initiates its softstart cycle
only after VCC and VIN power and chip enabling signals
are ready . There is no special power-on sequence should
be took care especially while implement the chip in. The
internal Power-On Reset (POR) logic continually monitors
the voltage level of input power and ena bling pin; in which
the IC supply power is monitored via VCC pin and input
power VIN is via OCSET pin. An internal current source
with driving capability of 200uA causes a fixed voltage
drop across the resistor connecting VIN to OCSET pin.
The RT9232B internal logic will deem the input voltage
ready once the voltage of OCSET pin is high than 1.5V.
The preferred VIN ready level could be set by selecting an
appropri ate resistor R

IN_READY

<

SENSE

R

OCSET

−

μ

A200

as :

1.5VV

Ω

Once all voltages of VCC, OCSET, and EN pins ramp
higher than the internal specific thresholds. The intern al
POR logic will initialize the softstart operation then.
Moreover, the POR inhibits driver operation while pulling
the EN pin low . T ransitioning EN pin high after input supply
voltages ready to initialize soft-start operation.

SSE ramps up a nd domin ates the behavior of EA during
T1~T2. EA regulates COMP appropriately so that FB
ramps up along the SSE curve. The output voltage ramps
up accordingly . Thus upper MOSFET turns on at a limited
duty and output current overshoot ca n be reduced.

It is noted that lower MOSFET keeps off before the upper
MOSFET starts switching. This method provides smooth
start up when there is residual voltage on output ca pacitors.
The output voltage delay time and ramp up time are
calculated as Equation (1) a nd (2) respectively .

C0.8V

×

SS

(1)

T0T1

=−

T1T2

=−

μ

×

μ

FB

0.8V

(s)

A10

C0.8V

SS

(2)

(s)

A10

SSE SS

COMP

EA

PWM

Soft-Start

The behavior of RT9232B Soft-Start can be simply
described a s shown in Figure.1 below; and the Soft-Start
can be sliced to several time-fra mes with specific operation
respectively .

T0~T1

The RT9232B initiates the softstart cycle as shown in
Figure 1 when POR function is OK. An internal 10uA current
source charges an external capa citor on SS pin (Css) to
5V . The softstart function produces a n SSE signal that is
equal to SS−0.8V. Error Amplifier (EA) and PWM
comparator are triple-input devices. The non-inverting input

10

5V

0.8V

T0 T1 T2

Figure 1. Ti ming diagra m of softstart

SS

SSE

COMP
FB

DS9232B-03 March 2007www.richtek.com

RT9232B

Switching Frequency Setting

The default switching frequency is 200kHz when RT pin
left open. A resistor connected (RRT) from RT pin to ground
increa ses the switching frequency as Equation (3).

6

102.9

(3) (RRT to GND)

OSC

200kHzf

×

+=

RT

kHz

)(R

Ω

Conversely , connecting a pull-up resistor (RRT) from RT pin
reduces the switching frequency according to Equation (4)

6

1033

(4) (RRT to VCC = 12V)

OSC

200kHzf

×

−=

RT

kHz

)(R

Ω

Under Voltage Protection

The under voltage protection is enabled when the RT9232B
is activated and SS voltage is higher than 4V. The UVP
function is specified for protecting the converter from a n
instant output short circuit during normal operation. The
RT9232B continuously monitors the output voltage by
detecting the voltage on FB pin. The UVP function is
triggered and initiates the hiccup cycles when output
voltage lower than 75% of designated voltage with a 30us
delay .

Hiccup cycle turns off both upper and lower MOSFET first.
An internal 10uA current sink discharges the softstart
cap acitor CSS. SS pin voltage ramps down linearly . When
SS pin voltage touches 0V, hiccup cycle releases and
normal softstart cycle takes over. When SS voltage is
higher than 4V, the UVP function is enabled again. The
hiccup cycle restarts if the output short event still remains.
The converter is shutdown permanently after 3 time s hiccup
and only restarting supply voltages can enable the
converter.

Note that triggering the POR function or EN will reset the
hiccup counter. Ma ke sure that VCC, EN a nd OCSET pin
voltages are higher than their respective trip level when
output short circuit occurs or the UVP function may not
latch up the converter causing permanent da mage to the
converter.

Component Selection

Components should be appropri ately selected to ensure
stable operation, fa st tran sient response, high efficiency ,
minimum BOM cost and maximum reliability.

Output Inductor Selection

The selection of output inductor is based on the
considerations of efficiency, output power a nd operating
frequency . For a synchronous buck converter , the ri pple
current of inductor (ΔIL) can be calculated a s f ollows :

V

)V(VI

(5)

×−=Δ

OUTINL

OUT

OSCIN

LfV

××

Generally , an inductor that limits the ripple current between
20% and 50% of output current is a ppropriate. Ma ke sure
that the output inductor could handle the maximum output
current and would not saturate over the operation
temperature range.

Output Capacitor Selection

The output cap acitors determine the output ripple voltage
(ΔV

) and the initial voltage drop after a high slew-rate

OUT

load tran sient. The selection of output ca pacitor depends
on the output ripple requirement. The output ripple voltage
is described as Equation (6).

V

2

OSC

OUT

××

CLf

OUT

D)(1

−

(6)

ESRIV

LOUT

1

×+×Δ=Δ

8

For electrolytic capacitor application, typically 90~95%
of the output voltage ripple is contributed by the ESR of
output cap acitors. Paralleling lower ESR cera mic cap acitor
with the bulk capacitors could dramatically reduce the
equivalent ESR and consequently the ri pple voltage.

Input Capacitor Selection

Use mixed types of input bypass capacitors to control
the input voltage ripple and switching voltage spike a cross
the MOSFETs. The buck converter draws pulsewise
current from the input ca pacitor during the on time of upper
MOSFET . The RMS value of ri pple current flowing through
the input ca p acitor is described as :

(7)

OUTIN(RMS)

D)(1DII

−××=

The input bulk capacitor must be cable of handling this
ripple current. Sometime, for higher efficiency the low ESR
capacitor is necessarily. Appropriate high frequency
ceramic capacitors physically near the MOSFETs
effectively reduce the switching voltage spikes.

DS9232B-03 March 2007 www.richtek.com

11

RT9232B

MOSFET Selection

The selection of MOSFETs is based upon the
considerations of R

, gate driving requirements, and

DS(ON)

thermal management requirements. The power loss of
upper MOSFET consists of conduction loss and switching
loss and is expressed as :

(8)

2

OUT

where T

RISE

and T

FALL

upper MOSFET respectively. R

P P P

+=

SW_UPPERCOND_UPPERUPPER

1

I

DRI

+××=

OUTDS(ON)

2

f)T(TV

×+××

OSCFALLRISEIN

are rising and falling time of VDS of

and QG should be

DS(ON)

simultaneously considered to mini mize power loss of upper
MOSFET.

The power loss of lower MOSFET consists of conduction
loss, reverse recovery loss of body diode, and conduction
loss of body diode and is expressed as :

(9)

2

OUT

1
2

where T

is the conducting time of lower body diode.

DIODE

×××+

++=

P P P P

DIODERRCOND_LOWERLOWER

××+××=

fVQD)-(1RI

OSCINRRDS(ON)

fTV I

OSCDIODEFOUT

Special control scheme is adopted to minimize body diode
conducting time. As a result, the R

loss dominates

DS(ON)

the power loss of lower MOSFET. Use MOSFET with
adequate R

to minimize power loss and satisfy

DS(ON)

thermal requirements.

Feedback Compensation

Figure 2 highlights the voltage-mode control loop for a
synchronous buck converter. Figure 3 shows the
corresponding Bode plot. The output voltage (V

OUT

) is
regulated to the reference voltage. The error a mplifier EA
output (COMP) is compared with the oscillator (OSC)
sawtooth wave to provide a pulse-width modulated (PWM)
wave with an amplitude of VIN at the PHASE node. The
PWM wave is smoothed by the output filter (L a nd C

OUT

The modulator trans fer function is the small-signal transfer
function of V
DC gain and the output filter (L a nd C
pole break frequency at F

/COMP. This function is domin ated by a

OUT

), with a double

OUT

and a zero at F

P_LC

Z_ESR

. The
DC gain of the modulator is simply the input voltage (VIN)
divided by the peak-to-pea k oscillator voltage ΔV

OSC

.

The break frequency FLC and F

are expressed as

ESR

Equation (10) and (1 1) respectively .

1

F

P_LC

F

Z_ESR

(10)

=

LC2

π

OUT

(11)

=

1

CESR2

π

××

OUT

The compensation network consists of the error a mplifier
EA a nd the impeda nce networks ZIN and ZFB. The goal of
the compensation network is to provide a closed loop
transfer function with the highest DC gain, the highest
0dB crossing frequency (FC) and adequate pha se margin.
Typically, FC in range 1/5~1/10 of switching frequency is
adequate. The higher FC is, the faster dyn a mic response
is. A pha se margin in the range of 45°C~ 60°C is desira ble.

The equations below relate the compensation network’s
poles, zeros and gain to the components (R1, R2, R3,
C1, C2, and C3) in Figure 2.

1

F

Z1

F

Z2

F

P1

F

P2

).

(12)

=

π

(13)

=

π

(14)

=

π

(15)

=

π

ΔV

OSC

××

R22

××

1

OSC

Comparator

1

1

××

C1R22

C3R32

PWM

V

E/A

C1

COMP

C3)R3(R12

×+×

C2C1

×

C2C1

+

V

IN

Driver

Z

IN

R3

PHASE

C

V

OUT

L

­+

Z

FB

EA

EA

C2

­+

­+

R2

REF

REF

Z

FB

Driver

FB

C3

Z

IN

R1

Figure 2

OUT

ESR

V

OUT

12

DS9232B-03 March 2007www.richtek.com

RT9232B

100

80

60

40

20LOG

20

Gain (dB)

(R1/R2)

0

-20

-40

-60

Modulator

10 100 1K 10K 100K 1M 10M

FZ1FZ2FP1F

Gain

F

LC

Frequency (Hz)

20LOG

/ΔV

(V

IN

F

ESR

P2

Open Loop Error
AMP Gain

)

OSC

Compensation
Gain

Closed Loop Gain

Figure 3

Feedback Loop Design Procedure

Use these guidelines for locating the poles and zeros of
the compensation network :

1. Pick Gain (R2/R1) f or desired 0dB crossing frequency

(FC).

of high-side MOSFET. The MOSFETs of linear regulator
should have wide pad to dissipate the heat. In multilayer
PCB, use one layer as power ground a nd have a separate
control signal ground a s the reference of the all signal. To
avoid the signal ground is effect by noise a nd have best
load regulation, it should be connected to the ground
terminal of output. Furthermore, follows below guidelines
can get better performa nce of IC :

(1). The IC needs a bypa ssing ceramic ca pa citor as a R-C

filter to isolate the pulse current from power stage
and supply to IC, so the cera mic capa citor should be
placed adja cent to the IC.

(2). Place the high frequency ceramic decoupling close

to the power MOSFETs.

(3). The feedback part should be pla ced a s close to IC a s

possible and keep away from the inductor a nd all noise
sources.

(4). The components of bootstraps should be closed to

each other and close to MOSFETs.

2. Place 1ST zero FZ1 below modulator's double pole F

LC

(~75% FLC).

3. Place 2ND zero FZ2 at modulator's double pole FLC.

4. Place 1ST pole FZ1 at the ESR zero F

Z_ESR.

5. Place 2ND pole FZ2 at half the switching frequency.

6. Check gain against error a mplifier's open-loop gain.

7. Pick RFB for desired output voltage.

8. Estimate pha se margin and repeat if necessary.

Layout Consideration

Layout is very important in high frequency switching
converter design. If designed improperly , the PCB could
radiate excessive noise and contribute to the converter
instability . First, place the PWM power stage components.
Mount all the power components and connections in the
top layer with wide copper area s. The MOSFET s of Buck,
inductor, a nd output ca pacitor should be a s close to ea ch
other as possible. This can reduce the radiation of EMI
due to the high frequency current loop. If the output
capacitors are placed in parallel to reduce the ESR of
capacitor, equal sharing ripple current should be
considered. Place the input ca pa citor directly to the drain

(5).The PCB trace from Ug and Lg of controller to

MOSFETs should be as short as possible and can
carry 1A pea k current.

(6). Place all of the components a s close to IC a s possible.

DS9232B-03 March 2007 www.richtek.com

13

RT9232B

Outline Dimension

A

J

I

Dimensions In Millimeters Dimensions In Inches

Symbol

Min Max Min Max

A 8.534 8.738 0.336 0.344
B 3.810 3.988 0.150 0.157

B

F

C

D

H

M

C 1.346 1.753 0.053 0.069
D 0.330 0.508 0.013 0.020

F 1.194 1.346 0.047 0.053

H 0.178 0.254 0.007 0.010

I 0.102 0.254 0.004 0.010

J 5.791 6.198 0.228 0.244

M 0.406 1.270 0.016 0.050

Richtek Technology Corporation

Headquarter
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: [phone] Fax: [phone]

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Richtek Technology Corporation

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8F, No. 137, Lane 235, Paochiao Road, Hsintien City
Taipei County, Taiwan, R.O.C.
Tel: [phone] Fax: [phone]
Email: [e-mail]

14

DS9232B-03 March 2007www.richtek.com