Page 1
RT9218
5V/12V Synchronous Buck PWM DC-DC and Linear Power
Controller
General Description
The RT9218 is a dual output with one synchronous buck
PWM and one linear controller. The part is proposed to
generate logic-supply voltages for PC based systems. The
high-performance device includes internal soft-start,
frequency-compensation networks, power good signaling
with specific sequence, and it comes all of the logic control,
output adjustment, power monitoring and protection
functions into a small footprint package. The part is
operated at fixed 300kHz frequeny providing an optimum
compromise between efficiency, external component size,
and cost. The linear controller is implemented to drive an
external MOSFET for regulation and it's adjustable by
setting external resistors. Moreover the specific internal
PGOOD sequence and indicator is also implemented to
conform to Intel
®
new platform requirement on FSB_VTT
power plane. An adjustable over-current protection (OCP)
is proposed to monitor the voltage drop across the
RDS(ON) of the lower MOSFET for synchronous buck
PWM DC-DC controller.
Ordering Information
RT9218
Package Type
S : SOP-14
Operating Temperature Range
P : Pb Free with Commercial Standard
G : Green (Halogen Free with Commer cial Standard)
Note :
RichTek Pb-free and Green products are :
`RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
`Suitable for use in SnPb or Pb-free soldering processes.
`100% matte tin (Sn) plating.
Features
zz
Operating with 5V or 12V Supply Voltage
z
zz
zz
z Drives All Low Cost N-MOSFET s
zz
zz
z Voltage Mode PWM Control
zz
zz
z 300kHz Fixed Frequency Oscillator
zz
zz
z Fast T ra nsient Re sponse :
zz
``
`High-Speed GM Amplifier
``
``
`Full 0 to 100% Duty Ration
``
zz
z Internal Soft-Start
zz
zz
z Power Good Indicator
zz
zz
z Adaptive Non-Overlapping Gate Driver
zz
zz
z Over-Current Fault Monitor on MOSFET , No Current
zz
Sense Resistor Required
zz
z Specific power good indicator for Intel®
zz
Grantsdale FSB_VTT power sequence
zz
z RoHS Compliant and 100% Lead (Pb)-Free
zz
Applications
z Graphic Card
z Motherboard, Desktop Servers
z IA Equipments
z Telecomm Equipments
z High Power DC-DC Regulators
Pin Configurations
(TOP VIEW)
SOP-14
14
13
12
11
10
PHASE
OPS
FB
VCC
PGOOD
9
FBL
NC
8
BOOT
UGATE
GND
LGATE
DRV
NC
NC
2
3
4
5
6
7
DS9218-08 March 2007 www.richtek.com
1
Page 2
RT9218
Typical Application Circuit
5
t
S
V
O
U
C5 to C6
1000uF x 2
V
I
N
o
1
2
V
C1 to C2
1000uF x 2
T
REF
L1
2.2uH
C3 to C4
1uF x 2
R
C
REFOUT
REFOUT
2%)(0.8V
±
V
C
C
V
2
C7
1uF
C9
470uF
D1
1N4148
R1
4k
1
R
U
G
A
T
Q1
MU
PHASE
Q2
ML
LV
R5
+×=
(1VSV
(1VLV
)
R6
R1
+×=
)
R2
E
2.2
Q3
OUT
1
2
3
4
5
6
7
R2
8k
R
B
O
O
2.2
BOOT
UGATE
GND
LGATE
DRV
NC
NC
T
RT9218
PHASE
PGOOD
C8
0.1uF
OPS
FB
VCC
FBL
NC
1k/NC 0.1uF/NC
14
13
12
11
10
9
8
68R
R5
V
C
C
1
2
V
PHASE
R3
10R
C10
1uF
C11R4
Q4
R6
32R
R
OCSET
3904
Disable
voltage reference Internal:V
DS9218-08 March 2007www.richtek.com
2
Page 3
Functional Pin Description
RT9218
UGA TE (Pin 2)
Upper gate driver output. Connect to gate of the high-
side power N-MOSFET. This pin is monitored by the
adaptive shoot-through protection circuitry to determine
when the upper MOSFET has turned off.
BOOT (Pin 1)
Bootstrap supply pin for the upper gate driver. Connect
the bootstrap capacitor between BOOT pin and the PHASE
pin. The bootstrap capacitor provides the charge to turn
on the upper MOSFET.
PHASE (Pin 14)
Connect this pin to the source of the upper MOSFET and
the drain of the lower MOSFET.
OPS (OCSET, POR and Shut-Down) (Pin 13)
This pin provides multi-function of the over-current setting,
UGATE turn-on POR sensing, and shut-down features.
Connecting a resistor (R
pins sets the over-current trip point.
) between OPS and PHASE
OCSET
VCC (Pin 11)
Connect this pin to a well-decoupled 5V or 12V bias
supply. It is also the positive supply for the lower gate
driver, LGATE.
GND (Pin 3)
Both signal and power ground for the IC. All voltage levels
are measured with respect to this pin. Ties the pin directly
to the low-side MOSFET source and ground plane with
the lowest impedance.
DRV (Pin 5)
Connect this pin to the base/gate of an external transistor/
MOSFET. This pin provides the drive for the linear
regulator's pass transistor/MOSFET.
FBL (Pin 9)
Linear regulator feedback voltage. This pin is the inverting
input of the error amplifier and protection monitor. Connect
this pin to the external resistor divider network of the linear
regulator.
Pulling the pin to ground resets the device and all external
MOSFETs are turned off allowing the output voltage power
rails to float.
This pin is also used to detect VIN in power on stage and
issues an internal POR signal.
LGA TE (Pin 4)
Lower gate drive output. Connect to gate of the low-side
power N-MOSFET. This pin is monitored by the adaptive
shoot-through protection circuitry to determine when the
lower MOSFET has turned off.
FB (Pin 12)
Switcher feedback voltage. This pin is the inverting input
of the error amplifier. FB senses the switcher output
through an external resistor divider network.
PGOOD (Pin 10)
PGOOD is an open-drain output used to indicate that the
regulator is within normal operating voltage ranges and
it's implemented with a specific sequence as following
chart.
NC (Pin 6,7,8)
No internal connection.
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Page 4
RT9218
Function Block Diagram
VCC
DRV
FBL
PGOOD
FB
Bias & Regulators
(3V_Logic & 3VDD_Analog)
VCC
+
-
0.64V
0.64V
Reference
0.8V
+
-
+
-
+
GM
+
-
REF
UV_S
UV_L
EO
Power On
Reset
Soft-Start
&
Fault Logic
Oscillator
(300k/600kHz)
OC
+
+
-
EN
PH_M
+
-
+
-
3V
-
0.4V
+
+
-
Gate Control
Logic
0.15V
1.5V
40uA
OPS
BOOT
UGATE
PHASE
VCC
LGATE
Timing Diagram
FSB_VTT (1.2V @ 5Amp)
VTT_GD
GND
Specific Power Sequence for LDO
90%
80%
1-10ms
<1ms
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Page 5
Absolute Maximum Ratings (Note 1)
RT9218
z Supply Voltage, V
z BOOT, V
z PHASE to GND
BOOT
- V
-------------------------------------------------------------------------------------- 16V
CC
------------------------------------------------------------------------------------ 16V
PHASE
DC------------------------------------------------------------------------------------------------------------- −5V to 15V
< 200ns ------------------------------------------------------------------------------------------------------ −10V to 30V
z BOOT to PHASE ------------------------------------------------------------------------------------------ 15V
z BOOT to GND
DC------------------------------------------------------------------------------------------------------------- −0.3V to VCC+15V
< 200ns ------------------------------------------------------------------------------------------------------ −0.3V to 42V
z UGATE ------------------------------------------------------------------------------------------------------- V
z LGATE ------------------------------------------------------------------------------------------------------- GND − 0.3V to V
z Input, Output or I/O Voltage ----------------------------------------------------------------------------- GND − 0.3V to 7V
z Package Thermal Resistance (Note 4)
PHASE
− 0.3V to V
SOP-14, θJA------------------------------------------------------------------------------------------------- 127.67°C/W
z Junction Temperature ------------------------------------------------------------------------------------- 150°C
z Lead Temperature (Soldering, 10 sec.) --------------------------------------------------------------- 260°C
z Storage Temperature Range ---------------------------------------------------------------------------- −40°C to 150°C
z ESD Susceptibility (Note 2)
HBM (Human Body Mode) ------------------------------------------------------------------------------ 2kV
MM (Machine Mode) -------------------------------------------------------------------------------------- 200V
BOOT
VCC
+ 0.3V
+ 0.3V
Recommended Operating Conditions (Note 3)
z Supply Voltage, V
z Junction Temperature Range---------------------------------------------------------------------------- −40°C to 125°C
z Ambient Temperature Range---------------------------------------------------------------------------- −40°C to 85°C
-------------------------------------------------------------------------------------- 5V ± 5%,12V ± 10%
CC
Electrical Characteristics
(V
= 5V/12V, T
CC
VCC Supply Current
Nominal Supply Current
Power-On Reset
POR Threshold
Hysteresis
Switcher Reference
Reference Voltage
Oscillator
Free Running Frequency
Ramp Amplitude
= 25°C, unless otherwise specified)
A
Parameter Symbol Test Conditions Min Typ Max Units
I
CC
V
CCRTH
V
CCHYS
V
REF
f
OSC
ΔV
OSC
UGATE and LGATE Open -- 6 15 mA
Rising
V
CC
0.35 0.5 -- V
= 12V
V
CC
= 12V
V
CC
-- 4.1 4.5 V
0.784 0.8 0.816 V
250 300 350 kHz
-- 1.5 --
V
P-P
To be continued
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Page 6
RT9218
Parameter Symbol Test Conditions Min Typ Max Units
Error Amplifier (GM)
E/A Transconductance
Open Loop DC Gain
g
m
A
O
Linear Regulator
DRV Driver Source
Reference Voltage
V
I
DS
V
REFREG
PWM Controller Gate Drivers (VCC = 12V)
Upper Gate Source
Upper Gate Sink
Lower Gate Source
Lower Gate Sink
Dead Time
I
UGATE
R
UGATE
VCC = 12V, V
I
LGATE
R
LGATE
T
DT
Protection
FB Under-Voltage Trip
FBL Under-Voltage Trip
OC Current Source
Soft-Start Interval
Δ
FBUVT
Δ
FBLUVT
V
I
OC
T
SS
Power Good
-- 0.2 -- ms
-- 90 -- dB
= 6V
DRV
V
= 12V
CC
V
− V
BOOT
V
UGATE
V
BOOT
V
UGATE
− V
− V
− V
PHASE
PHASE
VCC = 12V, V
PHASE
PHASE
LGATE
LGATE
= 12V
= 6V
= 12V
= 1V
= 6V
= 1V
--
0.784 0.8 0.816 V
0.6 1 -- A
-- 4 --
0.6 1 -- A
-- 3 4
1.4
--
mA
Ω
Ω
-- -- 100 ns
FB Falling 70 75 80 %
FB and FBL Falling 70 75 80 %
PHASE
= 0V
-- 40 --
μA
-- 3.5 -- ms
Power Good Rising Threshold
Power Good Hysteresis
PG Sink Capability
Power Good Rising Delay
Power Good Falling Delay
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are
for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may remain possibility to affect device reliability.
Note 2. Devices are ESD sensitive. Handling precaution recommended.
Note 3. The device is not guaranteed to function outside its operating conditions.
Note 4. θ
is measured in the natural convection at TA = 25°C on a low effective thermal conductivity test board of
JA
JEDEC 51-3 thermal measurement standard.
V
= 12V
CC
V
= 12V
CC
V
= 12V, 1mA
CC
V
= 12V
CC
V
= 12V
CC
-- 90 -- %
-- 10 -- %
-- 0.2 0.4 V
1 3 10 ms
-- 15 -- us
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Page 7
Typical Operating Characteristics
)
(V
= 2.5V, unless otherwise specified )
OUT
1
Efficiency v s. Output Current
RT9218
Efficiency vs. Output Current
1
Reference Voltage (V)
0.95
0.9
0.85
0.8
0.75
Efficiency(%)
0.7
0.65
V
= 12V
CC
V
= 5V
IN
0.6
0 5 10 15 20 25
Output Current (A)
Reference Voltage vs. Temperature
0.812
V
= 12V
CC
V
= 5V
IN
0.81
0.808
0.806
0.804
0.802
0.8
0.95
0.9
0.85
0.8
0.75
Efficiency(%)
0.7
0.65
V
= 5V
CC
V
= 5V
IN
0.6
0 5 10 15 20 25
Output Current (A)
Frequency vs. Temperature
350
330
310
290
Frequency (kHz
270
0.798
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature
(°C)
POR vs. Temperature
4.75
Rising
4.5
4.25
4
3.75
POR Rising or Falling (V)
3.5
-40 -10 20 50 80 110 140
DS9218-08 March 2007 www.richtek.com
Rising
Falling
Falling
Temperature
(°C)
250
-40 -10 20 50 80 110 140
Temperature
(°C)
OCP
UGATE
I
L
VCC = 12V, V
I
= 20A
OCSET
R
= 15kΩ
OCSET
= 5V
IN
Time (5us/Div)
(10V/Div)
(10A/Div)
7
Page 8
RT9218
SV
OUT
I
OUT
UGATE
V
SV
OUT
CC
VCC = 12Vto 5V
I
= 10A
OUT
V
= 5V
IN
VCC Switching
Time (10ms/Div)
Power On
(500mV/Div)
(100mV/Div)
(10A/Div)
(20V/Div)
(10V/Div)
SV
OUT
I
OUT
UGATE
V
(20V/Div)
CC
VCC = 5V to 12V
I
= 10A, V
OUT
VCC Switching
= 5V
IN
Time (10ms/Div)
Power Off
V
CC
(100mV/Div)
(10A/Div)
(10V/Div)
SV
OUT
I
OUT
UGATE
VCC = V
I
= 25A
OUT
Time (500us/Div)
Dead Time (Rising)
= 5V
IN
Time (25ns/Div)
(2A/Div)
(10V/Div)
UGATE
PHASE
LGATE
VCC = 12V
V
= 5V
IN
I
= 25A
OUT
UGATE
PHASE
Time (5ms/Div)
Dead Time (Falling)
LGATE
Time (10ns/Div)
V
UGATE
IN
DS9218-08 March 2007www.richtek.com
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Page 9
RT9218
UGATE
(10V/Div)
SV
OUT
(100mV/Div)
I
L
(10A/Div)
PGOOD
Transient Response (Rising)
VCC = V
I
OUT
f = 1/20ms, SR = 2.5A/us
= 12V
IN
= 0A to 15A
Time (5us/Div)
Soft Start & PGOOD
(1V/Div)
L = 2.2uH
C = 2000uF
UGATE
(10V/Div)
SV
OUT
(100mV/Div)
I
L
(10A/Div)
Transient Response (Falling)
L = 2.2uH
C = 2000uF
VCC = V
I
OUT
f = 1/20ms
SR = 2.5A/us
= 12V
IN
= 15A to 0A
Time (25us/Div)
SV
OUT
I
L
(500mV/Div)
(2A/Div)
Time (10ms/Div)
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9
Page 10
RT9218
Application Information
Inductor Selection
The selection of output inductor is based on the
considerations of efficiency, output power and operating
frequency. Low inductance value has smaller size, but
results in low efficiency, large ripple current and high output
ripple voltage. Generally, an inductor that limits the ripple
current (ΔIL) between 20% and 50% of output current is
appropriate. Figure 1 shows the typical topology of
synchronous step-down converter and its related
waveforms.
i
S1
+
i
S1
V
IN
S2
V
TONT
g1
V
g2
S2
T
S
OFF
I
L
L
-
V
L
V
V
OC
+
OR
-
+
i
C
r
C
+
C
OUT
-
I
OUT
R
L
V
OUT
According to Figure 1 the ripple current of inductor can be
calculated as follows :
ΔI
VV L ; Δt; D
−= = =
IN OUT
L(V V )
=− ×
IN OUT
L
ΔtfsV
VfsΔI
D
V
OUT
××
IN L
V
OUT
IN
(1)
Where :
V
= Maximum input voltage
IN
V
= Output Voltage
OUT
Δt = S1 turn on time
ΔIL = Inductor current ripple
fS = Switching frequency
+
D = Duty Cycle
-
rC = Equivalent series resistor of output capacitor
Output Capa citor
The selection of output capacitor depends on the output
ripple voltage requirement. Practically, the output ripple
voltage is a function of both capacitance value and the
equivalent series resistance (ESR) rC. Figure 2 shows
the related waveforms of output capacitor.
VIN - V
OUT
V
L
- V
OUT
i
L
IL = I
ΔI
L
i
S1
i
S2
OUT
Figure 1. The waveforms of synchronous step-down
converter
10
di
VIN-V
L
=
L
t1 t2
OUT
i
L
dt
i
C
0
V
OC
V
OR
0
di
V
L
OUT
=
dt
L
I
OUT
T
S
ΔI
1/2
L
ΔI
L
ΔV
ΔIL x r
OC
c
Figure 2. The related waveforms of output capacitor
DS9218-08 March 2007www.richtek.com
Page 11
RT9218
The AC impedance of output capacitor at operating
frequency is quite smaller than the load impedance, so
the ripple current (ΔIL) of the inductor current flows mainly
through output capacitor. The output ripple voltage is
described as :
ΔVΔVΔV
+=
OCOROUT
1
t2
rcΔIΔV
+×=
LOUT
C
O
rcΔIΔIΔV
LLOUT
dtic
∫
t1
1
OUT
CV8
OL
2
D)T(1
−+××=
S
(2)
(3)
(4)
where ΔVOR is caused by ESR and ΔVOC by capacitance.
For electrolytic capacitor application, typically 90 to 95%
of the output voltage ripple is contributed by the ESR of
output capacitor. So Equation (4) could be simplified as :
ΔV
= ΔIL x rc
OUT
(5)
Users could connect capacitors in parallel to get calculated
ESR.
Input Capacitor
The selection of input capacitor is mainly based on its
maximum ripple current capability. The buck converter
draws pulsewise current from the input capacitor during
the on time of S1 as shown in Figure 1. The RMS value of
ripple current flowing through the input capacitor is
described as :
Z
is the shut impedance at the output node to ground
OUT
(see Figure 3 and Figure 4),
GM
C
1
R
1
V
OUT
C
2
Figure 3. A Type 2 error-amplifier with shut network to
ground
V
OUT
O
EA+
EA-
+
+
GM
-
R
Figure 4. Equivalent circuit
Pole and Zero :
F
P
1
=
×
F ;
CR2
Z
21
1
=
CR2
×
ππ
11
We can see the open loop gain and the Figure 3 whole
loop gain in Figure 5.
OUT
(A) D)D(1IIrms
−=
(6)
Open Loop, Unloaded Gain
The input capacitor must be cable of handling this ripple
current. Sometime, for higher efficiency the low ESR
capacitor is necessarily.
PWM Loop Stability
A
Gain (dB)
F
Z
Gain = GMR
Closed Loop, Unloaded Gain
F
P
1
B
RT9218 is a voltage mode buck converter using the high
gain error amplifier with transconductance (OTA,
Operational Transconductance Amplifier).
The transconductance :
dI
OUT
=
GM
The mid-frequency gain :
G
DS9218-08 March 2007 www.richtek.com
dV
dV
dVm
OUT
IN
==
GMZ
OUT
RT9218 internal compensation loop :
GM = 0.2ms, R1 = 75kΩ, C1 = 2.5nF, C2 = 10pF
==
ZGMdVZdIdV
OUTINOUTOUTOUT
100 1000 10k 100k
Frequency (Hz)
Figure 5. Gain with the Figure 2 circuit
11
Page 12
RT9218
OPS (Over Current Setting, VIN_POR and Shutdown)
1.OCP
Sense the low-side MOSFET's R
Connecting a resistor (R
) from this pin to the source of the upper MOSFET and the drain of the lower MOSFET
OCSET
sets the over-current trip point. R
set the converter over-current trip point (I
to set over-current trip point.
DS(ON)
, an internal 40μA current source, and the lower MOSFET on resistance, R
OCSET
) according to the following equation :
OCSET
I
OCSET
=
R
DS(ON)
OCSET
0.4VR40uA
−×
MOSFET lower the of
DS(ON)
OPS pin function is similar to RC charging or discharging circuit, so the over-current trip point is very sensitive to
parasitic capacitance (ex. shut-down MOSFET) and the duty ratio.
Below Figures say those effect. And test conditions are Rocset = 15kΩ (over -current trip point = 20.6A), Low-side
MOSFET is IR3707.
OCP
UGATE (10V/Div)
OCP
UGATE
(10V/Div)
,
V
= 5V, VCC = 12V
IN
V
= 1.5V
OUT
V
= 12V, VCC = 12V
IN
V
= 1.5V
OUT
Time (5μs/Div)
OCP
Time (2.5μs/Div)
IL (10A/Div)
UGATE (10V/Div)
IL (10A/Div)
OPS (200mV/Div)
V
= 5V, VCC = 12V
IN
V
= 1.5V
OUT
V
= 12V, VCC = 12V
IN
V
= 1.5V
OUT
IL (10A/Div)
Time (5μs/Div)
OCP
OPS
(200mV/Div)
UGATE
(10V/Div)
IL (10A/Div)
Time (2.5μs/Div)
12
DS9218-08 March 2007www.richtek.com
Page 13
RT9218
2. VIN_POR
UGATE will continuously generate a 10kHz colck with
1% duty cycle before VIN is ready. VIN is recognized ready
by detecting V
falling). R
R
OCSET
OCSET
will keep V
crossing 1.5V four times (rising &
OPS
must be kept lower than 37.5kΩ for large
always higher than 1.5V. Figure 6
OPS
shows the detail actions of OCP and POR. It is highly
recommend-ed that R
3V
40uA
OC
POR_H
V
IN
PHASE_M
-
0.4V
+
10pF
+
-
+
-
1.5V
be lower than 30kΩ.
OCSET
R
OPS
Cparasitic
1st 2nd 3rd 4th
UGATE
(1) Internal Counter will count (V
four times (rising & falling) to recognize
V
IN
(2) R
OCSET
detect V
OCSET
Q2
is ready.
can be set too large. Or can
is ready (counter = 1, not equal 4)
IN
PHASE
DISABLE
OPS
waveform
OPS
Figure 6. OCP and VIN_POR actions
3. Shutdown
Pulling low the OPS pin by a small single transistor can
shutdown the RT9218 PWM controller as shown in typical
application circuit.
Soft Start
A built-in soft-start is used to prevent surge current from
power supply input during power on. The soft-start voltage
is controlled by an internal digital counter. It clamps the
ramping of reference voltage at the input of error amplifier
and the pulse-width of the output driver slowly. The typical
soft-start duration is 3ms.
> 1.5V)
1) Mode 1 (SS< Vramp_valley)
Initially the COMP stays in the positive saturation. When
SS< V
RAMP_Valley
, there is no non-inverting input available
to produce duty width. So there is no PWM signal and
V
is zero.
OUT
2) Mode 2 (V
When SS>V
RAMP_Valley
RAMP_Valley
< SS< Cross-over)
, SS takes over the non-inverting
input and produce the PWM signal and the increasing
duty width according to its magnitude above the ramp
signal. The output follows the ramp signal, SS. However
while V
increases, the difference between V
OUT
OUT
and
SSE (SS − VGS) is reduced and COMP leaves the
saturation and declines. The takeover of SS lasts until it
meets the COMP. During this interval, since the feedback
path is broken, the converter is operated in the open loop.
3) Mode3 ( Cross-over< SS < VGS + V
REF
)
When the Comp takes over the non-inverting input for PWM
Amplifier and when SSE (SS − VGS) < V
, the output of
REF
the converter follows the ramp input, SSE (SS − VGS).
Before the crossover, the output follows SS signal. And
when Comp takes over SS, the output is expected to follow
SSE (SS − VGS). Therefore the deviation of VGS is
represented as the falling of V
for a short while. The
OUT
COMP is observed to keep its decline when it passes the
cross-over, which shortens the duty width and hence the
falling of V
happens.
OUT
Since there is a feedback loop for the error amplifier, the
output’ s response to the ramp input, SSE (SS − V
GS
) is
lower than that in Mode 2.
4) Mode 4 (SS > VGS + V
When SS > VGS + V
the desired V
REF
signal and the soft start is completed
REF
)
REF
, the output of the converter follows
now.
COMP
V
RAMP_Valley
Cross-over
SS_Internal
VCORE
SSE_Internal
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RT9218
Under Voltage Protection
The voltage at FB and FBL pin is monitored and protected
against UV (under voltage). The UV threshold is the FB
or FBL under 75%. UV detection has 30μs triggered delay.
When OC or UV_FBL is trigged, a hiccup restart
sequence will be initialized, as shown in Figure 7 Only 4
times of trigger are allowed to latch off. Hiccup is disabled
during soft-start interval, but UV_FB has some difference
from OC and UV_FBL, it will always trigger VIN power
sensing after 4 times hiccup, as shown in Figure 8.
Internal
COUNT = 1 COUNT = 2
4V
SS
2V
0V
0A
Inductor Current
OVERLOAD
APPLIED
T0
T1 T2 T3
COUNT = 3 COUNT = 4
T4
TIME
Figure 7. UV and OC trigger hiccup mode
Power Off
UGATE
V
FB
OUT
V
IN
(20V/Div)
(500mV/Div)
I
= 2A
OUT
UV
Time (10ms/Div)
V
Power
IN
Sensing
(2V/Div)
(2V/Div)
Figure 8, UV_FB trigger VIN power sensing
LDO Power Sequence
In VGA field, the MOSFET of LV
voltage not by SV
OUT
.
is sourced by external
OUT
This connection may trigger UV protection to shutdown
RT9218, but using the typical application circuit won't have
this issue. See figure 9 using OPS pin to control the power
sequence.
VIN_SW (5V/12V)
VIN_LDO (3.3V)
OPS_Disable
EnableShutdown
Figure 9. LDO power sequence
PWM Layout Considerations
MOSFETs switch very fast and efficiently. The speed with
which the current transitions from one device to another
causes voltage spikes across the interconnecting
impedances and parasitic circuit elements. The voltage
spikes can degrade efficiency and radiate noise, that results
in over-voltage stress on devices. Careful component
placement layout and printed circuit design can minimize
the voltage spikes induced in the converter. Consider, as
an example, the turn-off transition of the upper MOSFET
prior to turn-off, the upper MOSFET was carrying the full
load current. During turn-off, current stops flowing in the
upper MOSFET and is picked up by the low side MOSFET
or schottky diode. Any inductance in the switched current
path generates a large voltage spike during the switching
interval. Careful component selections, layout of the
critical components, and use shorter and wider PCB traces
help in minimizing the magnitude of voltage spikes.
There are two sets of critical components in a DC-DC
converter using the RT9218. The switching power
components are most critical because they switch large
amounts of energy, and as such, they tend to generate
equally large amounts of noise. The critical small signal
components are those connected to sensitive nodes or
those supplying critical bypass current.
The power components and the PWM controller should
be placed firstly. Place the input capacitors, especially
the high-frequency ceramic decoupling capacitors, close
to the power switches. Place the output inductor and
output capacitors between the MOSFETs and the load.
Also locate the PWM controller near by MOSFETs.
A multi-layer printed circuit board is recommended.
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DS9218-08 March 2007www.richtek.com
Page 15
RT9218
Figure 10 shows the connections of the critical components in the converter. Note that the capacitors CIN and C
OUT
each
of them represents numerous physical capacitors. Use a dedicated grounding plane and use vias to ground all critical
components to this layer. Apply another solid layer as a power plane and cut this plane into smaller islands of common
voltage levels. The power plane should support the input power and output power nodes. Use copper filled polygons on
the top and bottom circuit layers for the PHASE node, but it is not necessary to oversize this particular island. Since the
PHASE node is subjected to very high dV/dt voltages, the stray capacitance formed between these island and the
surrounding circuitry will tend to couple switching noise. Use the remaining printed circuit layers for small signal
routing. The PCB traces between the PWM controller and the gate of MOSFET and also the traces connecting source
of MOSFETs should be sized to carry 2A peak currents.
5V/12V
GND
IQ1
+
Q1
Q2
LGATE
UGATE
IQ2
VCC
IL
GND
RT9218
FB
V
OUT
+
+
LOAD
Figure 10. The connections of the critical components in the converter
Below PCB gerber files are our test board for your reference :
DS9218-08 March 2007 www.richtek.com
15
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RT9218
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Page 17
According to our test experience, you must still notice two items to avoid noise coupling :
1.The ground plane should not be separated.
2.VCC rail adding the LC filter is recommended.
RT9218
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RT9218
Outline Dimension
A
J
I
Dimensions In Millimeters Dimensions In Inches
Symbol
Min Max Min Max
A 8.534 8.738 0.336 0.344
B 3.810 3.988 0.150 0.157
B
F
C
D
H
M
C 1.346 1.753 0.053 0.069
D 0.330 0.508 0.013 0.020
F 1.194 1.346 0.047 0.053
H 0.178 0.254 0.007 0.010
I 0.102 0.254 0.004 0.010
J 5.791 6.198 0.228 0.244
M 0.406 1.270 0.016 0.050
Richtek Technology Corporation
Headquarter
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
14–Lead SOP Plastic Package
Richtek Technology Corporation
Taipei Office (Marketing)
8F, No. 137, Lane 235, Paochiao Road, Hsintien City
Taipei County, Taiwan, R.O.C.
Tel: (8862)89191466 Fax: (8862)89191465
Email: marketing@richtek.com
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DS9218-08 March 2007www.richtek.com
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