Datasheet rt8857 Datasheets

Page 1

RT8857/A

4/3/2/1-Phase PWM Controller with Embedded Drivers for CPU Core Power Supply

General Description

The RT8857/A is a 4/3/2/1-phase synchronous buck controller with 2 integrated MOSFET drivers for Intel VR11.1/VR10.x and AMD K8/K8_M2 CPUs power application. RT8857/A uses differential inductor DCR current sense to achieve pha se current balance a nd active voltage positioning. Other features include adjustable operating frequency, adjustable soft start, power good indication, external error-a mp compensation, over voltage protection, over current protection, VRHOT sensing a n d IMON f or various applications. RT8857/A comes to a small footprint with WQFN-48L 7x7 pa ckage

Ordering Information

RT8857/A

Package Type QW : WQFN-48L 7x7 (W-Type)

Operating Temperature Range G : Green (Halogen Free with Commer cial Standard)

Features



12V Power Supply Voltage





 4/3/2/1-Phase Power Conversion



 2 Embedded MOSFET Drivers



 Internal Regulated 5V Output



 VID table for INTEL VR11.1/VR10.x and AMD K8/



K8_M2 CPUs



 Continuous Differential Inductor DCR Current Sense



 Adjustable Soft Start



 Adjustable Frequency



 Power Good Indication



 Adjustable Over Current Protection



 Over Voltage Protection



 VRHOT Sensing with External Thermistor



 IMON Output Current Indication



 Power State Indicator (PSI)



 Support MOSFET Power Stage Input Voltage (V



Down to 5V (RT8857A Only)



 Small 48-Lead WQFN Package



 RoHS Compliant and Halogen Free



)

Support V Support V

: 5/12V

: 12V

Note :

 V

is the input voltage of MOSFET power stage.

 Richtek Green products are :

 RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

 Suitable for use in SnPb or Pb-free soldering processes.

Applications

 Desktop CPU Core Power  Low V oltage, High Current DC/ DC Converter

Pin Configurations

(TOP VIEW)

VOUT

VIDSEL

VID0

VID1

VID2

GND

ISP3

ISP2

ISN3

WQFN-48L 7x7

FBRTN

QR1

QR2 SS/EN COMP

OFS

ADJ

IMAX

IMAXPSI

IMONF B

PSI

1 2 3 4 5 6 7 8

9 10 11 12

ISP4

ISN4

IMON

VID3

ISN2

VID4

ISN1

VID5

ISP1

VID6

VID7

373839404142434445464748

242322212019181716151413

TSEN

VRHOT

EN/VTT

36 35 34 33 32 31 30 29 28 27 26 25

VCC5

PWRGD BOOT1 UGATE1 PHASE1 LGATE1 VCC12 LGATE2 PHASE2 UGATE2 BOOT2 PWM3 PWM4

DS8857/A-00 February 2009 www.richtek.com

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RT8857/A

Typical Application Circuit

E R O C

T N

T T V

/ N E

T O H R V

5 8

8 T R

3534333

1 T

O O B

S T

B F N

X A

I S P X A

111224

LOAD

)

( d

a P

1 P S

5 C C V

38 to 45

]

[

S F

T U O V

30292827

E T

A H

2 R Q

E T

A G

3 M W

3 P S

B F

N S

P M O C

N T R B F

4 M W

4 P

2 C T N

T T

V 5

VCC

GND

PWM

BOOT

UGATE

PHASE

LGATE

2 1

2 L

RT9619

VCC

GND

PWM

RT9619

BOOT

UGATE

PHASE

LGATE

2 1

2 L

DS8857/A-00 February 2009www.richtek.com

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Table 1. VR11.1 VID CodeTable

RT8857/A

V ID7 V ID6 VID5 VID4 VID 3 VID2 VID 1 V ID0 Vo lta g e

0 0 0 0 0 0 0 0 OFF 0 0 0 0 0 0 0 1 OFF 0 0 0 0 0 0 1 0 1.60000 0 0 0 0 0 0 1 1 1.59375 0 0 0 0 0 1 0 0 1.58750 0 0 0 0 0 1 0 1 1.58125 0 0 0 0 0 1 1 0 1.57500 0 0 0 0 0 1 1 1 1.56875 0 0 0 0 1 0 0 0 1.56250 0 0 0 0 1 0 0 1 1.55625 0 0 0 0 1 0 1 0 1.55000 0 0 0 0 1 0 1 1 1.54375 0 0 0 0 1 1 0 0 1.53750 0 0 0 0 1 1 0 1 1.53125 0 0 0 0 1 1 1 0 1.52500 0 0 0 0 1 1 1 1 1.51875

VID7VID6 VID5 VID4 VID3 VID2VID1 VID0 Vo ltage

0 0 1 0 0 0 1 1 1.39375 0 0 1 0 0 1 0 0 1.38750 0 0 1 0 0 1 0 1 1.38125 0 0 1 0 0 1 1 0 1.37500 0 0 1 0 0 1 1 1 1.36875 0 0 1 0 1 0 0 0 1.36250 0 0 1 0 1 0 0 1 1.35625 0 0 1 0 1 0 1 0 1.35000 0 0 1 0 1 0 1 1 1.34375 0 0 1 0 1 1 0 0 1.33750 0 0 1 0 1 1 0 1 1.33125 0 0 1 0 1 1 1 0 1.32500 0 0 1 0 1 1 1 1 1.31875 0 0 1 1 0 0 0 0 1.31250 0 0 1 1 0 0 0 1 1.30625

0 0 1 1 0 0 1 0 1.30000 0 0 0 1 0 0 0 0 1.51250 0 0 0 1 0 0 0 1 1.50625 0 0 0 1 0 0 1 0 1.50000 0 0 0 1 0 0 1 1 1.49375 0 0 0 1 0 1 0 0 1.48750 0 0 0 1 0 1 0 1 1.48125 0 0 0 1 0 1 1 0 1.47500 0 0 0 1 0 1 1 1 1.46875 0 0 0 1 1 0 0 0 1.46250 0 0 0 1 1 0 0 1 1.45625 0 0 0 1 1 0 1 0 1.45000 0 0 0 1 1 0 1 1 1.44375 0 0 0 1 1 1 0 0 1.43750 0 0 0 1 1 1 0 1 1.43125 0 0 0 1 1 1 1 0 1.42500 0 0 0 1 1 1 1 1 1.41875 0 0 1 0 0 0 0 0 1.41250

0 0 1 1 0 0 1 1 1.29375

0 0 1 1 0 1 0 0 1.28750

0 0 1 1 0 1 0 1 1.28125

0 0 1 1 0 1 1 0 1.27500

0 0 1 1 0 1 1 1 1.26875

0 0 1 1 1 0 0 0 1.26250

0 0 1 1 1 0 0 1 1.25625

0 0 1 1 1 0 1 0 1.25000

0 0 1 1 1 0 1 1 1.24375

0 0 1 1 1 1 0 0 1.23750

0 0 1 1 1 1 0 1 1.23125

0 0 1 1 1 1 1 0 1.22500

0 0 1 1 1 1 1 1 1.21875

0 1 0 0 0 0 0 0 1.21250

0 1 0 0 0 0 0 1 1.20625

0 1 0 0 0 0 1 0 1.20000

0 1 0 0 0 0 1 1 1.19375 0 0 1 0 0 0 0 1 1.40625 0 0 1 0 0 0 1 0 1.40000

0 1 0 0 0 1 0 0 1.18750

0 1 0 0 0 1 0 1 1.18125

To be continued

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RT8857/A

VID7 VID6 VID5 VID4 VID3 VID2VID1VID0 Voltage

0 1 0 0 0 1 1 0 1.17500 0 1 0 0 0 1 1 1 1.16875 0 1 0 0 1 0 0 0 1.16250 0 1 0 0 1 0 0 1 1.15625 0 1 0 0 1 0 1 0 1.15000 0 1 0 0 1 0 1 1 1.14375 0 1 0 0 1 1 0 0 1.13750 0 1 0 0 1 1 0 1 1.13125 0 1 0 0 1 1 1 0 1.12500 0 1 0 0 1 1 1 1 1.11875 0 1 0 1 0 0 0 0 1.11250 0 1 0 1 0 0 0 1 1.10625 0 1 0 1 0 0 1 0 1.10000 0 1 0 1 0 0 1 1 1.09375 0 1 0 1 0 1 0 0 1.08750 0 1 0 1 0 1 0 1 1.08125

VID7VID6 VID5 VID4 VID3 VID2VID1 VID0 Voltage

0 1 1 0 1 0 1 0 0.95000

0 1 1 0 1 0 1 1 0.94375

0 1 1 0 1 1 0 0 0.93750

0 1 1 0 1 1 0 1 0.93125

0 1 1 0 1 1 1 0 0.92500

0 1 1 0 1 1 1 1 0.91875

0 1 1 1 0 0 0 0 0.91250

0 1 1 1 0 0 0 1 0.90625

0 1 1 1 0 0 1 0 0.90000

0 1 1 1 0 0 1 1 0.89375

0 1 1 1 0 1 0 0 0.88750

0 1 1 1 0 1 0 1 0.88125

0 1 1 1 0 1 1 0 0.87500

0 1 1 1 0 1 1 1 0.86875

0 1 1 1 1 0 0 0 0.86250

0 1 1 1 1 0 0 1 0.85625 0 1 0 1 0 1 1 0 1.07500 0 1 0 1 0 1 1 1 1.06875 0 1 0 1 1 0 0 0 1.06250 0 1 0 1 1 0 0 1 1.05625 0 1 0 1 1 0 1 0 1.05000 0 1 0 1 1 0 1 1 1.04375 0 1 0 1 1 1 0 0 1.03750 0 1 0 1 1 1 0 1 1.03125 0 1 0 1 1 1 1 0 1.02500 0 1 0 1 1 1 1 1 1.01875 0 1 1 0 0 0 0 0 1.01250 0 1 1 0 0 0 0 1 1.00625 0 1 1 0 0 0 1 0 1.00000 0 1 1 0 0 0 1 1 0.99375 0 1 1 0 0 1 0 0 0.98750 0 1 1 0 0 1 0 1 0.98125 0 1 1 0 0 1 1 0 0.97500

0 1 1 1 1 0 1 0 0.85000

0 1 1 1 1 0 1 1 0.84375

0 1 1 1 1 1 0 0 0.83750

0 1 1 1 1 1 0 1 0.83125

0 1 1 1 1 1 1 0 0.82500

0 1 1 1 1 1 1 1 0.81875

1 0 0 0 0 0 0 0 0.81250

1 0 0 0 0 0 0 1 0.80625

1 0 0 0 0 0 1 0 0.80000

1 0 0 0 0 0 1 1 0.79375

1 0 0 0 0 1 0 0 0.78750

1 0 0 0 0 1 0 1 0.78125

1 0 0 0 0 1 1 0 0.77500

1 0 0 0 0 1 1 1 0.76875

1 0 0 0 1 0 0 0 0.76250

1 0 0 0 1 0 0 1 0.75625

1 0 0 0 1 0 1 0 0.75000 0 1 1 0 0 1 1 1 0.96875 0 1 1 0 1 0 0 0 0.96250 0 1 1 0 1 0 0 1 0.95625

1 0 0 0 1 0 1 1 0.74375

1 0 0 0 1 1 0 0 0.73750

1 0 0 0 1 1 0 1 0.73125

DS8857/A-00 February 2009www.richtek.com

To be continued

Page 5

RT8857/A

VID7 VID6 VID5 VID4 VI D3 VID2 VID1 VID 0 Voltage

1 0 0 0 1 1 1 0 0.72500 1 0 0 0 1 1 1 1 0.71875 1 0 0 1 0 0 0 0 0.71250 1 0 0 1 0 0 0 1 0.70625 1 0 0 1 0 0 1 0 0.70000 1 0 0 1 0 0 1 1 0.69375 1 0 0 1 0 1 0 0 0.68750 1 0 0 1 0 1 0 1 0.68125 1 0 0 1 0 1 1 0 0.67500 1 0 0 1 0 1 1 1 0.66875 1 0 0 1 1 0 0 0 0.66250 1 0 0 1 1 0 0 1 0.65625 1 0 0 1 1 0 1 0 0.65000 1 0 0 1 1 0 1 1 0.64375 1 0 0 1 1 1 0 0 0.63750 1 0 0 1 1 1 0 1 0.63125

VID7VID6 VID5 VID4 VID3 VID2VID1 VID0 Vo ltage

1 0 1 1 0 0 1 0 0.50000

1 1 1 1 1 1 1 0 OFF

1 1 1 1 1 1 1 1 OFF

1 0 0 1 1 1 1 0 0.62500 1 0 0 1 1 1 1 1 0.61875 1 0 1 0 0 0 0 0 0.61250 1 0 1 0 0 0 0 1 0.60625 1 0 1 0 0 0 1 0 0.60000 1 0 1 0 0 0 1 1 0.59375 1 0 1 0 0 1 0 0 0.58750 1 0 1 0 0 1 0 1 0.58125 1 0 1 0 0 1 1 0 0.57500 1 0 1 0 0 1 1 1 0.56875 1 0 1 0 1 0 0 0 0.56250 1 0 1 0 1 0 0 1 0.55625 1 0 1 0 1 0 1 0 0.55000 1 0 1 0 1 0 1 1 0.54375 1 0 1 0 1 1 0 0 0.53750 1 0 1 0 1 1 0 1 0.53125 1 0 1 0 1 1 1 0 0.52500 1 0 1 0 1 1 1 1 0.51875 1 0 1 1 0 0 0 0 0.51250 1 0 1 1 0 0 0 1 0.50625

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RT8857/A

Table 2. Output Voltage Program (VRD10.x + VID6)

Pin Name

VID4 VID3 VID2 VID1 VID0 VID5 VID6

0 1 0 1 0 1 1 1.60000V 0 1 0 1 0 1 0 1.59375V 0 1 0 1 1 0 1 1.58750V 0 1 0 1 1 0 0 1.58125V 0 1 0 1 1 1 1 1.57500V 0 1 0 1 1 1 0 1.56875V 0 1 1 0 0 0 1 1.56250V 0 1 1 0 0 0 0 1.55625V 0 1 1 0 0 1 1 1.55000V 0 1 1 0 0 1 0 1.54375V 0 1 1 0 1 0 1 1.53750V 0 1 1 0 1 0 0 1.53125V 0 1 1 0 1 1 1 1.52500V 0 1 1 0 1 1 0 1.51875V 0 1 1 1 0 0 1 1.51250V 0 1 1 1 0 0 0 1.50625V 0 1 1 1 0 1 1 1.50000V 0 1 1 1 0 1 0 1.49375V 0 1 1 1 1 0 1 1.48750V 0 1 1 1 1 0 0 1.48125V 0 1 1 1 1 1 1 1.47500V 0 1 1 1 1 1 0 1.46875V 1 0 0 0 0 0 1 1.46250V 1 0 0 0 0 0 0 1.45625V 1 0 0 0 0 1 1 1.45000V 1 0 0 0 0 1 0 1.44375V 1 0 0 0 1 0 1 1.43750V 1 0 0 0 1 0 0 1.43125V 1 0 0 0 1 1 1 1.42500V 1 0 0 0 1 1 0 1.41875V 1 0 0 1 0 0 1 1.41250V 1 0 0 1 0 0 0 1.40625V 1 0 0 1 0 1 1 1.40000V 1 0 0 1 0 1 0 1.39375V 1 0 0 1 1 0 1 1.38750V 1 0 0 1 1 0 0 1.38125V 1 0 0 1 1 1 1 1.37500V 1 0 0 1 1 1 0 1.36875V 1 0 1 0 0 0 1 1.36250V

Nominal Output Voltage DACOUT

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To be continued

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RT8857/A

Pin Name

VID4 VID3 VID2 VID1 VID0 VID5 VID6

1 0 1 0 0 0 0 1.35625V 1 0 1 0 0 1 1 1.35000V 1 0 1 0 0 1 0 1.34375V 1 0 1 0 1 0 1 1.33750V 1 0 1 0 1 0 0 1.33125V 1 0 1 0 1 1 1 1.32500V 1 0 1 0 1 1 0 1.31875V 1 0 1 1 0 0 1 1.31250V 1 0 1 1 0 0 0 1.30625V 1 0 1 1 0 1 1 1.30000V 1 0 1 1 0 1 0 1.29375V 1 0 1 1 1 0 1 1.28750V 1 0 1 1 1 0 0 1.28125V 1 0 1 1 1 1 1 1.27500V 1 0 1 1 1 1 0 1.26875V 1 1 0 0 0 0 1 1.26250V 1 1 0 0 0 0 0 1.25625V 1 1 0 0 0 1 1 1.25000V 1 1 0 0 0 1 0 1.24375V 1 1 0 0 1 0 1 1.23750V 1 1 0 0 1 0 0 1.23125V 1 1 0 0 1 1 1 1.22500V 1 1 0 0 1 1 0 1.21875V 1 1 0 1 0 0 1 1.21250V 1 1 0 1 0 0 0 1.20625V 1 1 0 1 0 1 1 1.20000V 1 1 0 1 0 1 0 1.19375V 1 1 0 1 1 0 1 1.18750V 1 1 0 1 1 0 0 1.18125V 1 1 0 1 1 1 1 1.17500V 1 1 0 1 1 1 0 1.16875V 1 1 1 0 0 0 1 1.16250V 1 1 1 0 0 0 0 1,15625V 1 1 1 0 0 1 1 1.15000V 1 1 1 0 0 1 0 1.14375V 1 1 1 0 1 0 1 1.13750V 1 1 1 0 1 0 0 1.13125V 1 1 1 0 1 1 1 1.12500V 1 1 1 0 1 1 0 1.11875V

Nominal Output Voltage DACOUT

To be continued

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RT8857/A

Pin Name

VID4 VID3 VID2 VID1 VID0 VID5 VID6

1 1 1 1 0 0 1 1.11250V 1 1 1 1 0 0 0 1.10625V 1 1 1 1 0 1 1 1.10000V 1 1 1 1 0 1 0 1.09375V 1 1 1 1 1 0 1 OFF 1 1 1 1 1 0 0 OFF 1 1 1 1 1 1 1 OFF 1 1 1 1 1 1 0 OFF 0 0 0 0 0 0 1 1.08750V 0 0 0 0 0 0 0 1.08125V 0 0 0 0 0 1 1 1.07500V 0 0 0 0 0 1 0 1.06875V 0 0 0 0 1 0 1 1.06250V 0 0 0 0 1 0 0 1.05625V 0 0 0 0 1 1 1 1.05000V 0 0 0 0 1 1 0 1.04375V 0 0 0 1 0 0 1 1.03750V 0 0 0 1 0 0 0 1.03125V 0 0 0 1 0 1 1 1.02500V 0 0 0 1 0 1 0 1.01875V 0 0 0 1 1 0 1 1.01250V 0 0 0 1 1 0 0 1.00625V 0 0 0 1 1 1 1 1.00000V 0 0 0 1 1 1 0 0.99375V 0 0 1 0 0 0 1 0.98750V 0 0 1 0 0 0 0 0.98125V 0 0 1 0 0 1 1 0.97500V 0 0 1 0 0 1 0 0.96875V 0 0 1 0 1 0 1 0.96250V 0 0 1 0 1 0 0 0.95625V 0 0 1 0 1 1 1 0.95000V 0 0 1 0 1 1 0 0.94375V 0 0 1 1 0 0 1 0.93750V 0 0 1 1 0 0 0 0.93125V 0 0 1 1 0 1 1 0.92500V 0 0 1 1 0 1 0 0.91875V 0 0 1 1 1 0 1 0.91250V 0 0 1 1 1 0 0 0.90625V 0 0 1 1 1 1 1 0.90000V

Nominal Output Voltage DACOUT

To be continued

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RT8857/A

Pin Name

VID4 VID3 VID2 VID1 VID0 VID5 VID6

0 0 1 1 1 1 0 0.89375V 0 1 0 0 0 0 1 0.88750V 0 1 0 0 0 0 0 0.88125V 0 1 0 0 0 1 1 0.87500V 0 1 0 0 0 1 0 0.86875V 0 1 0 0 1 0 1 0.86250V 0 1 0 0 1 0 0 0.85625V 0 1 0 0 1 1 1 0.85000V 0 1 0 0 1 1 0 0.84375V 0 1 0 1 0 0 1 0.83750V 0 1 0 1 0 0 0 0.83125V

Nominal Output Voltage DACOUT

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RT8857/A

VID4 VID3 VID2 VID1 VID0 Nominal Output Voltage DACOUT

0 0 0 0 0 1.550 0 0 0 0 1 1.525 0 0 0 1 0 1.500 0 0 0 1 1 1.475 0 0 1 0 0 1.450 0 0 1 0 1 1.425 0 0 1 1 0 1.400 0 0 1 1 1 1.375 0 1 0 0 0 1.350 0 1 0 0 1 1.325 0 1 0 1 0 1.200 0 1 0 1 1 1.275 0 1 1 0 0 1.250

Table 3. Output Voltage Program (K8)

0 1 1 0 1 1.225 0 1 1 1 0 1.200 0 1 1 1 1 1.175 1 0 0 0 0 1.150 1 0 0 0 1 1.125 1 0 0 1 0 1.100 1 0 0 1 1 1.075 1 0 1 0 0 1.050 1 0 1 0 1 1.025 1 0 1 1 0 1.000 1 0 1 1 1 0.975 1 1 0 0 0 0.950 1 1 0 0 1 0.925 1 1 0 1 0 0.900 1 1 0 1 1 0.875 1 1 1 0 0 0.850 1 1 1 0 1 0.825

1 1 1 1 0 0.800 1 1 1 1 1 Shutdown

Note: (1) 0 : Connected to GND

(2) 1 : Open

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Table 4. Output Voltage Program (K8_M2)

RT8857/A

Pin Name

VID5 VID4 VID3 VID2 VID1 VID0

0 0 0 0 0 0 1.5500 0 0 0 0 0 1 1.5250 0 0 0 0 1 0 1.5000 0 0 0 0 1 1 1.4750 0 0 0 1 0 0 1.4500 0 0 0 1 0 1 1.4250 0 0 0 1 1 0 1.4000 0 0 0 1 1 1 1.3750 0 0 1 0 0 0 1.3500 0 0 1 0 0 1 1.3250 0 0 1 0 1 0 1.3000 0 0 1 0 1 1 1.2750 0 0 1 1 0 0 1.2500 0 0 1 1 0 1 1.2250 0 0 1 1 1 0 1.2000

Nominal Output Voltage DACOUT

0 0 1 1 1 1 1.1750 0 1 0 0 0 0 1.1500 0 1 0 0 0 1 1.1250 0 1 0 0 1 0 1.1000 0 1 0 0 1 1 1.0750 0 1 0 1 0 0 1.0500 0 1 0 1 0 1 1.0250 0 1 0 1 1 0 1.0000 0 1 0 1 1 1 0.9750 0 1 1 0 0 0 0.9500 0 1 1 0 0 1 0.9250 0 1 1 0 1 0 0.9000 0 1 1 0 1 1 0.8750 0 1 1 1 0 0 0.8500 0 1 1 1 0 1 0.8250 0 1 1 1 1 0 0.8000 0 1 1 1 1 1 0.7750 1 0 0 0 0 0 0.7625 1 0 0 0 0 1 0.7500

To be continued

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RT8857/A

Pin Name

VID5 VID4 VID3 VID2 VID1 VID0

1 0 0 0 1 0 0.7375 1 0 0 0 1 1 0.7250 1 0 0 1 0 0 0.7125 1 0 0 1 0 1 0.7000 1 0 0 1 1 0 0.6875 1 0 0 1 1 1 0.6750 1 0 1 0 0 0 0.6625 1 0 1 0 0 1 0.6500 1 0 1 0 1 0 0.6375 1 0 1 0 1 1 0.6250 1 0 1 1 0 0 0.6125 1 0 1 1 0 1 0.6000 1 0 1 1 1 0 0.5875 1 0 1 1 1 1 0.5750 1 1 0 0 0 0 0.5625

Nominal Output Voltage DACOUT

1 1 0 0 0 1 0.5500 1 1 0 0 1 0 0.5375 1 1 0 0 1 1 0.5250 1 1 0 1 0 0 0.5125 1 1 0 1 0 1 0.5000 1 1 0 1 1 0 0.4875 1 1 0 1 1 1 0.4750 1 1 1 0 0 0 0.4625 1 1 1 0 0 1 0.4500 1 1 1 0 1 0 0.4375 1 1 1 0 1 1 0.4250 1 1 1 1 0 0 0.4125 1 1 1 1 0 1 0.4000 1 1 1 1 1 0 0.3875

1 1 1 1 1 1 0.3750

Note: (1) 0 : Connected to GND

(2) 1 : Open (3) The voltage above are load independent for desktop and server platforms. For mobile platforms the voltage above

correspond to zero load current.

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Page 13

Functional Pin Description

Pin No. Pin Name Pin Function

1 FBRTN Negative Remote Sense Pin of Output Voltage. 2 QR1 Quick Response Setting Pins for Load Transition. 3 QR2 Quick Response Setting Pins for Load Transition.

4 SS/EN 5 COMP Output of error-amp and input of PWM comparator.

6 FB Inv erting input of error-amp. 7 OFS Connect this pin to GND or 5V by a resistor to set no-load offset voltage. 8 RT Connect this pin to GND by a resistor to adjust frequency.

9 ADJ Connect this pin to GND by a resistor to set load line. 10 IMAX 11 IMAXPSI OCP Setting in Power Saving Mode.

12 IMONFB Current Monitor Gain/Offset Adjustment. 13 IMON Current Monitor Output.

14, 17, 18, 21 ISP4, ISP3, ISP2, ISP1 Positive current sense pin of channel 1, 2, 3 and 4. 15, 16, 19, 20 ISN4, ISN3, ISN2, ISN1 Negative current sense pin of channel 1, 2, 3 and 4.

22 VRHOT Temperature Monitor Output. 23 TS EN Temperatur e Sense Input. 24 VCC5 5V LDO Output for System Power Supply.

25, 26 PWM4, PWM3 PWM Output for Channel 4 and Channel 3. 27, 35 BOOT2, BOOT1 Bootstrap Supply for Channel 2 and Channel 1. 28, 34 UGATE2, UGATE1 Upper Gate Driver for Channel 2 and Channel 1. 29, 33 PHASE2, PHASE1 Switching Node of Channel 2 and Channel 1. 30, 32 LGATE2, LGATE1 Lower Gate Driver for Channel 2 and Channel 1.

31 VCC12 IC Power Supply. Connect to 12V. 36 PWRGD Power Good Indicator. 37 EN/VTT VTT Voltage Detector Input.

38 to 45 VID7 to VID0 Voltage Identification Input for DAC.

47 PSI Power Status Indicator II. 48 VOUT Feedback of Regulated Output. 46 VIDSEL VID DAC Selection Pin. 49

(Exposed pad)

GND

Connect this pin to GND by a capacitor to adjust soft start time. Pull this pin to GND to disable controller.

Negati ve input of OCP comparator. (Positive input of OCP comparator is ADJ).

The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation.

RT8857/A

VID Table Selection

VIDSEL VID [7] Table

VTT X VR11

GND X VR10.x VCC5 VTT K8 VCC5 GND K8_M2

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RT8857/A

Function Block Diagram

COMP

OFS

VOUT

QR1/QR2

SS/EN

EN/VTT

VIDOFF

Modulator Waveform Generator

Offset

Transient

Response

Enhancement

OV OC

POR

850mV

150mV

Soft Start

and

Fault

Logic

POR

Power-On

Reset

Regulator

I_SEN1

MOSFET

Driver

MOSFET

Driver

CH1 Current SENSE

VCC12

VCC5

BOOT1 UGATE1 PHASE1 LGATE1

BOOT2 UGATE2 PHASE2 LGATE2

PWM3

PWM4

PSI

ISP1 ISN1

VIDSEL

VID7 to VID0

FBRTN

ADJ

IMAX/

IMAXPSI

IMONFB

GND

VID

Table

Generator

Load Current

Monitor

IMON

Temperature

Monitor

TSEN

I_SEN2

AVG

I_SEN3

I_SEN4

CH2 Current SENSE

CH3 Current SENSE

CH4 Current SENSE

ISP2 ISN2

ISP3 ISN3

ISP4 ISN4

VRHOT

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RT8857/A

Absolute Maximum Ratings (Note 1)

 Supply Input Voltage----------------------------------------------------------------------------------------------−0.3V to 15V  BOOTx to PHASEx-----------------------------------------------------------------------------------------------−0.3V to 15V  BOOTx to GND

DC---------------------------------------------------------------------------------------------------------------------−0.3V to 30V < 200ns --------------------------------------------------------------------------------------------------------------−0.3V to 42V

 PHASEx to GND

DC---------------------------------------------------------------------------------------------------------------------−2V to 15V < 200ns --------------------------------------------------------------------------------------------------------------−5V to 30V

 Input/Output V oltage---------------------------------------------------------------------------------------------- −0.3V to (VCC5 +0.3)V  Power Dissipation, P

WQFN−48L 7x7---------------------------------------------------------------------------------------------------- 3.226W

 Package Thermal Resistance (Note 4)

WQFN−48L 7x7, θJA----------------------------------------------------------------------------------------------31°C/W

 Junction T emperature--------------------------------------------------------------------------------------------- 150°C  Lead Temperature (Soldering, 10 sec.)-----------------------------------------------------------------------260°C  ESD Susceptibility (Note 2)

HBM (Human Body Mode) --------------------------------------------------------------------------------------2kV MM (Ma chine Mode)---------------------------------------------------------------------------------------------- 200V

@ T

= 25°C

Recommended Operating Conditions (Note 3)

 Supply V oltage, VCC12------------------------------------------------------------------------------------------ 12V ± 10%  Junction T emperature Range------------------------------------------------------------------------------------−40°C to 125°C  Ambient T emperature Range------------------------------------------------------------------------------------

0°C to 70°C

Electrical Characteristics

(VCC12 = 12V, V

Parameter Symbol Conditions Min Typ Max Unit

VCC12 Supply Input

VCC12 Supply Voltage VCC12 10.8 12 13.2 V VCC12 Supply Current ICC -- 6 -- mA

VCC5 Power

VCC5 Supply Voltage VCC5 I VCC5 Output Sourcing I

P ower-On Rese t

VCC12 Rising Threshold V VCC12 Hysteres is V

Load Current Monitor

IMON Maximum Output Voltage

EN/VTT

EN/VTT Rising Threshold V Enable Hyster esis V

= 0V, TA = 25°C, unless otherwise specified)

GND

= 10mA (Note 6) 4.75 5.0 5.25 V

LOAD

10 -- -- mA

VCC5

VCC12TH VCC12HY

VCC12 Rising 9.2 9.6 10.0 V

VCC12 Falling -- 0.9 -- V

EN/VTT Rising 0.80 0.85 0.90 V

ENVTT ENVTTHY

EN/VTT Falling -- 100 -- mV

VTT

(Note 5)

-- V

To be continued

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Page 16

RT8857/A

Parameter Symbol Conditions Min Typ Max Unit

Reference Voltage accuracy

1V to 1.6V 0.5 -- +0.5 %

DA C Accu ra cy

Error Amplifier

DC Gain ADC No Load -- 80 -- dB Gain-Bandwidth GBW C Slew Rate SR C

Output vo ltag e rang e V Max Current I

COMP

EA_SLEW

Power Sequence

0.8V to 1V 5 -- +5 mV

0.5V to 0.8V 8 -- +8 mV

= 10pF -- 10 -- MHz

LOAD

= 10pF 10 -- -- V/us

LOAD

0.5 3.6 V Slew 300 -- -- uA

PWRGD Low Voltage V

PGOOD

PWRGD

= 4mA -- -- 0.4 V Soft-Start Delay TD1 -- 2 -- ms V

Duration TD3 -- 0.8 -- ms

BOOT

PWRGD Delay TD5

Me asur ed the ti me fo rm V to PWRGD = 1

BOOT

chang e

-- 1.6 -- ms

Current Sens e Am plifier

= 1.3V

Max Current I Input Offset Voltage V

Running Frequency f

GMMAX

2 0 +2 mV

OSCS

OSC

R T Pin Voltage VRT R Ramp Slope V

RAMP

CSP

Sink Current from CSN

= 40k 270 300 330 kHz

= 40k 0.76 0.8 0.84 V

= 40k -- 22 -- %/V

100 -- -- uA

Soft Start

Soft Start Current I VID Change Current I

Slew 12 16 20 uA

SS1

Slew 120 160 200 uA

SS2

Gate Driver

UGATE Drive Source R

UGATE Drive Sink R LGATE Drive Source R

LGATE Drive Sink R

UGATEsr

UGATEsk

LGATEsr LGATEsk

BOOT  PHASE = 8V 250mA Source Current BOOT PHASE = 8V 250mA Sink Current

= 8V -- 1 -- 

LGATE

-- 1 -- 

250mA Sink Current -- 0.8 -- 

Protection

Over-Voltage Threshold V O ver-Cu rrent Threshol d V

Sweep FB Voltage, VFB  V

OVP

Sweep IMAX Voltage, V

OCP

IMAX

125 150 175 mV

EAP

 V

10 0 +10 mV

ADJ

Dynamic Characteristic

UGATE Rise Time t

UGATE Fall Time t LGATE Rise Time t LGATE Fall Time t

rUGATE

fUGATE rLGATE fLGATE

-- 10 -- ns Ciss = 3000p

-- 15 -- ns

-- 10 -- ns

-- 15 -- ns

To be continued

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Page 17

RT8857/A

Parameter Symbol Conditions Min Typ Max Unit

Input Threshold

VID7 to VID0, VIDSEL Rising Threshold

VID7 to VID0 Hysteresis V PSI Rising Threshold

Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for

stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability.

Note 2. Devices are ESD sensitive. Handling precaution is recommended. Note 3. The device is not guaranteed to function outside its operating conditions. Note 4. θ

Note 5. The maximum output voltage of power monitor will be restricted by EN/VTT pin input voltage. Note 6. Test condition : RT8857/A normal operating, an extra static DC current load 10mA applying at VCC5 pin.

is measured in the natural convection at TA = 25°C on a effective single layer thermal conductivity test board of

JEDEC thermal measurement standard.

ID7 to 0

IDSEL ID7 to 0_Hy

PSI

VID7 to VID0 Rising,

VID SEL Ris in g

VID7 to VID0 Falling -- 25 -- mV

PSI Rising

1/2V

12.5mV

1/2V

12.5mV

-- V

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RT8857/A

Application Information

RT8857/A is a 4/3/2/1-phase synchronous buck DC/DC converter with 2 embedded MOSFET drivers. The internal VID DAC is designed to interface with the Intel VR11.x/

10.x and AMD K8/K8_M2 compatible CPUs.

1200

1000

800

Frequency vs. R

Power Ready Detection

During start-up, RT8857/A will dete ct VCC12, VCC5 an d VTT. When VCC12 > 9.6V , VCC5 > 4.6V and VTT > 0.85V , POR will go high. POR (Power On Reset) is the internal signal to indicate all powers are ready to let RT8857/A and the companioned MOSFET drivers work properly. When POR = L, RT8857/A will try to turn off both high side and low side MOSFETs.

VCC12

VCC5

9.6V

4.6V

0.85V

CMP

POR : Power On Reset

CMP

POR

Figure 1. Circuit for Power Ready Detection

Phase Detection

The number of operational phas e s is determined by the internal circuitry that monitors the ISNn voltages during start up. Normally, the RT8857/A operates as a 4-phase PWM controller. Pull ISN4 and ISP4 to VCC5 programs 3-phase operation, pull ISN3 a nd ISP3 to VCC5 progra ms 2-phase operation, and pull ISN2 and ISP2 to VCC5 programs 1-pha se operation. RT8857/A detects the voltage of ISN4, ISN3 and ISN2 at POR rising edge. At the rising edge, RT8857/A detects whether the voltage of ISN4, ISN3 and ISN2 are higher than “VCC5 − 1V” respectively to decide how many phases should be active. Phase detection is only active during start up. When POR = H, the number of operational phases is determined and latched. The unused PWM pins can be connected to 5V or GN D or left floating.

600

400

Frequency ( kH z)

200

0 40 80 120 160 200 240 280

RRT (k ohm)

(kΩ)

Figure 2. RRT vs Phase Switching Frequency

Soft Start

Output current of OPSS (I

DAC

OPSS

) is limited and variant

SSQ

ADJ

NTC

EAP

(ErrorAmp positive input)

Figure 4. Circuit for Soft Start and Dyn amic VID

The V

start-up time is set by a capacitor from the SS

OUT

pin to GND. In power_on_re set state (POR = L), the SS pin is held at GND. After power_on_reset stae (POR = H) and a n extra delay 1600us, VSS and V V

SSQ

= V

BOOT

. When V

SSQ

= V

BOOT

begin to rise till

SSQ

, RT8857/A stays in this state for 800us waiting for valid VID code sent by CPU. After receiving valid VID code, V

continues

OUT

ramping up or down to the voltage spe cified by VID code. Before PWRGD = H, output current of OPSS (ISS) is limited to 8uA (ISS1). When PWR G D = H, ISS is limited to 80uA (ISS2). The soft start waveform is shown in Figure 5.

Phase Switching Frequency

The phase switching frequency of the R T8857/A is set by an external resistor connected from the RT pin to GND. The frequency follows the gra ph in Figure 2.

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Page 19

RT8857/A

VCC12

VCC5

DAC

SSQ

PWRGD

0.85V

9.6V

4.6V

T1 T2 T3

T4 T5

Figure 5. Soft Start Waveforms

will trace V

OUT

is a small voltage signal which is proportional to

ADJ

. This voltage is used to generate loadline a nd will be

OUT

which is equal to “V

EAP

SSQ

− V

described later. T1 is the delay time from power_on_reset state to the beginning of V

T1 = 1600μs + 0.6V x C T2 is the soft start time from V

rising.

OUT

/ I

(1)

SS1

= 0 to V

OUT

= V

SS SSQ

ADJ

BOOT

”.

Output Voltage Differential Sensing

The RT8857/A uses differential sensing by a high gain low offset ErrorAmp. The CPU voltage is sensed between

the FB and FBRT N pins. A resistor (RFB) connects FB pin and the positive remote sense pin of the CPU (V

CCP

FBRT N pin connects to the negative remote sense pin of CPU (V V

DAC

) directly. The ErrorAmp compares EAP (=

CCN

−V

) with the VFB to regulate the output voltage.

ADJ

No-Load Offset

In Figure 6, I offset. Either I

OFSN

or I

are used to generate no-load

OFSP

is active during normal operation.

OFSP

It should be noted that users can only enable one polarity of no-load offset. Do not connect OFS pin to GND and to V

at the same ti me. Conne ct a resistor from OFS pin

CC5

to GND to activate I

OFSN

. I

flows through R

OFSN

ADJ

from ADJ pin to GND. In this ca se, negative no-load offset voltage (V

) is generated.

OFSN

= I

OFSN

x R

= 0.8 x R

ADJ

ADJ/ROFS

(4)

T2 = V T3 is the dwelling time for V T4 is the soft start time from V T4 ~= |V

BOOT

DAC

x C

- V

/ I

BOOT

(2)

SS1

OUT

= V

OUT

= V

BOOT

. T3 = 800us.

to V

| x CSS/ISS1 (3)

OUT

= V

DAC

T5 is the power good delay time, T5 ~= 1600us.

Dynamic VID

The RT8857/A can accept VID input changing while the controller is running. This allows the output voltage (V

OUT

to change while the DC/DC converter is running and supplying current to the load. This is commonly referred to as VID on-the-fly (OTF). A VID OTF can occur under either light or heavy load conditions. The CPU changes the VID inputs in multiple steps from the start code to the finish code. This change can be positive or negative. Theoretically , V

should follow V

OUT

which is a staircase

DAC

waveform. In RT8857/A, a s mentioned in soft start session, V

slew rate is limited by ISS2/CSS when PWR GD = H.

DAC

This slew rate limiter works as a low pass filter of V and makes the bandwidth of V smoothening V

staircase wavef orm, V

DAC

waveform finite. By

DAC

will no longer

OUT

DAC

overshoot or undershoot. On the other hand, CSS will increa se the settling time of V

during VID OTF . In most

OUT

cas es, 1nF to 30nF cera mic capacitor is suitable for CSS.

Connect a resistor from OFS pin to VCC5 to activate I I

flows through RFB from the V

OFSP

case, positive no-loa d offset voltage (V

to FB pin. In this

CCP

) is generated.

OFSP

When positive no-load offset is selected, the RT8857/A will generate another internal 8uA current source to eliminate dead zone problem of droop function. This 8uA current will be injected into ADJ resistors, producing a small initial negative no-load offset. Therefore, when OFS pin is connected to VCC5 through a resistor , the positive

)

no-load offset ca n be calculated as :

VIR8uAR

6.4 8uA R



OFSP OFSP FB ADJ

  

OFS

RT8857/A provides wide range no-load positive of fset for over-clocking application s. The I

cap ability can supply

OFSP

from 30uA to 640uA, which mea n s in Equation (5), R can ra nge from 240kΩ to 10kΩ. Other resistances of R exceeding this range can also provide no-load positive offset but cannot be guara nteed by Equation (5).

OFSP

(5)

OFS OFS

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RT8857/A

CCP

(Positive remote

sense pin of CPU)

(Negative remote

sense pin of CPU)

CCN

ADJ

Figure 6. Circuit for V

OFSP

DAC

FBRTN

ADJ

Differential Sensing and No

OUT

EAP

OFSN

COMP

Load Offset

Load T r ansient Quick Response

RT8857/A utilizes a new quick response feature to supply heavy load current demand during instantaneous load application tra nsient. RT8857/A detects load tra nsient and reacts via VOUT pin. When VOUT drops during load application transient,the quick response comparator will send asserted sign als to turn on high side MOSFET s a nd turn off low side MOSFETs. The LA1 signal, which is a weaker quick response sign al, will turn on only arbitrary two channels', high side MOSFETs while turning off low side MOSFET s also. The LA2 signal , which is a stronger quick response signal, will turn on all channel's high side MOSFETs while turning off low side MOSFETs also. Therefore, the influence of total quick response function of RT8857/A is adjustable, and the magnitude of quick response is flexible via fine-tuning the resistors connected to pin QR1 and QR2.

OUT

Output Current Sensing

The RT8857/A provides low input offset current-sense amplifier (CSA) to monitor the output current of every channel. Output current of CSA (IX[n]) is used for channel current balance a nd active voltage position. In this inductor current sensing topology , RS and CS must be set according to the equation below :

L/DCR = RS x CS (6) Then the output current of CSA will follow the equation

below : IX = [IL x DCR − V /R

(7)

CSN

OFS-CSA

+ 235n x (R

CSP

− R

CSN

)]

235nA is typical value of CSA input offset current. V

OFS-CSA

RT8857/A is smaller than +/- 1mV. Usually, “V 235n x (R

is the input offset voltage of CSA. V

CSP

− R

)” is negligible except at very light

CSN

OFS-CSA

load and the equation can be simplified as the equation below :

IX = IL x DCR/R

(8)

CSN

Loadline

Output current of CSA is summed and averaged in RT8857/A. Then 0.5Σ(IX[n]) is sent to ADJ pin. Because ΣIX[n] is a PTC (Positive T emperature Coef ficient) current, an NTC (Negative Temperature Coefficient) resistor is needed to connect ADJ pin to GND. If the NTC resistor is properly selected to compensate the temperature coefficient of IX[n], the voltage on ADJ pin will be proportional to I A, the positive input of ErrorAmp is “V will follow “V decreasing linearly with I

without temperature effect. In RT8857/

OUT

− V

DAC

− V

DAC

”, too. Thus, the output voltage

ADJ

is obtained. The loadline is

OUT

ADJ

”. V

OUT

defined as LL(loadline) = ΔV = 0.5 x DCR x R

OUT

/ΔI

OUT

= ΔV

/ΔI

ADJ

ADJ/RCSN

OUT

(9)

QR2

QR1

Figure 7

Briefly, the resistance of R loadline. The temperature coefficient of R

sets the resistance of

ADJ

compensates

ADJ

the temperature effect of loadline.

Current Balance

In Figure 8, IX[n] is the current signal which is proportional to current flowing through channel n. In Figure 9, the

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RT8857/A

current error signals I

n (= IX[n] − A V G(IX[n])) are used

ERR

to raise or lower the internal sawtooth waveforms (RAMP[1] to RAMP[n]) which are compared with ErrorAmp output (COMP) to generate PWM signal. The raised sawtooth waveform will decrease the PWM duty of the corresponding channel while the lowered will increase. Eventually , current flowing through each channel will be balanced.

DCR

CSA: Current Sense Amplifier

235nA

OFS_CSA

235nA

ISP

ISN

ISP

ISN

Figure 8. Circuit for Channel Current Sensing

COMP

, total

OUT

Constant ra tio

, total

OUT

Constant difference

Figure 10. Channel Current vs. Total Current

Over Current Protection (OCP)

RT8857/A provides sing phase OCP and multi-pha se OCP according to the operation condition. In Figure 1 1, single phase OCP (IMAXPSI) and multi-phase OCP (IMAX) thresholds can be set by external resistors :

RAMP[1]

Interleaved

RAMP[n]

ERR

[1] x R

[n] x R

CMP

BUF

PWM[1]

PWM[n]

Figure 9. Circuit for Channel Current Bala nce

Channel Current Adjust

If channel current is not bala nced due to asymmetric PCB layout of power stage, external resistors can be adjusted to correct current imbalance. Figure 10 shows two type s of current imbalance, constant ratio type and constant difference type.

If the initial current distribution is constant ratio type, according to Equation (8), reduce R

[1] can reduce IL[1]

CSN

and improve current bala nce. If the initial current distribution is constant difference type, according to Equation (7),

increase R

[1] can reduce IL[1] and improve current

CSP

balance.



IMAX CC5

IMAXPSI CC5

Once V



is larger than the negative input of CP

ADJ

R2 + R3

R1 + R2 + R3

(10)

(1 1)

comparator, OCP will be triggered and latched, and RT8857/A will turn off both high side and low side MOSFETs of all channels. A 20us delay after OCP detection is used to prevent false trigger.

Over Voltage Protectiom (OVP)

The over voltage protection monitors the output voltage via the FB pin. Once VFB exceeds “V

+ 150mV”, OVP

EAP

is triggered and latched. RT8857/A will try to turn on low side MOSFET and turn of f high side MOSFET to protect CPU. A 20us delay is used in OVP detection circuit to prevent false trigger.

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RT8857/A

CC5

IMAX

IMAXPSI

Figure 1 1. Over Current Protection

ADJ

CC5

0.28 x V

0.33 x V

CC5

VRHOT

OCP

NTC

TSEN

Figure 13. Thermal Monitoring

Output Current Monitoring (IMON)

RT8857/A sen ses load current and output a voltage signal to indicated the instanta neous load current status. Since the sensed total current is injected into the resistors connected to ADJ pin, ADJ voltage than is used for IMON function as shown in Figure 12. Through the resistor network R1, R2 and R3, IMON voltage will be proportional to ADJ pin voltage a ccording to the Equation :

VVV



IMON ADJ TT

R3 R3

R1 // R2 // R3 R1

ADJ

IMONFB

IMON

(12)

Figure 12. Output Current Monitoring

Thermal Monitoring (VRHOT)

RT8857/A provides thermal monitoring function via sensing TSEN pin voltage. Through the voltage divider R1 a nd R

NTC

the voltage of TSEN is typically set to be higher than

0.33 x V

when ambient temperature is lower than

CC5

VRHOT a ssertion target. When a mbient temperature rises, TSEN voltage will fall, and VRHOT signal will be set to high if TSEN voltage drops below 0.28 x V

CC5

. Accordingly, VRHOT will be reset to low once TSEN voltage rises above 0.33 x V resistance of R1 a nd R

can a ssert and de-a ssert VRHOT

NTC

. Correctly choose the

CC5

accurately at target a mbient te mperature.

Power State Indicator (PSI)

The RT8857/A supports PSI# function for V R11.1 CPUs and platform users. The RT8857/A will monitor PSI pin input voltage to change the operating state. When PSI is high (higher than 1/2 V

+ 12.5mV), the RT8857/A

operates as a full-cha nnel interleaving PWM controller and all channels are a ctive. When in put voltage is low (lower than V

+ 12.5mV), the RT8857/A will change to single

phase operation mode a nd only channel 1 is a ctive. Since channel 2 includes embedded driver, the RT8857/A will automatically disable channel 2 by f orcing UGATE2 and LGA TE2 into high impedance state when input voltage is low. The R T8857/A will also disable cha nnel 3 and cha nnel 4 by sending continuous tri-state signals (~2.5V) from PWM3 and PWM4 to external drivers when input voltage is low. Therefore, 2 external drivers which support tri-state shutdown should be used if PSI function is considered, and the RT9619 is recommended to be the extern al drivers for VR11.1 compatibility.

During PSI asserted period, e.g., in put voltage is low, if the RT8857/A receives dynamic VID change command, the RT8857/A will enter interle aving mode operation and all channels will be a ctivated. PSI command will be ignored during dyna mic VID operation, and PSI will be bla nked for about 100us after dyna mic VID cha nge is completed.

Loop Compensation

The RT8857/A is a synchronous Buck converter with two control loops : voltage loop and current balance loop. Since the function of the current balance loop is to maintain the current balance between ea ch active cha nnel, its influence to converter stability will be negligible compared with the voltage feedback loop. Therefore, to compensate the

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Page 23

RT8857/A

voltage loop will be the main task to maintain converter stability.

The converter duty-to-output trans fer function Gd is :

OUT











(13)

and the modulator gain of the converter is :



Where V

is the output voltage of the converter, R is

OUT

(14)

the loading resistance, L and C are the output inducta nce and capacitance, and VP is the peak-to-peak voltage of ramp a pplied at modulator input. The overall loop gain after compensation can be described as :

Loop Gain = T = Gd x F

x A (15)

Where A denotes as compensation gain. T o compensate a typical voltage mode buck converter, there are two ordinary compensation schemes, well known as type-II compensator and type-III compensator . The choice of using type-II or type-III compensator will be up to platform designers, and the main concern will be the position of the capacitor ESR zero and mid-frequency to highfrequency gain boost. Typically, the ESR zero of output cap acitor will tend to stabilize the effe ct of output LC double poles, hence the positon of the output cap acitor ESR zero in frequency domain may influence the design of voltage loop compensation. If F

ZERO,ESR

is <1/2F

where F

denotes cross-over frequency , type-II compensation will be sufficient for voltage stability. If F

ZERO,ESR

is > 1/2F

(or higher gain and phase margin is required at midfrequency to high-frequency), then type-III compensation may be a better solution for voltage loop compensation.

REF

Figure 14. T ype-II Compensation

R1 can be determined independently from DC considerations. Normally choose R1 that the current pa ssing by will be around 1mA. Therefore,



REF

1mA

(16)

Then determine R2 by the boosted gain of loop gain at crossover :



R2 R1

  

Where V

VFF

IN(MAX) LC ZERO, ESR

is the max input voltage of power stage,

IN(MAX)

ZERO, ESR

 

(17)

VP is the peak-to-pea k voltage of ramp a pplied at modulator input, F

ZERO,ESR

zero, and F

ZERO, ESR



2LC



is the frequency of output cap acitor ESR

is the frequency of output LC :







2R C

ESR



(18)

(19)

After determining the phase margin at crossover frequency, the position of zero and pole produced by type-II compensation network, FZ and F

can then be

determined. The bode plot of type-II compensation is shown in Figure15, where

A typical type-II compensation network is shown in Figure 14.

Gain (dB)

Frequency (Hz)

Figure 15. Bode Plot of T ype-II Compensation

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Page 24

RT8857/A



can be determined by the following Equation :

-1 -1

tan tan 90

P.M. tan



By properly choosing F

2R2C1





2 R2 (C1 // C2)





 

   



ZCO



-1

 

ZERO, ESR

to fit equation (22), C1 can then



(20) (21)

(22)

be determined by :







2R2F

(23)

and C2 ca n be determined by :



2R2



 

FC1

(24)

A typical type-III compensation contains two zeros and two poles where the extra one zero and one pole compared with type-II compensation are added for stabilizing the system when ESR zero is relatively far from LC double poles in frequency domain. Figure16. and Figure.17 shows the typical circuit and bode plot of the type-III compensation.

After determining desired phase margin, a ccording to the following Equation :

 

-1 -1

tan tan 45

   



FF2

ZCO

P.M.



(25)

and

F =

F F

and F

ratio to meet Equation (25). Again, R1 ca n be determined

can be determined by choosing proper FCO to

(26)

by the Equation (16). R2 can be determined by the following Equation :

R2 R1

  

VFF

IN(MAX) LC CO



 

(27)

Other component values of the T ype-III compensation can then be calculated as :



2R2F





2R2F





2R1F





2C3F









(28)

(29)

(30)

(31)

REF

Figure 16. T ype-III Compensation

FP = F

FZ = F

= F

Gain (dB)

Frequency (Hz)

= F

Figure 17. Bode Plot of the T ype-III Compensation

Layout Considerations

For best performance of the RT8857/A, the following

guidelines must be strictly followed :

 Input bulk capacitors and MLCCS have to be put near

high side MOSFETs. The connection plane of input capa citors a nd high side MOSFET s then can be kept a s square a s possible.

 The shape of phase planes (the connection plane

between high side MOSFETs, low side MOSFETs a nd output inductors) have to be as s quare as possible. Long traces, thin bars or separated isla nds must be avoided in phase pla nes.

 Keep snubber circuits or damping elements near its

objects. Phase RC snubbers have to be close to low side MOSFETs, UGATE da mping re sistors have to be close to high side MOSFET s, and boot to pha se da mping resistors have to be close to high side MOSFETs and phase planes. Also keep the traces of these snubbers circuits as short as possible.

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RT8857/A

 The area of VIN plane (power stage 12V VIN) and V

plane (output bulk ca pa citors and inductors connection plane) have to be as wide as possible. Long traces or thin bars must be avoided in these planes. The plane trace width must be wide enough to carry large input/ output current (40mil/A).

 The following traces have to be wide and short : UGA TE,

LGATE, BOOT, PHASE, and VCC12. Make sure the width of these traces are wide enough to carry large driving current(at lea st 40mil).

 The voltage feedback loop contains two traces, VCC

and VSS, which are Kelvin sensed from CPU socket or output capa citors. These two traces are suggested a bove 10mil width and put away from high (di/dt) switching elements such as high side MOSFETs, low side MOSFETs, phase plane etc. The circuit elements of voltage feedback loop, such as feedback loop short resistors and voltage loop compensation RCs, have to be kept near the RT8857/A a nd also away from switching elements.

OUT

 The current sense mechanism of the RT8857/A is fully

differential Kelvin sense. Therefore, the current sense loops of the RT8857/A contain two tra ces : the positive traces(ISP1 to ISP4) come from the positive node of output inductors(the node connecting phase pla ne) a nd the negative traces (ISN1 to ISN4) come from the negative node of output inductors(the node connecting output plane).

DO NOT conne ct the current sense traces from phase plane or output pla ne. Only connect these traces from both sides of output inductors can achieve the goal of precise Kelvin sense. The current sense feedba ck loops have to be routed away from switching elements, and the current sense RC elements have to be put near their respective ISN or ISP pins of the RT8857/A and also away from noise switching elements. At lease 10 mil width is suggested for current sense feedba ck loops.

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RT8857/A

Outline Dimension

DETAIL A

Pin #1 ID a nd T ie Bar Mark Option s

Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated.

Dimensions In Milli m eters Dimensions In Inches

Symbol

Min Max Min Max

A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010

b 0.200 0.300 0.008 0.012

D 6.950 7.050 0.274 0.278

D2 5.050 5.250 0.199 0.207

E 6.950 7.050 0.274 0.278 E2 5.050 5.250 0.199 0.207

e 0.500 0.020

L 0.350 0.450

Richtek Technology Corporation

Headquarter 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611

Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.

W-Type 48L QFN 7x7 Package

Richtek Technology Corporation

Taipei Office (Marketing) 8F, No. 137, Lane 235, Paochiao Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862)89191466 Fax: (8862)89191465 Email: [email protected]

0.014 0.018

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