Datasheet rt8800a Datasheets

RT8800A

General Purpose 3-Phase PWM Controller for High-Density
Power Supply

General Description

The RT8800A is a general-purposed multi-phase
synchronous buck controller dedicating for high power
density applications. The RT8800A operates with 2 or 3
synchronous buck switching stages in interleaved phase
set automatically. The multiphase architecture provides
high output current while maintaining low power dissipation
on power devices and low stress on input and output
capacitors.

The output voltage is precisely regulated to the external
reference voltage at PI pin. The RT8800A can provide Intel
VRD10.x or AMD® K8 compliant output voltage when
companioned with DAC generator RT9401A/B.

The RT8800A adopts innovative time-sharing DCR current
sensing technique for channel current balance, droop
tuning, and over current protection. Using one common
GM amplifier for current sensing eliminates offset errors
and linearity variation between GMs. As sub-milli-ohm­grade inductors are widely used in modern mother boards,
slight mismatch of GM amplifiers offset and linearity results
in considerable current shift between phases. The time­sharing DCR current sensing technique is extremely
important to guarantee phase current balance at mass
production.

Other features include overvoltage protection, undervoltage
protection and internal softstart. The RT8800A comes to
a VQFN-16L 3x3 package.

Features

zz

5V Power Supply Voltage

z

zz

zz

2/3-Phase Power Conversion with Automatic Phase

z

zz

Selection

zz

Output Voltage Controlled by External Reference

z

zz

Voltage

zz

Precise Core Voltage Regulation

z

zz

zz

Power Stage Thermal Balance by DCR Current

z

zz

Sensing

zz

z Extreme Low-Cost, Lossless Time Sharing Current

zz

®

Sensing

zz

z Internal Soft-Start

zz

zz

z Hiccup Mode Over-Current Protection

zz

zz

z Over-Voltage Protection

zz

zz

z Adjustable Operating Frequency and Typical at

zz

300kHz Per Phase

zz

z Power Good Indication

zz

zz

z Small 16-Lead VQFN Package

zz

zz

z RoHS Compliant and 100% Lead (Pb)-Free

zz

Applications

z Desktop CPU Core Power

z Low Output Voltage, High Power Density DC-DC

Converters

z Voltage Regulator Modules

Marking Information

Ordering Information

RT8800A

Package Type

For marking information, contact our sales representative
directly or through a Richtek distributor located in your
area, otherwise visit our website for detail.

QV : VQFN-16L 3x3 (V-Type)

Operating Temperature Range
P : Pb Free with Commercial Standard
G : Green (Halogen Free with Commer­ cial Standard)

Note :

Richtek Pb-free and Green products are :

`RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

`Suitable for use in SnPb or Pb-free soldering processes.

`100% matte tin (Sn) plating.

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1

RT8800A

Pin Configurations

(TOP VIEW)

IMAX

1

VID125

FB

DVD

2

3

4

VQFN-16L 3x3

Functional Pin Description

IMAX (Pin 1)

Over current protection setting.

VID125 (Pin 2)

Connect a resistor from this pin to GND can raise V

FB (Pin 3)

The pin is defined as the inverting input of internal error
amplifier.

D VD (Pin 4)

The pin is defined as a programmable power UVLO
detection input. Trip threshold = 0.8V at V

DVD

COMP (Pin 5)

The pin is defined as the output of the error amplifier and
the input of all PWM comparators.

OUT

rising.

PWM3

GND

PI

17

PWM2

RT

PWM1

13141516

ISP1

12

ISP2

11

ISP3

10

PGOOD

9

8765

ICOMMON

VDD

COMP

ICOMMON (Pin 8)

Common negative input of current sense amplifiers for all
three channels.

PGOOD (Pin 9)

.

Output power-good indication. The signal is implemented
as an output signal with open-drain type.

ISP1 , ISP2 , ISP3 (Pin 12, Pin 11, Pin 10)

Current sense positive inputs for individual converter
channel current sense.

PWM1 , PWM2 , PWM3 (Pin 13, Pin 14, Pin 15)

PWM outputs for each phase switching drive.

V DD (Pin 16)

Chip power supply. Connect this pin to a 5V supply.

PI (Pin 6)

The pin is defined as the positive input of the error amplifier.

RT (Pin 7)

Switching frequency setting. Connect this pin to GND with
a resistor to set the frequency.

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2

GND [Exposed Pad (17)]

The exposed pad must be soldered to a large PCB and
connected to GND for maximum power dissipation.

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Typical Application Circuit

3-phase with RT9401A/B DAC generator

C25 to C36

1000uF x 12

L1

0.5uH

PHASE3

Q7

C24

10uF x 4

C37 to C40

3.3nF

RT8800A

CORE

V

L2

0.5uH

2.2

R22

Q8

Q9

IN

V

L3

0.5uH

PHASE2

C16

3.3uF

2.2

R14

12V

9

C23

BOOT3

1uF

12V

PHASE1

SB

5V

10

1uF

VDD

R19

C20

8

0

R18

LGATE1

PVCC1

PHASE1

1uF

C19

12V

Q6

C21

3.3nF

Q5

2.2

R17

1uF

0

R21

C22

0

R20

Q3

Q2

C17

TS

3

R15

0

1uF

12V

LGATE2

20

PVCC2

21

PHASE2

12V

11

PVCC3

PHASE3

GND

10

UGATE3

14

15

LGATE3

RT9605

1917

R13

C9

D1

C10

1uF

1000uF

C11 to C14

5V

Optional

C1

1uF

C15

1500uF x 4

C5

C3

R2

33pF

0

4.7uF

Q1

IN

V

1uH

UGATE2

BOOT2

PWM3

PWM2

PWM1

BOOT1

5

14

RT8800A

IMAX

1

10k

R4

4

10

PWM2

GND

2

16k

R5

2

PHASE3

R10

Optional

11

ISP3

ISP2

ICOMMON

PGOOD

VID125

9

10k

R6

R

ISP1

DVD

7

16

15

PWM3

PWM1

13

16

VDD

3

FB

5

3k

COMP

R3

PI

6

C2

10nF

ADJ

15k

R

R1

1uF

C6

RT

UGATE1

3.3V

1242223

PHASE2

R11

Optional

12

8

7

4

27k

R7

R16

12V

C18

R

C7

0

1uF

R9

Q4

IN

V

D2

12V

PHASE1

R

C8

R12

1uF

16k

3k

R8

1uF

CORE

V

Optional

430

SKY

D

COMM

R

Optional

7

8

VID3

VID4

CS

R

CSN

R

5

6

GND

VID0

C4

10nF

RT9401A/B

VID1

VID2

1

2

3

VDA

VDD

4

5V

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3

RT8800A

Function Block Diagram

RT

DVD

PWM1

& Driver

PWM Logic

INH

-

+

+

&

Oscillator

PWMCP

+

+

Ramp Generator

PWM2

& Driver

PWM Logic

INH

-

+

+

+

PWMCP

+

PWM3

& Driver

PWM Logic

INH

+

+

-

+

PWMCP

+

-

ICOMMON

-

EA

+

+

GM

Sample

ISP1

ISP2

ISP3

Mux

Mux

& Hold

OCP

& Hold

Sample

SUM/N

MAJ

& Hold

Sample

& OCP

Detection

GND

IMAX

VDD

PGOOD

Power On

Reset

Soft Start

COMP

FB

OVP

500mV

PI

0.8V

REF

V

+

-

VID125

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4

Absolute Maximum Ratings (Note 1)

RT8800A

z Supply Voltage, V

z Input, Output or I/O Voltage ---------------------------------------------------------------------------------- GND − 0.3V to V

z Power Dissipation, P

------------------------------------------------------------------------------------------- 7V

DD

@ T

D

= 25°C

A

VQFN-16L 3x3 -------------------------------------------------------------------------------------------------- 1.47W

z Package Thermal Resistance (Note 4)

VQFN-16L 3x3, θJA--------------------------------------------------------------------------------------------- 68°C/W

z Junction Temperature ------------------------------------------------------------------------------------------ 150°C

z Lead Temperature (Soldering, 10 sec.)-------------------------------------------------------------------- 260°C

z Storage Temperature Range --------------------------------------------------------------------------------- −65°C to 150°C

z ESD Susceptibility (Note 2)

HBM (Human Body Mode) ----------------------------------------------------------------------------------- 2kV

MM (Machine Mode) ------------------------------------------------------------------------------------------- 200V

Recommended Operating Conditions (Note 3)

z Supply Voltage, V

z Ambient Temperature Range --------------------------------------------------------------------------------- 0°C to 70°C

z Junction Temperature Range--------------------------------------------------------------------------------- 0°C to 125°C

------------------------------------------------------------------------------------------- 5V ± 10%

DD

Electrical Characteristics

(V

DD

= 5V, T

= 25°C, unless otherwise specified)

A

Parameter Symbol Test Conditions Min Typ Max Units

DD

+ 0.3V

V

Supply Current

DD

Nominal Supply Current

I

DD

PWM 1,2,3 Open

--

5 -- mA

Power-On Reset

Rising 4.0 4.2 4.5 V

VDD Threshold

Hysteresis 0.2 0.5 -- V

DVD Rising Threshold 0.75 0.8 0.85 V

DVD Hysteresis -- 65 -- mV

Oscillator

Free Running Frequency

Frequency Adjustable Range

Ramp Amplitude

Ramp Valley

f

R

OSC

f

OSC_ADJ

ΔV

V

RV

RRT = 16kΩ

OSC

= 16kΩ

RT

50 -- 400 kHz

-- 1.0 -- V

170 200 230 kHz

-- 1.7 -- V

Maximum On-Time of Each Channel 62 66 75 %

RT Pin Voltage

Reference Voltage

IMAX Reference Voltage

VID125 Reference Voltage

V

R

RT

R

V

IMAX

VID125

R

V

= 16kΩ

RT

IMAX

VID125

= 16kΩ

= 16kΩ

0.77 0.82 0.87 V

0.75 0.8 0.85 V

0.75 0.8 0.85 V

To be continued

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5

RT8800A

Parameter Symbol Test Conditions Min Typ Max Units

Error Amplifier

DC Gain -- 65 -- dB

Gain-Ban dwidth Product GBW CL = 10pF -- 10 -- MHz

Slew R ate SR CL = 10pF -- 8 -- V/us

Current Sense GM Amplifier

Recom mended Full Sca le Source C urrent 100 -- -- uA

Protection

Over-Voltage Trip (VFB – VPI) 360 46 0 560 mV

Power Good

PGOOD Output Low Voltage V

PGOOD Delay T

Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for

stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the

operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended

periods may remain possibility to affect device reliability.

Note 2. Devices are ESD sensitive. Handling precaution recommended.
Note 3. The device is not guaranteed to function outside its operating conditions.
Note 4. θ

is measured in the natural convection at TA = 25°C on a low effective thermal conductivity test board of

JA

JEDEC 51-3 thermal measurement standard.

PGOOD

PGOOD_Delay

I

PGOOD

90% * V

= 4mA -- -- 0.2 V

to PGOOD_H 4 -- 8 ms

OUT

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6

Typical Operating Characteristics

RT8800A

Load Line

1.4

1.38

1.36

1.34

1.32

1.3

1.28

Output Voltage (V)

1.26

1.24
0 102030405060708090100

1000

900

800

700

600

500

400

300

Frequency (kHz)

200

100

0

0 5 10 15 20 25 30 35 40 45 50 55 60

R

= 1.5mΩ, R

LL

CSN

Output Current (A)

Frequency vs. R

RRT (kٛ)

(kΩ)

= 10kΩ, R

RT

ADJ

= 100Ω

V

IN

= 12V

Efficiency vs. Output Current

100

90

80

70

60

50

40

Efficiency (%)

30

20

10

0

0 102030405060708090100

Output Current (A)

V

IN

= 12V, V

OUT

Driver RT9605

GM

90

80

70

60

50

(uA)

40

ADJ

I

30

20

10

0

0 102030405060708090100110

VC (mV)

R

COMM

= 430Ω

= 1.4V

GM3

GM3

GM2

GM2

GM1

GM1

V

0.815

0.81

0.805

(V)

0.8

0.795

VID125

V

0.79

0.785

0.78

-25 -10 5 20 35 50 65 80 95 110 125

vs. Temperature

VID125

Temperature

(°C)

Frequency vs. Temperature

350

300

250

200

150

100

Frequency (kHz)

50

R

0

-25-105 203550658095110125

Temp erature

(°C)

RT

= 16kΩ

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7

RT8800A

V

CORE

(200mV/Div)

UGATE1

(20V/Div)

UGATE2

(20V/Div)

UGATE3

(20V/Div)

V

CORE

(200mV/Div)

UGATE1

(20V/Div)

UGATE2

(20V/Div)

UGATE3

(20V/Div)

Load Transient Response

phase 1, I

= 5A to 85A @SR = 93A/us)

OUT

Time (2.5μs/Div)

Load Transient Response

phase 3, I

= 5A to 85A @SR = 93A/us)

OUT

V

CORE

(200mV/Div)

UGATE1

(20V/Div)

UGATE2

(20V/Div)

UGATE3

(20V/Div)

IL1+I

L2

(50A/Div)

V

CORE

(1V/Div)

PWM1

(10V/Div)

V

COMP

(2V/Div)

Load Transient Response

phase2, I

= 5A to 85A @SR = 93A/us)

OUT

Time (2.5μs/Div)

Over Current Protection

Short While Turn_On

IL1+I

(50A/Div)

V

CORE

(1V/Div)

PWM1

(10V/Div)

V

COMP

(2V/Div)

8

Time (2.5μs/Div)

Over Current Protection

Short After Turn_On

L2

PWM

(5V/Div)

V

CORE

Time (10ms/Div)

VID On the Fly Falling

I

OUT

= 5A

(100mV/Div)

V

FB

(200mV/Div)

VID0

(2V/Div)

Time (10ms/Div)

Time (25μs/Div)

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RT8800A

V

CORE

(50mV/Div)

PWM

(5V/Div)

V

FB

(200mV/Div)

VID0

(2V/Div)

PWM

(5V/Div)

VID On the Fly Falling

Time (25μs/Div)

VID On the Fly Rising

I

I

OUT

OUT

= 90A

= 90A

PWM

(5V/Div)

V

CORE

(200mV/Div)

V

FB

(200mV/Div)

VID0

(2V/Div)

VID On the Fly Rising

Time (10μs/Div)

I

OUT

= 5A

V

CORE

(200mV/Div)

V

FB

(200mV/Div)

VID0

(2V/Div)

Time (10μs/Div)

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9

RT8800A

Applications Information

The RT8800A is a general-purposed multi-phase
synchronous buck controller dedicating for high power
density applications. The RT8800A operates with 2 or 3
synchronous buck switching stages in interleaved phase
set automatically. The multiphase architecture provides
high output current while maintaining low power dissipation
on power devices and low stress on input and output
capacitors.

Initialization

The RT8800A initiates after 2 pins are ready : VDD pin
power on reset (POR) and DVD pin is higher than 1V. VDD
POR is to make sure RT8800A is powered by a voltage
high enough for normal work. The rising threshold voltage
of VDD POR is 4.2V typically. At VDD POR, RT8800A
checks PWM3 status to determine phase number of
operation. Pull high PWM3 for two-phase operation. The
unused current sense pins should be connected to GND
or left floating.

DVD is to make sure that ATX12V is ready for the
companion MOSFET drivers to work normally. Connect a
voltage divider from ATX12V to DVD pin as shown in the
Typical Application Circuit. Make sure that DVD pin voltage
is below its threshold voltage before drivers are ready and
above its threshold voltage for minimum ATX12V during
normal operation. If one of VDD and DVD is not ready,
RT8800A keeps its PWM outputs high impedance and
the companion drivers turn off both upper and lower
MOSFETs.

Soft-Start

After VDD and DVD are ready, RT8800A initiates its soft
start cycle as shown in Figure 1. The error amplifier and
PWM comparator are triple-input devices. The non-inverting
input whichever is smaller dominates the behavior of the
device. The soft start function generates SS and SSE for
the non-inverting input of PWM comparator and error
amplifier respectively where SSE = SS - VGS. VGS is
threshold voltage of internal MOSFET. The typical soft­start duration is 3ms. The soft start can be sliced to
several time frames with specific operation respectively.

1) Mode 1 (SS < V

RAMP_Valley

)

Initially the COMP stays in the positive saturation due to
offset of the error amplifier. Since SS < V

RAMP_Valley

PWM comparator keeps its output low and V

2) Mode 2 (V

Since V

RAMP_Valley

RAMP_Valley

< SS < Cross-over)

< SS < Cross-over, SS dominates the

OUT

, the

is zero.

non-inverting inputs of the PWM comparators. The PWM
duty cycles increase according to the ramping up SS
signal. The output voltage ramps up accordingly. However
as V

OUT

(SS - V

increases, the difference between V

) is reduced and COMP leaves the saturation

GS

and SSE

OUT

and declines. The takeover of SS lasts until it meets the
COMP. During this interval, since the feedback path is
broken, the converter is operated in the open loop.

3) Mode3 (Cross-over < SS < VGS + VPI)

When the V

takes over the non-inverting input for PWM

COMP

Amplifier and when SSE (SS - VGS) < VPI, the output of
the converter follows the ramp input, SSE (SS - VGS).
Before the crossover, the output follows SS signal. And
when V

takes over SS, the output is expected to

COMP

follow SSE (SS - VGS). Therefore the deviation of VGS is
represented as the falling of V

for a short while. The

OUT

COMP is observed to keep its decline when it passes the
cross-over, which shortens the duty width and hence the
falling of V

happens. Since there is a feedback loop for

OUT

the error amplifier, the output's response to the ramp input,
SSE (SS - VGS) is lower than that in Mode 2.

4) Mode 4 (SS > VGS + VPI)

When SS > VGS + VPI, the output of the converter follows
the desired V

signal and the soft start completes.

PI

However, the SS keeps ramping up to 3.3V and stays
there. The PGOOD pin trips to high impedance as SS
reaches 3.3V.

Soft Start

SSSSE

FB

PI

+

EA

­+

+
+

-

PWM

10

Figure 1. Soft Start Block Diagram.

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COMP

V

RAMP_Valley

Cross-over

S/H CKT

RT8800A

I

L

R

X

R

X

+

-

T1

+ V

LX

LX

C

X

-

X

V

OUT

SS_Internal

V

CORE

SSE_Internal

Figure 2

Time-Sharing DCR Current Sensing

RT8800A adopts an innovative time-sharing DCR current
sensing technique to sense the phase currents for phase
current balance (phase thermal balance), over current
protection and load line regulation as shown in Figure 3.
The current sensing amplifier GM samples and holds
voltages VX across the current sensing capacitor CX by
turns in a switching cycle. According to the Basic Circuit
Theory, if

L

X

R

LX

XX

RI VthenCR

×=×=

LXLXX

I

X

T3

T2

R

COMM

+

Figure 3

Figure 4 and 5 show the linearity of GM amplifier and its
test circuit respectively. A voltage source is applied to
ISPx while other ISPx pins are short to V
V

across resistor R

ADJ

is measured. It is observed from

ADJ

. The voltage

OUT

Figure 5 shows that all ISPx share the same
transconductance linearity and voltage offset.

GM

70

Consequently, the sensing current IX is proportional to
inductor current ILX and is expressed as

RII×

R

COMM

LXLX

=

X

The sensed current IX is used for current balance, over
current protection, and droop tuning as described as

60

50

40

(uA)

30

ADJ

I

20

GM1

GM3

GM2

followed. Since all phases share one common GM, GM
offset and linearity variation effect are eliminated in
practical applications. As sub-milli-ohmgrade inductors are
widely used in modern motherboards, slight mismatch of
GM amplifiers offset and linearity results in considerable

10

0

0 20406080100

VC (mV)

V

X

current shift between phases. The time sharing DCR current
sensing technical is extremely important to guarantee

Figure 4. The Linearity of GMx

phase current balance at mass production.

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11

RT8800A

I

ADJ

R

ADJ

+ V

ADJ

DAC_OUT

RT9401

-

-

EA

PI

+

SUM/N

Figure 5. Test Circuit of GM.

S/H

MUX

MUX

GM

I

X

+

-

ISP1

ISP2
ISP3

ICOMMON

Over Current Protection

V

X

-

+

V

CORE

PWM

(5V/Div)

I

L

(5V/Div)

Phase Current Balance

The sampled and held phase current IX are injected to the
corresponding saw tooth waveforms of PWM comparators.
If phase current IX is larger than other phase currents, its
saw tooth waveform will be lift higher than the others. The
RT8800A reduces the duty cycle of corresponding phase
to decrease the phase current accordingly, vice versa.

Over Current Protection

RT8800A uses an external resistor R
IMAX pin to generate a reference current I

connected to

IMAX

IMAX

for over

current protection:

V

I =

IMAX

where V

IMAX

R

IMAX

is 0.8V typical. OCP comparator compares

IMAX

each sensed phase current IX with this reference current
as shown in Figure 6. Equivalently, the maximum phase
current is calculated as :

I =

LX(MAX)

3

RV2

IMAX

IMAX

R

COMM

R

LX

OCP Comparator

1/3 I

+

1/2 I

-

X

IMAX

Figure 6. Over Current Comparator.

The RT8800A uses hiccup mode to eliminate nuisance
detection of OCP or reduce output current when output is
shorted to ground as shown in Figure 7 and 8. The
RT8800A shuts down and latches off after 3 time OCP
hiccups. It can only restart by resetting one of VDD or
DVD pin.

Time (25ms/Div)

Figure 7. The Over Current Protection in the interval

Over Current Protection

PWM

V

(5V/Div)

(5V/Div)

SS

Time (25ms/Div)

Figure 8. Over Current Protection at steady state

Voltage Reference for Converter Output & Load
Droop

The output voltage is sensed at FB pin. The RT8800A
receives an external reference voltage at PI pin as the
non-inverting of the error amplifier and precisely regulates
the FB voltage to this reference voltage. The RT8800A
can provide Intel® VRD10.x or AMD® K8 compliant output
voltage when companioned with DAC generator
RT9401A/B as shown in Figure 9. The RT9401A/B receives
VID[0:4] and produces DAC_OUT that complies with
VRD10.x or K8 VID table. The DAC_OUT is fed to PI pin
through a resistor R

as the reference voltage of the

ADJ

error amplifiers. The VID125 provides a 12.5mV offset for
full compliance of VRD10.x table.

12

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RT8800A

COMP

A negative IX is required to correctly sense the negative

voltage. However, the RT8800A CANNOT provide a negative

V

CORE

VID [0 : 4]

R

FB

DAC_OUT

R

R

RT9401

VID125

ADJ

FB

PI

1/2 I

Current

VID125

OFS

Mirror

I

OFS

+

-

0.8V

V

REF

­+

OVP500mV

1
3

SUM/N

)sum(I

X

I

IX and consequently cannot sense negative inductor
current. This results in dead zone of load line performance
as shown in Figure 10. Therefore a technique as shown in
Figure 11 is required to eliminate the dead zone of load
line at light load condition.

V

X

V

OFFSET

CORE

Load Line

DAC_OUT

Figure 9

Spec_High

>

R

Droop and Load Lind Setting

The sampled and held phase current IX are summed to get
sum(IX). RT8800A then sinks a current that is 1/3 sum(IX)
and produces a droop voltage that is proportional to the

Figure 10

CSN

=

R

CSN

R

<

CSN

Spec_Low

I

CORE

average phase voltage.

X

C

X

SKY

CORE

CS

RI

LXLX_Valley

I

L

L

X

R

L_X

V

CORE

- V

F

RI

×

LXLX_Valley

0

≥

V

= 1/3 sum(IX) x R

ADJ

V

is then subtracted form DAC generator output as the

ADJ

ADJ

R

real reference voltage at non-inverting input of the error
amplifier. Consequently, load line slope is calculated as:

Line Load −==

ΔV

ΔI

CORE

CORE

R x 3

R x R

COMM

LXADJ

­+

Output V oltage Offset Function

I

VID125 pin is internally regulated to be around 0.8V. An
external resistor R
generates the offset current .

FB pin will sink a current which is half of I
a current mirror FB and VID125. The output offset voltage
is calculated to be

V R

OFS FB

0.8V 1

=××

R2

VID125

Thus, the output voltage becomes

V V + V V

CORE FB OFS FB

Note : To maintain VID125 voltage around 0.8V, R

must not be less than 16kΩ.

==

between VID125 and GND

VID125

I =

OFS

R

0.8V R

+

2R

×

0.8V

VID125

OFS

×

VID125

FB

because of

VID125

Referring to Figure 11, the Schottky diode provides a
constant voltage drop VF with enough bias current. IX is
expressed as:

I

X

To make sure RT8800A could sense the inductor current,
right hand side of Equation (1) should always be positive:

Dead Zone Elimination and Output Voltage Offset
Function

RT8800A samples and holds inductor valley current by
time-sharing sourcing a current IX to R

. At light load

COMM

condition the inductor valley current and consequently the
voltage VX across the sensing capacitor may be negative.

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Since VF >> (I
Equation (2) could be simplified as:

V

R

CSN

X

RIV

=

F

R

R

CSN

≥

CSN

×+

LX_Valley

R

COMM

×+

RIV

LXLX_ValleyF

RI

×

+
V

X

-

R

COMM

R

CSN

D

V

R

Figure 11

LXLX_ValleyF

+

R

COMM

R

COMM

×

+

x RLX) in practical application,

LXLX_Valley

(1)

(2)

(3)

13

RT8800A

Rewriting Equation (3), we get

RV

×

COMMF

RI

×

R

≥

LXLX_Valley

CSN

(4)

The technique mentioned above also provides output voltage
offset function specified by Intel

®

VRD10.x. The offset

voltage level is calculated as:

R

ADJ

V =

OFFSET

R

CSN

V

F

Enough bias current is required for a Schottky to act like
a voltage source. Users should choose the appropriate
RCS based on the IV characteristic of the diode
(Figure 12)

I

IV Characteristic

Zone 1 Zone 2

Current Ratio Setting

Current ratio adjustment is possible as described below.
It is important for achieving thermal balance in practical
application where thermal conditions between phases are
not identical. Figure 13 shows the application circuit of
GM for current ratio requirement. According to Basic Circuit
Theory, if

L

X

R

LX

R

V

=

X

PX

+

RR

PXSX

then C)//R(R

×=

XPXSX

RI

××

LXLX

With other phase kept unchanged, this phase would share
(RPX+RSX)/RPX times current than other phases. Figure 14
and 15 show different current ratio setting for the power
stage when Phase 3 is programmed 2 times current than
other phases. Figure 16 and 17 compare the above current
ratio setting results.

I

L

R

X

LX

LX

V

Figure 12

According to Figure 12, the forward voltage of diode will
be different results from the different conduction current.
So when the characteristic of diode in the circuit you
design is in zone 1, this will result in Spec. mis-met. It is
because when the V
node V

- VF is also changed to produce the differential

CORE

is changed during DVID, the

CORE

conduction current of diode ΔI and the ΔI will result in
producing the differential forward voltage of diode ΔV
Referring to Equation (1). The ΔVF would get ΔIX. Then
the V
x R

- V

(MIN)

must be subtracted the extra voltage V

CORE

) during DVID. So you will get the ΔV

ADJ

- V

during DVID tests. In order to reduce the

(EXT)

CORE

(EXT)

= V

(ΔI

(MAX)

effect results from diode. The better choice is to decrease
the Rcs to increase the conduction current of diode I to
get better V characteristic of diode in Zone 2.

Over Voltage Protection (OVP)

The RT8800A continuously monitors voltage at FB pin.
OVP is triggered if FB voltage is 500mV higher than the
voltage at PI pin. RT8800A latches off and turns on lower
MOSFET to protect the load from damage upon on OVP
trip. It can only be reset by DVD and VDD pins.

+ V

R

PX

C

X

-

X

V

OUT

+

R

SX

T

T

Figure 13

F

I

L3

X

1.5uH

3k

1m

1uF

3k

Figure 13. GM4 Setting for current ratio function.

I

L1 to L2

1.5uH

1.5k 1uF

1m

Figure 14. GM1 to GM3 Setting for current ratio

function.

14

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DS8800A-05 November 2007www.richtek.com

RT8800A

(A)

LX

I

40

35

30

25

20

15

10

Current Balance Func t ion

I

L3

I

L2

I

L1

5

Power Sequence & SS

DVD pin external resistor and SS pin capacitor.

PCB Layout

a.Sense for current sense GM amplifier input.

b.Refer to layout guide for other items.

Voltage Loop Setting

Design Example

Given:

0

0 20406080100

I

(A)

CORE

Figure 15

45

40

35

30

25

(A)

20

LX

I

15

10

5

0

0 1530 45607590

Current Ratio Function

I

(A)

CORE

I

L3

I

L2

I

L1

Figure 16

Design Procedure Suggestion

a.Output filter pole and zero (Inductor, output capacitor

value & ESR).

b.Error amplifier compensation & sawtooth wave amp-

litude (compensation network).

Apply for four phase converter

VIN = 12V

V

= 1.5V

CORE

I

LOAD(MAX)

V

DROOP

= 100A

= 100mV at full load (1mΩ Load Line)

OCP trip point set at 35A for each channel (S/H)

DCR = 1mΩ of inductor at 25°C

L = 1.5μH

C

= 8000μF with 5mΩ equivalent ESR.

OUT

1. Compensation Setting

a. Modulator Gain, Pole and Zero:

From the following formula:

Modulator Gain =VIN/V

where V

: ramp amplitude of saw-tooth wave

RAMP

=12/2.4=5 (i.e 14dB)

RAMP

LC Filter Pole = 1.45kHz and

ESR Zero =3.98kHz

b. EA Compensation Network:

Select R1 = 4.7k, R2 = 15k, C1 = 12nF, C2 = 68pF
and use the Type 2 compensation scheme shown in
Figure 21. By calculation, the FZ = 0.88kHz,
FP = 322kHz and Middle Band Gain is 3.19 (i.e

Current Loop Setting

a.GM amplifier S/H current (current sense component

DCR, ICOMMON pin external resistor value).

b.Over-current protection trip point (R

ICOMMON1

resistor).

VRM Load Line Setting

10.07dB).

RB1

4.7k

C2 68pF

RB2

15k

-

EA

+

C1

12nF

a.Droop amplitude (PI pin resistor).

b.No load offset (R

ICOMMON2

)

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Figure 17. Type 2 compensation network of EA

15

RT8800A

2. Over-Current Protection Setting

Consider the temperature coefficient of copper
3900ppm/°C,

DCRI

×

L

R

ICOMMON1

1.39mI

L

330

35.6AI

=

L

Ω×

Ω

A150

=

μ

A150

=

μ

Layout Guide

Place the high-power switching components first, and
separate them from sensitive nodes.

1. Most critical path:

The current sense circuit is the most sensitive part of
the converter. The current sense resistors tied to
ISP1,2,3 and ICOMMON should be located not more
than 0.5 inch from the IC and away from the noise
switching nodes. The PCB trace of sense nodes should

be parallel and as short as possible. R&C filter of choke
should place close to PWM and the R & C connect
directly to the pin of each output choke, use 10 mil
differencial pair, and 20 mil gap to other phase pair.
Less via as possible.

2. Switching ripple current path:

a. Input capacitor to high side MOSFET.

b. Low side MOSFET to output capacitor.

c. The return path of input and output capacitor.

d. Separate the power and signal GND.

e. The switching nodes (the connection node of high/
low side MOSFET and inductor) is the most noisy
points.Keep them away from sensitive small­signal node.

f . Reduce parasitic R, L by minimum length, enough
copper thickness and avoiding of via.

3. MOSFET driver should be closed to MOSFET.

SW1

V

IN

R

IN

C

V

IN

SW2

L1

V

OUT

C

OUT

L2

R

L

Figure 18. Power Stage Ripple Current Path

16

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RT8800A

+12V

0.1uF

VCC

VIN

BST

DRVH

SW

RT9603

DRVL

GND

Locate near MOSFETs

Next to IC

C

C

IN

BOOT

+12V or +5V

L

O1

V

CORE

C

OUT

R

ICOM

Figure 19. Layout Consideration

PWM

RT

GND

RT8800A

ICOMMON

CSPx

GND

VCC

COMP

FB

+5V

IN

C

BP

Next to IC

C

C

R

C

Locate next

FB

R

to FB Pin

DRD

R

PI

Figure 20

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DS8800A-05 November 2007 www.richtek.com

17

RT8800A

Figure 21

18

Figure 22

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DS8800A-05 November 2007www.richtek.com

Figure 23

RT8800A

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19

RT8800A

Outline Dimension

D

E

A

A3

A1

D2

e

SEE DETAIL A

1

E2

b

L

1
2

1
2

DETAIL A

Pin #1 ID and Tie Bar Mark Options

Note : The configuration of the Pin #1 identifier is optional,

but must be located within the zone indicated.

Dimensions In Millimeters Dimensions In Inches

Symbol

Min Max Min Max

A 0.800 1.000 0.031 0.039

A1 0.000 0.050 0.000 0.002

A3 0.175 0.250 0.007 0.010

b 0.180 0.300 0.007 0.012

D 2.950 3.050 0.116 0.120

D2 1.300 1.750 0.051 0.069

E 2.950 3.050 0.116 0.120

E2 1.300 1.750 0.051 0.069

e 0.500 0.020

L 0.350 0.450

Richtek Technology Corporation

Headquarter

5F, No. 20, Taiyuen Street, Chupei City

Hsinchu, Taiwan, R.O.C.

Tel: [phone] Fax: [phone]

0.014 0.018

V-Type 16L QFN 3x3 Package

Richtek Technology Corporation

Taipei Office (Marketing)

8F, No. 137, Lane 235, Paochiao Road, Hsintien City

Taipei County, Taiwan, R.O.C.

Tel: [phone] Fax: [phone]

Email: [e-mail]

20

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