Datasheet RLP1N08LE Datasheet (Intersil)

RLP1N08LE

Data Sheet April 1999

1A, 80V, 0.750 Ohm, Current Limited,
N-Channel Power MOSFET

The RLP1N08LE is a semi-smart monolithic power circuit
which incorporates a lateral bipolar transistor, two resistors,
a zener diode, and a PowerMOS transistor. Good control of
the current limiting levels allows use of these devices where
a shorted load condition may be encountered. “Logic level”
gates allow this device to be fully biased on with only 5V
from gate to source. The zener diode provides ESD
protection up to 2kV. These devices can be produced on the
standard PowerMOS production line.

Formerly developmental type TA09842.

Ordering Information

PART NUMBER PACKAGE BRAND

RLP1N08LE TO-220AB L1N08LE

NOTE: When ordering, use the entire part number.

File Number

Features

• 1A, 80V

•r

•I

• Built-in Current Limiting

• ESD Protected

• Controlled Switching Limits EMI and RFI

• Specified for 150

• Temperature Compensated Spice Model Provided

• Related Literature

- TB334 “Guidelines for Soldering Surface Mount

= 0.750Ω

DS(ON)

at 150oC = 1.5A Maximum

LIMIT

o

C Operation

Components to PC Boards”

Symbol

D

2252.3

Packaging

G

S

JEDEC TO-220AB

SOURCE

DRAIN

GATE

DRAIN (FLANGE)

6-435

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.

http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

RLP1N08LE

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Specified

C

RLP1N08LE UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

DSS

DGR

80 V

80 V

Electrostatic Voltage at 100pF, 1500Ω. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ESD 2 kV

Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Gate to Source Voltage (Reverse Voltage Gate Bias Not Allowed). . . . . . . . . . . . . . . . . . . . V

Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P

D

GS

D

Self Limited

5.5 V
30 W

Power Dissipation Derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.24 W/oC

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, T

STG

-55 to 150

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

L

pkg

300
260

o

C

o

C

o

C

NOTE:

1. TJ= 25oC to 150oC.

Electrical Specifications T

= 25oC, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV
Gate to Threshold Voltage V
Zero Gate Voltage Drain Current I

DSSID

GS(TH)VGS

DSS

= 250µA, VGS = 0V, Figure 7 80 - - V

= VDS, ID = 250µA, Figure 8 1 - 2 V

VDS = 65V, VGS = 0V TC = 25oC--1µA

TC = 150oC--50µA
Gate to Source Leakage Current I
Drain to Source On Resistance (Note 2) r

Limiting Current I

DS(ON)ID

DS(Lim)VDS

Turn-On Time t
Turn-On Delay Time t

d(ON)

Rise Time t
Turn-Off Delay Time t

d(OFF)

Fall Time t
Turn-Off Time t

(OFF)

Thermal Resistance Junction to Case R
Thermal Resistance Junction to Ambient R

GSS

(ON)

θJC
θJA

VGS = 5V, TC = 150oC--50µA

= 1A, VGS = 5V

Figure 6

= 15V, VGS = 5V

Figure 3

VDD = 30V, ID = 1A, VGS = 5V, RGS = 25Ω
RL = 30Ω

r

TC = 25oC - - 0.750 Ω

TC = 150oC - - 1.5 Ω

TC = 25oC 1.8 - 3 A

TC = 150oC 1.1 - 1.5 A

- - 6.5 µs

- - 1.5 µs

1-5µs

- - 7.5 µs

f

1-5µs

- - 12.5 µs

- - 4.17oC/W

TO-220AB - - 62

o

C/W

Electrostatic Voltage ESD Human Model (100pF, 1.5kΩ) 2000 - - V

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage (Note 2) V

SD

Reverse Recovery Time t

NOTES:

2. Pulsed: pulse duration = ≤ 300µs maximum, duty cycle = ≤ 2%.

3. Repititive rating: pulse width limited by maximum junction temperature.

6-436

ISD = 1A - - 1.5 V
ISD = 1A - - 1 ms

rr

RLP1N08LE

Typical Performance Curves

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 150

TC, CASE TEMPERATURE (oC)

Unless Otherwise Specified

125

FIGURE 1. NORMALIZED POWERDISSIPATION vs CASE

TEMPERATURE

2.0

1.5

1.0

0.5

0

NORMALIZED DRAIN TO SOURCE CURRENT

-50 0 50 100 150
T

, CASE TEMPERATURE (oC)

C

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.

= 10V, VGS = 5V

V

DS

10

TJ = MAX RATED

ID MAX AT 25oC

ID MIN AT 150oC

1.0
OPERATION IN THIS

AREA MAY BE
LIMITED BY r

, DRAIN CURRENT (A)

D

I

0.1

1 10 100

DS(ON)

, DRAIN TO SOURCE VOLTAGE (V)

V

DS

V

DSS

MAX = 80V

100µs

1ms

10ms

DC

FIGURE 2. FORWARD BIAS SAFE OPERATING AREA

3.0

TC = 25oC

2.5

2.0

1.5

1.0

0.5

, DRAIN TO SOURCE CURRENT (A)

DS

I

0

012345

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.

V

, DRAIN TO SOURCE VOLTAGE (V)

DS

8V
6V
5V

VGS = 10V

4V

3V

2V

FIGURE 3. NORMALIZED CURRENT LIMIT vs CASE

FIGURE 4. SATURATION CHARACTERISTICS

TEMPERATURE

4.2
PULSE TEST
PULSE DURATION = 80µs

3.5

DUTY CYCLE = 0.5% MAX
V

= 15V

DS

2.8

2.1

1.4

, DRAIN TO SOURCE CURRENT (A)

0.7

DS(ON)

I

0

0 2.5 5.0 7.5

, GATE TO SOURCE VOLTAGE (V)

V

GS

-55oC

25oC

150oC

2.5
VGS = 5V, ID = 1A

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.

2.0

1.5

1.0

ON RESISTANCE

0.5

NORMALIZED DRAIN TO SOURCE

0

-50 0 50 100 150
TJ, JUNCTION TEMPERATURE (oC)

FIGURE 5. TRANSFER CHARACTERISTICS FIGURE 6. NORMALIZED DRAIN TO SOURCEON

RESISTANCE vs JUNCTION TEMPERATURE

6-437

RLP1N08LE

Typical Performance Curves

1.4
ID = 250µA

1.2

1.0

0.8

BREAKDOWN VOLTAGE

0.6

NORMALIZED DRAIN TO SOURCE

0.4

-50 0 50 100 150
T

, JUNCTION TEMPERATURE (oC)

J

Unless Otherwise Specified (Continued)

FIGURE 7. NORMALIZED DRAIN TO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

500

VGS = 0V, f = 1MHz

= CGS + C

C

400

300

200

C, CAPACITANCE (pF)

100

C

OSS

C

RSS

C

ISS

C
C

ISS
RSS
OSS

= C

GD

≈ CDS + C

GD

GD

1.2

1.1

1.0

0.9

0.8

NORMALIZED GATE

THRESHOLD VOLTAGE

0.7

0.6

-50 0 50 100 150
, JUNCTION TEMPERATURE (oC)

T

J

VGS = V

DS

ID = 250µA

FIGURE 8. NORMALIZED GATE THRESHOLD VOLTAGE vs

JUNCTION TEMPERATURE

V

DD

R

L

V

V

GS

+

0

G

R

GS

D

DS

0

0 5 10 15 20 25

V

, DRAIN TO SOURCE VOLTAGE (V)

DS

S

FIGURE 9. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 10. SWITCHING TEST CIRCUIT

20

HSTR = 0oC/W

15

1oC/W

2oC/W

10

5oC/W

10oC/W

5

, DRAIN TO SOURCE VOLTAGE (V)

25oC/W

DS

V

0

25 50 75 100 125 150

, AMBIENT TEMPERATURE (oC)

T

A

FREE AIR R

TJ = 150oC
I

= 1.5A

LIM

R

= 4.17oC/W

θJC

= 80oC/W

θJC

FIGURE 11. DC OPERATION IN CURRENT LIMITING

80

60

DUTY CYCLE = 20%

40

20

, DRAIN TO SOURCE VOLTAGE (V)

MAX PULSE WIDTH = 100ms

DS

TJ = 150oC, I

V

0

25 50 75 100 125 150

50%

= 1.5A, R

LIM

, AMBIENT TEMPERATURE (oC)

T

A

NOTE: Heatsink thermal resistance = 2

10% 5% 2% 1%

= 4.17oC/W

θJC

o

C/W

FIGURE 12. MAXIMUM VDS vs TA IN CURRENT LIMITING

6-438

RLP1N08LE

Typical Performance Curves

80

MAX PULSE WIDTH = 100ms

TJ = 150oC
I

= 1.5A

LIM

R

= 4.17oC/W

θJC

60

40

DUTY CYCLE = 20%

20

, DRAIN TO SOURCE VOLTAGE (V)

DS

V

0

25 50 75 100 125 150

50%

, AMBIENT TEMPERATURE (oC)

T

A

10%

Unless Otherwise Specified (Continued)

5% 2% 1%

NOTE: Heatsink thermal resistance = 5oC/W

FIGURE 13. MAXIMUM VDS vs TA IN CURRENT LIMITING

80

MAX PULSE WIDTH = 100ms

T

= 150oC

J

I

= 1.5A

LIM

R

= 4.17oC/W

θJC

60

1%

80

MAX PULSE WIDTH = 100ms
TJ = 150oC
I

= 1.5A

LIM

R

= 4.17oC/W

θJC

60

40

DUTY CYCLE = 20%

20

, DRAIN TO SOURCE VOLTAGE (V)

DS

V

0

25 50 75 100 125 150

10%

50%

, AMBIENT TEMPERATURE (oC)

T

A

5%

2% 1%

NOTE: Heatsink thermal resistance = 10oC/W

FIGURE 14. MAXIMUM VDS vs TA IN CURRENT LIMITING

80

DUTY CYCLE = 1%

60

MAX PULSE WIDTH = 100ms

T

= 150oC

J

I

= 1.5A

LIM

R

= 4.17oC/W

θJC

40

20

, DRAIN TO SOURCE VOLTAGE (V)

DS

V

0

25 50 75 100 125 150

5%

10%

20%
50%

, AMBIENT TEMPERATURE (oC)

T

A

DUTY CYCLE = 2%

NOTE: Heatsink thermal resistance = 25oC/W

FIGURE 15. MAXIMUM VDS vs TA IN CURRENT LIMITING

10

8

STARTING
TEMP = 25oC

C (s)

o

TIME TO 150

125oC 100oC 75oC 50oC

6

4

2

R

θJC

4.17

o

=

C/W

40

10%

20

, DRAIN TO SOURCE VOLTAGE (V)

DS

V

0

25 50 75 100 125 150

2%

20%

50%

5%

, AMBIENT TEMPERATURE (oC)

T

A

NOTE: No external heatsink.

FIGURE 16. MAXIMUM VDS vs TA IN CURRENT LIMITING

C (s)

o

TIME TO 150

10

8

6

125oC 100oC 75oC 50oC

4

2

R

θJC

STARTING
TEMP = 25oC

= 4.17oC/W

0

0 5 10 15 20

, DRAIN TO SOURCE VOLTAGE (V)

V

DS

NOTE: Heatsink thermal resistance = 2oC/W

Heatsink thermal capacitance = 4j/oC

FIGURE 17. TIME TO 150oC IN CURRENT LIMITING

6-439

0

0 5 10 15 20

, DRAIN TO SOURCE VOLTAGE (V)

V

DS

NOTE: Heatsink thermal resistance = 5oC/W

Heatsink thermal capacitance = 2j/oC

FIGURE 18. TIME TO 150oC IN CURRENT LIMITING

RLP1N08LE

Typical Performance Curves

10

8

STARTING

C (s)

6

o

125oC 100oC 75oC 50oC

4

TIME TO 150

2

0

0 5 10 15 20

, DRAIN TO SOURCE VOLTAGE (V)

V

DS

TEMP = 25oC

Unless Otherwise Specified (Continued)

R

θJC

NOTE: Heatsink thermal resistance = 10oC/W

Heatsink thermal capacitance = 1j/oC

FIGURE 19. TIME TO 150oC IN CURRENT LIMITING

10

8

= 4.17oC/W

10

8

STARTING

C (s)

6

o

125oC

4

TIME TO 150

2

0

0 5 10 15 20

100oC

TEMP = 25

75oC

V

, DRAIN TO SOURCE VOLTAGE (V)

DS

50oC

o

C

R

NOTE: Heatsink thermal resistance = 25oC/W

Heatsink thermal capacitance = 0.5j/oC

FIGURE 20. TIME TO 150oC IN CURRENT LIMITING

= 4.17oC/W

θJC

C (s)

6

o

4

TIME TO 150

125oC

2

0

0 5 10 15 20

STARTING
TEMP = 25oC

100oC

75oC

V

, DRAIN TO SOURCE VOLTAGE (V)

DS

50oC

NOTE: No external heatsink.

FIGURE 21. TIME TO 150oC IN CURRENT LIMITING

6-440

RLP1N08LE

Temperature Dependence of Current Limiting and
Switching Speed

The RLP1N08LE is a monolithic power device which
incorporates a logic level PowerMOS transistor with a
resistor in series with the source. The base and emitter ofa
lateral bipolar transistor is connected across this resistor,
and the collector of the bipolar transistor is connected to
the gate of the PowerMOS transistor. When the voltage
across the resistor reaches the value required to forward
bias the emitter base junction of the bipolar transistor, the
bipolar transistor “turns on”. A series resistor is
incorporated in series with the gate of the PowerMOS
transistor allowing the bipolar transistor to drive the gate of
the PowerMOS transistorsto a voltagewhich just maintains
a constant current in the PowerMOS transistor. Since both
the resistance of the resistor in series with the PowerMOS
transistor source and voltage required to forward bias the
base emitter junction of the bipolar transistor vary with the
temperature, the current at which the device limits is a
function of temperature. This dependence is shown in
figure 3.

The resistor in series with the gate of the PowerMOS
transistor results in much slower switching than in most
PowerMOS transistors. This is an advantage where fast
switchingcan cause EMI or RFI.The switching speedis very
predictable, and a minimum as well as maximum fall time is
given in the device characteristics for this type.

DC Operation of the RLP1N08LE

The limit of the drain to source voltage for operation in
current limiting on a steady state (DC) basis is shown as
Figure 11. The dissipation inthe device is simply the applied
drain tosource voltage multipliedby the limiting current.This
device,like most Power MOSFET devices today, is limited to

o

150

C. The maximum voltage allowable can, therefore be

expressed as:

150oCT

–()

V

----------------------------------------------------------=

DS

I

LIMRθJCRθCA

AMBIENT

+()×

(EQ. 1)

Duty Cycle Operation of the RLP1N08LE

In many applications either the drain to source voltage or
the gate driveis not available100% of the time. The copper
header on which the RLP1N08LE is mounted has a very
large thermal storage capability, so for pulse widths of less
than 100 milliseconds, the temperature of the header can
be considered a constant case temperature calculated
simply as:

T

VDSIDDR

C

×××()T

θCA

+=

AMBIENT

(EQ. 2)

Generally the heat storage capability of the silicon chip in a
power transistor is ignored for duty cycle calculations.
Making this assumption, limiting junction temperature to

o

150

C and using the TC calculated above, the expression

for maximum V

V

------------------------------------------=

DS

I

LIM

under duty cycle operation is:

DS

150 TC–

DR

××

θJC

(EQ. 3)

These values are plotted as Figures 12 thru 16 for various
heat sink thermal resistances.

Limited Time Operations of the RLP1N08LE

Protection for a limited period of time is sufficient for many
applications. As stated above the heat storage in the silicon
chip can usually be ignored for computations of over 10
milliseconds and the thermal equivalent circuit reduces to a
simple enough circuit to allow easy computation on the
limiting conditions. The variation in limiting current with
temperature complicates the calculation of junction
temperature, but a simple straight line approximation of the
variation is accurate enough to allow meaningful
computations. The curves shown as figures 17 thru 21 give
an accurate indication of how long the specified voltage can
be applied to the device in the current limiting mode without
exceeding the maximum specified 150
termperature. In practice this tells you how long you have to
alleviate the condition causing the current limiting to occur.

o

C junction

6-441

RLP1N08LE

Spice Model

.SUBCKT RLP1N08LE213;rev 09/16/91
*Nominal Temperature = 25oC
.MODEL MOSMOD NMOS (VTO=1.7 KP=2.1 IS=1e-30 N=10 TOS=1 L=1u W=1u)
Vto 21 6 0.33
Rsource 8 7 RDSMOD 0.28
Rdrain 5 16 RDSMOD 0.2
.MODEL RDSMOD RES (TC1=7.54E-3 TC2=2.23E-5)
.MODEL RVTOMOD RES (TC1=-2.23E3 TC2=-5.29E-7)
.MODEL RVTOMOD2 RES (TC1=0 TC2=0)
Ebreak 11 7 17 18 107.3
.MODEL RBKMOD RES (TC1=1.11E-3 TC2=-6.83E-7)
.MODEL DBKMOD D (RS=2.78 TRS1=-8.88E-3 TRS2=2.55E-5)
.MODEL DBDMOD D (IS=9.91E-15 RS=3.01E-1 TRS1=3.79E-3 TRS2=1.11E-6 +CJO=4.32E-10 TT=2E-7
Cin 6 8 3.75E-10
Ca 12 8 6.5E-10
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3 VOFF=-1)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1 VOFF=-3)
.MODEL DPLCAPMOD D (CJO=2E-10 IS=1e-30 N=10)
Cb 12 14 6.5E-10
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.65 VOFF=3.35)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=3.35 VOFF=-1.65)
Rgate 9 20 4.48E3
Lgate 1 9 9.5E-10
Ldrain 2 5 2.5E-9
Lsource 3 7 2.5E-9
Dbody 7 5 DBDMOD
Dbreak 5 11 DBKMOD
Dplcap 10 5 DPLCAPMOD
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg610681
Evto 20 6 18 8 1
It8171
MOS1 16 6 8 8 MOSMOD M=0.99
MOS2 16 21 8 8 MOSMOD M=0.01
Rbreak 17 18 RBKMOD 1
Rin 6 8 1e9
Rvto 18 19 RVTOMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
Vbat 8 19 DC 1
*Current Limiting Control Section
.MODEL RSMOD RES (TC1=3.2E-3)
Q Control 20 8 7 QMOD 10
.MODEL QMOD NPN (BF=5 VJE=0.5)
*ESD Protection
DESD 7 9 DESMOD
.MODEL DESMOD D(BV=7.185 TBV1=3.5E-4 TBV2=2.2E-6)
.ENDS

(RLP1N08LE)

6-442

RLP1N08LE

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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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