Datasheet RL0512PAG-712, RL0512PAQ-712, RL1024PAQ-712, RL1024PAG-712, RL2048PAG-712 Datasheet (Perkinelmer)
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Imaging
Telecom
Imaging Product Line
P-Series Linear Photodiode Array Imagers
14µm, single output, 512, 1024, 2048 elements
DATASHEET
Description
In the P-series linear imagers,
PerkinElmer has combined the best
features of high-sensitivity photodiode
array detection and high-speed chargecoupled scanning to offer an uncompromising solution to the increasing
demands of advanced imaging
applications.
These high-performance imagers
feature low noise, high sensitivity,
impressive charge storage capacity,
and lag-free dynamic imaging in a
convenient single-output architecture.
The 14 µm square contiguous pixels in
these imagers reproduce images with
minimum information loss and artifact
generation, while their unique photodiode structure provides excellent blue
response extending below 250 nm in
the ultraviolet.
The two-phase CCD readout register
requires only five volts for clocking
yet achieves excellent charge transfer
efficiency. Additional electrodes
provide independent control of exposure and antiblooming. Finally, the
high-sensitivity readout amplifier
provides a large output signal to relax
the noise requirements on the camera
electronics that follow.
Available in array lengths of 512, 1024
and 2048 elements with either lowcost glass or UV-enhanced fused silica
windows, these versatile imagers are
widely used in high-speed document
reading, web inspection, mail sorting,
production measurement and gauging
position sensing, spectroscopy and
many other industrial and scientific
applications requiring peak imager
performance.
Note: While the P-Series imagers have been
designed to resist electrostatic discharge
(ESD), they can be damaged from such discharges. Always observe proper ESD precautions when handling and storing this imager.
Features
• Extended spectral range—250 to
1000 nm
• 40 MHz pixel readout rate
• 2500:1 dynamic range
• 5-volt clocking
• Line rates to 70 kHz
• Ultra low image lag
• Electronic exposure control
• Antiblooming control
• Square pixels with 100% fill factor
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DSP-101 01H - 7/2002W Page 1
Linear Photodiode Array
Imagers
Description (cont.)
P-series imagers combine high-performance photodiodes with high-speed
CCD readout registers and a highsensitivity readout amplifier. Refer
to Figure 1 for construction details.
Light Detection Area
The light detection area in P-series
imagers is a linear array of contiguous
pinned photodiodes on 14 µm centers.
These photodiodes are constructed
using PerkinElmer’s advanced photodiode design that extends short-wavelength sensitivity into the deep UV
below 250 nm, while preserving 100%
fill factor and delivering extremely
low image lag. This unique design
also avoids polysilicon layers in the
light detection area that reduces the
quantum efficiency of most CCD
imagers. The P-series imagers are supplied with glass windows for general
visible use, and fused silica windows
for use in the ultraviolet below 350 nm.
See Figure 2 for the sensitivity and
window transmission curves.
For lowest lag, all P-series imagers
feature pinned photodiodes. Pinning,
which requires a special semiconductor process step, provides a uniform
internal voltage reference for the
charge stored in every photodiode.
This stable reference assures that
every photodiode is fully discharged
after every scan.
Figure 2a: Spectral Sensitivity Curve
100
90
80
70
2
60
50
40
Responsivity (V/ J/cm )
30
20
10
0
250
350 450
Left Scale
650
550
Wavelength (nm)
Figure 2b: Window Transmission Curve
100
Fused Silica
90
80
70
60
50
40
30
Transmission (%)
20
10
0
150
Photodiodes covered with light
shields included at one or both ends
of the imager provide a dark current
reference for clamping. These are
separated from the active photodiodes by two unshielded transition
Glass
550
450
350250
Wavelength (nm)
100
950
1050
850
90
80
70
60
50
QE (%)
40
30
20
10
0
1050
950
Right Scale
750 850
650
750
pixels that assure uniform response
out to the last active photodiode.
Due to the potential for light leakage, the two dark pixels nearest
the transition pixels should not
be used as a dark reference.
Figure 1: Imager Functional Diagram
N = 512 for the RL0512P
N = 1024 for the RL1024P
N = 2048 for the RL2048P
3 Isolation stages
10 Dark pixels (D1 ... D10)
2 Transition pixels (T1, T2)
(Light shield ends between D10 and T1)
N Active pixels (1...N)
2 Transition pixels (T3, T4)
(Light shield ends between T4 and D11)
10 Dark pixels (D11...D20) (Not used in RL0512P)
Output
Amp
3 CCD Isolation Stages
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D1 . . . . . . . . . . . . . . . . . . . .D10
{
Antiblooming/Exposure Control Gate
T1 T2 1
2-Phase Buried Channel CCD Shift Register
3
. . . . . . . . .
2
Transfer Gate
N-1
N
T3
T4
D11 . . . . . . . . . . . . . . . . . . . .D20
DSP-101 01H - 7/2002W Page 2
Linear Photodiode Array
Imagers
Figure 3: Transfer Timing Diagram
Horizontal Shift Registers
Charge packets collected in the photodiodes as light is received are converted
to a serialized output stream through a
buried-channel, two-phase CCD shift
register that provides high charge transfer efficiency at shift frequencies up to
40 MHz. The PerkinElmer 5-volt CCD
process used in this design enables
low-power, high-speed operation
with inexpensive, readily available
driver devices.
The transfer gate (Ø
movement of charge packets from the
photodiodes to the CCD shift register.
During charge integration, the voltage
controlling the transfer gate
held in its low state to isolate the
photodiodes from the shift register.
When transfer of charge to the shift
register is desired,
its high state to create a transfer
channel between the photodiodes and
the shift register. The charge transfer
sequence, detailed in Figure 4, proceeds
as follows:
After readout of a particular image line
(n), the shift register is empty of charge
and ready to accept new charge packets
from the photodiodes representing
image line (n+1). To begin the transfer
sequence, the horizontal clock pulses
(
ø
and ø2) are stopped with ø1held in
1
its high state, and
The transfer gate voltage phase (
then switched high to start the transfer
of charge to the shift register. Once the
transfer gate reaches its high state, the
photo gate voltage (
complete the transfer. It is recommended that the photo gate voltage be
held in the high state for at least 0.1 µs
to ensure complete transfer. After this
interval, the photo gate voltage is
returned to its low state, and when
that is completed, the transfer gate
voltage is also returned to the low
state. The details of the transfer timing
are shown in Figure 3 with ranges and
tolerances in Table 1.
After transfer, the charge is transported
along the shift register by the alternate
action of two horizontal phase voltages
TG) controls the
is
ø
is switched to
TG
ø
in its low state.
2
ø
) is set high to
PG
ø
) is
TG
t
6
t
5
Ø
PG
t
2
Ø
TG
Ø
AB
Ø
1
V
Out
Notes:
1. Transition and dark pixels
2. Active pixels
t
1
t
3
t
4
t
8
Note 1 Note 2
t
6
t
7
Table 1. Transfer Timing Requirements
Item Sym Min Typ Max
Delay of
ø
falling edge from
TG
ø
falling edge
PG
Delay of
ø
rising edge from end
TG
of
ø
and ø2clocks
1
Delay of
ø
rising edge from
AB
ø
falling edge
PG
ø
pulse width t
TG
ø
pulse width t
PG
Rise/fall time t
Integration time t
ø
pulse width t
AB
Note 1: 750ns is the typical time to fully reset the photodiode.
t
1
t
2
t
3
4
5
6
7
8
5 ns 20 ns -
0 ns 10 ns -
5 ns 5 ns -
100 ns 500 ns -
100 ns 400 ns -
10 ns 20 ns -
0 ns
--
-
750 ns
1
Figure 4: Readout Timing Waveforms
t
1
Ø
1
Ø
2
t
6
t
4
Ø
RG
t
2
t
5
-
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DSP-101 01H - 7/2002W Page 3
Linear Photodiode Array
Imagers
Horizontal Shift Registers (cont.)
ø
and ø2. While the two-phase CCD
1
shift register architecture allows
relaxed timing tolerances over those
required in three- or four-phase designs,
optimum charge transfer efficiency
and lowest power dissipation is
obtained when the overlap of the twophase CCD clocks occurs around the
50% transition level. Additionally, the
phase difference between signals
and ø2should be maintained near
180° and the duty cycle of both signals
should be set near 50% to prevent loss
of full-well charge storage capacity
and charge transfer efficiency. Readout
timing details are shown in Figure 4
with ranges and tolerances in Table 2.
Timing Requirements
In high-speed applications, fast
waveform transitions allow maximum
settling time of the output signal.
However, it is generally advisable to
use the slowest rise and fall times
consistent with required video
performance because fast edges tend
to introduce more transition noise
into the video waveform. When the
highest speeds are required, careful
smoothing of the waveform transitions
may improve the balance between
speed and video quality.
Output Amplifier
Charge emerging from the last stage
of the shift register is converted to a
voltage signal by a charge integrator
and video amplifier. The integrator, a
capacitor created by a floating diffusion,
is initially set to a DC reference voltage (V
voltage (
out the charge,
turning the reset transistor off and
isolating the integrator from V
next time
packet is transferred to the integrator
where it generates a voltage proportional to the packet size. The reset
transistor voltage,
its low state prior to the high-to-low
transition of
of the video signal will result if this
), by setting the reset transistor
RD
ø
) to its high state. To read
RG
ø
is pulsed low
RG
ø
goes low, the charge
1
ø
, must reach
RG
ø
. An apparent clipping
1
RD
ø
1
. The
Table 2. Readout Timing Requirements
Item Sym Min Typ Max
ø
, ø2clock period t
1
ø
, ø2rise/fall time t
1
ø
rise/fall time t
RG
ø
clock - high duration t
RG
Delay of
ø
high - low t
1
transition from
Note: The cross over point for ø1and ø2clock transitions should occur within the 10 - 90% level of the clock amplitude.
ø
low*
RG
1
2
4
5
6
25 ns - -
-5 ns -
-5 ns 5 ns - 0 ns - -
Table 3. Imager Performance (Typical)
Pixel count 512 elements (RL0512P)
1024 elements (RL1024P)
2048 elements (RL2048P)
Pixel size 14 µm x 14 µm
Exposure control yes
Horizontal clocking 2
Number of outputs 1
Dynamic range
1
Readout noise (rms)
amplifier 25 electrons
reset transistor 55 electrons
total noise without CDS 60 electrons
Saturation exposure
Noise equivalent exposure
2
2
Amplifier sensitivity 4 µV/electrons
Saturation output voltage 600 mv
Saturation charge capacity 150,000 electrons
Charge transfer efficiency 0.99995
Peak responsivity 25V/µJ/cm
PRNU match across array ±10%
Dead pixels 0
Lag < 1%
Spectral response range 250 nm - 1000 nm
Data rate (per output) 40 MHz
Notes:
1. Defined as Q
2. For illumination at 750 nm.
/rms noise (total).
sat
Ø (5V clock amplitude)
2500:1
24 nJ/cm
9.6 pJ/cm
2
2
2
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DSP-101 01H - 7/2002W Page 4
empera
ture
olta
ge
(with
respect
to
GND)
Linear Photodiode Array
Imagers
Output Amplifier (cont.)
condition is not satisfied. Figure 4
details the clock waveform requirements and overlap tolerances.
The video amplifier buffers the signal
from the integrator for output from the
imager. Care must be taken to keep the
load on this amplifier within its ability
to drive highly reactive or low impedance loads. The half power bandwidth
into an external load of 10 pF is
150 MHz. It is recommended that the
output video signal be buffered with a
wide bandwidth emitter follower or
other appropriate amplifier to provide
a large Z
Keep the external amplifier close to
the output pins to minimize stray
inductive and capacitive coupling of
the output signal that can harm
signal quality.
to the output amplifier.
IN
Table 4. Operating Voltages
Signal Function State Voltage Tolerance
ø
, ø
1
Horizontal Clocks High 5 ±5%
2
Low 0
ø
Transfer Gate High 8 ±10%
TG
Low 0
ø
Photo Gate High 8 ±5%
PG
Low -4
ø
Antiblooming Gate High 4 ±5%
AB
Low -4
V
ø
Output Gate 3 ±5%
OG
Reset Gate High 8 ±10%
RG
Low 0
V
V
V
RD
Amplifier Voltage Supply 12 ±5%
DD
Amplifier Reset Drain 9.5 ±5%
RD
/LS Amplifier Return / Light Shield 0
Table 5. Absolute Maximum Rating Above Which Useful Life May Be Impaired
Exposure Control and
Antiblooming
An exposure control feature in the
P-series imagers supports variable
charge accumulation time in the photodiode. When the antiblooming gate
voltage (
charge is drained from the pixel
storage gate to the exposure control
drain. During normal charge collection
in the photodiode,
state. Due to the timing requirements
of the exposure control mode, charge
is always accumulated at the end of
the period just before the charge is
transferred to the readout register.
Figure 3 includes the timing requirements for exposure control with the
antiblooming gate. The exposure
control timing shown will act on the
charge packets that emerge as video
data on the next readout cycle.
ø
) is set to its high state,
AB
ø
is set to its low
AB
Min Max Units
Tempera
ture
Storage -25 +85 ° C
Operating -25 +55 ° C
Volta
ge
(with
respect
to
GND)
Pins 3, 4, 17 - 19 -0.3 +18 V
Pins 2, 10, 20 -0.3 +18 V
Pins 1, 11 -0.3 + 0 V
Pins 15, 16 -4.3 +18 V
Precautionary Note: The CCD output pin (Pin #2) must never be shorted to either VSSor VDDwhile power is
applied to the device. Catastrophic device failure will result!
Imager Performance
In P-series images each element performs its own function admirably
while integrating smoothly with the
other elements on the team. The photodiodes efficiently transform light
to charge, the readout registers accurately transport the charge to the
amplifier, and the amplifier delivers
a clean, robust signal for use in
image processing electronics. While
the actual performance of these
imagers depends strongly on the
details of the electronics and timing
the camera provides, their straightforward implementation requirements facilitate optimum designs.
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DSP-101 01H - 7/2002W Page 5
Linear Photodiode Array
Imagers
Operating Conditions
For optimum performance and longest
life, carefully follow the operational
requirements of these imagers. Provide
stable voltage sources free of noise and
variation and clean waveforms with
controlled edges. Protect the imager
from electrostatic discharge and excessive voltages and temperature. Do not
violate the limits on output register
speed or reduce timing margins below
the minimums.
Imager Configuration
All P-series imagers are constructed
using ceramic packages and opticallyflat windows. Imager die are secured
to precision leadframes by thermal
silver-filled epoxy. Packages are baked
before sealing to elminate moisture,
and tested for seal integrity.
Table 6. Pinout Description and Capacitance Values of Clocked Phases
Capacitance (pF) (Typ)
Pin Sym Function Pixels 2048 1024 512
1V
2V
3
4
5 N/C No connection
6 N/C No connection
7 N/C No connection
8 N/C No connection
9 N/C No connection
10 V
11 LS Light shield/die attach
12 N/C No connection
13 N/C No connection
14 N/C No connection
15
16
17
18 V
19
20 V
Amplifier return 50 30 20
SS
Signal output 75 45 30
Out
ø
CCD horizontal phase 2 270 140 70
2
ø
CCD horizontal phase 1 350 180 90
1
Amplifier drain supply
DD
ø
Antiblooming gate 70 35 20
AB
ø
Photo gate 100 50 25
PG
ø
Transfer gate 90 50 25
TG
Output gate 8 8 8
OG
ø
Reset gate 7 2 2
RG
Reset drain
RD
Figure 5. Pinout Configuration
V
1
SS
V
2
Out
Ø
3
H2
4
Ø
H1
5
N/C
N/C
6
7
N/C
N/C
8
9
N/C
10
V
DD
20
V
RD
Ø
19
RG
V
18
OG
Ø
17
TG
Ø
16
PG
Ø
15
AB
14
N/C
13
N/C
12
N/C
11
LS
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DSP-101 01H - 7/2002W Page 6
Linear Photodiode Array
Imagers
Figure 6: Outline Drawings
Pixel 1
0.205 ± 0.0075
(5.21 ± 0.19)
•
0.450 ± 0.0075
(11.43 ± 0.19)
0.100 ± 0.005
(2.54 ± 0.13)
Ordering Information
The RL0512, RL1024 and RL2048
P-series imagers are available with
either glass or fused silica windows.
On special orders, PerkinElmer can
supply anti-reflectance coated windows
or windowless packages. Imagers are
individually packed in electrostaticresistant boxes and identified by lot
number for tracking.
A
Sensing Area
B
0.900 ± 0.005
(22.86 ± 0.13)
* Measurements in inches (millimeters)
* Maximum angular error is ±15 milliradians
0.395 ± 0.008
14 m
(10.03 ± 0.20)
0.020 ± 0.002
(0.50 ± 0.05)
0.300
0.170
(4.32)
(7.62)
0.018 ± 0.002
(0.46 ± 0.05)
able 7. Package Dimensions and Tolerances
T
0.020 ± 0.002
(0.508 ± 0.05)
0.400 ± 0. 010
(10.16 ± 0.25)
(at stand off)
0.020 ± 0.002
(0.508 ± 0.05)
0.080 ± 0.009
(2.032 ± 0.23)
AB
Device Inches mm Inches mm
RL0512P 0.284 7.224 1.500 ± 0.15 38.1 ±0.381
RL1024P 0.566 14.392 1.500 ± 0.15 38.1 ± 0.381
RL2048P 1.131 28.728 1.500 ± 0.15 38.1 ± 0.381
Notes:
1. Includes active and transition pixels.
able 8. Stock Part Numbers
T
Window
512 1024 2048
Glass RL0512PAG-712 RL1024PAG-712 RL2048PAG-712
Fused Silica RL0512PAQ-712 RL1024PAQ-712 RL2048PAQ-712
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Active Pixels
DSP-101 01H - 7/2002W Page 7
Linear Photodiode Array
Imagers
For more information e-mail us at
opto@perkinelmer.com or visit our web
site at www.perkinelmer.com/opto.
All values are nominal; specifications
subject to change without notice.
Table 9. Sales Offices
North America
United States PerkinElmer Optoelectronics
2175 Mission College Blvd.
Santa Clara, CA 95054
Toll Free: 800-775-OPTO (6786)
Phone: +1-408-565-0830
Fax:+1-408-565-0703
Europe
Germany PerkinElmer Optoelectronics GmbH
Wenzel-Jaksch-Str. 31
D-65199 Wiesbaden, Germany
Phone: +49-611-492-570
Fax:+49-611-492-165
Asia
Japan PerkinElmer Optoelectronics
NEopt. 18F, Parale Mitsui Building 8
Higashida-Cho, Kawasaki-Ku
Kawasaki-Shi, Kanagawa-Ken 210-0005 Japan
Phone: +81-44-200-9170
Fax:+81-44-200-9160
www.neopt.co.jp
Singapore 47 Ayer Rajah Crescent #06-12
Singapore 139947
Phone: +65-770-4925
Fax:+65-777-1008
© 2000 PerkinElmer Inc. All rights reserved. PerkinElmer, the PerkinElmer logo and the stylized “P” are trademarks of PerkinElmer, Inc. DSP-101.01H - 7/2002W
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Page 8
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