The RHR1K160 is a hyperfast diode with soft recovery
characteristics (t
< 25ns). It has half the recovery time of
rr
ultrafast diodes and is silicon nitride passivated ionimplanted epitaxial planar construction.
This device is intended for use as freewheeling/clamping
diodes and rectifiers in a variety of switching power supplies
and otherpowerswitching applications. Its low stored charge
and hyperfast soft recovery minimize ringing and electrical
noise in many power switching circuits reducing power loss
in the switching transistors.
Formerly developmental type TA49185.
Ordering Information
PART NUMBERPACKAGEBRAND
RHR1K160MS-012AARHR1K160
NOTE: When ordering, use the entire partn umber. For ordering in tape
and reel, add the suffix 96 to the part number, i.e. RHR1K16096.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IF = 1A, dIF/dt = 200A/µs--25ns
IF = 1A, dIF/dt = 200A/µs-10.5-ns
IF = 1A, dIF/dt = 200A/µs-5-ns
IF = 1A, dIF/dt = 200A/µs-20-nC
VR = 10V, IF = 0A-10-pF
Pad Area = 0.769 in2(Note 1)--50
Pad Area = 0.054 in2(Note 2) (Figure 13)--177
Pad Area = 0.0115 in2(Note 2) (Figure 13)--217
DEFINITIONS
VF = Instantaneous forward voltage (pw = 300µs, D = 2%).
IR = Instantaneous reverse current.
trr= Reverse recovery time (See Figure 10), summation of ta+tb.
ta = Time to reach peak reverse current (See Figure 10).
tb = Time from peak IRM to projected zero crossing of IRM based on a straight line from peak IRM through 25% of IRM (See Figure 10).
Qrr = Reverse recovery charge.
CJ = Junction Capacitance.
R
= Thermal resistance junction to ambient.
θJA
pw = Pulse width.
D = Duty cycle.
NOTES:
1. Measured using FR-4 copper board at 3.2 seconds.
2. Measured using FR-4 copper board at 1000 seconds.
o
o
o
C/W
C/W
C/W
3-2
Page 3
Typical Performance Curves
RHR1K160
10
100oC
1
, FORWARD CURRENT (A)
F
I
0.1
00.511.522.54
150oC
VF, FORWARD VOLTAGE (V)
25oC
3.53
10
1
0.1
REVERSE CURRENT (µA)
0.01
R,
I
0.001
0600100500200
o
150
C
o
C
100
25oC
300400
VR, REVERSE VOLTAGE (V)
FIGURE 1. FORWARD CURRENT vs FORWARD VOLTAGEFIGURE 2. REVERSE CURRENT vs REVERSE VOLTAGE
FIGURE 3. trr,taAND tbCURVES vs FORWARD CURRENTFIGURE 4. trr,taAND tbCURVES vs FORWARD CURRENT
50
TA = 150oC, dIF/dt = 200A/µs
40
30
20
t, RECOVERY TIMES (ns)
10
0
0.1
t
rr
t
b
t
a
0.5
IF, FORWARD CURRENT (A)
1
1.0
0.8
0.6
0.4
0.2
, AVERAGE FORWARD CURRENT (A)
0
F(AV)
I
SQ. WAVE
DC
507512525150100
, AMBIENT TEMPERATURE (oC)
T
A
R
θJA
= 50oC/W
FIGURE 5. trr,taAND tbCURVES vs FORWARD CURRENTFIGURE 6. CURRENT DERATING CURVE
1
3-3
Page 4
Typical Performance Curves (Continued)
50
40
30
20
10
, JUNCTION CAPACITANCE (pF)
J
C
0
020406010080
FIGURE 7. JUNCTION CAPACITANCE vs REVERSE VOLTAGE
RHR1K160
, REVERSE VOLTAGE (V)
V
R
10
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
1
0.05
0.02
0.01
, NORMALIZED
0.1
JA
θ
Z
THERMAL IMPEDANCE
0.01
-5
10
SINGLE PULSE
-4
10
10
FIGURE 8. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
Test Circuits and Waveforms
VGE AMPLITUDE AND
RG CONTROL dIF/dt
t
1 ANDt2
CONTROL I
F
L
R
= 50oC/W
θJA
P
DM
t
1
t
JA
1/t2
10
x R
2
2
+ T
JA
A
θ
3
10
NOTES:
DUTY FACTOR: D = t
PEAK TJ = PDM x Z
-3
-2
10
-1
10
0
10
1
10
θ
t, RECTANGULAR PULSE DURATION (s)
DUT
CURRENT
R
G
V
GE
t
1
t
2
IGBT
SENSE
dI
+
V
DD
-
0
F
I
F
dt
t
rr
t
a
t
b
0.25 I
RM
I
RM
FIGURE 9. trr TEST CIRCUITFIGURE 10. trr WAVEFORMS AND DEFINITIONS
3-4
Page 5
RHR1K160
Test Circuits and Waveforms (Continued)
L = 20mH
R < 0.1Ω
E
AVL
Q
= IGBT (BV
1
= 1/2LI2 [V
Q
CES
1
R(AVL)
> DUT V
/(V
R(AVL)
R(AVL)
CURRENT
SENSE
DUT
- VDD)]
)
LR
V
+
V
DD
I
L
IV
V
DD
-
t
0
AVL
I
L
t
1
t
2
FIGURE 11. AVALANCHE ENERGY TEST CIRCUITFIGURE 12. AVALANCHE CURRENT AND VOLTAGE
WAVEFORMS
Thermal Resistance vs Mounting Pad Area
The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maximum allowabledevicepower dissipation, P
DM
,inan
application.Therefore the application’s ambient temperature,
T
(oC), and thermal resistance R
A
reviewed to ensure that T
JM
is never exceeded. Equation 1
(oC/W) must be
θJA
mathematically represents the relationship and serves as
the basis for establishing the rating of the part.
P
TJMTA–()
-----------------------------=
DM
Z
θJA
(EQ. 1)
In using surface mount devices such as the SO-8 package,
the environment in which it is applied will have a significant
influence on the part’s current and maximum power
dissipation ratings. Precise determination of the P
DM
is
complex and influenced by many factors:
1. Mounting padarea onto which the device isattached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle andthe transient thermal response ofthe part,
the board and the environment they are in.
Intersil provides thermal information to assist the designer’s
preliminary application evaluation. Figure 13 defines the
for the device as a function of the top copper
R
θJA
(component side) area. This is for a horizontally positioned
FR-4 board with 2 oz. copper after 1000 seconds of steady
state power with no air flow. This graph provides the
necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Intersil device Spice
thermal model or manually utilizing the normalized maximum
transient thermal impedance curve.
350
300
C/W)
o
250
200
217oC/W - 0.0123in
150
, THERMAL IMPEDANCE
θJA
100
R
JUNCTION TO AMBIENT (
50
0.001
CATHODE MOUNTING AREA, TOP COPPER AREA (in
FIGURE 13. THERMAL RESISTANCEvs MOUNTING PAD
AREA
Displayed on the curve are R
R
= 101.6 - 25.82 x ln(AREA)
θJA
2
0.01
values listed in the
θJA
Electrical Specifications table. These points were chosen to
depict the compromise between the copper board area, the
thermal resistance and ultimately the power dissipation,
P
. Thermal resistances corresponding to other
DM
component side copper areas can be obtained from Figure
13 or by calculation using Equation 2. The area, in square
inches is the top copper area including the cathode pad
area.
R
θJA
101.6 25.82Area()ln×–=
177oC/W - 0.054in
0.11.0
t
2
(EQ. 2)
2
)
3-5
Page 6
RHR1K160
The transient thermal impedance (Z
) is also effected by
θJA
various top copper board areas. Figure 14 shows the effect
of copper pad area on the single pulse transient thermal
impedance. Each trace represents a copper pad area in
square inches corresponding to the descending list in the
graph. Spice and SABER thermal models are provided for
each of the listed pad areas.
150
COPPER BOARD AREA - DESCENDING ORDER
2
0.049 in
2
0.296 in
2
0.523 in
0.769 in
1.000 in
-1
2
2
0
10
t, RECTANGULAR PULSE DURATION (s)
FIGURE 14. TRANSIENT THERMAL IMPEDANCE vs MOUNTING PAD AREA
100
C/W)
o
, THERMAL
JA
θ
Z
IMPEDANCE (
50
0
10
Copper pad area has no perceivable effect on transient
thermal impedance for pulse widths less than 100ms. For
pulse widths less than 100ms the transient thermal
impedance is determined by the die and package. Therefore,
CTHERM1 through CTHERM5 and RTHERM1 through
RTHERM4 remain constant for each of the thermal models.
A listing of the model component values is available in
Table 1.
1
10
2
10
3
10
3-6
Page 7
RHR1K160
SPICE Thermal Model
th
JUNCTION
REV August 1998
RHR1K160
Copper Area = 0.769 in
CTHERM1 th 8 5e-6
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only.Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However ,no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
3-7
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RHR1K160
MS-012AA
8 LEAD JEDEC MS-012AA SMALL OUTLINE PLASTIC PACKAGE