Datasheet RFW2N06RLE Datasheet (Intersil)

RFW2N06RLE

Data Sheet July 1999

2A, 60V, 0.160 Ohm, Logic Level,
N-Channel Power MOSFET

The RFW2N06RLE N-Channel, logic level, ESD protected,
power MOSFET is manufactured using the MegaFET
process. This process, which uses feature sizes
approaching those of LSI integrated circuits, gives optimum
utilization of silicon, resulting in outstanding performance.
The RFW2N06RLE was designed for use with logic level
(5V) driving sources in applications such as programmable
controllers, automotive switching, switching regulators,
switching converters, motor and relay drivers and emitter
switches for bipolar transistors. This performance is
accomplished through a special gate oxide design which
provides full rated conductance at gate biases in the 3V to
5V range, thereby facilitating true on-off power control
directly from logic circuit supply voltages.

Formerly developmental type TA9861.

Ordering Information

PART NUMBER PACKAGE BRAND

RFW2N06RLE HEXDIP RFW2N06RLE

NOTE: When ordering, use the entire part number.

File Number

Features

• 2A, 60V
(on) = 0.160Ω

•r

DS

• UIS Rating Curve (Single Pulse)

• Design Optimized For 5 Volt Gate Drive

• Can be Driven Directly from CMOS, NMOS, TTL

Circuits

• Compatible with Automotive Drive Requirements

• SOA is Power Dissipation Limited

• Nanosecond Switching Speeds

• Linear Transfer Characteristics

• High Input Impedance

• Majority Carrier Device

• Electrostatic Discharge Protected

• Related Literature

- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”

Symbol

D

2838.3

Packaging

G

S

4 PIN HEXDIP

DRAIN

GATE

SOURCE

6-283

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.

http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

RFW2N06RLE

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Specified

C

RFW2N06RLE UNITS

Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

DGR

Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Maximum Power Dissipation (Figure 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

DS

D

DM

GS

D

60 V
60 V

2

14

-5 to 10 V

1.09 W

A
A

Linear Derating Factor (Figure 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.009 W/oC

Single Pulse Avalanche Energy Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E

AS

Refer to UIS Curve

Electrostatic Discharge Rating, MIL-STD-883, Catagory B(2). . . . . . . . . . . . . . . . . . . . . . . .ESD 2 KV

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ,T

STG

-55 to 150

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

L

pkg

300
260

o

C

o

C

o

C

NOTE:

1. TJ= 25oC to 125oC.

Electrical Specifications T

= 25oC, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV
Gate Threshold Voltage V
Zero Gate Voltage Drain Current I

DSSID

GS(TH)VGS

DSS

=250µA, VGS = 0V 60 - - V

= VDS, ID = 250µA1-2V
VDS = Rated BV
VDS = 0.8 x Rated BV

, VGS = 0V - - 1 µA

DSS

DSS

, VGS = 0V

--25µA

TC = 125oC

Gate to Source Leakage Current I
Drain to Source On Resistance (Note 2) r

GSS

DS(ON)ID

VGS =-5V to 10V - - ±100 nA

= 2A, VGS = 5V (Figure 8) - - 160 mΩ

ID = 2A, VGS = 4.3V (Figure 8) - - 200 mΩ

Turn-On Time t
Turn-On Delay Time t

(ON)

d(ON)

Rise Time t
Turn-Off Delay Time t

d(OFF)

Fall Time t
Turn-Off Time t
Total Gate Charge Q

(OFF)
g(TOT)VGS

Gate Charge at 5V Qg(5) VGS = 0 to 5V - 11 16 nC
Threshold Gate Charge Qg(TH) VGS = 0 to 1V - 0.6 1.0 nC

Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Thermal Resistance, Junction to Ambient R

OSS
RSS

θJA

VDD = 30V, ID = 2A, RL = 15Ω, VGS = 5V,
RG = 25Ω (Figures 12, 13, 14)

r

f

= 0 to 10V VDD = 48V, ID = 2A,

I

G(REF)

RL = 24Ω
(Figures 12, 15, 16)

VDS = 25V, VGS = 0V, f = 1MHz

ISS

(Figure 11)

- - 100 ns

-13- ns

-42- ns

-95- ns

-45- ns

- 200 ns

-2030nC

=0.5mA,

- 535 - pF

- 175 - pF

-32-pF

- - 115oC/W

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage (Note 2) V

SD

Reverse Recovery Time t

NOTES:

2. Pulse test: width ≤ 300µs duty cycle ≤ 2%.

3. Repetitive rating: pulse width limited by maximum junction temperature.

6-284

ISD = 2A - - 1.2 V
ISD = 2A, dlSD/dt = 100A/µs - - 200 ns

rr

RFW2N06RLE

Typical Performance Curves

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 150

TC, CASETEMPERATURE (oC)

Unless Otherwise Specified

125

FIGURE 1. NORMALIZEDPOWER DISSIPATION vs CASE

TEMPERATURE

10

ID MAX CONTINUOUS

1

OPERATION IN THIS

0.10

, DRAIN CURRENT, (A)

D

I

AREA IS LIMITED
BY r

DS(ON)

TJ = MAX RATED
T

= 25oC

C

2.5

2.0

1.5

1.0

, DRAIN CURRENT (A)

D

I

0.5

0

25 75 125

50 100

TC, CASE TEMPERATURE (oC)

FIGURE 2. MAXIMUMCONTINUOUSDRAIN CURRENT vs

CASE TEMPERATURE

50

IF R = 0

(A)

AS

I

= (L)(Ias) / (1.3 RATED BV

t

av

IF R ≠ 0

= (L/R) IN ((Ias x R) / (1.3 RATED BV

t

av

Idm

10

- VDD)

DSS

- VDD) + 1)

DSS

STARTING TJ = 25oC
STARTING T

= 150oC

J

150

0.01

0.1 1 10 100
, DRAIN TO SOURCE VOLTAGE (V)

V

DS

1

0.01 0.1 1 10
T

, TIME IN AVALANCHE (ms)

AV

FIGURE 3. FORWARD BIAS SAFE OPERATING AREA FIGURE 4. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY

15

10

5

, DRAIN TO SOURCE CURRENT (A)

D

I

0

0123456

5V

10V

V

DS

4V

, DRAIN TO SOURCE VOLTAGE (V)

PULSE DURATION = 250µs
DUTY CYCLE = 0.5% MAX
T

C

= 25oC

3V

2V

15

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

= 15V

V

DD

-55oC

o

25

10

5

, DRAIN TO SOURCE CURRENT (A)

DS(ON)

I

0

0123456

, GATE TO SOURCE VOLTAGE (V)

V

GS

150

C

o

C

FIGURE 5. SATURATION CHARACTERISTICS FIGURE 6. TRANSFER CHARACTERISTICS

6-285

RFW2N06RLE

Typical Performance Curves

1.50

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
ID = 2A

1.25

1.00

ON RESISTANCE

0.75

NORMALIZED DRAIN TO SOURCE

0.50

4.0 4.5 5.0 5.5 6.0 6.5 7.0
, GATE TO SOURCE VOLTAGE (V)

V

GS

Unless Otherwise Specified (Continued)

FIGURE 7. NORMALIZED DRAINTO SOURCE ON VOLTAGE

vs GATE VOLTAGE

1.50

1.25

= VDS, ID = 250µA

V

GS

2.5

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 5V, ID = 2A

2.0

1.5

1.0

ON RESISTANCE

0.5

NORMALIZED DRAIN TO SOURCE

0

-50 0 50
T

, JUNCTION TEMPERATURE (oC)

J

100

FIGURE 8. NORMALIZEDDRAINTO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

1.50

= 250µA

I

D

1.25

150

1.00

0.75

0.50

0.25

NORMALIZED GATE THRESHOLD VOLTAGE

-50 0 50
T

, JUNCTION TEMPERATURE (oC)

J

100

150

FIGURE 9. NORMALIZEDGATE THRESHOLD VOLTAGE vs

JUNCTION TEMPERATURE

1500

1200

900

C

C

C

ISS

OSS

RSS

600

C, CAPACITANCE (pF)

300

0

01020

515

VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS = 0V, f = 1MHz

= CGS + C

C
C
C

ISS
RSS
OSS

= C

≈ CDS + C

GD

GD

GS

FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

1.00

0.75

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0.50

-50 0 50
TJ, JUNCTION TEMPERATURE (oC)

100

150

FIGURE 10. NORMALIZEDDRAINTO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

DSS

10

5

, GATE TO SOURCE VOLTAGE (V)

GS

V

0

60

45

30

VDD = BV

15

, DRAIN TO SOURCE VOLTAGE (V)

DS

V

25

0

20

DSS

DRAIN SOURCE VOLTAGE

I

G(REF)

I

G(ACT)

RL = 30Ω

I

G(REF)

V

SOURCE

VOLTAGE

0.75 BV

0.50 BV

0.25 BV

= 0.5mA

= 5V

GS

GATE

DSS
DSS
DSS

0.50 BV

0.25 BV

VDD = BV

0.75 BV

DSS

DSS

DSS

I

80t, TIME (µs)

I

G(REF)
G(ACT)

NOTE: Refer to Harris Application Notes AN7254 and AN7260.

FIGURE 12. NORMALIZEDSWITCHING WAVEFORMS FOR

CONSTANT GATE CURRENT

6-286

Test Circuits and Waveforms

RFW2N06RLE

t

ON

0V

t

d(ON)

90%

50%

10%

t

r

PULSE WIDTH

R

L

V

DS

V

GS

V

GS

R

GS

DUT

+

-

V

DS

0

V

GS

10%

0

t

d(OFF)

90%

FIGURE 13. SWITCHING TIME TEST CIRCUIT FIGURE 14. RESISTIVE SWITCHING WAVEFORMS

V

I

G(REF)

DS

R

L

V

GS

DUT

+

V

DD

-

V

DD

VGS= 1V

0

Q

g(TOT)

V

DS

Q

g(5)

V

GS

Q

g(TH)

VGS= 5V

t

OFF

50%

t

f

10%

VGS= 10V

90%

I

G(REF)

0

FIGURE 15. GATE CHARGE TEST CIRCUIT FIGURE 16. GATE CHARGE WAVEFORMS

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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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