Datasheet RFT1P06E Datasheet (Intersil)

RFT1P06E

Data Sheet August 1999

1.4A, 60V, 0.285 Ohm, ESD Rated,
P-Channel Power MOSFET

These products are P-Channel power MOSFETs
manufactured using the MegaFET process. This process,
which uses feature sizes approaching those of LSI circuits,
gives optimum utilization of silicon, resulting in outstanding
performance. They were designed for use in applications
such as switching regulators, switching converters, motor
drivers, and relay drivers. These transistors can be operated
directly from integrated circuits.

Formerly developmental type TA49044.

Ordering Information

PART NUMBER PACKAGE BRAND

RFT1P06E SOT-223 R1P06E

NOTE: RFT1P06E is available only in tape and reel.

File Number

Features

• 1.4A, 60V

•r

• 2kV ESD Protected

• Temperature Compensating PSPICE

• SPICE Thermal Model

• Peak Current vs Pulse Width Curve

• UIS Rating Curve

• 150

• Related Literature

- TB334, “Guidelines for Soldering Surface Mount

= 0.285Ω

DS(ON)

o

C Operating Temperature

Components to PC Boards”

®

Model

Symbol

D

4495.1

Packaging

G

S

SOT-223

DRAIN

(FLANGE)

SOURCE

DRAIN

GATE

4-171

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.

PSPICE® is a registered trademark of MicroSim Corporation.

http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999.

RFT1P06E

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Specified

A

RFT1P06E UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

DSS

DGR

GS

-60 V

-60 V

±20V V

Drain Current

Continuous (Figure 2) (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

D

DM

AS

D

Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, T

STG

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

L

pkg

1.4

Figure 5

Figures 6, 14, 15

1.1

9.09

-55 to 150

300
260

A

W

mW/oC

o

C

o

C

o

C

NOTE:

1. TJ = 25oC to 125oC.

Electrical Specifications T

= 25oC, Unless Otherwise Specified

A

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV
Gate to Source Threshold Voltage V
Zero Gate Voltage Drain Current I

DSSID

GS(TH)VGS

DSS

= 250µA, VGS = 0V (Figure 11) -60 - - V

= VDS, ID = 250µA (Figure 10) -2 - -4 V
VDS = -60V, VGS = 0V - - -1 µA
VDS = -60V, VGS = 0V, TA = 150oC - - -50 µA

Gate to Source Leakage Current I
Drain to Source On Resistance r

DS(ON)ID

Turn-On Time t
Turn-On Delay Time t

d(ON)

Rise Time t
Turn-Off Delay Time t

d(OFF)

Fall Time t
Turn-Off Time t
Total Gate Charge Q

g(TOT)VGS

Gate Charge at 10V Q
Threshold Gate Charge Q

Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Thermal Resistance Junction to Ambient R

GSS

ON

OFF

g(-10)
g(TH)

ISS
OSS
RSS

θJA

VGS = ±10V - - ±100 nA

= 1.4A, VGS = -10V (Figure 9) - 0.215 0.285 W

VDD = -30V, I
RL = 21.4Ω, VGS= -10V,
RGS = 18Ω

r

≅ 1.4A,

D

- - 51 ns

-9-ns

-25-ns

-35-ns

f

-28-ns

- - 95 ns

= 0V to -20V VDD = -30V, ID≅ 1.4A,
VGS = 0V to -10V - 17 20 nC
VGS = 0V to -2V - 1.1 1.3 nC

RL = 21.4Ω
I

= 1.0mA

G(REF)

(Figure 13)

VDS =-25V, VGS = 0V,
f = 1MHz
(Figure 12)

-3137nC

- 600 - pF

- 175 - pF

-40-pF
Pad Area = 0.122in2 (Note 2) - - 110
Pad Area = 0.071in2 (Note 2) - - 119

- - 137

o
o
o

C/W
C/W
C/WPad Area = 0.026in2 (Note 2)

NOTE:

2. 110oC/W measured using FR-4 board with 0.122in2 footprint at 1000 seconds (See Technical Brief 337).

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage V
Reverse Recovery Time t
Reverse Recovered Charge Q

4-172

SD

rr

RR

ISD = -1.4A - - -1.25 V
ISD = -1.4A, dISD/dt = -100A/µs--71ns
ISD = -1.4A, dISD/dt = -100A/µs - - 192 nC

Typical Performance Curves

RFT1P06E

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 150

125

TA, AMBIENT TEMPERATURE (oC)

FIGURE 1. NORMALIZEDPOWERDISSIPATIONvs AMBIENT

TEMPERATURE

DUTY CYCLE - DESCENDING ORDER

1

0.5

0.2

0.1

0.1

0.05

0.02

0.01

0.001

0.01

SINGLE PULSE

-5

10

-4

10

-3

10

10

t, RECTANGULAR PULSE DURATION (s)

, NORMALIZED

θJA

Z

THERMAL IMPEDANCE

0.0001

-1.5

R

= 110 oC/W

θJA

-1.125

-0.75

, DRAIN CURRENT (A)

-0.375

D

I

-0
25 50 75 100 125 150

TA, AMBIENT TEMPERATURE (oC)

FIGURE 2. MAXIMUMCONTINUOUSDRAIN CURRENT vs

AMBIENT TEMPERATURE

R

= 110 oC/W

θJA

P

DM

t

1

t

NOTES:
DUTY FACTOR: D = t
PEAK TJ = PDM x Z

-2

-1

10

0

10

1

10

θJA

1/t2

10

x R

2

+ T

θJA

A

2

3

10

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

-100
TJ = MAX RATED

T

= 25oC

A

-10

-1

, DRAIN CURRENT (A)

D

I

OPERATION IN THIS
AREA MAY BE
LIMITED BY r

-0.1

-1 -10 -100

DS(ON)

, DRAIN TO SOURCE VOLTAGE (V)

V

DS

V

DSS(MAX)

= -60V

100µs

1ms

10ms

-30

-10

, PEAK CURRENT (A)

DM

I

-1

-3

10

-2

10

TA = 25oC

FOR TEMPERATURES
ABOVE 25
CURRENT AS FOLLOWS:

-1

10

0

10

t, PULSE WIDTH (s)

I = I

o

C DERATE PEAK

25

1

10

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY

4-173

150 - T

125

A

2

10

3

10

RFT1P06E

Typical Performance Curves

-10
If R = 0
tAV = (L)(IAS)/(1.3*RATED BV

If R ≠ 0
t

= (L/R)ln[(IAS*R)/(1.3*RATED BV

AV

STARTING TJ = 150oC

, AVALANCHE CURRENT (A)

AS

I

-1

0.01 0.1 1 100
tAV, TIME IN AVALANCHE (ms)

DSS

(Continued)

- VDD)

- VDD) +1]

DSS

STARTING TJ = 25oC

10

NOTE: Refer to Intersil Application Notes AN9321 and AN9322.

FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY

-20

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD= -15V

-15

-55oC

o

C

25

-20

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TA = 25oC

-15

-10

, DRAIN CURRENT (A)

-5

D

I

0

0 -1.5 -3.0 -4.5 -6 -7.5

VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS = -20V

V

FIGURE 7. SATURATION CHARACTERISTICS

2.5

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V

= -10V, ID = -1.4A

GS

2.0

= -10V

GS

VGS = -7V

VGS = -6V

VGS = -5V

-10

DRAIN CURRENT (A)

-5

D,

I

0

0

-2 -4 -6 -8 -10
VGS, GATE TO SOURCE VOLTAGE (V)

150oC

1.5

ON RESISTANCE

1.0

NORMALIZED DRAIN TO SOURCE

0.5

-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)

FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. NORMALIZEDDRAINTO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

1.2

1.0

0.8

NORMALIZED GATE

0.6

THRESHOLD VOLTAGE

0.4

-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)

VGS = VDS, ID = -250µA

1.2
ID = -250µA

1.1

1.0

0.9

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0.8

-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)

FIGURE 10. NORMALIZEDGATE THRESHOLD VOLTAGE vs

JUNCTION TEMPERATURE

4-174

FIGURE 11. NORMALIZEDDRAIN TO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

RFT1P06E

Typical Performance Curves

800

C

C

C

ISS

OSS

RSS

600

400

C, CAPACITANCE (pF)

200

0

0 -10 -20 -30 -40 -50 -60

VDS, DRAIN TO SOURCE VOLTAGE (V)

(Continued)

VGS = 0V, f = 1MHz

= CGS + C

C
C
C

ISS
RSS
OSS

= C
= CDS + C

GD

GD

GD

-10
WAVEFORMS IN
DESCENDING ORDER:

ID = -1.4A

-8

-6

-4

-2

, GATE TO SOURCE VOLTAGE (V)

GS

V

0

= -1.0A

I

D

= -0.5A

I

D

0 5 10 15 20

Q

VDD = -30V

, GATE CHARGE (nC)

g

FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE NOTE: Refer to Intersil Application Notes AN7254 and AN7260.

FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT

GATE CURRENT

Test Circuits and Waveforms

V

VARY tP TO OBTAIN
REQUIRED PEAK I

0V

t

P

-V

GS

AS

DS

L

0

R

G

DUT

I

AS

0.01Ω

-

V

DD

+

V

DD

I

AS

t

P

BV

t

AV

V

DS

DSS

FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT

V

DS

R

L

V

I

G(REF)

GS

DUT

-

V

+

FIGURE 16. GATE CHARGE TEST CIRCUIT

4-175

DD

FIGURE 15. UNCLAMPED ENERGY WAVEFORMS

Q

GS

g(TH)

Q

g(-10)

Q

g(TOT)

VGS= -10V

0

VGS= -2V

V

DD

0

I

G(REF)

-V

FIGURE 17. GATE CHARGE WAVEFORM

V

DS

VGS= -20V

RFT1P06E

Test Circuits and Waveforms

V

GS

0V

R

GS

-V

GS

(Continued)

R

L

V

DS

DUT

-

+

FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. RESISTIVE SWITCHING WAVEFORMS

Thermal Resistance vs Mounting Pad Area

The maximum rated junction temperature, T
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, P
in an application. Therefore the application’s ambient
temperature, T
must be reviewed to ensure that T

(oC), and thermal impedance R

A

J(MAX)

(oC) is never
exceeded. Equation 1 mathematically represents the
relationship and serves as the basis for establishing the
rating of the part.

J(MAX)

θJA

, and the

D(MAX)

(oC/W)

,

t

ON

t

d(ON)

t

0

V

DS

0

10%

V

GS

r

10%

90%

50%

PULSE WIDTH

t

d(OFF)

t

OFF

50%

90%

90%

t

f

10%

state power with no air flow. This graph provides the
necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Intersil device Spice
thermal model or manuallyutilizingthenormalizedmaximum
transient thermal impedance curve.

200

R

= 73.0 - 17.4 * ln(AREA)

θJA

P

DMAX

JMAXTA

--------------------------------------- -=

R

θJA

(EQ. 1)

T

–()

In using surface mount devices such as the SOT-223
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of the
P

is complex and influenced by many factors:

D(MAX)

1. Mounting pad area ontowhichthedevice is attached and
whether there is copper on one side or both sides of the
board.

2. The number of copper layersand the thickness of the
board.

3. The use of external heat sinks.

4. The use of thermal vias.

5. Air flow and board orientation.

6. For non steady state applications, the pulse width, the
duty cycleandthetransient thermal responseofthepart,
the board and the environment they are in.

Intersil provides thermal information to assist the designer’s
preliminary application evaluation. Figure 20 defines the

for the device as a function of the top copper

R

θJA

(component side) area. This is for a horizontally positioned
FR-4 board with 1oz copper after 1000 seconds of steady

150

C/W)

o

(

θJA

R

119oC/W - 0.071in

100

50

0.01 0.1 1.0

137oC/W - 0.026in

2

AREA, TOP COPPER AREA (in2)

2

110oC/W - 0.122in

2

FIGURE 20. THERMAL RESISTANCE vs MOUNTING PAD AREA

Displayed on the curve are the three R

values listed in

θJA

the Electrical Specifications table. The three points where
chosen to depict the compromise between the copper board
area, the thermal resistance and ultimately the power
dissipation, P

. Thermal resistances corresponding to

D(MAX)

other component side copper areas can be obtained from
Figure 20 or by calculation using Equation 2. The area, in
square inches is the top copper area including the gate and
source pads.

θJA

73.0 17.4 Area()ln×–=

(EQ. 2)

R

4-176

SG

RFT1P06E

PSPICE Electrical Model

SUBCKT RFT1P06E 2 1 3; rev 10/16/97

CA 12 8 7.42e-10
CB 15 14 8.04e-10
CIN 6 8 5.5e-10

DBODY 5 7DBODYMOD
DBREAK 7 11 DBREAKMOD
DPLCAP 10 6DPLCAPMOD
DESD1 91 9 DESD1MOD
DESD2 91 7DESD2MOD

EBREAK 5 11 17 18 -69.1

DPLCAP

EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 5 10 8 6 1
EVTHRES 6 21 19 8 1
EVTEMP 6 20 18 22 1

IT 8 17 1
LDRAIN 2 5 1e-9

GATE

1

LGATE

RLGATE

RGATE

9

DESD1

91

DESD2

EVTEMP

20

18

22

LGATE 1 9 1.73e-9
LSOURCE 3 7 3.9e-10

MMED 16 6 8 8 MMEDMOD

S1A

12

MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD

RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 9.52e-2
RGATE 9 20 3.95
RLDRAIN 2 5 10

S1B

CA

EGS

RLGATE 1 9 17.3
RLSOURCE 3 7 39
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD .144
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1

S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD

VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*22),9))}
.MODEL DBODYMOD D (IS = 4.15e-15 RS = 5.54e-2 TRS1 = -1.32e-3 TRS2 = -2.48e-6 CJO = 6.06e-10 TT = 7.54e-8)

.MODEL DBREAKMOD D (RS = 4.66e-1 TRS1 = 1.48e-3 TRS2 = -7.49e-6)
.MODEL DPLCAPMOD D (CJO = 2.49e-10 IS = 1e-30 N = 10)
.MODEL DESD1MOD D (BV=20.2 TBV1=-1.25e-3 TBV2=5.79e-7 RS=36 NBV=1 IBV=7e6)
.MODEL DESD2MOD D (BV=25.4 TBV1=-8.3e-4 TBV2=8.9e-7 NBV=1 IBV=7e6)
.MODEL MMEDMOD NMOS (VTO = -3.32 KP =.258 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MSTROMOD NMOS (VTO = -3.824 KP = 4.8 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = -3.0 KP = 0.05 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL RBREAKMOD RES (TC1 = 9.48e-4 TC2 = -1.42e-7)
.MODEL RDRAINMOD RES (TC1 = 5.4e-3 TC2 = 1.25e-5)
.MODEL RSLCMOD RES (TC1 = 1.75e-3 TC2 = 3.9e-6)
.MODEL RSOURCEMOD RES (TC1 = 5.4e-3 TC2 = 1.25e-5)
.MODEL RVTHRESMOD RES (TC1 = 0 TC2 = 0)
.MODEL RVTEMPMOD RES (TC1 = -3.55e-3 TC2 = -3.43e-6)

.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON =5.1 VOFF= 3.1)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON =3.1 VOFF= 5.1)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.10 VOFF= -2.9)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.9 VOFF= 2.10)

.ENDS

NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global

Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.

E

5

+

10

13

8

8
6

RSLC1

CIN

CB

51

+

5
8

51
+

5

ESLC

50
RDRAIN

MSTRO

14

MWEAK

RBREAK

17

RVTHRES

17
18

IT

EBREAK

16

21

MMED

8

DBREAK

RSOURCE

8

RSLC2

EVTHRES

+

19

+

13

+

8

6

S2A

15

14
13

S2B

6

EDS

8

+

11

7

18

RVTEMP

19

+

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

VBAT

DRAIN

2

SOURCE

3

4-177

RFT1P06E

SPICE Thermal Model

rev 10/16/97

RFT1P06E

CTHERM1 7 6 1.3e-4
CTHERM2 6 5 5.0e-4
CTHERM3 5 4 2.0e-3
CTHERM4 4 3 5.0e-3
CTHERM5 3 2 4.75e-2
CTHERM6 2 1 3.8e-1

RTHERM1 7 6 4.0e-2
RTHERM2 6 5 9.0e-2
RTHERM3 5 4 5.0e-1
RTHERM4 4 3 3.5
RTHERM5 3 2 20
RTHERM6 2 1 75

RTHERM1

RTHERM2

RTHERM3

RTHERM4

5

4

7

6

JUNCTION

CTHERM1

CTHERM2

CTHERM3

CTHERM4

3

RTHERM5

RTHERM6

2

CASE

1

CTHERM5

CTHERM6

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications atan ytime with­out notice. Accordingly,the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor f orany infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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4-178